JP2017017358A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art capable of preventing reliability degradation caused by element isolation in a semiconductor device which is formed on an SOI substrate and an element region of a semiconductor layer which composes the SOI substrate is surrounded by element isolation.SOLUTION: In a semiconductor device manufacturing method, by making a trench width of an upper part of a deep trench 4 which provides trench isolation be narrower than 1.2 μm, a hollow 7 generated when an insulation film 5 is embedded inside the deep trench 4 can be prevented from being exposed on a top face of the insulation film 5. An issue of concern that voltage withstanding between element regions adjacent to each other deteriorates due to decrease in trench width of the upper part of the deep trench 4 is prevented by forming at the upper part of the deep trench 4, a LOCOS insulation film 6 connected to the insulation film 5 embedded inside the deep trench 4.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to an element isolation structure that electrically isolates high breakdown voltage semiconductor elements formed on a main surface of an SOI (Silicon On Isolation) substrate and manufacturing the same. It relates to effective technology.

  In recent years, a surface having almost the same height as the main surface of the semiconductor substrate has been obtained for element isolation that electrically isolates adjacent semiconductor elements provided on the main surface of the semiconductor substrate, and LOCOS (Local Oxidation of Silicon). ) Trench isolation, which allows finer processing than isolation, is employed. The trench isolation is formed by forming a groove in the main surface of the semiconductor substrate and then embedding an insulating film in the groove.

  For example, in Japanese Patent Laid-Open No. 2002-43413 (Patent Document 1), a forward-tapered trench formed by anisotropic etching is located near the surface of a semiconductor substrate, and a lower trench connected to the trench is formed on the bottom surface. There is disclosed a trench formed by isotropic etching so that the width is equal to or greater than the bottom width of a forward tapered trench.

  Japanese Patent Laid-Open No. 2008-60383 (Patent Document 2) discloses that after forming a groove on the surface of a silicon substrate, the inner surface of the groove is cleaned to remove contaminants, and further, a defect on the inner surface of the groove is detected. In order to remove the layer, a technique of etching the inner surface of the groove by isotropic etching with radicals is disclosed.

  Japanese Patent Laid-Open No. 2009-99815 (Patent Document 3) discloses that a groove is formed between wells of the same type, and further, a silicide layer is formed on at least the bottom surface of the groove so that the same type of wells can be connected with low resistance. A semiconductor device in which a common potential between wells can be obtained by connection is disclosed. The groove is formed by first patterning the semiconductor substrate by anisotropic etching and then widening the opening width by isotropic etching.

  Japanese Patent Laid-Open No. 2008-306003 (Patent Document 4) discloses that a trench having an aspect ratio of 10 or more is formed on a semiconductor substrate by anisotropic dry etching, and then the entire wall surface of the trench is damaged by isotropic dry etching. Techniques for removing the layer are disclosed.

  Japanese Patent Laid-Open No. 11-40666 (Patent Document 5) discloses an interlayer insulating film having a silicon oxide film having holes between adjacent wirings and an insulating film having a low dielectric constant on the silicon oxide film. A technique for reducing the capacitance between wirings in the same layer and different layers by forming the layer is disclosed.

  Japanese Patent Laid-Open No. 2007-110119 (Patent Document 6) discloses that a first layer, which is a first insulating material, is formed by a plasma chemical vapor deposition method so as to provide a gap between adjacent wirings. A technique for depositing a second layer, which is a second insulating material, on the first layer after retreating is disclosed.

  Japanese Patent Laid-Open No. 2000-150807 (Patent Document 7) has a substantially polygonal trench so as to surround the periphery of the element region, and the corner of the trench is rounded or tapered. Thus, a technique for suppressing the dishing phenomenon is disclosed.

  Japanese Patent Application Laid-Open No. 2009-518838 (Patent Document 8) has corners that are chamfered or rounded at an intersection region or a junction region of a trench, and further, a central island is arranged in the intersection region or the junction region. Thus, an insulating trench structure having a uniform insulating trench width is disclosed by making the width of the insulating trench in the intersecting region or the merged region the same as the width of the insulating trench other than the intersecting region or the merged region.

JP 2002-43413 A JP 2008-60383 A JP 2009-99815 A JP 2008-306003 A Japanese Patent Laid-Open No. 11-40666 JP 2007-110119 A JP 2000-150807 A JP 2009-518838 A

  The present inventors are developing a semiconductor device having a high breakdown voltage semiconductor element that requires a breakdown voltage of 20 V or more and is formed on the main surface of an SOI substrate. In this semiconductor device, a dielectric isolation method combining an SOI substrate and trench isolation is employed for element isolation.

  In the dielectric isolation method, the high breakdown voltage semiconductor element is formed in the element region of the semiconductor layer constituting the SOI substrate. This element region is formed in the insulator constituting the SOI substrate and the semiconductor layer constituting the SOI substrate, and inside the deep trench (groove, separation groove, U groove, trench) reaching the insulator constituting the SOI substrate. Surrounded by an insulator embedded in. That is, each high breakdown voltage semiconductor element is formed in an island-shaped element region of a semiconductor layer constituting an SOI substrate separated from each other by a dielectric.

  Therefore, this dielectric isolation method has an advantage that the degree of integration of the semiconductor device can be increased because the insulation isolation distance between the high voltage semiconductor elements adjacent to each other can be shortened as compared with the pn junction isolation method. In addition, this dielectric isolation method can eliminate in principle parasitic transistors between adjacent high-voltage semiconductor elements, prevent malfunctions such as latch-up due to this, and increase the reliability of the semiconductor device.

  However, there are various technical problems described below for the dielectric isolation method combining the SOI substrate and the trench isolation.

  First, the trench isolation forming method studied by the present inventors prior to the present invention will be briefly described.

First, a deep trench reaching the insulator constituting the SOI substrate is formed in the semiconductor layer constituting the SOI substrate by anisotropic drain etching using the resist pattern as a mask. Next, after removing the resist pattern, a buried insulating film is deposited on the upper surface of the semiconductor layer constituting the SOI substrate so as to bury the inside of the deep trench. This buried insulating film is an insulator having a high covering property such as a TEOS (Tetra Ethyl Ortho Silicate; Si (OC ₂ H ₅ ) ₄ ) film formed by, for example, a plasma CVD (Chemical Vapor Deposition) method. Next, the upper surface of the buried insulating film is polished and flattened by, for example, a CMP (Chemical Mechanical Polishing) method. As a result, trench isolation in which the inside of the deep trench is filled with the buried insulating film is formed.

  However, in the trench isolation formed by the above method, as shown in FIGS. 23A and 23B, the buried insulating film 52 is not completely filled in the deep trench 51, and the upper surface of the buried insulating film 52 is not filled. A recess 54 is formed, or a hollow (a seam, an air gap, an air gap) 53 is formed inside the deep trench 51. The depression 54 on the upper surface of the buried insulating film 52 is hollow 53 when the trench width of the deep trench 51 is wider (FIG. 23B) than when the trench width of the deep trench 51 is narrow (FIG. 23A). Deeply formed. The hollow 53 is also buried when the trench width of the deep trench 51 is wider (FIG. 23B) than when the trench width of the deep trench 51 is narrow (FIG. 23A), particularly at 1.2 μm or more. It is formed up to a position close to the upper surface of the insulating film 52.

  Subsequently, when the upper surface of the buried insulating film 52 is polished to the position indicated by the dotted line in FIGS. 23A and 23B by, for example, the CMP method, the trench width of the deep trench 51 is narrow (FIG. 23A). The depression 54 on the upper surface of the buried insulating film 52 is eliminated, and the upper surface of the buried insulating film 52 becomes flat. However, when the trench width of the deep trench 51 is wide (FIG. 23B), the recess 54 remains on the upper surface of the buried insulating film 52, and the hollow 53 appears when polishing is continued.

  In a subsequent process, when a conductive film is deposited on the upper surface of the buried insulating film 52, when the trench width of the deep trench 51 is wide (FIG. 23B), the depression 54 or the hollow 53 on the upper surface of the buried insulating film 52 is also formed. The conductive film is deposited, and problems such as a malfunction of the high voltage semiconductor element, an increase in parasitic capacitance, or a decrease in breakdown voltage due to trench isolation due to the conductive film remaining in the depression 54 or the hollow 53 on the upper surface of the buried insulating film 52 occur. .

  Therefore, in order to prevent the formation of the deep recess 54 on the upper surface of the buried insulating film 52 and the formation of the hollow 53 near the upper surface of the buried insulating film 52, the trench width of the deep trench 51 is set to 1. It was examined to make it narrower than 2 μm. However, when the trench width of the deep trench 51 is narrower than 1.2 μm, the breakdown voltage of the trench isolation is reduced. In particular, when the trench width of the deep trench 51 is narrower than 0.7 μm, the breakdown voltage of the trench isolation is significantly reduced. occured.

  An object of the present invention is a technology capable of preventing a decrease in reliability due to element isolation in a semiconductor device formed on an SOI substrate and surrounded by element isolation in an element region of a semiconductor layer constituting the SOI substrate. Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  In this embodiment, a semiconductor device formed on an SOI substrate including a support substrate, a BOX layer made of an insulator formed on the main surface of the support substrate, and an active layer formed on the upper surface of the BOX layer. And the LOCOS insulating film formed on the upper surface of the active layer in a plan view, and the LOCOS insulating film formed in a ring on the upper surface of the active layer. The LOCOS includes a deep trench that is continuously formed and reaches the BOX layer, and an insulating film that is embedded in the deep trench and also functions as an interlayer insulating film that covers a semiconductor element formed in the element region. The trench width of the deep trench formed in a part of the insulating film is narrower than the trench width of the deep trench formed in the active layer and smaller than 1.2 μm. .

  In addition, this embodiment provides a high withstand voltage to an SOI substrate including a support substrate, a BOX layer made of an insulator formed on the main surface of the support substrate, and an active layer formed on the upper surface of the BOX layer. A method of manufacturing a semiconductor device for forming a semiconductor element, the step of forming a LOCOS insulating film surrounding the element region in a ring shape in plan view on the upper surface of the active layer, and the step of forming the semiconductor element in the active layer of the element region And a step of depositing a first insulating film covering the semiconductor element on the upper surface of the active layer, and dry etching using the resist pattern as a mask, the predetermined region surrounding the element region on the LOCOS insulating film in a plan view The step of etching the first insulating film in the region, and after removing the resist pattern, anisotropic dry etching using the first insulating film as a mask performs the LOCOS insulating film and the active layer. Etch only the side of the deep trench formed in the active layer by etching the layers sequentially, enclosing the element region in a plan view in a plan view, forming a deep trench reaching the BOX layer, and isotropic dry etching A step of depositing a second insulating film inside the deep trench and on the first insulating film, and a step of processing the upper surface of the second insulating film flat.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  In a semiconductor device formed on an SOI substrate and surrounding the element region of a semiconductor layer constituting the SOI substrate by element isolation, it is possible to prevent a decrease in reliability due to element isolation.

It is principal part sectional drawing which shows the high voltage | pressure-resistant semiconductor element formed in the SOI substrate by Embodiment 1 of this invention. It is principal part sectional drawing which expands and shows the element isolation of FIG. It is principal part sectional drawing of the high voltage semiconductor element which shows an example of the manufacturing method of the high voltage semiconductor element formed in the SOI substrate by Embodiment 1 of this invention. FIG. 4 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element subsequent to FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element subsequent to FIG. 4. FIG. 6 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element subsequent to FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element subsequent to FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 7; FIG. 9 is an essential part cross-sectional view of the same place as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the same portion as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the same place as that in FIG. 3 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 10; It is principal part sectional drawing which shows the high voltage | pressure-resistant semiconductor element formed in the SOI substrate by Embodiment 2 of this invention. It is principal part sectional drawing of the high voltage semiconductor element which shows an example of the manufacturing method of the high voltage semiconductor element formed in the SOI substrate by Embodiment 2 of this invention. FIG. 14 is a fragmentary cross-sectional view of the same place as that in FIG. 13 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the same portion as that of FIG. 13 during a manufacturing step of the high breakdown voltage semiconductor element subsequent to FIG. 14. FIG. 16 is a fragmentary cross-sectional view of the same place as that in FIG. 13 during a manufacturing step of the high breakdown voltage semiconductor element following that of FIG. 15; FIG. 17 is an essential part cross-sectional view of the same portion as that of FIG. 13 of the high breakdown voltage semiconductor element during the manufacturing step following that of FIG. 16; It is a top view which shows the element isolation | separation made into the figure 8 shape which the deep trench which each encloses two element area | regions which were mutually examined cyclically, and which was examined by the present inventors. It is a top view which shows the element isolation | separation made into the figure 8 shape with which the deep trench which each encloses two element area | regions adjacent to each other cyclically | annularly by Embodiment 3 of this invention was connected. It is a graph explaining the relationship between the diagonal mask dimension and the hollow mask dimension in the T-shaped portion of element isolation according to the third embodiment of the present invention. The upper surface of the deep trench when the two element isolations each having an 8-shaped configuration in which the deep trenches surrounding the two adjacent element regions in an annular shape are connected to each other according to the third embodiment of the present invention are arranged adjacent to each other FIG. It is a top view of the element isolation | separation made into the shape of the rice field with which the deep trench surrounding each four element area | regions adjacent to each other cyclically | annularly by Embodiment 3 of this invention was connected. (A) And (b) is sectional drawing explaining the shape of the insulating film deposited inside the deep trench, respectively.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, and an n-channel type MISFET is abbreviated as nMIS. In the following embodiments, the term “wafer” mainly refers to an SOI (Silicon On Insulator) wafer, but the shape thereof is not limited to a circle or a substantially circle but includes a square, a rectangle, and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The structure of the high voltage semiconductor element formed on the SOI substrate according to the first embodiment is shown in FIGS. FIG. 1 is a fragmentary cross-sectional view showing a high voltage semiconductor element formed on an SOI substrate, and FIG. Here, an n-channel type MISFET (hereinafter referred to as a high breakdown voltage nMIS) is illustrated as the high breakdown voltage semiconductor element.

  As shown in FIG. 1, the high breakdown voltage nMIS is formed on the SOI substrate. The SOI substrate includes a support substrate 1, a BOX (Buried Oxide) layer (embedded insulating film, insulator) 2 formed on the main surface of the support substrate 1, and an active layer (semiconductor layer) formed on the upper surface of the BOX layer 2. 3). The support substrate 1 is made of single crystal silicon and has a thickness of, for example, about 760 μm. The BOX layer 2 is made of silicon oxide and has a thickness of about 1.5 μm, for example. The active layer 3 is made of, for example, p-type single crystal silicon formed by an epitaxial method, and the thickness thereof is, for example, about 5 μm.

  On the upper surface of the active layer 3, a LOCOS insulating film 6 surrounding a predetermined region (element region) in a plan view is formed. The width of the LOCOS insulating film 6 is, for example, 1.2 μm or more, and the thickness of the thickest portion is, for example, about 0.6 μm. Further, a deep trench (groove, isolation groove, U groove, trench) 4 reaching the BOX layer 2 is formed continuously to a part of the LOCOS insulating film 6 and the active layer 3 therebelow. An insulating film 5 made of, for example, silicon oxide is embedded in the deep trench 4. The LOCOS insulating film 6 and a part of the insulating film 5 embedded in the deep trench 4 are connected to each other to form an integrated structure as element isolation.

  Therefore, the BOX layer 2, the insulating film 5 embedded in the deep trench 4 connected to the BOX layer 2, and a part of the insulating film 5 embedded in the deep trench 4 are connected to the upper surface of the active layer 3. The island-shaped active layer 3 surrounded by the formed LOCOS insulating film 6 becomes an element region in which a high breakdown voltage nMIS is formed. In other words, the element isolation according to the first embodiment employs a dielectric isolation system in which SOI isolation, trench isolation, and LOCOS isolation are combined.

  The shape and trench width of the deep trench 4 vary depending on the part. For example, the upper part of the deep trench 4 formed in a part of the LOCOS insulating film 6 is processed almost straight, but the trench width is formed narrower than the trench width of other parts. In addition, the trench width in the middle of the deep trench 4 formed in the active layer 3 below the deep trench 4 is formed to be, for example, about 0.1 μm wider than the trench width in the upper portion of the deep trench 4. Has been. The lower part of the deep trench 4 has a flared shape, and the trench width in contact with the BOX layer 2 is about twice the trench width of the upper part of the deep trench 4. This is probably because anisotropic dry etching is used to form the deep trench 4, so that the etching ions rebound and scatter in the BOX layer 2 to etch the active layer 3.

  For example, as shown in FIG. 2, the trench width (first width L1) of the upper part of the deep trench 4 (part formed in a part of the LOCOS insulating film 6) is, for example, about 0.7 to 0.8 μm. The trench width (second width L2) of the middle portion of the deep trench 4 (the portion formed between the upper portion of the deep trench 4 and the bottom-shaped portion) is, for example, about 0.8 to 0.9 μm. The trench width (third width L3) of the portion in contact with the BOX layer 2 at the lower portion (the portion in contact with the BOX layer 2 and the skirt-shaped portion in the vicinity thereof) is, for example, about 1.6 to 1.8 μm.

  In addition, an insulating film 5 made of, for example, silicon oxide is embedded in the deep trench 4, but the deep trench 4 is not completely filled with the insulating film 5, and is hollow (so, seam, air gap, Voids) 7 are formed. In the lower part and the middle part of the deep trench 4, there is also a part where a hollow 7 having a width of about 0.3 μm is formed. However, the width of the hollow 7 formed in the upper portion of the deep trench 4 is narrower than the width of the hollow 7 formed in the lower and middle portions of the deep trench 4, and the tip of the hollow 7 is the upper surface of the LOCOS insulating film 6. Located in the vicinity. That is, the upper surface of the deep trench 4 is closed by the insulating film 5, and the hollow 7 does not appear on the upper surface of the insulating film 5.

  As a result of studies by the present inventors, when the trench width of the deep trench 4 becomes narrower than 1.2 μm, the tip of the hollow 7 is positioned near the upper surface of the LOCOS insulating film 6, and the hollow 7 is located above the upper surface of the LOCOS insulating film 6. As a result, it was difficult to form the insulating film 5 deposited thereon. In the first embodiment, the trench width in the upper part of the deep trench 4 is, for example, about 0.7 to 0.8 μm, and the trench width in the middle part 7 is, for example, about 0.8 to 0.9 μm. Since the tip of the hollow 7 is located near the upper surface of the film 6 and the upper surface of the deep trench 4 can be closed by the insulating film 5, the hollow 7 does not appear on the upper surface of the insulating film 5.

  On the other hand, when the trench width of the deep trench 4 becomes narrower than 0.7 μm, there is a concern that the breakdown voltage between adjacent element regions may be lowered. However, since the LOCOS insulating film 6 having a width of 1.2 μm or more is formed on the deep trench 4 having a trench width of, for example, about 0.7 to 0.8 μm, the LOCOS insulating film 6 causes the above breakdown voltage. Can be prevented.

  A LOCOS insulating film 6 a that is not connected to the insulating film 5 of the deep trench 4 is also formed on a part of the main surface of the element region of the active layer 3. The LOCOS insulating film 6a is provided, for example, to define (enclose) a power feeding region of a well (a p-type well 8 described later) formed in the element region.

An n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the element region of the active layer 3, and the impurity concentration is, for example, about 1 × 10 ¹⁵ cm ⁻³ . Further, a p-type well 8 is formed in the element region of the active layer 3 by introducing a p-type impurity such as boron (B). The p-type well 8 is also a portion that becomes a channel region of the high breakdown voltage nMIS.

  The high breakdown voltage nMIS is formed in a p-type well 8 in an element region surrounded by element isolation (SOI isolation, trench isolation, and LOCOS isolation) of the active layer 3. A gate insulating film 9 made of, for example, silicon oxide is formed on the upper surface of the active layer 3 (p-type well 8), and a gate electrode 10 made of, for example, polycrystalline silicon is further formed thereon.

  Low-concentration n-type impurities are introduced into the active layer 3 (p-type well 8) on both sides of the gate electrode 10, and a pair of n-type semiconductor regions 11 are formed in a self-aligned manner with respect to the gate electrode 10. Yes. A sidewall 12 is formed on the side wall of the gate electrode 10, and a high concentration n-type impurity is introduced into the active layer 3 (p-type well 8) on both sides of the sidewall 12 to form a pair of n-type semiconductors. The region 13 is formed in a self-aligned manner with respect to the sidewall 12. One n-type semiconductor region 11, 13 constitutes a source region of high breakdown voltage nMIS, and the other n-type semiconductor region 11, 13 constitutes a drain region of high breakdown voltage nMIS. Therefore, the high breakdown voltage nMIS has a source region and a drain region having an LDD (Lightly Doped Drain) structure.

  A p-type semiconductor region 14 is formed by introducing a high-concentration p-type impurity into the power supply region of the p-type well 8 surrounded by the LOCOS insulating films 6 and 6b.

  Further, the same insulating film 5 as the insulating film 5 embedded in the deep trench 4 described above is formed on the upper surface of the active layer 3 so as to cover the high breakdown voltage nMIS. That is, the insulating film 5 serves both as a function of filling the deep trench 4 and as an interlayer insulating film.

  In the insulating film 5, contact holes 16 reaching the gate electrode 10 of the high breakdown voltage nMIS, the n-type semiconductor region 13 of the high breakdown voltage nMIS, and the p-type semiconductor region 14 formed in the power supply region of the p-type well 8 are formed. ing.

  A plug 17 made of a conductive material, for example, a metal such as tungsten (W), is embedded in the contact hole 16. On the insulating film 5, for example, a plurality of wirings 18 made of aluminum (Al) as a main conductor are formed. These wirings 18 are respectively connected to the high breakdown voltage nMIS gate electrode 10 and the high breakdown voltage nMIS via plugs 17. The n-type semiconductor region 13 and the p-type semiconductor region 14 formed in the power supply region of the p-type well 8 are electrically connected.

  Next, an example of a method for manufacturing a high voltage semiconductor element formed on the SOI substrate according to the first embodiment will be described in the order of steps with reference to FIGS. 3 to 11 are cross-sectional views of the main part showing the high breakdown voltage nMIS formed on the SOI substrate.

  First, as shown in FIG. 3, an SOI substrate is prepared. The SOI substrate at this stage is made of a substantially circular planar member called a wafer, and includes a support substrate 1, a BOX layer 2 formed on the main surface of the support substrate 1, and an active layer formed on the upper surface of the BOX layer 2. 3. The support substrate 1 is made of single crystal silicon, and has a thickness of, for example, about 760 μm and a resistivity of, for example, about 3-6 mΩcn. The BOX layer 2 is made of silicon oxide and has a thickness of about 1.5 μm, for example. The active layer 3 is made of, for example, p-type single crystal silicon formed by an epitaxial method, and has a thickness of, for example, about 5 μm and a resistivity of, for example, about 18-23 Ωcm.

  Next, as shown in FIG. 4, LOCOS insulating films 6 and 6a made of silicon oxide are formed in a predetermined region on the upper surface of the active layer 3 by a LOCOS method in which the active layer 3 is selectively thermally oxidized. The width of the LOCOS insulating film 6 is, for example, 1.2 μm or more, and the thickness of the thickest portion is, for example, about 0.6 μm.

  Next, as shown in FIG. 5, a p-type well 8 is formed by selectively introducing a p-type impurity such as boron (B) into the active layer 3. Subsequently, after performing a cleaning process on the SOI substrate, a gate insulating film 9 made of, for example, silicon oxide is formed on the upper surface of the active layer 3 (p-type well 8). Subsequently, after forming a conductor film made of, for example, polycrystalline silicon on the gate insulating film 9, the conductor film is processed by dry etching using the resist pattern as a mask to form the gate electrode.

  Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the active layer 3 (p-type well 8) on both sides of the gate electrode 10 to form a pair of n-type semiconductor regions 11 as gate electrodes. 10 in a self-aligned manner. Subsequently, an insulating film is deposited on the upper surface of the active layer 3, and this insulating film is processed by the RIE (Reactive Ion Etching) method to form the sidewall 12 on the side wall of the gate electrode 10. Thereafter, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the active layer 3 (p-type well 8) on both sides of the sidewall 12 so that the pair of n-type semiconductor regions 13 are formed in the sidewall 12. In contrast, it is formed in a self-aligning manner. Thereby, a source region having an LDD structure composed of n-type semiconductor regions 11 and 13 is formed in the active layer 3 (p-type well 8) on one side of the gate electrode 10, and the active layer 3 (on the other side of the gate electrode 10 ( A drain region having an LDD structure composed of n-type semiconductor regions 11 and 13 is formed in the p-type well 8).

  Next, a p-type impurity such as boron (B) is ion-implanted into the power feeding region of the p-type well 8 of the active layer 3 to form the p-type semiconductor region 14.

Next, as shown in FIG. 6, an insulating film (hard mask) 15 is deposited on the upper surface of the active layer 3. The insulating film 15 is a TEOS film formed by a plasma CVD method using TEOS and ozone (O ₃ ) as source gases, for example.

Next, as shown in FIG. 7, a resist pattern 19 is formed so as to cover other than the region where the deep trench 4 is to be formed. Subsequently, the insulating film 15 is processed by anisotropic dry etching using the resist pattern 19 as a mask, and the insulating film 15 in a region where the deep trench 4 is formed is removed. For this dry etching, for example, a fluorocarbon-based gas (for example, CF ₄ gas) is used.

Next, as shown in FIG. 8, after removing the resist pattern 19, the deep trench 4 reaching the BOX layer 2 to the LOCOS insulating film 6 and the active layer 3 by anisotropic dry etching using the insulating film 15 as a mask. Form. The trench width of the deep trench 4 here is, for example, about 0.7 to 0.8 μm. For the dry etching of the LOCOS insulating film 6, for example, a fluorocarbon gas (for example, CF ₄ gas) is used, and for the dry etching of the active layer 3, for example, SF ₆ gas is used. Thereby, the deep trench 4 having a trench width substantially equal to the mask dimension of the resist pattern 19 is formed.

  In anisotropic dry etching in which the deep trench 4 is formed in the active layer 3, etching ions are bounced back and scattered in the BOX layer 2 to etch the active layer 3. It has a spreading shape.

  Next, as shown in FIG. 9, the side surface of the deep trench 4 formed in the active layer 3 is etched by isotropic dry etching, so that the trench width of the deep trench 4 formed in the active layer 3 is, for example, Spread about 0.1 μm. When the trench width of the deep trench 4 becomes narrower than 0.7 μm, the withstand voltage between adjacent element regions (trench isolation) decreases, so that the deep trench 4 formed in the active layer 3 is formed by isotropic dry etching. Increase the trench width.

  The LOCOS insulating film 6 is formed on the deep trench 4. However, since the LOCOS insulating film 6 and the active layer 3 are made of different materials, in the isotropic dry etching, the LOCOS insulating film 6 and An etching process with good selectivity with the active layer 3 can be performed, and the trench width of the deep trench 4 formed in the active layer 3 can be easily widened. Although isotropic dry etching is employed here, dry etching or wet etching may be used as long as it is isotropic etching.

  The deep trench 4 is formed by the process described with reference to FIGS. 8 and 9 described above, but the trench width differs depending on the part. The trench width (the first width L1 in FIG. 2 described above) of the deep trench 4 formed in a part of the LOCOS insulating film 6 is, for example, about 0.7 to 0.8 μm formed in the active layer 3. The trench width in the middle part of the deep trench 4 (the second width L2 in FIG. 2 described above) is, for example, about 0.8 to 0.9 μm, and the trench width of the portion in contact with the BOX layer 2 in the deep trench 4 (see FIG. 2 described above). The third width L3) is, for example, about 1.6 to 1.8 μm. The trench width of the upper part of the deep trench 4 is, for example, about 0.7 to 0.8 μm, but since a LOCOS insulating film 6 having a wide width of, for example, 1.2 μm or more is formed in this part, A decrease in breakdown voltage between adjacent element regions (trench isolation) can be avoided.

  Next, as shown in FIG. 10, the insulating film 5 is deposited on the insulating film 15. The insulating film 5 is a BPSG (Boron Phospho Silicate Glass) film formed by, for example, a thermal CVD method, and is subjected to a reflow process at a temperature of, for example, 780 ° C. after being deposited.

  This insulating film 5 is also deposited inside the deep trench 4 to bury the inside of the deep trench 4. Here, the insulating film 5 cannot be completely filled in the deep trench 4, and the hollow 7 is formed in the deep trench 4. However, since the trench width at the upper part of the deep trench 4 is narrower than 1.2 μm, the width of the hollow 7 at this portion is narrowed, and the tip of the hollow 7 is located near the upper surface of the LOCOS insulating film 6. Therefore, since the upper surface of the deep trench 4 is closed by the insulating film 5, the hollow 7 does not appear on the upper surface of the insulating film 5. Further, a deep depression (for example, a deep depression 54 as shown in FIG. 23B described above) is not formed at a position facing the deep trench 4 on the upper surface of the insulating film 5.

  Next, as shown in FIG. 11, the upper surface of the insulating film 5 is polished by, for example, a CMP method. At this time, since the depression on the upper surface of the insulating film 5 is shallow, the depression on the upper surface of the insulating film 5 can be removed without polishing the upper surface of the insulating film 5 thickly. Further, since the tip of the hollow 7 formed inside the deep trench 4 is located near the upper surface of the LOCOS insulating film 6, the upper surface of the insulating film 5 is flattened without the hollow 7 appearing on the upper surface of the insulating film 5. Can be processed.

  Next, by dry etching using the resist pattern as a mask, the high breakdown voltage nMIS gate electrode 10, the high breakdown voltage nMIS n type semiconductor region 13, and the p type semiconductor region 14 formed in the power supply region of the p type well 8, respectively. A reaching contact hole 16 is formed in the insulating films 5 and 15. Subsequently, after filling the inside of the contact hole 16 and depositing a metal film made of a conductive material such as tungsten (W) on the insulating film 5, the metal film is polished by, for example, a CMP method to obtain a contact hole. The metal film is left only in the interior of 16. As a result, the plug 17 is formed inside the contact hole 16. Subsequently, after depositing a metal film having, for example, aluminum (Al) as a main conductor on the insulating film 5, the metal film is processed by dry etching using a resist pattern as a mask and connected to the upper surface of the plug 17. A plurality of wirings 18 are formed. Through the above steps, the high breakdown voltage nMIS according to the first embodiment is substantially completed.

  In the first embodiment, since the breakdown voltage between adjacent element regions is reduced, the trench width of the deep trench 4 is required to be 0.7 μm or more. However, the high breakdown voltage nMIS used reduces the breakdown voltage. Since the trench width that can be prevented is different, the trench width is not limited to 0.7 μm or more.

  In the first embodiment, the trench width in the middle portion of the deep trench 4 is increased by, for example, about 0.1 μm by isotropic etching compared to the trench width in the upper portion of the deep trench 4, but may be further expanded. Thereby, the withstand voltage between the element regions adjacent to each other can be improved.

  As described above, in the first embodiment, element isolation is configured by combining SOI isolation, trench isolation, and LOCOS isolation. Then, the trench width of the deep trench 4 constituting the trench isolation is made smaller than 1.2 μm except for the portion in contact with the BOX layer 2 and the lower portion of the skirt shape portion in the vicinity thereof. For example, the upper trench width of the deep trench 4 is set to about 0.7 to 0.8 μm, and the middle trench width between the upper and lower portions is set to about 0.8 to 0.9 μm. Thereby, when the inside of the deep trench 4 is filled with the insulating film 5, no deep depression is formed at a position facing the deep trench 4 on the upper surface of the insulating film 5, and the hollow 7 inside the deep trench 4 is formed. However, the tip is located near the upper surface of the LOCOS insulating film 6, and the upper surface of the deep trench 4 can be closed by the insulating film 5. Therefore, the upper surface of the insulating film 5 can be processed flat without a depression without the hollow 7 appearing on the upper surface of the insulating film 5.

  On the other hand, when the trench width of the deep trench 4 becomes narrower than 0.7 μm, the breakdown voltage between adjacent element regions is reduced. However, the trench width of the deep trench 4 having a trench width of, for example, about 0.7 to 0.8 μm is generated. Since the LOCOS insulating film 6 having a width of, for example, 1.2 μm or more is formed on the upper portion, the LOCOS insulating film 6 can prevent the above breakdown voltage from being lowered.

  Accordingly, since no depression is formed on the upper surface of the insulating film 5 and the hollow 7 does not appear, for example, even if a metal film constituting the plug 17 or a metal film constituting the wiring 18 is deposited on the insulating film 5, these metal films Does not remain on the upper surface of the insulating film 5 and does not enter the hollow 7. Furthermore, the width of element isolation can be set to a width that can prevent a decrease in breakdown voltage between adjacent element regions. Accordingly, it is possible to prevent a decrease in reliability of the semiconductor device due to element isolation.

(Embodiment 2)
FIG. 12 shows the structure of a high breakdown voltage semiconductor element formed on the SOI substrate according to the second embodiment. FIG. 12 is a cross-sectional view of a main part showing a high voltage semiconductor element formed on an SOI substrate, and a high voltage nMIS is exemplified as the high voltage semiconductor element.

  As shown in FIG. 12, the high breakdown voltage nMIS is formed on the SOI substrate as in the first embodiment. Further, it is surrounded by the BOX layer 2, the insulating film 5 embedded in the deep trench 4 connected to the BOX layer 2, and the LOCOS insulating film 6 connected to a part of the insulating film 5 embedded in the deep trench 4. The island-shaped active layer 3 becomes an element region where the high breakdown voltage nMIS is formed. That is, even in the element isolation according to the second embodiment, a dielectric isolation method in which SOI isolation, trench isolation, and LOCOS isolation are combined is adopted.

  However, the difference from the first embodiment described above is that the cap film 20 is formed on the insulating film 5 which is formed to serve both as a function of filling the deep trench 4 and as a function of an interlayer insulating film. It has been done. The cap film 20 is an insulating film, for example, a TEOS film formed by a plasma CVD method. The thickness is, for example, about 0.12 μm.

  That is, in Embodiment 1 described above, when the insulating film 5 is embedded in the deep trench 4 and the upper surface thereof is polished by the CMP method, a recess remains at a position facing the deep trench 4 on the upper surface of the insulating film 5. In addition, in order to prevent the hollow 7 formed inside the deep trench 4 from appearing on the upper surface of the insulating film 5, the trench width of the deep trench 4 is narrower than 1.2 μm (the portion in contact with the BOX layer 2 and its portion). Excluding the lower part of the nearby tail shape). However, in the second embodiment, even if a recess remains on the upper surface of the insulating film 5 or the hollow 7 formed inside the deep trench 4 appears on the upper surface of the insulating film 5, the upper surface of the insulating film 5 is capped. Covering with the membrane 20 and covering the recess or hollow 7 prevents the metal membrane from entering the recess or hollow 7.

  In order to improve the breakdown voltage between adjacent element regions, for example, when the trench width of the deep trench 4 is 1.2 μm or more, a deep recess is formed at a position facing the deep trench 4 on the upper surface of the insulating film 5. (For example, see FIG. 23B described above). For this reason, even if the upper surface of the insulating film 5 is polished by, for example, the CMP method, the recess remains on the upper surface of the insulating film 5. If the upper surface of the insulating film 5 is further polished in order to remove the depression, the hollow 7 appears on the upper surface of the insulating film 5. However, after that, by covering the upper surface of the insulating film 5 with the cap film 20, the depression or the hollow 7 can be covered. Even if the cap film 20 enters the recess or the hollow 7, the cap film 20 is an insulating film, so that there is no problem in element isolation.

  Next, an example of a method for manufacturing a high voltage semiconductor element formed on the SOI substrate according to the second embodiment will be described in the order of steps with reference to FIGS. 13 to 17 are cross-sectional views of the main part showing the high breakdown voltage nMIS formed on the SOI substrate. The manufacturing process (the process described with reference to FIGS. 3 to 7 in the first embodiment described above) until the high breakdown voltage nMIS is formed in the element region of the SOI substrate and the insulating film 15 is formed is the same as that described above. Since this is the same as the first embodiment, the description thereof is omitted.

Following the process described with reference to FIG. 7 in the first embodiment described above, as shown in FIG. 13, the LOCOS insulating film 6 and the active layer 3 are BOXed by anisotropic dry etching using the insulating film 15 as a mask. A deep trench 4 reaching the layer 2 is formed. Here, the trench width of the deep trench 4 is, for example, about 1.3 μm. For the dry etching of the LOCOS insulating film 6, for example, a fluorocarbon gas (for example, CF ₄ gas) is used, and for the dry etching of the active layer 3, for example, SF ₆ gas is used.

  In the anisotropic dry etching in which the deep trench 4 is formed in the active layer 3 as in the first embodiment, the active layer 3 is etched because the etching ions rebound and scatter in the BOX layer 2. For this reason, the lower part of the deep trench 4 has a hem-extended shape.

  Next, as shown in FIG. 14, the insulating film 5 is deposited on the insulating film 15. The insulating film 5 is a BPSG film formed by, for example, a thermal CVD method, and after the deposition, a reflow process is performed at a temperature of 780 ° C.

  This insulating film 5 is also deposited inside the deep trench 4 to bury the inside of the deep trench 4. Here, the insulating film 5 cannot be completely filled in the deep trench 4, and the hollow 7 is formed in the deep trench 4. Since the trench width in the upper part of the deep trench 4 is as wide as about 1.3 μm, for example, the hollow 7 is formed further above the upper surface of the LOCOS insulating film 6.

  Next, as shown in FIG. 15, the upper surface of the insulating film 5 is polished and flattened by, for example, a CMP method. However, even if the upper surface of the insulating film 5 is polished, a recess remains on the upper surface of the insulating film 5. If the upper surface of the insulating film 5 is further polished in order to remove this depression, the hollow 7 appears on the upper surface of the insulating film 5.

  Next, as shown in FIG. 16, a cap film 20 is deposited on the insulating film 5. The cap film 20 is a TEOS film formed by, for example, a plasma CVD method, and the thickness thereof is, for example, about 0.12 μm. By covering the upper surface of the insulating film 5 with the cap film 20, the depression or hollow 7 on the upper surface of the insulating film 5 can be covered.

  After that, as shown in FIG. 17, the high breakdown voltage nMIS according to the second embodiment is substantially completed by forming the contact hole 16, the plug 17, the wiring 18, and the like in the same manner as in the first embodiment. To do.

  In the second embodiment, the trench width of the deep trench 4 is set to, for example, about 1.3 μm. However, the present invention is not limited to this, and a decrease in breakdown voltage between adjacent element regions can be prevented. An arbitrary trench width can be set.

  In the second embodiment, the trench width at the upper part of the deep trench 4 (the upper part formed in a part of the LOCOS insulating film 6) and the middle part of the deep trench 4 (formed in a part of the LOCOS insulating film 6). The trench width between the upper part and the part in contact with the BOX layer 2 and the lower part of the skirt-shaped part in the vicinity thereof is the same. However, as in the first embodiment, the upper part of the deep trench 4 is The trench width in the middle of the deep trench 4 can be made narrower.

  As described above, according to the second embodiment, when the upper surface of the insulating film 5 is processed to be flat, even if a recess remains on the upper surface of the insulating film 5, or the hollow formed in the deep trench 4. Even if 7 appears, by covering the depression or hollow 7 with the cap film 20, for example, the metal film constituting the plug 17 or the metal film constituting the wiring 18 does not enter the depression or hollow 7. Furthermore, the width of element isolation can be set to a width that can prevent a decrease in breakdown voltage between adjacent element regions. Thereby, it is possible to prevent a decrease in reliability of the semiconductor device due to element isolation.

(Embodiment 3)
The element isolation according to the third embodiment has a structure in which two deep trenches surrounding two or more adjacent element regions are connected.

  First, since the element isolation structure according to the third embodiment is considered to be clearer, two or more adjacent to each other before application of the present invention studied by the present inventors prior to the present invention. The element isolation in which the deep trenches surrounding the element regions in an annular shape are connected will be briefly described.

  FIG. 18 is a top view showing element isolation, which is studied by the present inventors, in which two deep trenches that surround two adjacent element regions in a ring shape are connected. The first direction used in the description here is the x direction shown in FIG. 18, and the second direction is the y direction orthogonal to the first direction shown in FIG.

  As shown in FIG. 18, the first element region 21 and the second element region 22 which are adjacent to each other along the second direction (y direction) are surrounded by the deep trench 23. Therefore, in the deep trench 23, three deep trenches 23x formed along the first direction (x direction) and two deep trenches 23y formed along the second direction (y direction) are connected. Has the shape of

  Here, the end of the deep trench 23x between the first element region 21 and the second element region 22 is connected to the deep trench 23y, and the connected portion has a T-shape. In this T-shaped portion of the deep trench 23, the trench width is wider than the deep trench 23x formed along the first direction (x direction) or the deep trench 23y formed along the second direction (y direction). There is a place to become. That is, the trench width Lr in the diagonal direction indicated by the arrow in the T-shaped portion of FIG. 18 is formed along the deep trench 23x formed along the first direction (x direction) or along the second direction (y direction). The depth of the deep trench 23y is about 1.4 times. Therefore, even if the trench width of the deep trench 23x formed along the first direction (x direction) or the deep trench 23y formed along the second direction (y direction) is 0.8 μm, for example, a T-shaped portion The trench width in the diagonal direction is 1.2 to 1.3 μm. When the trench width of the deep trench 23 is 1.2 μm or more, when an insulating film is embedded in the deep trench 23, a deep depression is easily formed at a position facing the deep trench 23 on the upper surface of the insulating film, A hollow is easily formed near the top surface of the insulating film. Therefore, even if the upper surface of the insulating film is polished by a CMP method or the like, a dent on the upper surface of the insulating film remains, and when the upper surface of the insulating film is further polished to remove this dent, a hollow appears.

  Therefore, in Embodiment 3, the trench width in the T-shaped portion of the deep trench 23 is formed along the deep trench 23x formed along the first direction (x direction) or along the second direction (y direction). Further, by making the trench width the same as or narrower than the trench width of the deep trench 23y, the remaining of the depression or the hollow exposure in the T-shaped portion of the deep trench 23 is prevented.

  The element isolation structure according to the third embodiment will be described with reference to FIG. FIG. 19 is a top view showing element isolation in which deep trenches surrounding two adjacent element regions in an annular shape are connected. FIG. 19 shows a mask pattern used for forming a deep trench, and the dimensions here are so-called mask dimensions. FIG. 19 shows only the shape of the deep trench, but as in the first or second embodiment described above, the actual element isolation is a dielectric in which SOI isolation, trench isolation, and LOCOS isolation are combined. The separation method is adopted.

  As shown in FIG. 19, the first element region 24 and the second element region 25 adjacent to each other along the second direction (y direction shown in FIG. 19) are surrounded by the deep trench 26. Accordingly, the deep trench 26 is formed along three deep trenches 26x formed along a first direction (x direction shown in FIG. 19) orthogonal to the second direction and along the second direction (y direction). The portion where the deep trench 26y is connected to the two deep trenches 26y and the end of the deep trench 26x between the first element region 24 and the second element region 25 is connected to the deep trench 26y is T It has a letter shape.

  Here, the side surface of the deep trench 26x in contact with the first element region 24 is the first x side surface T1x, the side surface of the deep trench 26y in contact with the first element region 24 is the first y side surface T1y, and the side of the deep trench 26x in contact with the second element region 25. The side surface of the deep trench 26y contacting the second element region 25 is the second y side surface T2y, the side surface of the outer trench deep trench 26x opposite to the first x side surface T1x, and the side surface opposite to the second x side surface T2x. The side surface is a third x side surface T3x, the side surface opposite to the first y side surface T1y of the deep trench 26y of the outer frame, and the side surface opposite to the second y side surface T2y are the third y side surface T3y.

  In the T-shaped portion, the intersection between the first x side surface T1x and the first y side surface T1y and the intersection between the second x side surface T2x and the second y side surface T2y form 90 ° in plan view. Further, in the T-shaped portion, the third y side surface T3y is recessed in a wedge shape toward the deep trench 26x between the first element region 24 and the second element region 25 in plan view. The dimension (Ly) along the second direction (y direction) of the wedge-shaped depression is the same as the trench width of the deep trench 26x between the first element region 24 and the second element region 25. The dimension (Lx) along the first direction (x direction) of the recess is desirably half the trench width of the deep trench 26y.

  FIG. 20 is a cross section of the T-shaped portion of FIG. 19 from the intersection of the first x side surface T1x of the deep trench 26x contacting the first element region 24 and the first y side surface T1y of the deep trench 26y to the apex of the wedge-shaped depression. The mask dimension (the dimension Lt shown in FIG. 19 and hereinafter referred to as the diagonal mask dimension) and the mask dimension from the third y side surface T3y of the deep trench 26y to the apex of the wedge-shaped depression (the dimension Lx shown in FIG. 19). FIG. 5 is a graph illustrating the relationship with the recess mask dimension. The trench widths (mask dimensions) of the deep trenches 26x and 26y are 0.8 μm.

  As shown in FIG. 20, when the recess mask dimension (Lx) is 0.4 μm, which is half the trench width, the diagonal mask dimension (Lt) is substantially the same as the trench width 0.8 μm. When the dent mask dimension (Lx) is larger than 0.4 μm, the diagonal mask dimension (Lt) is further decreased, and the T-shaped portion is hollow to the deep pit on the upper surface of the insulating film or near the upper surface of the insulating film. It becomes difficult to form. However, when the trench width of the deep trench 26 becomes too narrow, the breakdown voltage between the element regions is reduced in the T-shaped portion.

  In order to prevent a local drop in breakdown voltage, it is desirable that the trench width of the deep trench 26 be uniform. Therefore, in Embodiment 3, the trench width of the deep trench 26 is made substantially uniform (about 0.8 μm) by setting the recess mask dimension (Lx) to 0.4 μm.

  FIG. 21 shows another example of the element isolation structure according to the third embodiment. FIG. 21 is a top view of a deep trench in a case where two element isolations each having an 8-shaped configuration in which two deep trench elements surrounding two adjacent element regions are connected to each other are arranged adjacent to each other.

  Since the wedge-shaped depression is formed in the T-shaped portion, the deep trench 26 is formed outside the extension line Li (the line indicated by the dotted line in FIG. 21) of the third y side surface T3y of the deep trench 26. Absent. Therefore, two element isolations adjacent to each other can be arranged with a minimum design dimension, which is convenient for high integration of a semiconductor device.

  FIG. 22 shows another example of the element isolation structure according to the third embodiment. FIG. 22 is a top view of element isolation in the shape of a rice field in which deep trenches surrounding four element regions adjacent to each other in an annular shape are connected. Although only the shape of the deep trench is shown here, as in the first or second embodiment described above, element isolation is performed by a dielectric isolation method in which SOI isolation, trench isolation, and LOCOS isolation are combined. Adopted.

  As shown in FIG. 22, four element regions (a first element region 27, a second element region 28, a third element region 29, and a fourth element region 30) adjacent to each other are surrounded by a deep trench 31. Therefore, the deep trench 31 includes two deep trenches 31xo formed along a first direction (x direction shown in FIG. 22) constituting an outer frame of element isolation and a second direction (FIG. 22) orthogonal to the first direction. 2 deep trenches 31yo formed along the first direction (x direction) constituting the inner frame of the element isolation, and the second direction. It has the shape of a rice field in which two deep trenches 31yi1 and 31yi2 formed along (y direction) are connected.

  In the T-shaped portion formed on the outer frame of the element isolation, wedge-shaped depressions are formed in the deep trench 31xo and the deep trench 31yo as in the element isolation shown in FIG.

  Furthermore, wedge-shaped depressions are formed in the deep trenches 31yi1 and 31yi2 also in the T-shaped portion formed in the inner frame for element isolation. That is, the two deep trenches 31yi1 and 31yi2 formed along the second direction (y direction) constituting the inner frame for element isolation are formed on the same line, but the first trench constituting the inner frame for element isolation is formed. The two deep trenches 31xi1 and 31xi2 formed along the direction (x direction) are not formed on the same line. Therefore, a portion where the end of the deep trench 31xi1 between the first element region 27 and the second element region 28 and the deep trench 31yi1 are connected, and a deep portion between the third element region 29 and the fourth element region 30. A portion where the end of the trench 31xi2 and the deep trench 31yi2 are connected has a T shape.

  Here, the side surfaces of the deep trenches 31xo and 31xi1 in contact with the first element region 27 are in contact with the first x side surface T1x, and the side surfaces of the deep trenches 31yo and 31yi1 in contact with the first element region 27 are in contact with the first y side surface T1y and the second element region 28. The side surfaces of the deep trenches 31xo, 31xi1 are the second x side surface T2x, the side surfaces of the deep trenches 31yo, 31yi1, 31yi2 in contact with the second element region 28 are the second y side surface T2y, and the side surfaces of the deep trenches 31xo, 31xi2 in contact with the third element region 29 The third x side surface T3x, the side surfaces of the deep trenches 31yo, 31yi1 in contact with the first element region 29 are the third y side surface T3y, the side surfaces of the deep trenches 31xo, 31xi2 in contact with the fourth element region 30 are the fourth x side surface T4x, and the fourth element region 30. Deep trench 31 in contact with o, the side of the 31yi2 to the first 4y side T4y. Further, the outer frame deep trench 31xo has a side surface opposite to the first x side surface T1x, a side surface opposite to the second x side surface T2x, a side surface opposite to the third x side surface T3x, and a side surface opposite to the fourth x side surface T4x. The fifth x side surface T5x, the side surface opposite to the first y side surface T1y of the deep trench 31yo of the outer frame, the side surface opposite to the second y side surface T2y, the side surface opposite to the third y side surface T3y, and the side opposite to the fourth y side surface T4y The side surface is defined as a fifth y side surface T5y.

  In one T-shaped portion formed in the inner frame of the element isolation, the third y side surface T3y of the third element region 29 has a deep trench 31xi1 between the first element region 27 and the second element region 28 in plan view. It is recessed like a wedge. The dimension along the second direction (y direction) of the wedge-shaped depression is the same as the trench width of the deep trench 31xi1 between the first element region 27 and the second element area 28. The dimension along one direction (x direction) is desirably half the trench width of the deep trench 31yi1. In the other T-shaped portion, the second y side surface T2y of the second element region is recessed in a wedge shape toward the deep trench 31xi2 between the third element region 29 and the fourth element region 30 in plan view. Yes. The dimension along the second direction (y direction) of the wedge-shaped depression is the same as the trench width of the deep trench 31xi2 between the third element region 29 and the fourth element region 30, and the wedge-shaped depression The dimension along one direction (x direction) is desirably half the trench width of the deep trench 31yi2.

  Thus, according to the third embodiment, the first direction (x direction) is between the first element region and the second element region that are arranged adjacent to each other along the second direction (y direction). Deep trench formed along the second direction (y direction) in the T-shaped portion where the end of the deep trench formed along the T is connected to the deep trench formed along the second direction (y direction) The side surfaces opposite to the first element region and the second element region are recessed in a wedge shape toward the deep trench between the first element region and the second element region in plan view, and a pair of T-shaped portions is formed. The trench width in the angular direction is equal to or smaller than the trench width of the deep trench formed along the first direction (x direction) or the deep trench formed along the second direction (y direction). To do. As a result, when the insulating film is embedded in the deep trench in the T-shaped portion of the deep trench, the recess formed at the position facing the deep trench on the upper surface of the insulating film becomes shallow, and the upper surface of the insulating film is It can be processed flat without deep polishing. Further, since the hollow formed inside the deep trench is not formed close to the upper surface of the insulating film, exposure of the hollow can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to element isolation for electrically isolating adjacent high-breakdown-voltage semiconductor elements formed on an SOI substrate.

1 Support substrate 2 BOX layer (embedded insulating film, insulator)
3 Active layer (semiconductor layer)
4 Deep trench (groove, separation groove, U groove, trench)
5 Insulating film 6, 6a LOCOS insulating film 7 Hollow (soil, seam, air gap, air gap)
8 p-type well 9 gate insulating film 10 gate electrode 11 n-type semiconductor region 12 sidewall 13 n-type semiconductor region 14 p-type semiconductor region 15 insulating film (hard mask)
16 Contact hole 17 Plug 18 Wiring 19 Resist pattern 20 Cap film 21 First element region 22 Second element region 23, 23x, 23y Deep trench 24 First element region 25 Second element region 26, 26x, 26y Deep trench 27 First Element region 28 Second element region 29 Third element region 30 Fourth element region 31 Deep trench 31xi1, 31xi2, 31xo Deep trench 31yi1, 31yi2, 31yo Deep trench 51 Deep trench (groove, isolation groove, U groove, trench)
52 Embedded insulating film 53 Hollow (soil, seam, air gap, air gap)
54 Depression L1 First width L2 Second width L3 Third width Lr, Lt, Lx, Ly Dimensions Li Extension line T1x 1x side surface T1y 1y side surface T2x 2x side surface T2y 2y side surface T3x 3x side surface T3y 2nd 3y side surface T4x 4x side surface T4y 4y side surface T5x 5x side surface T5y 5y side surface

Claims (3)

A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing an SOI substrate including a support substrate, a BOX layer made of an insulator formed on a main surface of the support substrate, and an active layer formed on an upper surface of the BOX layer;
(B) forming a LOCOS insulating film on the upper surface of the active layer so as to surround the element region in a plan view;
(C) forming a semiconductor element in the active layer in the element region;
(D) depositing a first insulating film covering the semiconductor element on the upper surface of the active layer;
(E) etching the first insulating film on the LOCOS insulating film and in a predetermined region surrounding the element region in a plan view by dry etching using a resist pattern as a mask;
(F) removing the resist pattern;
(G) The LOCOS insulating film and the active layer are sequentially etched by anisotropic dry etching using the first insulating film as a mask so as to surround the element region in a plan view and reach the BOX layer. Forming a deep trench;
(H) depositing a second insulating film inside the deep trench and on the first insulating film;
(I) a step of processing the upper surface of the second insulating film flat;
(J) depositing a third insulating film on the second insulating film;
(K) forming a contact hole that penetrates the third insulating film and the second insulating film and reaches the element region;
(L) forming a plug by embedding a conductive material in the contact hole;
(M) forming a metal wiring in contact with the upper surface of the plug on the third insulating film; 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the following steps between the step (g) and the step (h):
(N) The side surface of the deep trench formed in the active layer is etched by isotropic etching, so that the trench is formed in the active layer rather than the trench width of the deep trench formed in the LOCOS insulating film. And a step of widening the trench width of the deep trench.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a BPSG film formed by a thermal CVD method, and the third insulating film is a TEOS film formed by a plasma CVD method. A method of manufacturing a semiconductor device.

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