JP2017011094A - Printed Wiring Board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board that can reduce attenuation of high-frequency signals.SOLUTION: A solid pattern L5S is disposed at a lower layer of a land L4I connected to the bottom portion of a via conductor 603 at the lowermost portion of a stacked via 60FF, 60FS, and the solid pattern L5S is provided with an opening L5H which is concentric with the land L4I. No floating capacitance occurs between the land L4I and the solid pattern L5S due to the opening L4H. Therefore, the impedance of the stacked via 60FF, 60FS is increased, impedance matching with a wiring is performed, and attenuation of high frequency signals is reduced.SELECTED DRAWING: Figure 1

Description

The present invention relates to a multilayer printed wiring board capable of handling high frequency signals.

Patent Document 1 is a build-up type multilayer printed wiring board, and by increasing the thickness of the conductor layer on the core substrate, the conductor resistance is reduced and the high frequency is supported.

JP 2011-2558997 A

In order to reduce attenuation of high frequency signals, it is important to achieve impedance matching. Here, FIG. 9A is a cross section of the printed wiring board that is symmetric with respect to the simulation, and FIG. 9B is a plan view of the land L4l and the signal line L4Si provided on the fourth conductor layer L4 of the printed wiring board. FIG. Stacked vias 60FF and 60FS composed of via conductors 601, 602, and 603 penetrating the resin insulating layers R1, R2, and R3 shown in the drawing are provided. It has been found that the impedance of the stacked vias 60FF and 60FS is lower than that of the wiring on the resin insulating layer, for example, the signal line L4Si, and impedance matching cannot be achieved. Here, via conductors 601, 602, 603 have a via bottom diameter D3 of 100 μm, lands L21, L31,. The diameter D4 of L4l is 250 μm. The insulation distance between the lands L2l, L3l, and L4l and the openings L2H, L3H, and L4H of the solid patterns L2S, L3S, and L4S is 100 μm.

The printed wiring board according to the present invention is formed by laminating a conductor layer and a resin insulating layer, and includes a via conductor penetrating the resin insulating layer. A solid pattern is disposed below the land connected to the bottom of the bottom via conductor of the stacked via in which the via conductors connected to the signal line are stacked in a straight line, and the solid pattern corresponds to the land. Is provided with an opening concentric with the land.

In the printed wiring board of the embodiment, a solid pattern is provided with an opening concentric with the land. There is no stray capacitance between the land connected to the bottom of the lowermost via conductor of the stacked via and the lower solid pattern. For this reason, the impedance of the stacked via is increased, impedance matching with the wiring is taken, and attenuation of a high-frequency signal can be reduced.

FIG. 1A is a cross-sectional view of a printed wiring board according to an embodiment of the present invention, and FIG. 1B is a plan view of a fourth conductor layer and a fifth conductor layer as viewed from the F-plane side. Sectional drawing of the printed wiring board which concerns on the 1st modification of embodiment. 3A is a cross-sectional view of a printed wiring board according to a second modification of the embodiment, and FIG. 3B is a plan view of the fourth conductor layer and the fifth conductor layer as viewed from the F-plane side. 3C is a plan view of the third conductor layer and the fourth conductor layer viewed from the F plane side, and FIG. 3D is a plan view of the seventh conductor layer and the sixth conductor layer viewed from the S plane side. It is a top view. The chart which shows the result of having simulated impedance Z0 of an embodiment. The figure which shows the result of having simulated the insertion loss by a stacked via part. The graph which shows the result of having simulated the impedance Z0 of the 2nd modification of embodiment. The graph which shows the result of having simulated the insertion loss by the stacked via | veer part and through-hole conductor of the 2nd modification of embodiment. The chart which shows the result of having simulated insertion loss [dB] of via diameter / land diameter: 75/150, 100/250. FIG. 9A is a cross-sectional view of a conventional printed wiring board, and FIG. 9B is a plan view of the land L4l and the signal line L4Si provided on the fourth conductor layer L4 of the conventional printed wiring board. It is.

[Embodiment]
FIG. 1A is a cross-sectional view showing stacked vias 60FF and 60FS of the printed wiring board 10 of the embodiment.
The printed wiring board 10 is composed of a build-up board and includes a first surface (upper surface) F and a second surface (lower surface) S. The printed wiring board 10 transmits a signal between a pair of electronic components mounted on the first surface. The printed wiring board includes a first conductor layer L1, a second conductor layer L2, a third conductor layer L3, a fourth conductor layer L4, a fifth conductor layer L5, a sixth conductor layer L6, a seventh conductor layer L7, and an eighth conductor layer. A conductor layer L8, a ninth conductor layer L9, and a tenth conductor layer L10 are provided. A first resin insulation layer R1 is provided between the first conductor layer L1 and the second conductor layer L2 of the printed wiring board. A second resin insulation layer R2 is provided between the second conductor layer L2 and the third conductor layer L3. A third resin insulation layer R3 is provided between the third conductor layer L3 and the fourth conductor layer L4. A fourth resin insulation layer R4 is provided between the fourth conductor layer L4 and the fifth conductor layer L5. A fifth resin insulating layer R5 is provided between the fifth conductor layer L5 and the sixth conductor layer L6. The fifth resin insulation layer R5 constitutes the core substrate at the center of the printed wiring board. A sixth resin insulating layer R6 is provided between the sixth conductor layer L6 and the seventh conductor layer L7. A seventh resin insulation layer R7 is provided between the seventh conductor layer L7 and the eighth conductor layer L8. An eighth resin insulating layer R8 is provided between the eighth conductor layer L8 and the ninth conductor layer L9. A ninth resin insulation layer R9 is provided between the ninth conductor layer L7 and the tenth conductor layer L10. An upper solder resist layer SRU is provided on the first conductor layer L1. A lower solder resist layer SRD is provided on the tenth conductor layer L10. The stacked vias 60FF and 60FS include a via conductor 601 penetrating the first resin insulating layer R1, a via conductor 602 penetrating the second resin insulating layer R2, and a via conductor 603 penetrating the third resin insulating layer R3. The via conductor 601, the via conductor 602, and the via conductor 603 are arranged linearly.

The sixth conductor layer L6, the seventh conductor layer L7, the eighth conductor layer L8, the ninth conductor layer L9, and the tenth conductor layer L10 are solid patterns. The first conductor layer L1 includes a via conductor 601 including a via land L1l and a solid pattern L1S including an opening L1H. The second conductor layer L2 includes a via conductor 602 including a via land L2l and a solid pattern L2S including an opening L2H. The third conductor layer L3 includes a via conductor 603 including a via land L3l and a solid pattern L3S including an opening L3H. The fourth conductor layer L4 includes a land L41, a signal line L4Si, and a solid pattern L4S. The fifth conductor layer L5 is composed of a solid pattern L2S having an opening L5H. FIG. 1B is a plan view of the fourth conductor layer L4 and the fifth conductor layer L5 as viewed from the F-plane side. The opening L5H of the solid pattern L5S is formed concentrically with the land L4l connected to the bottom of the bottom via conductor 603 of the stacked vias 60FF and 60FS. The fourth conductor layer L4 includes a land L4l and a signal line L4Si connected to the land L4l.

As shown in FIG. 1A, the diameter D1 of the bottoms of the via conductors 601, 602, 603 is 75 μm. The lands L2l, L3l, L4l connected to the bottoms of the via conductors 601, 602, 603 have a diameter D2 of 150 μm. The distances from the lands L2l, L3l, L4l connected to the bottoms of the via conductors 601, 602, 603 to the openings L2H, L3H, L4H are 150 μm. The distance from the land L1l of the first conductor layer L1 to the opening L1H is 150 μm. The opening L5H of the fifth conductor layer L5 is formed with a radius larger by 150 μm than the radius of the land L4l. The thickness (the distance from the upper surface of the second conductor layer L2 to the lower surface of the first conductor layer L1) t2 of the first resin insulating layer R1 is 60 μm. The thicknesses of the other resin insulation layers are also equal to the thickness of the second resin insulation layer. The thickness t1 of the first conductor layer to the tenth conductor layer is 25 μm.

The solid pattern L5S of the fifth conductor layer provided with the land L41 and the opening L5H is provided so as to face the land L41 and the one resin insulating layer R4.

The first resin insulating layer to the ninth resin insulating layer include inorganic particles such as glass and an epoxy thermosetting resin. Each resin insulating layer may further include a core material such as a glass cloth. The dielectric constants of the first resin insulating layer to the ninth resin insulating layer, the upper solder resist layer SRU, and the lower solder resist layer SRD are in the range of 3.6 to 4.3.

In the printed wiring board according to the embodiment, the signal transmission direction changes by 90 degrees between the stacked vias 60FF and 60FS that send signals in the vertical direction and the signal line L4Si that sends signals in the horizontal direction, so the tack vias 60FF and 60FS. Signal reflection easily occurs at the land L4l connected to the bottom of the lowermost via conductor 603. A solid pattern L5S is disposed below the land L4l connected to the bottom of the bottom via conductor 603 of the stacked vias 60FF and 60FS, and an opening L5H concentric with the land L4l is provided in the solid pattern L5S corresponding to the land L4l. It has been. No stray capacitance is generated between the land L41 and the solid pattern L5S by the opening L4H. For this reason, the impedance of the stacked vias 60FF and 60FS is increased, impedance matching with the wiring is taken, and attenuation of a high-frequency signal can be reduced.

It is desirable that the diameter D3 of the opening L5H of the fifth conductor layer and the diameter D2 of the land L4l are not less than 2 times and not more than 3 times. If it is less than twice, stray capacitance is generated between the land and the solid pattern, and impedance matching is difficult to obtain. In the case of more than 3 times, the effect of increasing the impedance does not increase. In addition, the area of the solid pattern is reduced.

As described above, in the printed wiring board according to the embodiment, the via diameter and the land diameter are reduced as compared with the printed wiring board described above with reference to FIG. 9, and the insulation distance between the land and the opening is increased. That is, in the configuration in FIG. 9, the via bottom diameter was 100 μm, the land diameter was 250 μm, and the insulation distance was 100 μm. In contrast, in the printed wiring board of the embodiment, the via bottom diameter is set to 75 μm, the land diameter is set to 150 μm, and the insulation distance is set to 150 μm.

FIG. 8 shows the result of simulating the insertion loss [dB] of the printed wiring board of via diameter / land diameter: 75/150 shown in FIG. 1A and 100/250 shown in FIG. FIG. 8A shows a case where the frequency is 5 GHz, and FIG. 8B shows a case where the frequency is 10 GHz. When the frequency is 5 GHz, -0.34 is a loss in the wiring portion, and 75/150 and 100/250 have the same value. The loss of -0.05 at 100/250 is a value at which impedance mismatch occurs in the via conductor. It accounts for 13% of the total loss. The loss of -0.02 at 75/150 is a value in which impedance irregularity is taken in the via conductor. It accounts for 6% of the total loss. When the frequency is 10 GHz, -0.58 is a loss in the wiring portion, and 75/150 and 100/250 have the same value. The loss of -0.10 at 100/250 is a value at which impedance mismatch occurs in the via conductor. It accounts for 15% of the total loss. The loss of −0.04 at 75/150 is a value in which impedance irregularity is taken in the via conductor. It accounts for 7% of the total loss. The insertion loss can be improved by 7% by optimizing the via diameter / land diameter.

The diameter of the bottom of the via conductor is 65 to 85 μm, and the impedance mismatch can be reduced by setting the diameter of the land connected to the via conductor to be 130 to 170 μm. Similarly, impedance mismatch can be reduced by providing a gap between the land connected to the bottom of the via conductor and the solid pattern provided around the land of 130 μm or more.

FIG. 4 is a chart showing the result of simulating the impedance Z0. The vertical axis represents impedance Z0, and the horizontal axis represents time [ps]. In the figure, a dotted line indicates a via diameter / land diameter: 100/250 shown in FIG. 9, and a printed wiring board in which no opening is provided in a solid pattern in the lower layer of the land connected to the bottom of the lowest via conductor of the stacked via (Before improvement) is shown, and the solid line shows the case where the configuration of the embodiment is adopted (after improvement). The decrease in impedance Z0 at 0 to 30 [ps] and 130 to 150 [ps] represents a decrease in impedance at the stacked via portion. The stable impedance Z0 at 30 to 130 [ps] represents the wiring portion. In the configuration of the embodiment represented by the solid line, the impedance reduction in the stacked via portion at 0 to 30 [ps] and 130 to 150 [ps] is improved to about 1/2 to 1/3.

FIG. 5 is a chart showing the result of simulating the transmission loss due to the stacked via portion. The vertical axis represents the insertion loss [dB], and the horizontal axis represents the frequency [GHz]. In the figure, the dotted line represents the case of the configuration shown in FIG. 9 (before improvement), and the solid line represents the case where the configuration of the embodiment is adopted (after improvement). At 5 [GHz] (before improvement), a loss of 0.39 [dB] was produced, while (after improvement) was improved to a loss of 0.36 [dB]. At 10 [GHz] (before improvement), a loss of 0.68 [dB] was obtained, whereas (after improvement) was improved to a loss of 0.62 [dB].

[First Modification of Embodiment]
FIG. 2 shows a configuration of a printed wiring board according to a first modification of the embodiment.
A printed wiring board according to a modified example of the embodiment includes resin insulating layers R1, R2, R3, R4 and conductor layers L1, L2, L3, L4 on the first surface F side of the fifth resin insulating layer R5 constituting the core substrate. Is built-up laminated, and resin insulation layers R6, R7, R8, R9 and conductor layers L7, L8, L9, L10 are built-up laminated on the second surface S side. A fifth conductor layer L5 is formed on the first surface side of the fifth resin insulating layer R5, and a sixth conductor layer L6 is formed on the second surface side. The through-hole conductor 36 penetrates the fourth resin insulating layer R4, the fifth resin insulating layer R5, and the sixth resin insulating layer R6. In the first conductor layer L1, a via conductor 601 penetrating the first resin insulation layer R1 is formed. A via conductor 602 that penetrates through the second resin insulation layer R2 is formed in the second conductor layer L2. A via conductor 603 that penetrates through the third resin insulation layer R3 is formed in the third conductor layer L3. The via conductors 601, 602, and 603 are linearly arranged as a stacked via 60F. The bottom of the via conductor 603 is connected to a land L4l formed in the fourth conductor layer L4. The land L4l is connected to the through-hole land L4L via the signal line L4Si. On the second surface S side of the through-hole conductor 36, a through-hole land L7L is formed as a seventh conductor layer. On the through-hole land L7L, a via conductor 608 penetrating the seventh resin insulating layer R7 is formed in the eighth conductor layer L8. In the ninth conductor layer L9, a via conductor 609 penetrating the eighth resin insulating layer R8 is formed. A via conductor 6010 penetrating through the ninth resin insulation layer R9 is formed in the tenth conductor layer L10. The via conductors 608, 609, and 6010 are linearly arranged as a stacked via 60S.

In the first modification of the embodiment, a signal is transmitted between the electronic component connected to the first surface F of the printed wiring board and the electronic component connected to the second surface S. Also in the first modification of the embodiment,
A solid pattern L5S is disposed below the land L41 connected to the bottom of the via conductor 603 at the bottom of the stacked via 60F, and an opening L5H concentric with the land L41 is provided in the solid pattern L5S corresponding to the land L41. A solid pattern L6S is disposed below the land L71 connected to the bottom of the via conductor 608 at the bottom of the stacked via 60S, and an opening L6H concentric with the land L71 is provided in the solid pattern L6S corresponding to the land L71. The stray capacitance is not generated between the land L41 and the solid pattern L5S by the opening L5H. No stray capacitance is generated between the land L71 and the solid pattern L6S due to the opening L6H. For this reason, the impedance of the stacked vias 60F and 60S is increased, impedance matching with the wiring is taken, and attenuation of high frequency signals can be reduced.

[Second Modification of Embodiment]
FIG. 3A shows a configuration of a printed wiring board according to a second modification of the embodiment.
The printed wiring board according to the second modification of the embodiment includes resin insulating layers R1, R2, R3, R4 and conductor layers L1, L2, L3, L4 on the first surface F side of the fifth resin insulating layer R5 constituting the core substrate. Is built-up laminated, and resin insulation layers R6, R7, R8, R9 and conductor layers L7, L8, L9, L10 are built-up laminated on the second surface S side. A fifth conductor layer L5 is formed on the first surface side of the fifth resin insulating layer R5, and a sixth conductor layer L6 is formed on the second surface side. The through-hole conductor 36 penetrates the fourth resin insulating layer R4, the fifth resin insulating layer R5, and the sixth resin insulating layer R6.

In the printed wiring board of the second modified example of the embodiment, an opening is formed in the solid pattern L5S facing the land L41 formed on the fourth conductor layer L4 connected to the bottom of the lowermost via conductor 603 of the linear stacked via 60F. L5H is formed. FIG. 3B is a plan view of the fourth conductor layer L4 and the fifth conductor layer L5 as viewed from the first surface F side. The openings L5H of the solid pattern L5S are formed concentrically with respect to the lands L41 formed on the fourth conductor layer L4. An opening L6H is formed in the solid pattern L6S opposed to the land L7l formed in the seventh conductor layer L7 connected to the bottom of the lowermost via conductor 608 of the linear stacked via 60S. FIG. 3D is a plan view of the seventh conductor layer L7 and the sixth conductor layer L6 as viewed from the second surface S side. The openings L6H of the solid pattern L6S are formed concentrically with respect to the lands L71 formed in the seventh conductor layer L7.

FIG. 3C is a plan view of the third conductor layer L3 and the fourth conductor layer L4 as viewed from the first surface F side. In the second modification of the embodiment, the third conductor layer L3, which is the upper layer of the through-hole land L4L on the first surface F side of the through-hole conductor, is provided with an opening L3h concentric with the through-hole land in the solid pattern L3S. Thus, stray capacitance is prevented from occurring between the through-hole land L4L and the solid pattern L3S. Similarly, the solid pattern L2S of the second conductor layer L2 on the upper layer of the third conductor layer L3 is provided with an opening L2h concentric with the through hole land, and stray capacitance is generated between the through hole land L4L and the solid pattern L2S. Is prevented.

In the eighth conductor layer L8, which is the upper layer of the through hole land L7L on the second surface S side of the through hole conductor, the solid pattern L8S is provided with an opening L8h concentric with the through hole land L7L. Further, the ninth conductor layer L9, which is the upper layer of the eighth conductor layer, is also provided with an opening L9h concentric with the through hole land in the solid pattern L9S, and floats between the through hole land L7L and the solid patterns L8S and L9S. It prevents the generation of capacity.

In the printed wiring board according to the second modification of the embodiment, the solid pattern L5S facing the land L4l formed on the fourth conductor layer L4 connected to the bottom of the lowermost via conductor 603 of the linear stacked via 60F is used. An opening L5H is formed. An opening L6H is formed in the solid pattern L6S opposed to the land L7l formed in the seventh conductor layer L7 connected to the bottom of the lowermost via conductor 608 of the linear stacked via 60S. The stray capacitance is not generated between the land L4l of the fourth conductor layer and the solid pattern L5S by the opening L5H, and the stray capacitance is not generated between the land L71 of the seventh conductor layer and the solid pattern L6S of the sixth conductor layer by the opening L6H. Does not occur. For this reason, the impedance of the stacked vias 60F and 60S is increased, impedance matching with the wiring is taken, and attenuation of high frequency signals can be reduced.

FIG. 6 is a chart showing the result of simulating the impedance Z0. The vertical axis represents impedance Z0, and the horizontal axis represents time [ps]. In the drawing, a dotted line represents a case where a solid pattern opening corresponding to a through-hole land and a solid pattern opening corresponding to a land at the bottom of a stacked via are not provided (before improvement), and a solid line represents a second modification of the embodiment. The case of adopting the configuration (after improvement) is shown. The decrease in impedance Z0 at 0 to 20 [ps] represents a decrease in impedance in the stacked via portion. The stable impedance Z0 at 30 to 125 [ps] represents the wiring portion. The decrease in impedance Z0 at 125 to 160 [ps] represents a decrease in impedance at the through-hole portion. In the configuration of the second modified example of the embodiment represented by the solid line, the decrease in impedance in the stacked via portion at 0 to 20 [ps] is improved to about 1/3. Moreover, the drop in impedance at the through-hole portion at 125 to 160 [ps] is improved to about 1/3.

FIG. 7 is a chart showing the results of simulating transmission loss due to stacked via portions and through-hole conductors. The vertical axis represents the insertion loss [dB], and the horizontal axis represents the frequency [GHz]. In the drawing, a dotted line represents a case where a solid pattern opening corresponding to a through-hole land and a solid pattern opening corresponding to a land at the bottom of a stacked via are not provided (before improvement), and a solid line represents a second modification of the embodiment. The case of adopting the configuration (after improvement) is shown. At 5 [GHz] (before improvement), a loss of 0.61 [dB] was obtained, whereas (after improvement) was improved to a loss of 0.39 [dB]. At 10 [GHz] (before improvement), a loss of 1.11 [dB] was obtained, whereas (after improvement) was improved to a loss of 0.67 [dB].

L1-L10 Conductor layer R1-R9 Resin insulation layer L5S Solid pattern L5H Opening L4l Land 60FF Stacked via 601 602 603 Via conductor

Claims (9)

A printed wiring board comprising a conductor layer and a resin insulation layer, and a via conductor penetrating the resin insulation layer,
A solid pattern is arranged on the lower layer of the land connected to the bottom of the bottom via conductor of the stacked via in which a plurality of the via conductors connected to the signal line are overlapped in a straight line,
Corresponding to the land, the solid pattern is provided with an opening concentric with the land. The printed wiring board according to claim 1,
The diameter of the concentric opening is 2 to 3 times the diameter of the land. The printed wiring board according to claim 1,
The land and the solid pattern are provided so as to face the land via a single resin insulating layer. The printed wiring board according to claim 1,
The stacked via is used for signal transmission between a pair of electronic components mounted on the same surface of a printed wiring board. The printed wiring board according to claim 1,
The stacked via is used for signal transmission between a pair of electronic components mounted on the front and back surfaces of a printed wiring board. The printed wiring board according to claim 5,
The printed wiring board includes a through-hole conductor connected to the stacked via, and has a first surface and a second surface opposite to the first surface,
A solid pattern is disposed on the first surface of the land on the first surface side of the through-hole conductor, and a solid pattern is disposed on the second surface of the land on the second surface side of the through-hole conductor,
Corresponding to the land on the first surface side of the through-hole conductor, a solid pattern on the first surface is provided with an opening concentric with the land on the first surface side,
Corresponding to the land on the second surface side of the through-hole conductor, an opening concentric with the land on the second surface side is provided in the solid pattern on the second surface side. The printed wiring board according to claim 1,
The resin insulating layer has a dielectric constant of 3.6 to 4.3. The printed wiring board according to claim 1,
The diameter of the bottom of the via conductor is 65 to 85 μm,
The diameter of the land connected to the bottom of the via conductor is 130 to 170 μm. The printed wiring board according to claim 7,
The gap between the land connected to the bottom of the via conductor and the opening of the solid pattern provided around the land is 130 μm or more.

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