KR102166048B1 - Multilayer circuit board - Google Patents

Abstract

The embodiment of the present invention can solve the problem of impedance discontinuity between patterns connected through vias in a multilayer circuit board, and impedance matching between patterns connected through the vias can be achieved by increasing the impedance by cutting the side of the via. In addition, it is possible to provide a multilayer circuit board capable of achieving impedance matching between patterns connected through the via by reducing the impedance of the via by forming irregularities on the inner side of the via.

Description

Multilayer circuit board {MULTILAYER CIRCUIT BOARD}

The present invention relates to a multilayer circuit board.

A multilayer circuit board is a multilayer circuit board in which a plurality of films on which a wiring pattern is formed is stacked, and may be composed of a printed circuit board (PCB), and the printed circuit board provides electrical wiring between electronic components and is used in circuit design. As a printed wiring board formed on the basis of the insulating layer, it is also referred to as a PCB board, a printed circuit board, or a printed wiring board.

The term printed circuit board (PCB) is derived from a variety of configurations, for example, a FR4 substrate, a metal core printed circuit board (MCPCB), a cast polymer resin cross-linked using ultraviolet radiation. It is used to define a circuit board selected from the formed substrate or other circuit board configurations that can be easily understood by a person in the present technical field.

In general, such a printed circuit board comprises a required circuit pattern by attaching a copper thin plate to the surface of a phenol resin insulating layer or an epoxy resin insulating layer, etc., and then etching the copper thin plate according to the circuit pattern. Manufactured by a method of densely mounting various electronic components such as capacitors and resistors.

Printed circuit boards are classified into single-sided boards, double-sided boards, and multi-layered boards according to the number of circuit layers and insulating layers, and the larger the number of layers, the better the mounting power of electronic components and used for high-precision products.

1 is a diagram showing a pattern structure of a conventional multilayer circuit board.

Referring to FIG. 1, a conventional multilayer circuit board 1 includes a first pattern 10 disposed on a first substrate, a second pattern 20 disposed on a second substrate disposed under the first substrate, and And a via hole 30 connecting the first and second patterns 10 and 20.

2 is a graph showing an impedance relationship between patterns formed on a conventional multilayer circuit board and via holes.

The graph of FIG. 2 shows the impedance change from point A to point B and point C of FIG. 1.

Referring to FIGS. 1 and 2, if the wiring width of the first pattern 10 is constant from point A to point B, the impedance has a constant value. In addition, if the second pattern 20 also has a constant wiring width from point B to point C, the impedance has a constant value. However, at point B, you can see that the impedance decreases rapidly.

This is because the impedance in the via hole 30 is smaller than that of the first and second patterns 10 and 20. Such a change in impedance between patterns on the conventional multilayer circuit board 1 may cause a rapid change in the via hole 30, and impedance matching is not performed due to such a sudden change in impedance, resulting in deterioration of signal quality due to various noises. .

In particular, in high-speed signal transmission, impedance mismatch becomes a bigger problem.

The above-described impedance change appeared as a phenomenon of a rapid decrease in impedance in the via hole 30, but is not limited thereto, and may also appear as a phenomenon in which the impedance increases rapidly in the via hole 30, and may have the above-described problems as it is. .

In recent years, with the miniaturization of printed circuit boards and high speed transmission of signals, impedance matching has emerged as a more important problem, and many studies are being conducted to prevent rapid changes in impedance between patterns on a multilayer circuit board.

An embodiment of the present invention provides a multilayer circuit board capable of solving an impedance discontinuity problem between patterns connected through vias in a multilayer circuit board.

An embodiment of the present invention may provide a multilayer circuit board capable of achieving impedance matching between patterns connected through the vias by increasing the impedance by cutting the side of the via.

An embodiment of the present invention may provide a multilayer circuit board capable of achieving impedance matching between patterns connected through the via by reducing the impedance of the via by forming irregularities on the inner surface of the via.

A multilayer circuit board according to an embodiment of the present invention is a multilayer circuit board in which one or more films are stacked, and the multilayer circuit board includes a first pattern and a second pattern, and a first via connecting the first and second patterns. And the first and second patterns are formed on one side of the first via, and the other side of the first via has a cross-sectional shape.

In the multilayer circuit board according to an embodiment of the present invention, the first pattern is formed on an upper surface of the film, and the second pattern is formed on a rear surface of the film.

In the multilayer circuit board according to an embodiment of the present invention, one side of the first via has a curved shape.

In the multilayer circuit board according to an embodiment of the present invention, the multilayer circuit board is plated on the inside of the first via to electrically connect the first and second patterns.

In the multilayer circuit board according to an embodiment of the present invention, the first via has a semi-cylindrical shape.

In the multilayer circuit board according to an embodiment of the present invention, the inner surface of the first via has an uneven shape.

In the multilayer circuit board according to the embodiment of the present invention, a multilayer circuit board in which a plurality of circuits are stacked, the multilayer circuit board includes a first pattern on a first substrate, a second pattern on a second substrate, and the first and second patterns. A multilayer circuit board comprising a first via connecting a pattern, and an inner surface of the first via having an uneven shape.

In the multilayer circuit board according to an embodiment of the present invention, the first and second patterns are formed on one side of the first via, and the other side of the first via has a cross-sectional shape.

In the multilayer circuit board according to an embodiment of the present invention, the multilayer circuit board is plated on the inside of the first via to electrically connect the first and second patterns.

In the multilayer circuit board according to the embodiment of the present invention, the multilayer circuit board connects the third pattern formed on the first substrate to the fourth pattern formed on the second substrate, and the third pattern and the fourth pattern. A multilayer circuit board further comprising a second via, wherein the third and fourth patterns are formed on one side of the third via, and the other side of the second via has a cross-sectional shape.

In the multilayer circuit board according to an embodiment of the present invention, the first and third patterns are differential signal transmission lines.

In the multilayer circuit board according to an embodiment of the present invention, the other side of the first via corresponds to the other side of the second via.

The embodiment of the present invention can solve the problem of impedance discontinuity between patterns connected through vias in a multilayer circuit board, and impedance matching between patterns connected through the vias can be achieved by increasing the impedance by cutting the side of the via. In addition, it is possible to provide a multilayer circuit board capable of achieving impedance matching between patterns connected through the via by reducing the impedance of the via by forming irregularities on the inner side of the via.

1 is a diagram showing a pattern structure of a conventional multilayer circuit board.
2 is a graph showing an impedance relationship between patterns formed on a conventional multilayer circuit board and via holes.
3 and 4 are views illustrating patterns and via holes on a multilayer circuit board according to an exemplary embodiment of the present invention.
5 to 7 are diagrams showing a method of forming a pattern and a via on a multilayer circuit board according to the present invention.
8 is a schematic diagram showing the impedance relationship between first and second patterns and vias.
9 is a view showing a via according to a second embodiment of the present invention.
10 is a schematic diagram showing the impedance relationship between first and second patterns and vias.
11 is a view showing a via according to a third embodiment of the present invention.
12 is a diagram illustrating a method of forming a via according to the second and third embodiments of the present invention.
13 is a diagram showing an arrangement structure of patterns and via holes in a conventional difference signal transmission, and FIG. 14 is a view showing an arrangement structure of patterns and vias according to difference signal transmission according to an embodiment of the present invention.
15 is a diagram showing a method of forming a multilayer circuit board according to a fourth embodiment of the present invention.

Hereinafter, with reference to the drawings of a multilayer circuit board according to an embodiment of the present invention will be described in detail. The following embodiments are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Throughout the specification, the same reference numbers indicate the same elements.

3 and 4 are views illustrating patterns and via holes on a multilayer circuit board according to an exemplary embodiment of the present invention.

Referring to FIGS. 3 and 4, a multilayer circuit board 100 on which one or more films of the present invention may be stacked and formed is a first pattern 110 and a second substrate formed on the first substrate 101. A second pattern 130 formed on 103 and a via 150 electrically connecting the first and second patterns 110 and 130 may be included.

A first pattern 110 may be formed on one side of the via 150, and the other side of the via 150 may have a planar shape. That is, the via 150 may have a semi-cylindrical shape.

The via 150 may include first and second surfaces 153 and 155. The second surface 155 is a surface corresponding to the first and second patterns 110 and 130 and may have a round shape or a curved shape. In addition, the first surface 153 on the other side of the via 150 may have a planar shape.

The first and second patterns 110 and 130 may be electrically connected to the inner surface of the via 150 through a plating treatment.

5 to 7 are diagrams showing a method of forming a pattern and a via on a multilayer circuit board according to the present invention.

Referring to FIG. 5, an electrical path for connecting the first and second patterns 110 and 130 by forming first and second patterns 110 and 130 on a multilayer substrate and forming a via hole 151 To form.

Although not shown in the drawing, in order to prevent oxidation of the first and second patterns 110 and 130, a suitable protective film made of a solder resist or the like may be coated.

The first and second patterns 110 and 130 may be formed on one side of the via hole 151.

6 and 7, FIG. 6 is a cross-sectional view of FIG. 5.

The via hole 151 shown in FIG. 5 may be cut through the other side of the via hole 151 using a drill 170 to form the via 150.

The via hole 151 of FIG. 5 has a cylindrical hole, and thus is referred to as a via hole 151, and the via 150 of FIGS. 6 and 7 has one side of the via hole 151 cut to form a semi-cylindrical hole. Since it is provided, it was separately referred to as a via 150.

The inner side of the via 150 is filled with a conductive thermoplastic resin containing a conductive material made of metal particles such as gold, silver, copper, nickel, lead, etc., so that the first and second patterns 110 and 130 are electrically Make the connection possible.

8 is a schematic diagram showing the impedance relationship between first and second patterns and vias.

In order to represent the impedance relationship between the first and second patterns 110 and 130 and the vias 150 on the multilayer circuit board 100 manufactured in the above-described manner, the semi-cylindrical via 150 is used as a flat pattern. Expressed assuming.

The left schematic diagram of FIG. 8 is a schematic diagram of the first and second patterns 110 and 130 and the via hole 151 of FIG. 5, and the right schematic diagram of FIG. 8 is the first and second patterns 110 and 130 of FIG. 6 or 7. ) And it is a schematic diagram of the via 150.

As can be seen in FIG. 8, when the via 150 is formed rather than the via hole 151, it can be seen that the difference in wiring width between the first and second patterns 110 and 130 and the pattern of the via 150 is not large. have. That is, according to the embodiment of the present invention, it can be seen that impedance discontinuity of the multilayer circuit board 100 can be minimized.

The above-described embodiment of the present invention can be applied when the impedance of the first and second patterns 110 and 130 is larger than the impedance of the via hole 151 of FIG. 5. At this time, one side of the via hole 151 of FIG. 5 is cut to form the via 150 of FIG. 6, and the area of the inner side of the via 150 is smaller than the area of the inner surface of the via hole 151 of FIG. Since it has an area, it is possible to have a higher impedance as a result, and accordingly, the impedances of the first and second patterns 110 and 130 can be matched.

As described above, the patterns 110 and 130 according to the exemplary embodiment of the present invention are formed in the side area of the via 150 rather than in the center area, and the other side area of the via 150 is cut to be inside the via 150. The area of the copper foil to be filled can be reduced.

9 is a view showing a via according to a second embodiment of the present invention.

Referring to FIG. 9, the via 150 according to the second embodiment may have an uneven shape on an inner side thereof.

As such, since the inner surface of the via 150 has an uneven shape, the area of the inner surface of the via 150 may be increased.

10 is a schematic diagram showing the impedance relationship between first and second patterns and vias.

In order to represent the impedance relationship between the first and second patterns 110 and 130 and the vias 150 on the multilayer circuit board 100 manufactured in the above-described manner, the semi-cylindrical via 150 is used as a flat pattern. Expressed assuming.

The left schematic diagram of FIG. 10 is a schematic diagram of the first and second patterns 110 and 130 and the via hole 151 of FIG. 5, and the right schematic diagram of FIG. 10 is the first and second patterns 110 and 130 and vias of FIG. It is a schematic diagram of (150).

The via 150 may be applied when the impedance of the first and second patterns 110 and 130 is higher than the impedance of the via 150. By increasing the area of the inner surface of the via 150, the impedance of the first and second patterns 110 and 130 may be matched.

In this way, by making the inner surface of the via 150 to have an uneven shape, the area of the copper foil on the inner surface of the via 150 may be increased.

According to the above-described first and second embodiments of the present invention, signal transmission by minimizing impedance discontinuities by enabling impedance control with only a simple process of cutting the side of the via 150 or forming irregularities on the inner side. Can improve quality.

11 is a view showing a via according to a third embodiment of the present invention.

Referring to FIG. 11, the via 150 according to the third embodiment may have an uneven shape on an inner side.

The via 150 may have a shape in which one side of the via 150 of FIG. 9 is cut so that one side has a planar shape like the via 150 of FIG. 6.

In the third embodiment, by adding a concave-convex shape to the inner surface of the via 150 (FIG. 6) described in the first embodiment, it is possible to precisely control the impedance, and accordingly, the first and second patterns 110 and 130 Impedance matching between vias 150 may be performed.

12 is a diagram illustrating a method of forming a via according to the second and third embodiments of the present invention.

Referring to FIG. 12, a via hole is formed on the multilayer circuit board 100, and a via 150 according to the second embodiment or the third embodiment is formed by forming irregularities in a portion indicated by a dotted line using a drill or the like. can do.

The number and size of dotted lines indicated in the drawing may vary according to impedance matching of the first and second patterns 110 and 130 and the vias 150.

13 is a diagram showing an arrangement structure of patterns and via holes in a conventional difference signal transmission, and FIG. 14 is a view showing an arrangement structure of patterns and vias according to difference signal transmission according to an embodiment of the present invention.

The differential signal transmission method is used to transmit signals that are resistant to noise.

The differential signal method uses a differential mode signal of two input signals, and since the common mode signal corresponds to noise, the common mode signal is used to remove it.

At this time, it is preferable to narrow the gap between the two patterns so that the patterns are simultaneously affected by noise.

Referring to FIG. 13, a structure of the conventional patterns 21, 23, 25, 27 and the via holes 31, 33 is described. The patterns 21, 23, 25, 27 are located in the center of the via holes 31 and 33. It is arranged to correspond to the area.

Among the patterns 21, 23, 25, 27, the first and second patterns 21 and 23 are patterns formed in parallel on the first substrate, and the third and fourth patterns 25 and 27 are 2 It is a pattern formed side by side on a substrate.

The first and third patterns 21 and 25 are electrically connected to each other through a first via hole 31, and the second and fourth patterns 23 and 27 are electrically connected to each other through a second via hole 33 do.

Since the conventional via holes 31 and 33 have holes, the distance between the two patterns is further increased as shown in FIG. 13 in the position where the via holes 31 and 33 are formed. That is, the gap A between the first and second patterns 21 and 23 may be narrower than the gap between the first and second via holes 31 and 33.

As the distance between the first and second via holes 31 and 33 becomes further as described above, there is a limitation in miniaturization of the multilayer circuit board, and there is a problem in that noise is weak because the spacing between patterns is not constant in the differential signal transmission method.

A multilayer circuit board 100 according to a fourth embodiment of the present invention that solves this problem will be described with reference to FIG. 14.

Referring to FIG. 14, when looking at the structures of the patterns 210, 230, 250, 270 and the vias 310, 330, the patterns 210, 230, 250, and 270 correspond to one area of the vias 310 and 330. It is arranged as much as possible.

Among the patterns 210, 230, 250, 270, the first and second patterns 210 and 230 are patterns that may be formed in parallel on the first substrate 110, and the third and fourth patterns 250 , 270 is a pattern that may be formed in parallel on the second substrate 130.

The first and third patterns 210 and 250 are electrically connected to each other through a first via hole 310, and the second and fourth patterns 203 and 270 are electrically connected to each other through a second via hole 330 do.

Since the via holes 310 and 330 according to the fourth embodiment of the present invention have a cross-sectional shape on the other side, the gap between the two patterns can be narrowed as shown in FIG. 14 at the location where the via holes 310 and 330 are formed. . That is, the gap A between the first and second patterns 210 and 230 may be matched at a level similar to the gap between the first and second via holes 310 and 330.

By matching the spacing between the first and second via holes 310 and 330 and the spacing between the patterns as described above, miniaturization of the multilayer circuit board 100 can be realized, and noise by maintaining the spacing between the patterns in the differential signal transmission method Has a strong effect on

15 is a diagram showing a method of forming a multilayer circuit board according to a fourth embodiment of the present invention.

Referring to FIG. 15, first and second patterns 210 and 230 are formed on a first substrate 101 on a multilayer circuit board 100, and a first pattern 210 and a second pattern 210 are formed on the second substrate 103. A third pattern 250 connected through the via 300 and a fourth pattern 270 connected through the second pattern 230 and the via 150 are formed.

And by cutting the dotted line portion of the via 300, that is, the middle region, by electrically separating the first and third patterns 210 and 250 from the second and fourth patterns 230 and 270, one side is It is possible to form two vias 300 of a semi-cylindrical shape having a round shape and a planar shape on the other side. Thus, the gap between the two patterns can be narrowed, and an effect of preventing a sudden decrease in impedance in the via 300 can be prevented. At this time, at least one unevenness may be formed on the inner surfaces of each of the two vias 300 for precise impedance matching.

In forming the via 300, it has been described that one via 300 can be formed and two vias 310 and 330 can be formed by cutting it, but the present invention is not limited thereto, and the two vias are used in each pattern. The first and second vias 310 and 330 of FIG. 14 may be formed by forming corresponding to and cutting each of the vias.

In the above-described fourth embodiment, the differential signal transmission method is described as an example, but the effect according to the embodiment of the present invention is not limited thereto, and it is necessary to narrow the spacing between patterns in order to reduce the size of the substrate. Even when there is a space limitation in forming the vias of the present invention, by forming the vias 150 according to the embodiment of the present invention, the total number of vias 150 can be reduced, and the spacing between patterns can also be reduced.

As described above, for the via 150 and the irregularities formed on the inner side of the via 150 according to the embodiment of the present invention, a multi-axis drilling equipment of a CNC method or a laser drill may be used.

In particular, by using a laser drill when forming irregularities, the area of the inner surface of the via 150 can be controlled to achieve precise impedance matching.

Meanwhile, it has been described that the first pattern 110 is formed on the first substrate 101 and the second pattern 130 is formed on the second substrate 103, but is not limited thereto. A pattern 110 is formed, a second pattern 130 is formed on the lower surface of the substrate, and a via 150 is formed on the substrate to electrically connect the first and second patterns 110 and 130 It is possible, and at least one or more substrates may be further included between the first and second substrates 101 and 103.

In the detailed description of the present invention described above, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those of ordinary skill in the relevant technical field of the present invention described in the claims to be described later It will be understood that various modifications and changes can be made to the present invention without departing from the spirit and technical scope. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10. The first pattern
20. The second pattern
21. The first pattern
23. The second pattern
25. Third Pattern
27. The fourth pattern
30. Via Hole
101. First substrate
103. Second substrate
110. The first pattern
130. Second Pattern
150. Via
153. Page 1
155. second page
151. Via Hole
170. Drill
210. The first pattern
230. The second pattern
250. Third Pattern
270. The fourth pattern
300. Via
310. First Via
330. Second Via

Claims (14)

delete delete delete delete delete delete A multilayer circuit board in which a plurality of circuits are stacked,
The multilayer circuit board includes a first pattern on a first substrate, a second pattern on a second substrate, and a first via connecting the first and second patterns,
The first and second patterns are formed on one side of the first via,
One side of the first via has a round shape, and the other side of the first via has a planar shape,
The multilayer circuit board further includes a third pattern formed on the first substrate, a fourth pattern formed on the second substrate, and a second via connecting the third pattern and the fourth pattern,
The third and fourth patterns are formed on one side of the second via,
One side of the second via has a round shape, and the other side of the second via has a planar shape,
A multilayer circuit board disposed so that the other side of the first via having a planar shape and the other side of the second via having a planar shape face each other. delete The method of claim 7,
A multilayer circuit board that is plated on the inside of the first via to electrically connect the first and second patterns. delete The method of claim 7,
The first and third patterns are differential signal transmission lines. delete delete The method of claim 7,
A multilayer circuit board having an uneven shape on the inner side of the first via.

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