JP2017011007A - Semiconductor device for power, and manufacturing method of semiconductor device for power - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress occurrence of discharge between a gate pad and an edge of a semiconductor chip during voltage resistance measurement while securing a large effective area.SOLUTION: A wiring electrode 42 connects a gate electrode 50 and a test pad electrode 41 with each other. A gate resistance layer 51 connects a gate pad electrode 33 and at least one of the test pad electrode 41 and the wiring electrode 42 with each other. A protective insulation film 65 partially covers each of a second electrode 32 and the gate pad electrode 33 and exposes a gate pad part PG of the gate pad electrode 33 and a test pad part PT of the test pad electrode 41. The protective insulation film 65 includes a first inner peripheral end ES on the second electrode 32 and a second inner peripheral end EG on the gate pad electrode. A minimum distance LG between an outer peripheral end EP and the second inner peripheral end EG is equal to or longer than a minimum distance LS between the outer peripheral end EP and the first inner peripheral end ES.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power semiconductor device and a method for manufacturing a power semiconductor device, and more particularly to a power semiconductor device having a gate electrode and a method for manufacturing a power semiconductor device having a gate electrode.

  Semiconductor switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as power semiconductor devices. In a typical use of the switching element, the higher the operation speed, that is, the higher the switching frequency, the lower the power loss. In particular, a unipolar element such as a MOSFET can increase the operation speed although it is inferior in the withstand voltage compared to a bipolar element such as an IGBT. In recent years, silicon carbide (SiC), which is advantageous for securing a withstand voltage, has begun to be used as a semiconductor material. As a result, a unipolar element can be used instead of a bipolar element even in a high withstand voltage region of about 600 V to 3.3 kV. It is becoming possible. As a result, high-speed switching has become possible not only in the low voltage region but also in the high withstand voltage region. Therefore, the importance of appropriately performing the high-speed operation of the switching element has further increased.

  There is a power capacity as a basic performance of the switching element other than the withstand voltage. When power exceeding the power capacity of a single semiconductor chip is handled, a necessary power capacity can be ensured by connecting a plurality of semiconductor chips in parallel. In this case, it is desirable that no deviation occurs in the on / off timing of the switching element between the semiconductor chips. Actually, due to variations in element characteristics between semiconductor chips, there is also some variation in on / off timing. If this variation is large, an undesired oscillation phenomenon may occur particularly in high-speed operation. In order to suppress oscillation, a gate resistor is connected in series to a gate terminal as a terminal to which a switching control signal is input. It is preferable that the resistance value of the gate resistor is set to a minimum necessary size so that high-speed operation itself is not difficult.

  The gate resistor can be built in the semiconductor switching element. For example, according to Japanese Unexamined Patent Application Publication No. 2011-238690 (Patent Document 1), a resistance element that connects a gate terminal and a gate electrode is provided on a semiconductor substrate.

  As such a gate resistance, that is, a built-in gate resistance, for example, a gate resistance layer made of the same material as the gate electrode is provided. The gate resistance layer is arranged to connect a gate electrode for generating a gate electric field and a gate pad for applying a signal to the gate electrode. Note that a protective insulating film, which may also be called a passivation film, is generally provided on the surface of the semiconductor chip. For example, as disclosed in Japanese Patent Application Laid-Open No. 2012-244102 (Patent Document 2), an opening for exposing the electrode pad is provided in the protective insulating film.

  Since there are manufacturing variations in the thickness and resistivity of the gate resistance layer, the gate resistance value also varies among semiconductor chips. The variation in the gate resistance value is large between wafers used for manufacturing semiconductor chips, and particularly large between wafers in different production lots. When the variation in the gate resistance value is large, the variation in the on / off timing of the switching element also increases. As a result, oscillation easily occurs even when a gate resistor is provided. Therefore, in order to suppress the variation in gate resistance among semiconductor chips, it is necessary to measure the resistance value of the built-in gate resistance and select the semiconductor chip based on the result. That is, a test by measuring the gate resistance is necessary.

  Another important test for power semiconductor chips is the measurement of withstand voltage. Since the measurement of the withstand voltage is performed at a high voltage, a discharge may occur at the terminal portion of the semiconductor chip. According to Japanese Patent Application Laid-Open No. 2012-247196 (Patent Document 3), a semiconductor test jig intended to prevent discharge at a terminal portion is disclosed. This jig has an insulator provided so as to surround the probe pin in plan view. The probe pin comes into contact with the electrode formed on the subject, and the insulator comes into contact with the subject.

JP2011-238690A JP 2012-244102 A JP 2012-247196 A

  The measurement of the resistance value of the gate resistance built in the semiconductor chip requires a test pad electrically connected between the gate resistance layer and the gate electrode. At the time of measurement, a probe is applied to each of the test pad and the gate pad. In order to sufficiently secure the measurement accuracy of the gate resistance, it is necessary to cancel the contact resistance between the probe and the pad, and for that purpose, it is necessary to use a four-terminal measurement method. Therefore, each of the gate pad and the test pad needs to be large enough to receive two probes. Due to the presence of the relatively large test pad, the area of the region through which current flows, that is, the effective area, of the total area of the semiconductor chip may be reduced.

  In order to increase the effective area of the semiconductor chip, it is conceivable to devise the arrangement of gate pads and test pads. However, depending on these arrangements, during the withstand voltage measurement in which a high voltage is applied between the drain electrode (first electrode) and the source electrode (second electrode), between the gate pad and the edge of the semiconductor chip. In some cases, discharge may occur. Although this discharge can be suppressed by the jig disclosed in JP 2012-247196 A, there are cases where it is desired to suppress the discharge more reliably. In some cases, it is desired to perform measurement without using such a special jig.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to secure a large effective area between the gate pad and the edge of the semiconductor chip during withstand voltage measurement. It is an object of the present invention to provide a semiconductor device capable of suppressing the occurrence of discharge. Another object is to provide a semiconductor device having a simple configuration while ensuring a large effective area. Still another object is to provide a method of manufacturing a semiconductor device that can secure a large effective area. Still another object is to provide a method of manufacturing a semiconductor device capable of suppressing the occurrence of discharge between a gate pad and an edge of a semiconductor chip during withstand voltage measurement while ensuring a large effective area. That is.

  A power semiconductor device according to one aspect of the present invention includes a semiconductor substrate, a first electrode, a second electrode, a gate electrode, a gate pad electrode, a test pad electrode, a wiring electrode, and at least one. A gate resistance layer; and a protective insulating film. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The first electrode is provided on the first surface of the semiconductor substrate. The second electrode is provided on the second surface of the semiconductor substrate. The gate electrode is provided on the semiconductor substrate in order to control the current between the first electrode and the second electrode. The gate pad electrode is provided on the second surface of the semiconductor substrate away from the gate electrode and has a gate pad portion. The test pad electrode is provided on the second surface of the semiconductor substrate away from the gate pad electrode, is disposed between the gate pad electrode and the edge of the semiconductor substrate, and has a test pad portion. . The wiring electrode is separated from the gate pad electrode, and connects the gate electrode and the test pad electrode to each other. The gate resistance layer connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode to each other. The protective insulating film partially covers each of the second electrode and the gate pad electrode, and exposes the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode. The protective insulating film has an outer peripheral end, a first inner peripheral end on the second electrode, and a second inner peripheral end on the gate pad electrode. The minimum distance between the outer peripheral end and the second inner peripheral end is equal to or greater than the minimum distance between the outer peripheral end and the first inner peripheral end.

  A power semiconductor device according to another aspect of the present invention includes a semiconductor substrate, a first electrode, a second electrode, a gate electrode, a gate pad electrode, a test pad electrode, a wiring electrode, and at least one A gate resistance layer. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The first electrode is provided on the first surface of the semiconductor substrate. The second electrode is provided on the second surface of the semiconductor substrate. The gate electrode is electrically separated from the second electrode and provided on the semiconductor substrate in order to control the current between the first electrode and the second electrode. The gate pad electrode is provided on the second surface of the semiconductor substrate away from the gate electrode and has a gate pad portion. The test pad electrode is provided on the second surface of the semiconductor substrate away from the gate pad electrode, is disposed between the gate pad electrode and the edge of the semiconductor substrate, and has a test pad portion. . The wiring electrode is separated from the gate pad electrode, and connects the gate electrode and the test pad electrode to each other. The gate resistance layer connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode to each other.

  A method for manufacturing a power semiconductor device according to one aspect of the present invention includes the following steps. A power semiconductor device is prepared. The power semiconductor device includes a semiconductor substrate, a first electrode, a second electrode, a gate electrode, a gate pad electrode, a test pad electrode, a wiring electrode, at least one gate resistance layer, and a first electrode. And a protective insulating film. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The first electrode is provided on the first surface of the semiconductor substrate. The second electrode is provided on the second surface of the semiconductor substrate. The gate electrode is provided on the semiconductor substrate in order to control the current between the first electrode and the second electrode. The gate pad electrode is provided on the second surface of the semiconductor substrate away from the gate electrode and has a gate pad portion. The test pad electrode is provided on the second surface of the semiconductor substrate away from the gate pad electrode, is disposed between the gate pad electrode and the edge of the semiconductor substrate, and has a test pad portion. . The wiring electrode is separated from the gate pad electrode, and connects the gate electrode and the test pad electrode to each other. The gate resistance layer connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode to each other. The first protective insulating film partially covers each of the second electrode and the gate pad electrode, and exposes the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode. The electrical resistance between the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode is measured. The withstand voltage between the first electrode and the second electrode is measured while covering the test pad portion of the test pad electrode with an insulator.

  A method for manufacturing a power semiconductor device according to another aspect of the present invention includes the following steps. A power semiconductor device is prepared. The power semiconductor device includes a semiconductor substrate, a first electrode, a second electrode, a gate electrode, a gate pad electrode, a test pad electrode, a wiring electrode, and at least one gate resistance layer. . The semiconductor substrate has a first surface and a second surface opposite to the first surface. The first electrode is provided on the first surface of the semiconductor substrate. The second electrode is provided on the second surface of the semiconductor substrate. The gate electrode is provided on the semiconductor substrate in order to control the current between the first electrode and the second electrode. The gate pad electrode is provided on the second surface of the semiconductor substrate away from the gate electrode and has a gate pad portion. The test pad electrode is provided on the second surface of the semiconductor substrate away from the gate pad electrode, is disposed between the gate pad electrode and the edge of the semiconductor substrate, and has a test pad portion. . The wiring electrode is separated from the gate pad electrode, and connects the gate electrode and the test pad electrode to each other. The gate resistance layer connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode to each other. The electrical resistance between the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode is measured. Protection that covers the test pad part of the test pad electrode and exposes the gate pad part of the gate pad electrode after the step of measuring the electrical resistance between the gate pad part of the gate pad electrode and the test pad part of the test pad electrode An insulating film is formed. After the protective insulating film is formed, the withstand voltage between the first electrode and the second electrode is measured.

  According to the power semiconductor device according to one aspect of the present invention, first, the test pad electrode is provided using the region between the gate pad electrode and the edge of the semiconductor substrate. Thereby, a large effective area of the power semiconductor device can be secured. Second, regarding the protective insulating film, the minimum distance between the outer peripheral end and the second inner peripheral end is equal to or greater than the minimum distance between the outer peripheral end and the first inner peripheral end. This can prevent discharge from occurring between the outer peripheral end and the second inner peripheral end located on the gate pad electrode during withstand voltage measurement.

  According to the power semiconductor device according to another aspect of the present invention, first, the test pad electrode is provided using the region between the gate pad electrode and the edge of the semiconductor substrate. Thereby, a large effective area of the power semiconductor device can be secured. Second, the gate electrode is electrically isolated from the second electrode. Thus, there is no need to provide a configuration for electrically connecting the gate electrode and the second electrode. Therefore, the configuration of the power semiconductor device is simplified.

  According to the method for manufacturing the power semiconductor device according to one aspect of the present invention, the test pad electrode is provided using the region between the gate pad electrode and the edge of the semiconductor substrate. Thereby, a large effective area of the power semiconductor device can be secured.

  According to the method for manufacturing a power semiconductor device according to another aspect of the present invention, first, a test pad electrode is provided using a region between the gate pad electrode and the edge of the semiconductor substrate. Thereby, a large effective area of the power semiconductor device can be secured. Second, the withstand voltage is measured after the formation of the protective insulating film covering the test pad portion. This can prevent discharge from occurring between the test pad portion and the edge of the semiconductor substrate during withstand voltage measurement.

1 is a circuit diagram schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 1 is a top view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is the schematic top view which abbreviate | omitted illustration of the protective insulating film in FIG. FIG. 4 is a schematic partial sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a schematic partial sectional view taken along line VV in FIG. 2. It is a flowchart which shows schematically the structure of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 7 is a partial cross sectional view schematically showing a step of measuring a gate resistance in FIG. 6. FIG. 7 is a partial cross-sectional view schematically showing a step of measuring withstand voltage in FIG. 6. It is a top view which shows roughly the structure of the semiconductor device in Embodiment 2 of this invention, abbreviate | omitting illustration of a protective insulating film. It is a fragmentary sectional view which shows roughly the process of the withstand voltage measurement in the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 4 of this invention. It is a flowchart which shows schematically the structure of the manufacturing method of the semiconductor device in Embodiment 4 of this invention. FIG. 13 is a partial cross sectional view schematically showing a step for preparing a semiconductor chip in FIG. 12. FIG. 13 is a partial cross sectional view schematically showing a step of measuring a gate resistance in FIG. 12. FIG. 13 is a partial sectional view schematically showing a withstand voltage measurement step in FIG. 12. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 5 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
(Constitution)
FIG. 1 is a circuit diagram schematically showing a configuration of a semiconductor chip 91 (power semiconductor device) in the present embodiment. The semiconductor chip 91 has a gate resistance layer 51 as a gate resistance element between the gate electrode 50 of the transistor structure TR and the gate pad portion PG. Thereby, the gate signal applied to the gate pad part PG is input to the gate electrode 50 via the gate resistance layer 51 as a gate resistance element. In addition, the semiconductor chip 91 has a test pad portion PT connected between the gate resistance layer 51 and the gate electrode 50. Thereby, the electrical resistance between the gate pad part PG and the test pad part PT can be measured. Therefore, the resistance value of the gate resistance layer 51 as a gate resistance element can be known.

  FIG. 2 is a top view schematically showing the configuration of the semiconductor chip 91 in the present embodiment. FIG. 3 is a schematic top view in which the protective insulating film 65 in FIG. 2 is omitted. 4 and FIG. 5 are schematic partial cross-sectional views taken along lines IV-IV and VV in FIG.

  The semiconductor chip 91 (power semiconductor device) includes an epitaxial substrate 10 (semiconductor substrate), a drain electrode 31 (first electrode), a source electrode 32 (second electrode), a gate electrode 50, and a gate pad electrode. 33, a test pad electrode 41, a wiring electrode 42, a plurality of gate resistance layers 51, insulating films 61 and 62, and a protective insulating film 65. Epitaxial substrate 10 has lower surface S1 (first surface) and upper surface S2 (second surface) opposite to lower surface S1. On the upper surface S2, a MOSFET structure as a transistor structure TR (FIG. 1) and a breakdown voltage termination region 13 surrounding the MOSFET structure are provided. Hereinafter, a more specific configuration will be described.

  Epitaxial substrate 10 has an edge EW. The edge EW is formed by dicing on the semiconductor wafer. Epitaxial substrate 10 includes a single crystal substrate 11 that forms lower surface S1, and an epitaxial layer that is provided on the surface opposite to lower surface S1 of single crystal substrate 11 and forms upper surface S2. Single crystal substrate 11 has n-type (first conductivity type). Single crystal substrate 11 is made of SiC. The epitaxial layer has a drift layer 12, a breakdown voltage termination region 13, a well region 14, and a source region 15. The epitaxial layer is made of SiC.

  Drift layer 12 is provided on the surface of single crystal substrate 11 opposite to lower surface S1. Drift layer 12 has an n-type and has an impurity concentration higher than that of single crystal substrate 11. The breakdown voltage termination region 13 is provided on the drift layer 12 and has a p-type. The breakdown voltage termination region 13 is disposed on the outer peripheral region of the upper surface S2, and preferably surrounds the cell region that forms the transistor structure TR in a plan view (view of FIG. 3). The well region 14 is provided on the upper surface S2 and has a p-type. The source region 15 is provided on the well region 14 and is separated from the drift layer 12 by the well region 14. Source region 15 has n-type and has an impurity concentration higher than that of drift layer 12.

  The drain electrode 31 is provided on the lower surface S 1 of the epitaxial substrate 10. The source electrode 32 is provided on the upper surface S <b> 2 of the epitaxial substrate 10 and is in contact with each of the well region 14 and the source region 15. The source electrode 32 has a source pad portion PS for connection to the outside of the semiconductor chip 91. The source electrode 32 is made of, for example, aluminum (Al).

  The gate electrode 50 is provided on the upper surface S2 of the epitaxial substrate 10 via a gate insulating film. 4 and 5, the gate insulating film is a portion of the insulating film 62 between the epitaxial substrate 10 and the gate electrode 50. The gate electrode 50 is for controlling a current between the drain electrode 31 and the source electrode 32. Specifically, a channel on the well region 14 connecting the source region 15 and the drift layer 12 is formed. It is for control. When an on-voltage is applied to the gate electrode 50, an inversion layer is formed on the surface of the well region 14 facing the gate electrode 50 through the gate insulating film, thereby forming a channel. The gate electrode 50 is electrically isolated from the source electrode 32. The gate electrode 50 is made of, for example, doped polysilicon.

  The gate pad electrode 33 is provided on the upper surface S <b> 2 of the epitaxial substrate 10 away from the gate electrode 50. The gate pad electrode 33 has a gate pad portion PG for applying a gate voltage from the outside of the semiconductor chip 91.

  The test pad electrode 41 is provided on the upper surface S <b> 2 of the epitaxial substrate 10 away from the gate pad electrode 33, and is disposed between the gate pad electrode 33 and the edge EW of the epitaxial substrate 10. Test pad electrode 41 preferably includes a portion disposed on gate resistance layer 51. The test pad electrode 41 has a test pad portion PT for applying a probe when measuring the gate resistance of the semiconductor chip 91. The test pad electrode 41 is made of Al, for example.

  The wiring electrode 42 is separated from the gate pad electrode 33 and connects the gate electrode 50 and the test pad electrode 41 to each other. The wiring electrode 42 is made of, for example, Al. The test pad electrode 41 and the wiring electrode 42 may constitute an integrally formed electrode layer 40. The electrode layer 40 may surround the gate pad electrode 33 as shown in FIG. The electrode layer 40 is preferably a layer integrally formed of one material. The “one material” here may be a laminated material. The wiring electrode 42 is provided away from the source electrode 32. The wiring electrode 42 may surround the source electrode 32 as shown in FIG.

  The gate resistance layer 51 connects the gate pad electrode 33 and at least one of the test pad electrode 41 and the wiring electrode 42 (FIG. 3) to each other. In the present embodiment, the gate resistance layer 51 connects the gate pad electrode 33 and the wiring electrode 42 to each other, as shown in FIG. The thickness of the gate resistance layer 51 is, for example, about 0.5 μm. The gate resistance layer 51 is made of doped polysilicon, for example. In order to simplify the manufacturing method of the semiconductor chip 91, the gate resistance layer 51 is preferably made of the same material as that of the gate electrode 50.

  The size and arrangement of the gate resistance layer 51 are determined in consideration of the gate resistance value R and heat generation by the gate resistance layer 51. The gate resistance value R is determined by the length L, width W, and thickness d of the gate resistance layer 51. When the thickness d is fixed, the gate resistance value R can be adjusted by the ratio of the length L and the width W.

When the effective area of the semiconductor chip 91 is large, that is, when the capacitance is large, the gate capacitance is large, so that the current I that instantaneously flows through the gate resistance layer 51 during the switching operation is also large. The gate resistance layer 51 generates heat due to the power of I ² · R. The temperature of the gate resistance layer 51 is determined by the amount of heat generated and the thermal resistance value for cooling the gate resistance layer 51. When the thermal resistance value is high with respect to the amount of heat generated, the temperature of the gate resistance layer 51 rises greatly, and in some cases, the temperature becomes higher than the heat resistance temperature of the gate resistance layer 51, which may cause damage or permanent change in resistance value. . Even if these conditions are not reached, there is a problem that the gate resistance value R is deviated from the designed design value in actual use.

  In order to avoid such a problem, the thermal resistance value may be reduced by increasing the area of the gate resistance layer 51. For example, by changing the length L = 15 μm and the width W = 3 μm to the length L = 150 μm and the width W = 30 μm, the area of the gate resistance layer 51 can be reduced without changing the gate resistance value R. It can be 100 times. As a result, the thermal resistance can be reduced to approximately 1/100. Thus, in order to prevent the above problem, it is desirable to increase the area of the gate resistance layer 51. Here, a simple increase in the area of the gate resistance layer 51 may lead to a decrease in the effective area of the semiconductor chip 91. However, according to the present embodiment, as will be described later, such a decrease in the effective area can be suppressed. Is possible.

  The protective insulating film 65 partially covers each of the source electrode 32 and the gate pad electrode 33. The protective insulating film 65 is, for example, a polyimide film. The thickness of the protective insulating film 65 is, for example, several μm to several tens of μm. The protective insulating film 65 exposes the opening OG exposing the gate pad part PG of the gate pad electrode 33, the opening OT exposing the test pad part PT of the test pad electrode 41, and the source pad part PS of the source electrode 32. And an opening OS.

  The protective insulating film 65 has an outer peripheral end EP. The outer peripheral end EP is preferably arranged on the inner side of the edge EW of the epitaxial substrate 10 in order to facilitate dicing for forming the edge EW of the epitaxial substrate 10. The protective insulating film 65 has a first inner peripheral end ES on the source electrode 32, a second inner peripheral end EG on the gate pad electrode 33, and a test pad electrode 41 as an end opposite to the outer peripheral end EP. And a third inner peripheral end ET. The minimum distance LS between the outer peripheral end EP and the first inner peripheral end ES needs to be large enough to prevent discharge between them during the withstand voltage measurement. The minimum distance LS is, for example, about 1.5 mm when the withstand voltage is 3.3 kV. Further, the minimum distance LG between the outer peripheral end EP and the second inner peripheral end EG is set to be equal to or larger than the minimum distance LS in order to suppress the occurrence of discharge between them during the withstand voltage measurement.

(Production method)
Next, a method for manufacturing the semiconductor chip 91 will be described.

  First, a semiconductor chip 91 for which withstand voltage measurement has not yet been performed is prepared (FIG. 6: Step S10).

  Referring to FIG. 7, next, the electrical resistance between the gate pad part PG of the gate pad electrode 33 and the test pad part PT of the test pad electrode 41, that is, the gate resistance, is measured using a four-terminal measurement method. (FIG. 6: Step S30). Specifically, two probes 71 and 72 are applied to the test pad portion PT, and two probes 73 and 74 are applied to the gate pad portion PG. The voltage between the inner probes 72 and 73 is measured while a minute current is passed between the probes 71 and 74 located outside of the four probes 71 to 74. Thus, the resistance value can be accurately measured without being affected by the contact resistance of the probe. Each of the probes 71 to 74 can be held by the tester head 70. The probes 71 to 74 can be brought into contact with or separated from the semiconductor chip 91 by the displacement of the tester head 70. Based on the resistance value thus measured, the semiconductor chip 91 having a gate resistance that does not satisfy a predetermined specification is excluded from the process. Thereby, the semiconductor chip 91 having a gate resistance satisfying the specifications can be obtained.

  Referring to FIG. 8, next, the withstand voltage between drain electrode 31 and source electrode 32 is measured (FIG. 6: step S50). In this measurement, a high voltage is applied between the drain electrode 31 and the source electrode 32 using a probe or the like (not shown). At this time, the probe 75 is applied to the gate pad portion PG in order to control the voltage of the gate electrode 50. The probe 75 is not intended for measurement by a four-terminal measurement method, and may be a single probe. Based on the withstand voltage thus measured, the semiconductor chip 91 having a withstand voltage that does not satisfy the predetermined specification is removed from the process. Thereby, the semiconductor chip 91 having a withstand voltage satisfying the specifications can be obtained.

  As described above, the semiconductor chip 91 having a withstand voltage and a gate resistance satisfying the specifications is obtained.

(effect)
A power semiconductor module having a large power capacity can be obtained by electrically connecting a plurality of semiconductor chips 91 obtained in the above manner in parallel and then sealing with a gel or a molding material. Since this power semiconductor module has a small variation in gate resistance value among a plurality of semiconductor chips provided therein, an oscillation phenomenon is unlikely to occur even during high-frequency operation. Note that such a power semiconductor module can also be manufactured using semiconductor chips according to other embodiments described later.

  In order to suppress the discharge between the outer peripheral end EP and the second inner peripheral end EG at the time of measuring the withstand voltage of each semiconductor chip 91, the minimum distance LG (FIG. 2) needs to be increased to some extent. When the voltage is 3.3 kV, the minimum distance LG needs to be about 1.5 mm or more. For this reason, a region having a certain size exists outside the gate pad portion PG (upper side in FIG. 2). In the present embodiment, the test pad portion PT is arranged using this region. In other words, as shown in FIG. 3, the test pad electrode 41 is provided using the region between the gate pad electrode 33 (FIG. 3) and the edge EW (FIG. 2) of the epitaxial substrate 10. As a result, the test pad portion PT can be disposed without substantially reducing the area of the source electrode 32 (FIG. 3) that is a current path. Therefore, a large effective area of the semiconductor chip 91 can be secured.

  Further, by providing a plurality of gate resistance layers 51 instead of a single one, the gate resistance layers 51 can be dispersed and arranged in a wider region. Since the heat flow from the gate resistance layer 51 flows not only in the thickness direction (vertical direction in FIG. 5) but also in the oblique direction, the thermal resistance is more effective than the area S (= L × W) of the gate resistance layer 51 itself. It is determined by a large area. Accordingly, the thermal resistance can be reduced by using a plurality of divided gate resistance layers instead of one large gate resistance layer. Thereby, the thermal resistance of the gate resistance layer 51 can be reduced. Therefore, damage to the semiconductor chip 91 or change in gate resistance due to heat generation of the gate resistance layer 51 can be avoided more reliably.

  Regarding the protective insulating film 65, the minimum distance LG between the outer peripheral end EP and the second inner peripheral end EG is equal to or greater than the minimum distance LS between the outer peripheral end EP and the first inner peripheral end ES. Thereby, it is possible to prevent discharge from occurring between the outer peripheral end EP and the second inner peripheral end EG located on the gate pad electrode 33 during the withstand voltage measurement.

  The gate electrode 50 is electrically separated from the source electrode 32. Thereby, it is not necessary to provide a configuration for electrically connecting the gate electrode 50 and the source electrode 32. Therefore, the configuration of the semiconductor chip 91 is simplified.

  Test pad electrode 41 preferably includes a portion disposed on gate resistance layer 51. In this case, the region below the test pad electrode 41 is used for the arrangement of the gate resistance layer 51. Therefore, a larger effective area of the semiconductor chip 91 can be ensured.

<Embodiment 2>
FIG. 9 is a top view schematically showing the configuration of the semiconductor chip 92 (power semiconductor device) in the present embodiment, omitting the illustration of the protective insulating film 65 (FIG. 2). The semiconductor chip 91 has a plurality of gate resistance layers 51V instead of the gate resistance layer 51 (FIG. 3). Each of the gate resistance layers 51V is disposed outside the test pad electrode 41 in a plan view, and connects the gate pad electrode 33 and the wiring electrode 42 to each other. Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  According to the present embodiment, it is possible to dispose the gate resistance layer 51V so as not to overlap the test pad electrode 41 in plan view. Therefore, the gate resistance layer 51V can be dispersed and arranged in a wider region. Therefore, the thermal resistance of the gate resistance layer can be reduced. Therefore, damage to the semiconductor chip 91 or change in gate resistance due to heat generation of the gate resistance layer can be avoided more reliably. As a modification, in order to further reduce the thermal resistance of the gate resistance layer, both the gate resistance layer 51 (FIG. 3) of the present embodiment and the gate resistance layer 51V (FIG. 9) of the first embodiment are provided. May be.

  In order to obtain a large resistance value, it may be necessary to increase the length L of the gate resistance layer 51V. In this case, an increase in the distance between the gate pad electrode 33 and the wiring electrode 42 adjacent thereto can be suppressed by increasing the ratio of the portion of the gate resistance layer 51V located below the gate pad electrode 33. . As a result, it is possible to suppress a decrease in effective area due to the provision of the gate resistance layer 51V.

<Embodiment 3>
In the first embodiment described above, in step S50 (FIG. 6) for measuring the withstand voltage, the test pad portion PT of the test pad electrode 41 is exposed as shown in FIG. For this reason, at the time of withstand voltage measurement, in order to avoid discharge between the outer peripheral end EP of the protective insulating film 65 and the third inner peripheral end ET located on the test pad electrode 41, the test pad from the outer peripheral end EP The part PT needs to be arranged apart to some extent. For example, in the case of a withstand voltage of 3.3 kV, if the third inner peripheral end ET is separated from the outer peripheral end EP by about 1.5 mm, the occurrence of discharge can be suppressed considerably, but it is difficult to completely prevent discharge. . Larger separation of the third inner peripheral end ET from the outer peripheral end EP can lead to a large reduction in the effective area of the semiconductor chip 91.

  Referring to FIG. 10, in the present embodiment, the withstand voltage between drain electrode 31 and source electrode 32 is measured while covering test pad portion PT of test pad electrode 41 with an insulator. Specifically, the test pad portion PT is covered with a rubber pad 79 attached to the tester head 70 at the time of withstand voltage measurement. Preferably, rubber pad 79 is arranged so as to cover breakdown voltage termination region 13 provided in the outer peripheral region of epitaxial substrate 10.

  Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the present embodiment, without sacrificing the effective area of the semiconductor chip 91, between the outer peripheral end EP and the third inner peripheral end ET located on the test pad electrode 41 during the withstand voltage measurement. It is possible to prevent the occurrence of discharge more reliably.

  When the semiconductor chip 91 is actually used after the withstand voltage measurement, the test pad portion PT is covered with a gel or a molding material that seals the semiconductor chip 91. Therefore, no discharge occurs in the test pad portion PT at that time.

<Embodiment 4>
FIG. 11 is a partial cross-sectional view schematically showing a configuration of a semiconductor chip 94 (power semiconductor device) in the present embodiment. The semiconductor chip 94 has a protective insulating film 66 instead of the protective insulating film 65 (FIG. 5). The protective insulating film 66 exposes the gate pad part PG of the gate pad electrode 33 in the same manner as the protective insulating film 65, but covers the test pad part PT of the test pad electrode 41.

  Next, a method for manufacturing the semiconductor chip 92 will be described. Referring to FIG. 13, first, a semiconductor chip 90 in which the protective insulating film 66 is not yet formed is prepared (FIG. 12: Step S10). Referring to FIG. 14, the electrical resistance between gate pad portion PG of gate pad electrode 33 and test pad portion PT of test pad electrode 41, ie, the gate resistance, is measured (FIG. 12: Step S30). After this step S30, a protective insulating film 66 (FIG. 11) is formed (FIG. 12: step S40). Referring to FIG. 15, after step S40, the withstand voltage between drain electrode 31 and source electrode 32 is measured (FIG. 12: step S50).

  Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  According to the present embodiment, the withstand voltage is measured after the formation of the protective insulating film 66 covering the test pad portion PT. Thereby, it is possible to prevent a discharge from occurring between the test pad portion PT and the edge EW of the epitaxial substrate 10 without sacrificing the effective area of the semiconductor chip 92. Unlike the third embodiment, the test pad portion PT is covered with the protective insulating film 66 after the withstand voltage measurement and before the semiconductor chip 92 is sealed. Therefore, even when an intermediate inspection for measuring the withstand voltage is performed at such a time point, the occurrence of discharge can be suppressed.

  Note that the rubber pad 79 described in the third embodiment may also be used in the present embodiment in order to more reliably prevent discharge during the withstand voltage measurement.

<Embodiment 5>
FIG. 16 is a partial cross-sectional view schematically showing a configuration of a semiconductor chip 95 (power semiconductor device) in the present embodiment. The semiconductor chip 95 further includes a protective insulating film 67 (second protective insulating film) in addition to the configuration of the semiconductor chip 91 (FIG. 5) having the protective insulating film 65 (first protective insulating film). . The protective insulating film 67 covers the test pad portion PT where the protective insulating film 65 is exposed. The protective insulating film 67 has a withstand voltage between the drain electrode 31 and the source electrode 32 after the step of measuring the electrical resistance between the gate pad portion PG and the test pad portion PT (FIG. 6: step S10). It is formed before the measuring step (FIG. 6: Step S50). Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

  Also according to the present embodiment, substantially the same effect as in the fourth embodiment can be obtained. Note that the rubber pad 79 described in the third embodiment may also be used in the present embodiment in order to more reliably prevent discharge during the withstand voltage measurement.

  In each of the above embodiments, a plurality of gate resistance layers 51 are provided. However, a single gate resistance layer 51 may be provided instead of a plurality of gate resistance layers 51 as long as there is no particular problem in terms of thermal resistance. In each embodiment, the gate electrode 50 and the source electrode 32 are electrically separated, but the circuit configuration between the gate electrode 50 and the source electrode 32 may be more complicated. An element structure for electrically connecting the gate electrode 50 and the source electrode 32 may be provided. In each of the embodiments, the planar gate type gate electrode 50 provided on the flat upper surface S2 via the gate insulating film is illustrated, but the upper surface S2 provided with the trench via the gate insulating film. A trench gate type gate electrode may be provided by disposing the gate electrode 50. Further, by switching the above-described n-type and p-type, a MOSFET having a p-channel instead of the n-channel can be configured. Further, by using an insulating film that is not an oxide film as the gate insulating film, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that is not a MOSFET can be configured. Further, the semiconductor material is not limited to SiC, and other wide band gap semiconductors may be used, and silicon may be used when advantages by the wide band gap semiconductor are not particularly required. When a higher withstand voltage is required, a semiconductor layer having a conductivity type opposite to that of drift layer 12 is formed by reversing the conductivity type of single crystal substrate 11 or on lower surface S1 of epitaxial substrate 10. By providing, IGBT may be comprised instead of MISFET.

  Within the scope of the present invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

  EG second inner peripheral end, EP outer peripheral end, ES first inner peripheral end, ET third inner peripheral end, EW edge, OG, OS, OT opening, PG gate pad, S1 lower surface (first Surface), S2 upper surface (second surface), PS source pad portion, PT test pad portion, TR transistor structure, 10 epitaxial substrate (semiconductor substrate), 11 single crystal substrate, 12 drift layer, 13 breakdown voltage termination region, 14 well Region 15 source region 31 drain electrode (first electrode) 32 source electrode (second electrode) 33 gate pad electrode 40 electrode layer 41 test pad electrode 42 wiring electrode 50 gate electrode 51 51V gate resistance layer, 61, 62 insulating film, 65 protective insulating film (first protective insulating film), 66 protective insulating film, 67 protective insulating film (second protective insulating film), 7 Tester head, 71 to 75 probe, 79 rubber pads (power semiconductor device) 91,92,94,95 semiconductor chip.

Claims (7)

A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A first electrode provided on the first surface of the semiconductor substrate;
A second electrode provided on the second surface of the semiconductor substrate;
A gate electrode provided on the semiconductor substrate to control a current between the first electrode and the second electrode;
A gate pad electrode provided on the second surface of the semiconductor substrate away from the gate electrode and having a gate pad portion;
A test pad electrode provided on the second surface of the semiconductor substrate away from the gate pad electrode, disposed between the gate pad electrode and an edge of the semiconductor substrate, and having a test pad portion;
A wiring electrode separated from the gate pad electrode and connecting the gate electrode and the test pad electrode to each other;
At least one gate resistance layer that connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode;
A protective insulating film partially covering each of the second electrode and the gate pad electrode and exposing the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode;
The protective insulating film has an outer peripheral end, a first inner peripheral end on the second electrode, and a second inner peripheral end on the gate pad electrode, and the outer peripheral end and the The power semiconductor device, wherein a minimum distance between the second inner peripheral end is equal to or greater than a minimum distance between the outer peripheral end and the first inner peripheral end. A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A first electrode provided on the first surface of the semiconductor substrate;
A second electrode provided on the second surface of the semiconductor substrate;
A gate electrode electrically separated from the second electrode and provided on the semiconductor substrate to control a current between the first electrode and the second electrode;
A gate pad electrode provided on the second surface of the semiconductor substrate away from the gate electrode and having a gate pad portion;
A test pad electrode provided on the second surface of the semiconductor substrate away from the gate pad electrode, disposed between the gate pad electrode and an edge of the semiconductor substrate, and having a test pad portion;
A wiring electrode separated from the gate pad electrode and connecting the gate electrode and the test pad electrode to each other;
At least one gate resistance layer that connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode;
A power semiconductor device.   The power semiconductor device according to claim 1, wherein the test pad electrode includes a portion disposed on the gate resistance layer.   The at least one gate resistance layer includes a gate resistance layer that is disposed outside the test pad electrode in a plan view and connects the gate pad electrode and the wiring electrode to each other. 2. A power semiconductor device according to item 1. A step of preparing a power semiconductor device, wherein the power semiconductor device comprises:
A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A first electrode provided on the first surface of the semiconductor substrate;
A second electrode provided on the second surface of the semiconductor substrate;
A gate electrode provided on the semiconductor substrate to control a current between the first electrode and the second electrode;
A gate pad electrode provided on the second surface of the semiconductor substrate away from the gate electrode and having a gate pad portion;
A test pad electrode provided on the second surface of the semiconductor substrate away from the gate pad electrode, disposed between the gate pad electrode and an edge of the semiconductor substrate, and having a test pad portion;
A wiring electrode separated from the gate pad electrode and connecting the gate electrode and the test pad electrode to each other;
At least one gate resistance layer that connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode;
A protective insulating film partially covering each of the second electrode and the gate pad electrode and exposing the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode;
And measuring an electrical resistance between the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode;
Measuring the withstand voltage between the first electrode and the second electrode while covering the test pad portion of the test pad electrode with an insulator;
A method for manufacturing a power semiconductor device.   After the step of measuring the electrical resistance between the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode, and withstand voltage between the first electrode and the second electrode The method for manufacturing a power semiconductor device according to claim 5, further comprising a step of forming a second protective insulating film that covers the test pad portion of the test pad electrode before the step of measuring. A step of preparing a power semiconductor device, wherein the power semiconductor device comprises:
A semiconductor substrate having a first surface and a second surface opposite to the first surface;
A first electrode provided on the first surface of the semiconductor substrate;
A second electrode provided on the second surface of the semiconductor substrate;
A gate electrode provided on the semiconductor substrate to control a current between the first electrode and the second electrode;
A gate pad electrode provided on the second surface of the semiconductor substrate away from the gate electrode and having a gate pad portion;
A test pad electrode provided on the second surface of the semiconductor substrate away from the gate pad electrode, disposed between the gate pad electrode and an edge of the semiconductor substrate, and having a test pad portion;
A wiring electrode separated from the gate pad electrode and connecting the gate electrode and the test pad electrode to each other;
At least one gate resistance layer that connects the gate pad electrode and at least one of the test pad electrode and the wiring electrode;
And measuring an electrical resistance between the gate pad portion of the gate pad electrode and the test pad portion of the test pad electrode;
After the step of measuring the electrical resistance between the gate pad part of the gate pad electrode and the test pad part of the test pad electrode, the test pad part of the test pad electrode is covered and the gate pad electrode Forming a protective insulating film exposing the gate pad portion;
After the step of forming the protective insulating film, measuring a withstand voltage between the first electrode and the second electrode;
A method for manufacturing a power semiconductor device.

Images