JP2020098872A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

To provide a semiconductor device that has a gate resistance built in an element and can prevent a source electrode and the gate resistance from short-circuiting, and a method of manufacturing the semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises: a first semiconductor layer 2 of a first conductivity type provided on a top surface of a semiconductor substrate 1 of the first conductivity type; a second semiconductor layer 3 of a second conductivity type; a first semiconductor region 7 of the first conductivity type; a gate electrode 10 provided across a gate insulation film 9; and an inter-layer insulation film 11 provided on the gate electrode 10. The silicon carbide semiconductor device further comprises: a first electrode 13 provided on top surfaces of the second semiconductor layer 3 and first semiconductor region 7; a plating film 16 provided selectively on the first electrode 13; a solder film 17 provided on the plating film 16; gate wiring 33 electrically connecting with the gate electrode 10, and surrounding a circumference of an active region 40 where a main current flows in an ON state; a gate electrode pad 22 to which a gate signal is input; and a gate resistance 34 provided at a part, opposed to the solder film 17, of a region sandwiched between the gate electrode pad 22 and gate wiring 33.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a semiconductor device manufacturing method.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage and a large current. There are a plurality of types of power semiconductor devices such as a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc. Has been.

For example, a bipolar transistor or an IGBT has a higher current density and a larger current than a MOSFET, but cannot switch at high speed. Specifically, the bipolar transistor has a limit of use at a switching frequency of about several kHz, and the IGBT has a limit of use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than that of the bipolar transistor and the IGBT, and it is difficult to increase the current, but it can perform high-speed switching operation up to several MHz.

However, in the market, there is a strong demand for a power semiconductor device having both a large current and a high speed, and efforts are being made to improve the IGBT and the power MOSFET, and at present, the development is progressing to a point near the material limit. .. From the viewpoint of a power semiconductor device, a semiconductor material replacing silicon is being studied, and silicon carbide (SiC) is a semiconductor material capable of producing (manufacturing) a next-generation power semiconductor device excellent in low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

Silicon carbide is a chemically very stable semiconductor material, has a wide band gap of 3 eV, and can be used very stably as a semiconductor even at high temperatures. Further, since silicon carbide has a maximum electric field strength higher than that of silicon by one digit or more, it is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such characteristics of silicon carbide also apply to a wide bandgap semiconductor having a wider bandgap than other silicon, for example, gallium nitride (GaN). Therefore, by using the wide band gap semiconductor, the breakdown voltage of the semiconductor device can be increased.

In such a high breakdown voltage semiconductor device using silicon carbide, the switching loss generated during the on/off operation is reduced, so that when used in an inverter, the carrier frequency is one digit higher than that of a conventional semiconductor device using silicon. Applied. When the semiconductor device is applied at a high frequency, the heat generation temperature of the chip becomes high, which affects the reliability of the semiconductor device. In particular, a bonding wire is bonded to the front surface electrode on the front surface side of the substrate as a wiring material for extracting the electric potential of the front surface electrode to the outside. When used in, the adhesion between the front surface electrode and the bonding wire is reduced and reliability is affected.

Since the silicon carbide semiconductor device may be used at a high temperature of 230° C. or higher, a pin-shaped external terminal electrode may be bonded to the front surface electrode by soldering instead of the bonding wire. This can prevent the adhesion between the front surface electrode and the external terminal electrode from decreasing.

FIG. 14 is a top view showing a structure of a conventional silicon carbide semiconductor device. As shown in FIG. 14, in the semiconductor chip 150, an edge termination region 141 that surrounds the periphery of the active region 140 and holds the breakdown voltage is provided on the outer periphery of the active region 140 through which the main current flows. In the active region 140, the gate electrode pad 122 electrically connected to the gate electrode through the gate polysilicon electrode 133, the source electrode pad 115 electrically connected to the source electrode, and the gate resistor 1
34 and are provided.

A first protective film 121 is provided on the source electrode pad 115, and an external terminal electrode (not shown) is provided on the plated film 116 in the first protective film 121 via a solder (not shown). Similarly, a first protective film 121 is provided on the gate electrode pad 122, and an external terminal electrode (not shown) is provided on the plated film 116 in the first protective film 121 via a solder (not shown). ..

With the increase in current of devices using silicon carbide semiconductor devices, silicon carbide semiconductor devices are used in parallel connection in order to improve the current capacity of the silicon carbide semiconductor devices. If they are connected in parallel, uniform operation of the elements becomes difficult if there are variations in characteristics among the silicon carbide semiconductor elements. For example, an imbalance between elements may occur during switching, resulting in oscillation of current and voltage. Therefore, a method is known in which an external chip resistor is connected to achieve uniform operation of the silicon carbide semiconductor element.

However, as the number of silicon carbide semiconductor elements connected in parallel increases, the number of external chip resistors connected to each silicon carbide semiconductor element also increases, which complicates the manufacturing process and increases costs. Therefore, the gate resistor 134 having the same effect as the external chip resistor is built in the semiconductor element.

In order to suppress heat generation when a large current flows through the built-in gate resistor, the built-in gate resistor is formed on the upper surface of the field insulating film, the interlayer insulating film covers the built-in gate resistor, and the thickness of the interlayer insulating film is changed to the gate contact. A technique is known in which at least a part of a region between a hole and a gate contact hole is made thinner than other regions (for example, refer to Patent Document 1 below).

JP, 2016-58466, A

As shown in FIG. 14, the conventional gate resistor 134 is provided between the source electrode pad 115 and the gate electrode pad 122 so as to be adjacent to a part of the gate electrode pad 122 and embedded in the active region 140. To be The gate resistance 134 is provided so as to extend a part of the gate polysilicon electrode 133 (not shown) and serve as a resistance between the gate polysilicon electrode 133 and the gate electrode pad 122.

However, in the above structure, when the external terminal electrode is fixed to the source electrode pad 115, the solder wraps around between the first protective film 121 of the source electrode pad 115 and the source electrode, and the solder causes the source electrode and the gate electrode. The resistor 134 may be short-circuited and the silicon carbide semiconductor device may be deteriorated. Further, in order to prevent the source electrode and the gate resistor 134 from being short-circuited, the difficulty of the soldering process increases. Further, by providing the gate resistance 134 between the source electrode pad 115 and the gate electrode pad 112, the area of the active region 140 is reduced and the on-resistance is increased.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides a semiconductor device in which a gate resistor is built in the element and a short circuit between the source electrode and the gate resistor can be prevented, and a method of manufacturing the semiconductor device. And

In order to solve the above problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer having a lower impurity concentration than that of the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate. A second conductive type second semiconductor layer is selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of the first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side. A gate insulating film is provided in contact with the second semiconductor layer. A gate electrode is provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer. A first electrode is provided on the surfaces of the second semiconductor layer and the first semiconductor region. A plating film is selectively provided on the first electrode. A solder film is selectively provided on the plating film. A second electrode is provided on the back surface of the semiconductor substrate. A gate wiring is provided that is electrically connected to the gate electrode and surrounds an active region in which a main current flows in the ON state. A gate electrode pad to which a gate signal is input is provided. A gate resistance is provided in a portion facing the solder film in a region sandwiched between the gate electrode pad and the gate wiring.

In the semiconductor device according to the present invention according to the above-mentioned invention, the semiconductor device further includes a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, and the gate electrode is a trench of the trench. It is characterized in that it is provided inside through the gate insulating film.

Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the semiconductor device further includes a gate resistance pad for electrically evaluating the gate resistance and electrically connected to the gate wiring.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the gate resistance is adjacent to the first electrode.

In order to solve the problems described above and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step of forming a first conductive type first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate is performed on the front surface of the first conductive type semiconductor substrate. Then, a second step of selectively forming a second conductive type second semiconductor layer on the surface of the first semiconductor layer opposite to the semiconductor substrate side is performed. Next, a third step of selectively forming a first semiconductor region of the first conductivity type on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side is performed. Next, a fourth step of forming a gate insulating film in contact with the second semiconductor layer is performed. Next, a fifth step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer is performed. Next, a sixth step of forming an interlayer insulating film on the gate electrode is performed. Next, a seventh step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region is performed. Next, an eighth step of selectively forming a plating film on the first electrode is performed. Next, a ninth step of selectively forming a solder film on the plating film is performed. Next, a tenth step of forming a second electrode on the back surface of the semiconductor substrate is performed. Next, an eleventh step of forming a gate wiring that is electrically connected to the gate electrode and surrounds an active region in which a main current flows in the ON state is performed. Next, a twelfth step of forming a gate electrode pad to which a gate signal is input is performed. Next, a thirteenth step of forming a gate resistor in a portion facing the solder film in a region sandwiched between the gate electrode pad and the gate wiring is performed.

According to the invention described above, the gate resistance is provided in the portion of the gate polysilicon electrode sandwiched between the gate electrode pad and the edge termination region. This can prevent the source electrode and the gate resistance from being short-circuited. Further, since the gate resistance is not provided in the active region, the area of the active region does not decrease, and the on-resistance does not decrease due to the gate resistance.

According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, the effect that the gate resistance is built in the element and the short circuit between the source electrode and the gate resistance can be prevented.

It is a top view which shows the structure of the silicon carbide semiconductor device concerning embodiment. FIG. 3 is a cross-sectional view showing the structure of the portion along the line A-A′ in FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing a structure of a B-B′ portion in FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing a structure of a C-C′ portion of FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing the structure of the portion along the line D-D′ of FIG. 1 of the silicon carbide semiconductor device according to the embodiment. 7 is a graph showing GS short-circuit rates of a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. FIG. 3 is a cross-sectional view (1) schematically showing a state in which the silicon carbide semiconductor device according to the embodiment is being manufactured. FIG. 3 is a cross-sectional view (2) schematically showing a state in which the silicon carbide semiconductor device according to the embodiment is being manufactured. FIG. 6 is a cross-sectional view schematically showing a state in the process of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 3). FIG. 4 is a cross-sectional view schematically showing a state in the process of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 4). FIG. 7 is a cross-sectional view (5) schematically showing a state in which the silicon carbide semiconductor device according to the embodiment is being manufactured. FIG. 6 is a cross sectional view schematically showing a state in the process of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 6). FIG. 7 is a cross sectional view schematically showing a state in the process of manufacturing the silicon carbide semiconductor device according to the embodiment (No. 7). It is a top view which shows the structure of the conventional silicon carbide semiconductor device.

Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In the present specification and the accompanying drawings, in a layer or region prefixed with n or p, it means that electrons or holes are majority carriers. Further, + and − attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. The same notation for n and p including + and − indicates that the concentrations are close to each other, and the concentrations are not necessarily equal. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. Further, in the present specification, in the Miller index notation, "-" means a bar attached to the index immediately after it, and "-" is added before the index to represent a negative index.

(Embodiment)
The semiconductor device according to the present invention is configured by using a wide band gap semiconductor. In the embodiment, a silicon carbide semiconductor device manufactured by using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a MOSFET as an example.

FIG. 1 is a top view showing a structure of a silicon carbide semiconductor device according to an embodiment. As shown in FIG. 1, in the silicon carbide semiconductor device, an edge termination region 41 that surrounds the periphery of active region 40 and holds a breakdown voltage is provided on the outer periphery of active region 40 in which a main current flows.

In the active region 40, the gate electrode pad 22 electrically connected to the gate electrode via the gate polysilicon electrode (gate wiring) 33, the source electrode pad 15 electrically connected to the source electrode, and the gate resistor 34. , Are provided.

A first protective film 21 is provided on the source electrode pad 15, and an external terminal electrode (not shown) is provided on the plating film 16 in the first protective film 21 via a solder (solder film) (not shown). To be Similarly, the gate electrode pad 22 is provided with a first protective film 21, and an external terminal electrode (not shown) is provided on the plating film 16 in the first protective film 21 via a solder (not shown). ..

Further, the active region 40 may be provided with a gate resistance pad 35 which is an electrode pad for measuring the resistance value of the gate resistance 34. The gate resistance pad 35 is electrically connected to the gate electrode pad 22. Therefore, the gate resistance pad 35 is electrically connected to the gate electrode pad 22 via the gate resistance 34.

The edge termination region 41 is a region between the active region 40 and the side surface of the semiconductor chip 50, and is a region for relaxing the electric field on the front surface side of the semiconductor chip 50 and maintaining the breakdown voltage (withstand voltage). .. In the edge termination region 41, for example, a p-type region (not shown) forming a guard ring or a junction termination (JTE: Junction Termination Extension) structure, and a pressure resistant structure (not shown) such as a field plate and a RESURF are arranged. The breakdown voltage is a limit voltage at which the device does not malfunction or break down.

In the embodiment, the gate resistor 34 electrically connected to the portion of the gate polysilicon electrode 33 facing the solder in the region sandwiched between the gate electrode pad 22 and the edge termination region 41 is provided. Thereby, when the source electrode pad 15 is formed and the external terminal electrode is fixed to the source electrode pad 15 with solder, the solder (solder film) 17 wraps around between the first protective film 21 and the plating film 16. Even so, since the gate resistance 34 is provided on the side opposite to the source electrode pad 15, that is, in the region where the source electrode is not provided, the solder does not short-circuit the source electrode and the gate resistance 34. In addition, since the gate resistance 34 is not provided in the effective area (area that functions as a MOS gate) 1a in the active area 40, the area of the active area 40 does not decrease, and the on resistance may decrease due to the gate resistance 34. Absent. Further, since the gate resistor 34 is arranged between the gate electrode pad 22 and the gate polysilicon electrode 33, it is not necessary to form the gate polysilicon electrode 33 connected to the gate resistor 34, and the number of forming steps can be reduced. it can. In the region sandwiched between the gate electrode pad 22 and the edge termination region 41, where the gate resistor 34 is not provided, a MOS gate structure similar to that of the effective region 1a is provided. That is, the source electrode pads 15 are provided adjacent to both sides of the gate resistor 34.

FIG. 2 is a sectional view showing the structure of the AA′ portion in FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 2 shows the structure of the silicon carbide semiconductor device below the source electrode pad 15. As shown in FIG. 2, the silicon carbide semiconductor device according to the embodiment has a first main surface (front surface) of an n ⁺ type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example, (0001). An n-type silicon carbide epitaxial layer (first conductivity type first semiconductor layer) 2 is deposited on the surface (Si surface).

The n ⁺ type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer having a lower impurity concentration than the n ⁺ -type silicon carbide substrate 1 and doped with, for example, nitrogen. An n-type high concentration region 6 is formed on the surface of n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. The n-type high-concentration region 6 is a high-concentration n-type drift layer doped with, for example, nitrogen with an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. A p-type silicon carbide epitaxial layer 3 is provided on the base body first main surface side of the n-type silicon carbide epitaxial layer 2. Hereinafter, the n ⁺ type silicon carbide substrate 1, the n type silicon carbide epitaxial layer 2, and the type silicon carbide epitaxial layer (second semiconductor layer of the second conductivity type) 3 are collectively referred to as a silicon carbide semiconductor substrate.

As shown in FIG. 2, a back electrode 14 is provided on the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor substrate) of n ⁺ type silicon carbide substrate 1. The back surface electrode 14 constitutes a drain electrode. A drain electrode pad (not shown) is provided on the surface of the back electrode 14.

A stripe-shaped trench structure is formed on the first main surface side (p-type silicon carbide epitaxial layer 3 side) of the silicon carbide semiconductor substrate. Specifically, trench 18 is formed from the surface of p type silicon carbide epitaxial layer 3 opposite to the side of n ⁺ type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate) to p type silicon carbide epitaxial layer. The n-type high concentration region 6 is reached through the layer 3. A gate insulating film 9 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and a striped gate electrode 10 is formed inside the gate insulating film 9 in the trench 18. Gate electrode 10 is insulated by gate insulating film 9 from n-type high concentration region 6 and p-type silicon carbide epitaxial layer 3. A part of the gate electrode 10 projects from above the trench 18 (source electrode pad 15 side) to the source electrode pad 15 side.

A first p ⁺ type base region 4 is selectively provided in the surface layer of the n type high concentration region 6 on the side opposite to the n ⁺ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). Has been. The second p ⁺ type base region 5 is formed below the trench 18, and the width of the second p ⁺ type base region 5 is wider than the width of the trench 18. The first p ⁺ type base region 4 and the second p ⁺ type base region 5 are doped with, for example, aluminum.

The structure may be such that a part of the first p ⁺ type base region 4 is extended to the trench 18 side to be connected to the second p ⁺ type base region 5. In this case, a portion of the first 1p ⁺ -type base region 4, and the 1p ⁺ -type base region 4 a 2p ⁺ -type base region 5 and is arranged direction (hereinafter, referred to as a first direction) direction perpendicular to the y (hereinafter , And the second direction) x may have a planar layout in which the n-type high-concentration regions 6 are alternately and repeatedly arranged. For example, a structure in which a part of the first p ⁺ type base region 4 extends to the trench 18 side on both sides in the first direction x and is connected to a part of the second p ⁺ type base region 5 is periodically formed in the second direction x. It may be arranged at. The reason is that the holes generated when avalanche breakdown occurs at the junction between the second p ⁺ type base region 5 and the n-type silicon carbide epitaxial layer 2 are efficiently saved in the source electrode 13 so that the gate insulating film 9 is exposed. This is to reduce the burden and increase reliability.

Inside the p-type silicon carbide epitaxial layer 3, an n ⁺ type source region (first semiconductor region of the first conductivity type) 7 and a p ⁺⁺ type contact region 8 are selectively provided on the first main surface side of the substrate. ing. The n ⁺ type source region 7 is in contact with the trench 18. The n ⁺ type source region 7 and the p ⁺⁺ type contact region 8 are in contact with each other. Further, a region between the first p ⁺ type base region 4 and the second p ⁺ type base region 5 of the surface layer of the n-type silicon carbide epitaxial layer 2 on the side of the first main surface of the substrate, and the p-type silicon carbide epitaxial layer 3 An n-type high concentration region 6 is provided in a region sandwiched by the second p ⁺ type base regions 5.

In FIG. 2, only two trench MOS structures are shown, but more MOS gates having a trench structure (insulated gate made of metal-oxide film-semiconductor) structure may be arranged in parallel.

Interlayer insulating film 11 is provided on the entire surface of the first main surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 10 buried in trench 18. The source electrode 13 is in contact with the n ⁺ type source region 7 and the p ⁺⁺ type contact region 8 through a contact hole opened in the interlayer insulating film 11. The source electrode 13 is made of, for example, a NiSi film. The contact hole opened in the interlayer insulating film 11 has a stripe shape corresponding to the shape of the gate electrode 10. The source electrode 13 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 13. The source electrode pad 15 is formed by stacking, for example, a first TiN film 25, a first Ti film 26, a second TiN film 27, a second Ti film 28 and an Al alloy film 29. A barrier metal (not shown) that prevents diffusion of metal atoms from the source electrode 13 to the gate electrode 10 side may be provided between the source electrode 13 and the interlayer insulating film 11.

The plating film 16 is selectively provided on the source electrode pad 15, and the solder 17 is selectively provided on the surface side of the plating film 16. The solder 17 is provided with an external terminal electrode 19 which is a wiring material for extracting the potential of the source electrode 13 to the outside. The external terminal electrode 19 has a needle pin shape and is joined to the source electrode pad 15 in an upright state.

A portion of the surface of the source electrode pad 15 other than the plating film 16 is covered with the first protective film 21. Specifically, the first protective film 21 is provided so as to cover the source electrode pad 15, and the external terminal electrode 19 is bonded to the opening of the first protective film 21 via the plating film 16 and the solder film 17. ing. The boundary between the plating film 16 and the first protective film 21 is covered with the second protective film 23. The first protective film 21 and the second protective film 23 are, for example, polyimide films.

FIG. 3 is a cross-sectional view showing the structure of the portion BB′ of FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 3 shows the structure of the silicon carbide semiconductor device below the gate electrode pad 22. As shown in FIG. 3, the silicon carbide semiconductor device according to the embodiment has a first main surface (front surface) of an n ⁺ type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example, (0001). The n-type silicon carbide epitaxial layer 2 is deposited on the surface (Si surface).

An n-type high concentration region 6 is provided on the surface of n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. A p-type silicon carbide epitaxial layer 3 is provided on the base body first main surface side of the n-type silicon carbide epitaxial layer 2. First p ⁺ type base region 4 is provided between n type high concentration region 6 and p type silicon carbide epitaxial layer 3.

As shown in FIG. 3, back electrode 14 is provided on the second main surface (back surface, that is, back surface of the silicon carbide semiconductor substrate) of n ⁺ type silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back electrode 14.

On the surface of p type silicon carbide epitaxial layer 3 opposite to the side of n ⁺ type silicon carbide substrate 1, a gate insulating film 9 for insulating the potential of the source from gate electrode 10 is provided. A gate polysilicon electrode 33 electrically connected to the gate electrode 10 is provided in the contact hole of the interlayer insulating film 11 on the gate insulating film 9, and a gate electrode pad 22 is provided on the gate polysilicon electrode 33. There is.

The plating film 16 is selectively provided on the gate electrode pad 22, and the solder 17 is selectively provided on the surface side of the plating film 16. The solder 17 is provided with an external terminal electrode 19 which is a wiring material for extracting the potential of the gate electrode 10 to the outside. The external terminal electrode 19 has a needle pin shape and is joined to the gate electrode pad 22 in an upright state.

The portion of the surface of the gate electrode pad 22 other than the plating film 16 is covered with the first protective film 21. Specifically, the first protective film 21 is provided so as to cover the gate electrode pad 22, and the external terminal electrode 19 is bonded to the opening of the first protective film 21 via the plating film 16 and the solder film 17. ing. The boundary between the plating film 16 and the first protective film 21 is covered with the second protective film 23. The first protective film 21 and the second protective film 23 are, for example, polyimide films.

FIG. 4 is a cross-sectional view showing the structure of the CC′ portion of FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 4 shows the structure of the silicon carbide semiconductor device below the gate resistor 34. As shown in FIG. 4, the silicon carbide semiconductor device according to the embodiment has a first main surface (front surface) of an n ⁺ -type silicon carbide substrate (first conductivity type semiconductor substrate) 1, for example, (0001). The n-type silicon carbide epitaxial layer 2 is deposited on the surface (Si surface).

An n-type high concentration region 6 is provided on the surface of n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side. A p-type silicon carbide epitaxial layer 3 is provided on the base body first main surface side of the n-type silicon carbide epitaxial layer 2. First p ⁺ type base region 4 is provided between n type high concentration region 6 and p type silicon carbide epitaxial layer 3.

As shown in FIG. 4, back electrode 14 is provided on the second main surface (back surface, that is, back surface of silicon carbide semiconductor substrate) of n ⁺ type silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back electrode 14.

A gate insulating film 9 for insulating the gate electrode 10 from the source potential is provided on the surface of p type silicon carbide epitaxial layer 3 opposite to the side of n ⁺ type silicon carbide substrate 1. A gate resistor 34 is provided in the interlayer insulating film 11 on the gate insulating film 9. A first protective film 21 and a plating film 16 are provided on the interlayer insulating film 11.

FIG. 5 is a cross-sectional view showing the structure of the portion D-D′ of FIG. 1 of the silicon carbide semiconductor device according to the embodiment. FIG. 5 shows the structure of the silicon carbide semiconductor device below gate resistance 34 in a direction different from that of FIG. The shape from the back surface electrode 14 to the gate insulating film 9 is the same as that in FIG.

As shown in FIG. 5, a gate polysilicon electrode 33 and a gate resistor 34 are provided on the gate insulating film 9 so as to be separated from each other. By providing the gate electrode pad 22 between them, the gate polysilicon electrode 33 and the gate resistor 34 are electrically connected. A first protective film 21 is provided on the gate electrode pad 22 and the gate resistor 34, and a plating film is provided on the first protective film 21.

FIG. 6 is a graph showing the GS short-circuit rates of the silicon carbide semiconductor device according to the embodiment and the conventional silicon carbide semiconductor device. The GS short-circuit rate refers to the proportion of silicon carbide semiconductor devices in which the gate electrode 10 and the source electrode 13 are short-circuited in the manufactured silicon carbide semiconductor device. The short circuit between the gate electrode 10 and the source electrode 13 includes a short circuit between the source electrode 13 and the gate resistor 34 due to the solder 17.

As shown in FIG. 6, the GS short-circuit rate is about 40% in the conventional silicon carbide semiconductor device, while it is 0% in the silicon carbide semiconductor device according to the embodiment, and the gate resistance is within the element. It can be seen that the short circuit between the source electrode and the gate resistance can be prevented even when it is built in.

(Method of Manufacturing Silicon Carbide Semiconductor Device According to Embodiment)
Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described. 7 to 13 are cross-sectional views schematically showing a state in which the silicon carbide semiconductor device according to the embodiment is being manufactured.

First, an n ⁺ type silicon carbide substrate 1 made of n type silicon carbide is prepared. Then, a first n-type silicon carbide epitaxial layer 2a made of silicon carbide is doped on the first main surface of the n ⁺ -type silicon carbide substrate 1 while being doped with n-type impurities, for example, nitrogen atoms, and has a thickness of, for example, about 30 μm. Until then, epitaxially grow. This first n-type silicon carbide epitaxial layer 2a becomes n-type silicon carbide epitaxial layer 2 as described later. The state thus far is shown in FIG.

Then, on the surface of the first n-type silicon carbide epitaxial layer 2a, an ion implantation mask having a predetermined opening is formed of, for example, an oxide film by a photolithography technique. Then, a p-type impurity such as aluminum is injected into the opening of the oxide film to form the lower first p ⁺ -type base region 4a having a depth of about 0.5 μm. The second p ⁺ -type base region 5 to be the bottom of the trench 18 may be formed simultaneously with the lower first p ⁺ -type base region 4a. The first lower p ⁺ type base region 4a and the second lower p ⁺ type base region 5 adjacent to each other are formed to have a distance of about 1.5 μm. The impurity concentration of the lower first p ⁺ type base region 4a and the second p ⁺ type base region 5 is set to, for example, about 5×10 ¹⁸ /cm ³ . The state thus far is shown in FIG.

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening, and a part of the surface region of the first n-type silicon carbide epitaxial layer 2a has a depth of, for example, 0. A lower n-type high concentration region 6a of about 5 μm is provided. The impurity concentration of the lower n-type high concentration region 6a is set to, for example, about 1×10 ¹⁷ /cm ³ .

Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of the first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is set to be about 3×10 ¹⁵ /cm ³ . Thereafter, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b are combined to form the n-type silicon carbide epitaxial layer 2.

Next, on the surface of the second n-type silicon carbide epitaxial layer 2b, an ion implantation mask having a predetermined opening is formed by photolithography using, for example, an oxide film. Then, a p-type impurity such as aluminum is injected into the opening of the oxide film to form an upper first p ⁺ -type base region 4b having a depth of about 0.5 μm so as to overlap the lower first p ⁺ -type base region 4a. To do. The lower first p ⁺ -type base region 4a and the upper first p ⁺ -type base region 4b form a continuous region and become the first p ⁺ -type base region 4. The impurity concentration of the upper first p ⁺ type base region 4b is set to be, for example, about 5×10 ¹⁸ /cm ³ .

Next, a part of the ion implantation mask is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening to form a part of the surface region of the second silicon carbide epitaxial layer 2b at a depth of 0.5 μm, for example. The upper n-type high-concentration region 6b is provided to some extent. The impurity concentration of the upper n-type high concentration region 6b is set to, for example, about 1×10 ¹⁷ /cm ³ . The upper n-type high-concentration region 6b and the lower n-type high-concentration region 6a are formed so that at least a part thereof is in contact with each other to form the n-type high-concentration region 6. However, this n-type high concentration region 6 may or may not be formed on the entire surface of the substrate. The state thus far is shown in FIG.

Next, on the surface of the n-type silicon carbide epitaxial layer 2, a p-type silicon carbide epitaxial layer 3 doped with a p-type impurity such as aluminum is formed with a thickness of about 1.3 μm. The impurity concentration of the p-type silicon carbide epitaxial layer 3 is set to about 4×10 ¹⁷ /cm ³ . The state thus far is shown in FIG.

Next, on the surfaces of p-type silicon carbide epitaxial layer 3 and exposed n-type silicon carbide epitaxial layer 2, an ion implantation mask having a predetermined opening is formed by photolithography, for example, an oxide film. An n-type impurity such as phosphorus (P) is ion-implanted into this opening to form an n ⁺ -type source region 7 on a part of the surface of the p-type silicon carbide epitaxial layer 3. The impurity concentration of n ⁺ type source region 7 is set to be higher than the impurity concentration of p type silicon carbide epitaxial layer 3. Next, the ion implantation mask used for forming the n ⁺ type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed by the same method, and the surface of the p-type silicon carbide epitaxial layer 3 is removed. A p ⁺ -type contact region 8 is provided by ion-implanting a p-type impurity such as aluminum into a part of the. The impurity concentration of p ^{+ +} type contact region 8 is set to be higher than the impurity concentration of p type silicon carbide epitaxial layer 3. The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to remove the first p ⁺ type base region 4, the second p ⁺ type base region 5, the n ⁺ type source region 7, and the p ^{+ +} type contact region 8. Perform activation processing. As described above, the ion implantation regions may be collectively activated by one heat treatment, or the heat treatment may be performed and activated each time ion implantation is performed.

Next, on the surface of the p-type silicon carbide epitaxial layer 3, a mask for forming a trench having a predetermined opening is formed of, for example, an oxide film by photolithography. Next, a trench 18 penetrating the p-type silicon carbide epitaxial layer 3 and reaching the n-type high concentration region 6 is formed by dry etching. The bottom of the trench 18 may reach the first p ⁺ type base region 4 formed in the n type high concentration region 6. Then, the trench forming mask is removed. The state up to this point is shown in FIG.

Next, the gate insulating film 9 is formed along the surface of the n ⁺ type source region 7 and the bottom and side walls of the trench 18. The gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Further, the gate insulating film 9 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. The polycrystalline silicon layer may be formed so as to fill the trench 18. The gate electrode 10 is formed by patterning this polycrystalline silicon layer by photolithography and leaving it inside the trench 18.

Next, for example, phosphorous glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10 to form an interlayer insulating film 11. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form contact holes exposing the n ⁺ type source regions 7 and the p ⁺⁺ type contact regions 8. Then, heat treatment (reflow) is performed to planarize the interlayer insulating film 11. The state so far is shown in FIG.

Next, a conductive film to be the source electrode 13 is provided in the contact hole and on the interlayer insulating film 11. This conductive film is selectively removed to leave the source electrode 13 only in the contact hole, and the n ⁺ type source region 7 and the p ⁺ type contact region 8 are brought into contact with the source electrode 13. Next, the source electrode 13 other than the contact holes is selectively removed.

Next, a polycrystalline silicon film is formed and patterned to form a gate polysilicon electrode 33 on the outer peripheral portion of the active region 40. At this time, the gate resistor 34 is formed in a predetermined region of the gate polysilicon electrode 33 (a region sandwiched between the gate electrode pad 22 and the edge termination region 41).

Next, by, for example, a sputtering method, electrode pads to be the gate electrode pad 22 and the source electrode pad 15 are deposited on the source electrode 13 on the front surface of the silicon carbide semiconductor substrate and on the opening of the interlayer insulating film 11. For example, the first TiN film 25, the first Ti film 26, the second TiN film 27, and the second Ti film 28 are stacked by a sputtering method, and the Al alloy film 29 is formed to have a thickness of, for example, about 5 μm. The Al alloy film 29 may be an Al film. The Al alloy film 29 is, for example, an Al-Si film or an Al-Si-Cu film. This conductive film is patterned by photolithography and left in the active region 40 of the entire device to form the source electrode pad 15 and the gate electrode pad 22. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be formed of aluminum (Al-Si) containing silicon at a rate of 1%, for example. Next, the gate electrode pad 22 and the source electrode pad 15 are selectively removed.

Next, a polyimide film is formed so as to cover the gate electrode pad 22 and the source electrode pad 15. Next, the polyimide film is selectively removed by photolithography and etching to form a first protective film 21 that covers the gate electrode pad 22 and the source electrode pad 15, and the first protective film 21 is opened. ..

Next, the plating film 16 is selectively formed on the gate electrode pad 22 and the source electrode pad 15, and the second protective film 23 that covers each boundary between the plating film 16 and the first protective film 21 is formed. Next, the external terminal electrode 19 is formed on the plating film 16 via the solder 17.

Next, back electrode 14 made of nickel or the like is provided on the second main surface of n ⁺ type silicon carbide semiconductor substrate 1. Then, heat treatment is performed in an inert gas atmosphere at about 1000° C. to form the n ⁺ type source region 7, the p ⁺⁺ type contact region 8 and the back surface electrode 14 which makes ohmic contact with the n ⁺ type silicon carbide semiconductor substrate 1. .. As described above, the silicon carbide semiconductor device shown in FIGS. 1 to 4 is completed.

As described above, according to the silicon carbide semiconductor device of the embodiment, the gate resistance is provided at the portion of the gate polysilicon electrode sandwiched between the gate electrode pad and the edge termination region. This can prevent the source electrode and the gate resistance from being short-circuited. Further, since the gate resistance is not provided in the active region, the area of the active region does not decrease, and the on-resistance does not decrease due to the gate resistance.

In the above description of the present invention, the case where the main surface of the silicon carbide substrate made of silicon carbide is the (0001) plane and the MOS is formed on the (0001) plane has been described as an example, but the invention is not limited to this. It is possible to variously change the plane orientation of the semiconductor and the main surface of the substrate.

Further, although the trench type MOSFET has been described as an example in the embodiment of the present invention, the present invention is not limited to this, and can be applied to semiconductor devices of various configurations such as a planar type MOSFET and a MOS type semiconductor device such as an IGBT. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide band gap semiconductor has been described as an example, but the same applies when a wide band gap semiconductor other than silicon carbide such as gallium nitride (GaN) is used. The effect is obtained. Further, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is the same even if the first conductivity type is p-type and the second conductivity type is n-type. It holds.

INDUSTRIAL APPLICABILITY As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a high breakdown voltage semiconductor device used for a power converter and a power supply device for various industrial machines.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 2a first n type silicon carbide epitaxial layer 2b second n type silicon carbide epitaxial layer 3 p type silicon carbide epitaxial layer (base layer)
4 first p ⁺ type base region 4a lower first p ⁺ type base region 4b upper first p ⁺ type base region 5 second p ⁺ type base region 6 n-type high concentration region 6a lower n-type high concentration region 6b upper n-type high concentration region 7 n ⁺ type source region 8 p ⁺⁺ type contact region 9 gate insulating film 10 gate electrode 11 interlayer insulating film 12 insulating film 13 source electrode 14 back electrode 15, 115 source electrode pad 16, 116 plating film 17 solder 18 trench 19 external Terminal electrodes 21, 121 First protective films 22, 122 Gate electrode pad 23 Second protective film 25 First TiN film 26 First Ti film 27 Second TiN film 28 Second Ti film 29 Al alloy films 33, 133 Gate polysilicon electrodes 34, 134 Gate resistance 35 Gate resistance pads 40, 140 Active regions 41, 141 Edge termination regions 50, 150 Semiconductor chip

Claims (5)

A first conductivity type semiconductor substrate;
A first conductive type first semiconductor layer provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
A second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side;
A first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side;
A gate insulating film in contact with the second semiconductor layer;
A gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
A first electrode provided on the surfaces of the second semiconductor layer and the first semiconductor region;
A plating film selectively provided on the first electrode,
A solder film selectively provided on the plating film,
A second electrode provided on the back surface of the semiconductor substrate;
A gate wiring that is electrically connected to the gate electrode and surrounds an active region in which a main current flows when in an ON state,
A gate electrode pad to which a gate signal is input,
A gate resistance provided in a portion facing the solder film in a region sandwiched between the gate electrode pad and the gate wiring,
A semiconductor device comprising: A trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer,
The semiconductor device according to claim 1, wherein the gate electrode is provided inside the trench via the gate insulating film. The semiconductor device according to claim 1, further comprising a gate resistance pad electrically connected to the gate wiring for evaluating the gate resistance. The semiconductor device according to claim 1, wherein the gate resistor is adjacent to the first electrode. A first step of forming, on the front surface of the first conductivity type semiconductor substrate, a first conductivity type first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate;
A second step of selectively forming a second semiconductor layer of the second conductivity type on a surface of the first semiconductor layer opposite to the semiconductor substrate side;
A third step of selectively forming a first conductive type first semiconductor region on a surface layer of the second semiconductor layer opposite to the semiconductor substrate side;
A fourth step of forming a gate insulating film in contact with the second semiconductor layer,
A fifth step of forming a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer;
A sixth step of forming an interlayer insulating film on the gate electrode,
A seventh step of forming a first electrode on the surfaces of the second semiconductor layer and the first semiconductor region;
An eighth step of selectively forming a plating film on the first electrode,
A ninth step of selectively forming a solder film on the plating film,
A tenth step of forming a second electrode on the back surface of the semiconductor substrate;
An eleventh step of forming a gate wiring which is electrically connected to the gate electrode and surrounds an active region in which a main current flows in an ON state;
A twelfth step of forming a gate electrode pad to which a gate signal is input;
A thirteenth step of forming a gate resistor in a portion facing the solder film in a region sandwiched between the gate electrode pad and the gate wiring;
A method of manufacturing a semiconductor device, comprising:

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