JP2016531515A5 - - Google Patents

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JP2016531515A5
JP2016531515A5 JP2016536383A JP2016536383A JP2016531515A5 JP 2016531515 A5 JP2016531515 A5 JP 2016531515A5 JP 2016536383 A JP2016536383 A JP 2016536383A JP 2016536383 A JP2016536383 A JP 2016536383A JP 2016531515 A5 JP2016531515 A5 JP 2016531515A5
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challenge
response
function
physical
electronic device
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JP2016531515A (ja
JP6515100B2 (ja
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JP2016536383A 2013-08-23 2014-08-19 侵襲的なクローンアタックに抵抗するためのメモリベースｐｕｆのマスキング演算への回路遅延ベース物理的クローン化不能関数（ｐｕｆ）の適用 Active JP6515100B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/975,082 2013-08-23
US13/975,082 US9787480B2 (en) 2013-08-23 2013-08-23 Applying circuit delay-based physically unclonable functions (PUFs) for masking operation of memory-based PUFs to resist invasive and clone attacks
PCT/US2014/051718 WO2015026838A1 (en) 2013-08-23 2014-08-19 Applying circuit delay-based physically unclonable functions (pufs) for masking operation of memory-based pufs to resist invasive and clone attacks

Publications (3)

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JP2016531515A JP2016531515A (ja) 2016-10-06
JP2016531515A5 true JP2016531515A5 (enExample) 2017-09-07
JP6515100B2 JP6515100B2 (ja) 2019-05-15

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JP2016536383A Active JP6515100B2 (ja) 2013-08-23 2014-08-19 侵襲的なクローンアタックに抵抗するためのメモリベースｐｕｆのマスキング演算への回路遅延ベース物理的クローン化不能関数（ｐｕｆ）の適用

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US (2) US9787480B2 (enExample)
EP (1) EP3036621B1 (enExample)
JP (1) JP6515100B2 (enExample)
KR (1) KR102168502B1 (enExample)
CN (2) CN105474167B (enExample)
WO (1) WO2015026838A1 (enExample)

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