JP2016529639A5 - - Google Patents

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Publication number
JP2016529639A5
JP2016529639A5 JP2016540900A JP2016540900A JP2016529639A5 JP 2016529639 A5 JP2016529639 A5 JP 2016529639A5 JP 2016540900 A JP2016540900 A JP 2016540900A JP 2016540900 A JP2016540900 A JP 2016540900A JP 2016529639 A5 JP2016529639 A5 JP 2016529639A5
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JP
Japan
Prior art keywords
processor
owned
cache
processors
cache line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016540900A
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English (en)
Japanese (ja)
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JP2016529639A (ja
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Publication date
Priority claimed from US14/195,792 external-priority patent/US20150074357A1/en
Application filed filed Critical
Publication of JP2016529639A publication Critical patent/JP2016529639A/ja
Publication of JP2016529639A5 publication Critical patent/JP2016529639A5/ja
Pending legal-status Critical Current

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JP2016540900A 2013-09-09 2014-08-19 直接スヌープ介入 Pending JP2016529639A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361875436P 2013-09-09 2013-09-09
US61/875,436 2013-09-09
US14/195,792 US20150074357A1 (en) 2013-09-09 2014-03-03 Direct snoop intervention
US14/195,792 2014-03-03
PCT/US2014/051712 WO2015034667A1 (en) 2013-09-09 2014-08-19 Direct snoop intervention

Publications (2)

Publication Number Publication Date
JP2016529639A JP2016529639A (ja) 2016-09-23
JP2016529639A5 true JP2016529639A5 (enExample) 2017-09-07

Family

ID=52626708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016540900A Pending JP2016529639A (ja) 2013-09-09 2014-08-19 直接スヌープ介入

Country Status (6)

Country Link
US (1) US20150074357A1 (enExample)
EP (1) EP3044683A1 (enExample)
JP (1) JP2016529639A (enExample)
KR (1) KR20160053966A (enExample)
CN (1) CN105531683A (enExample)
WO (1) WO2015034667A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921962B2 (en) * 2015-09-24 2018-03-20 Qualcomm Incorporated Maintaining cache coherency using conditional intervention among multiple master devices
US10157133B2 (en) 2015-12-10 2018-12-18 Arm Limited Snoop filter for cache coherency in a data processing system
US9900260B2 (en) 2015-12-10 2018-02-20 Arm Limited Efficient support for variable width data channels in an interconnect network
US9990292B2 (en) * 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
US10042766B1 (en) 2017-02-02 2018-08-07 Arm Limited Data processing apparatus with snoop request address alignment and snoop response time alignment
US20200103956A1 (en) * 2018-09-28 2020-04-02 Qualcomm Incorporated Hybrid low power architecture for cpu private caches
US11507527B2 (en) * 2019-09-27 2022-11-22 Advanced Micro Devices, Inc. Active bridge chiplet with integrated cache
US11275688B2 (en) * 2019-12-02 2022-03-15 Advanced Micro Devices, Inc. Transfer of cachelines in a processing system based on transfer costs

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221311A (ja) * 1994-12-22 1996-08-30 Sun Microsyst Inc スーパースカラプロセッサにおけるロードバッファ及びストアバッファの優先順位の動的切換え
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US6662277B2 (en) * 2001-07-31 2003-12-09 Hewlett-Packard Development Company, L.P. Cache system with groups of lines and with coherency for both single lines and groups of lines
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US7676637B2 (en) * 2004-04-27 2010-03-09 International Business Machines Corporation Location-aware cache-to-cache transfers
US20060253662A1 (en) * 2005-05-03 2006-11-09 Bass Brian M Retry cancellation mechanism to enhance system performance
JP2007148952A (ja) * 2005-11-30 2007-06-14 Renesas Technology Corp 半導体集積回路
US8327158B2 (en) * 2006-11-01 2012-12-04 Texas Instruments Incorporated Hardware voting mechanism for arbitrating scaling of shared voltage domain, integrated circuits, processes and systems
US7870337B2 (en) * 2007-11-28 2011-01-11 International Business Machines Corporation Power-aware line intervention for a multiprocessor snoop coherency protocol
US20090138220A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor directory-based coherency protocol
EP2239578A1 (en) * 2009-04-10 2010-10-13 PamGene B.V. Method for determining the survival prognosis of patients suffering from non-small cell lung cancer (NSCLC)
US8190939B2 (en) * 2009-06-26 2012-05-29 Microsoft Corporation Reducing power consumption of computing devices by forecasting computing performance needs
JP4945611B2 (ja) * 2009-09-04 2012-06-06 株式会社東芝 マルチプロセッサ
US8667227B2 (en) * 2009-12-22 2014-03-04 Empire Technology Development, Llc Domain based cache coherence protocol
WO2012060824A1 (en) * 2010-11-02 2012-05-10 Hewlett-Packard Development Company, L.P. Solid-state disk (ssd) management

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