JP2016529639A - 直接スヌープ介入 - Google Patents

直接スヌープ介入 Download PDF

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Publication number
JP2016529639A
JP2016529639A JP2016540900A JP2016540900A JP2016529639A JP 2016529639 A JP2016529639 A JP 2016529639A JP 2016540900 A JP2016540900 A JP 2016540900A JP 2016540900 A JP2016540900 A JP 2016540900A JP 2016529639 A JP2016529639 A JP 2016529639A
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Japan
Prior art keywords
processor
cache line
cache
computer system
variables
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JP2016540900A
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English (en)
Japanese (ja)
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JP2016529639A5 (enExample
Inventor
ジョセフ・ジー・マクドナルド
ジャヤ・プラカシュ・スブラマニアム・ガナサン
トーマス・フィリップ・スパイアー
エリック・エフ・ロビンソン
ジェイソン・ローレンス・パナヴィッチ
トゥオン・キュー・トロン
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クアルコム，インコーポレイテッド
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Publication of JP2016529639A publication Critical patent/JP2016529639A/ja
Publication of JP2016529639A5 publication Critical patent/JP2016529639A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2016540900A 2013-09-09 2014-08-19 直接スヌープ介入 Pending JP2016529639A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361875436P 2013-09-09 2013-09-09
US61/875,436 2013-09-09
US14/195,792 US20150074357A1 (en) 2013-09-09 2014-03-03 Direct snoop intervention
US14/195,792 2014-03-03
PCT/US2014/051712 WO2015034667A1 (en) 2013-09-09 2014-08-19 Direct snoop intervention

Publications (2)

Publication Number Publication Date
JP2016529639A true JP2016529639A (ja) 2016-09-23
JP2016529639A5 JP2016529639A5 (enExample) 2017-09-07

Family

ID=52626708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016540900A Pending JP2016529639A (ja) 2013-09-09 2014-08-19 直接スヌープ介入

Country Status (6)

Country Link
US (1) US20150074357A1 (enExample)
EP (1) EP3044683A1 (enExample)
JP (1) JP2016529639A (enExample)
KR (1) KR20160053966A (enExample)
CN (1) CN105531683A (enExample)
WO (1) WO2015034667A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023504442A (ja) * 2019-12-02 2023-02-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 転送コストに基づく処理システムにおけるキャッシュラインの転送
JP2024102855A (ja) * 2019-09-27 2024-07-31 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 統合キャッシュを有するアクティブブリッジチップレット

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921962B2 (en) * 2015-09-24 2018-03-20 Qualcomm Incorporated Maintaining cache coherency using conditional intervention among multiple master devices
US10157133B2 (en) 2015-12-10 2018-12-18 Arm Limited Snoop filter for cache coherency in a data processing system
US9900260B2 (en) 2015-12-10 2018-02-20 Arm Limited Efficient support for variable width data channels in an interconnect network
US9990292B2 (en) * 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
US10042766B1 (en) 2017-02-02 2018-08-07 Arm Limited Data processing apparatus with snoop request address alignment and snoop response time alignment
US20200103956A1 (en) * 2018-09-28 2020-04-02 Qualcomm Incorporated Hybrid low power architecture for cpu private caches

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001101147A (ja) * 1999-08-26 2001-04-13 Internatl Business Mach Corp <Ibm> データ転送方法、コンピュータ・プログラム製品、データ転送システムおよびデータ処理システム
US20090138660A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor snoop coherency protocol
JP2009134716A (ja) * 2007-11-28 2009-06-18 Internatl Business Mach Corp <Ibm> マルチプロセッサ・データ処理システムにおいて共有キャッシュ・ラインを与える方法、コンピュータ読み取り可能な記録媒体及びマルチプロセッサ・データ処理システム
JP2011054077A (ja) * 2009-09-04 2011-03-17 Toshiba Corp マルチプロセッサ
JP2013515321A (ja) * 2009-12-22 2013-05-02 エンパイア テクノロジー ディベロップメント エルエルシー ドメインベースのキャッシュ・コヒーレンス・プロトコル

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08221311A (ja) * 1994-12-22 1996-08-30 Sun Microsyst Inc スーパースカラプロセッサにおけるロードバッファ及びストアバッファの優先順位の動的切換え
US6662277B2 (en) * 2001-07-31 2003-12-09 Hewlett-Packard Development Company, L.P. Cache system with groups of lines and with coherency for both single lines and groups of lines
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US7676637B2 (en) * 2004-04-27 2010-03-09 International Business Machines Corporation Location-aware cache-to-cache transfers
US20060253662A1 (en) * 2005-05-03 2006-11-09 Bass Brian M Retry cancellation mechanism to enhance system performance
JP2007148952A (ja) * 2005-11-30 2007-06-14 Renesas Technology Corp 半導体集積回路
US8327158B2 (en) * 2006-11-01 2012-12-04 Texas Instruments Incorporated Hardware voting mechanism for arbitrating scaling of shared voltage domain, integrated circuits, processes and systems
EP2239578A1 (en) * 2009-04-10 2010-10-13 PamGene B.V. Method for determining the survival prognosis of patients suffering from non-small cell lung cancer (NSCLC)
US8190939B2 (en) * 2009-06-26 2012-05-29 Microsoft Corporation Reducing power consumption of computing devices by forecasting computing performance needs
WO2012060824A1 (en) * 2010-11-02 2012-05-10 Hewlett-Packard Development Company, L.P. Solid-state disk (ssd) management

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001101147A (ja) * 1999-08-26 2001-04-13 Internatl Business Mach Corp <Ibm> データ転送方法、コンピュータ・プログラム製品、データ転送システムおよびデータ処理システム
US20090138660A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor snoop coherency protocol
JP2009134716A (ja) * 2007-11-28 2009-06-18 Internatl Business Mach Corp <Ibm> マルチプロセッサ・データ処理システムにおいて共有キャッシュ・ラインを与える方法、コンピュータ読み取り可能な記録媒体及びマルチプロセッサ・データ処理システム
JP2011054077A (ja) * 2009-09-04 2011-03-17 Toshiba Corp マルチプロセッサ
JP2013515321A (ja) * 2009-12-22 2013-05-02 エンパイア テクノロジー ディベロップメント エルエルシー ドメインベースのキャッシュ・コヒーレンス・プロトコル

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024102855A (ja) * 2019-09-27 2024-07-31 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 統合キャッシュを有するアクティブブリッジチップレット
JP2023504442A (ja) * 2019-12-02 2023-02-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 転送コストに基づく処理システムにおけるキャッシュラインの転送
JP7685495B2 (ja) 2019-12-02 2025-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 転送コストに基づく処理システムにおけるキャッシュラインの転送

Also Published As

Publication number Publication date
WO2015034667A1 (en) 2015-03-12
US20150074357A1 (en) 2015-03-12
EP3044683A1 (en) 2016-07-20
KR20160053966A (ko) 2016-05-13
CN105531683A (zh) 2016-04-27

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