CN105531683A - 定向窥探介入 - Google Patents

定向窥探介入 Download PDF

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Publication number
CN105531683A
CN105531683A CN201480049215.0A CN201480049215A CN105531683A CN 105531683 A CN105531683 A CN 105531683A CN 201480049215 A CN201480049215 A CN 201480049215A CN 105531683 A CN105531683 A CN 105531683A
Authority
CN
China
Prior art keywords
processor
variable
cache line
computer system
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480049215.0A
Other languages
English (en)
Chinese (zh)
Inventor
J·G·麦克唐纳
J·P·S·贾纳桑
T·P·施派尔
E·F·罗宾森
J·L·帕纳维哈
T·Q·特罗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105531683A publication Critical patent/CN105531683A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201480049215.0A 2013-09-09 2014-08-19 定向窥探介入 Pending CN105531683A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361875436P 2013-09-09 2013-09-09
US61/875,436 2013-09-09
US14/195,792 US20150074357A1 (en) 2013-09-09 2014-03-03 Direct snoop intervention
US14/195,792 2014-03-03
PCT/US2014/051712 WO2015034667A1 (en) 2013-09-09 2014-08-19 Direct snoop intervention

Publications (1)

Publication Number Publication Date
CN105531683A true CN105531683A (zh) 2016-04-27

Family

ID=52626708

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480049215.0A Pending CN105531683A (zh) 2013-09-09 2014-08-19 定向窥探介入

Country Status (6)

Country Link
US (1) US20150074357A1 (enExample)
EP (1) EP3044683A1 (enExample)
JP (1) JP2016529639A (enExample)
KR (1) KR20160053966A (enExample)
CN (1) CN105531683A (enExample)
WO (1) WO2015034667A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921962B2 (en) * 2015-09-24 2018-03-20 Qualcomm Incorporated Maintaining cache coherency using conditional intervention among multiple master devices
US10157133B2 (en) 2015-12-10 2018-12-18 Arm Limited Snoop filter for cache coherency in a data processing system
US9900260B2 (en) 2015-12-10 2018-02-20 Arm Limited Efficient support for variable width data channels in an interconnect network
US9990292B2 (en) * 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
US10042766B1 (en) 2017-02-02 2018-08-07 Arm Limited Data processing apparatus with snoop request address alignment and snoop response time alignment
US20200103956A1 (en) * 2018-09-28 2020-04-02 Qualcomm Incorporated Hybrid low power architecture for cpu private caches
US11507527B2 (en) * 2019-09-27 2022-11-22 Advanced Micro Devices, Inc. Active bridge chiplet with integrated cache
US11275688B2 (en) * 2019-12-02 2022-03-15 Advanced Micro Devices, Inc. Transfer of cachelines in a processing system based on transfer costs

Citations (7)

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Publication number Priority date Publication date Assignee Title
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US20030028730A1 (en) * 2001-07-31 2003-02-06 Gaither Blaine D. Cache system with groups of lines and with coherency for both single lines and groups of lines
US20050240735A1 (en) * 2004-04-27 2005-10-27 International Business Machines Corporation Location-aware cache-to-cache transfers
CN1858721A (zh) * 2005-05-03 2006-11-08 国际商业机器公司 用于处理多处理器系统中的存储器访问的方法和装置
US20090138660A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor snoop coherency protocol
US20110060880A1 (en) * 2009-09-04 2011-03-10 Kabushiki Kaisha Toshiba Multiprocessor
US20130179631A1 (en) * 2010-11-02 2013-07-11 Darren J. Cepulis Solid-state disk (ssd) management

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
JPH08221311A (ja) * 1994-12-22 1996-08-30 Sun Microsyst Inc スーパースカラプロセッサにおけるロードバッファ及びストアバッファの優先順位の動的切換え
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
JP2007148952A (ja) * 2005-11-30 2007-06-14 Renesas Technology Corp 半導体集積回路
US8327158B2 (en) * 2006-11-01 2012-12-04 Texas Instruments Incorporated Hardware voting mechanism for arbitrating scaling of shared voltage domain, integrated circuits, processes and systems
US20090138220A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor directory-based coherency protocol
EP2239578A1 (en) * 2009-04-10 2010-10-13 PamGene B.V. Method for determining the survival prognosis of patients suffering from non-small cell lung cancer (NSCLC)
US8190939B2 (en) * 2009-06-26 2012-05-29 Microsoft Corporation Reducing power consumption of computing devices by forecasting computing performance needs
US8667227B2 (en) * 2009-12-22 2014-03-04 Empire Technology Development, Llc Domain based cache coherence protocol

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US20030028730A1 (en) * 2001-07-31 2003-02-06 Gaither Blaine D. Cache system with groups of lines and with coherency for both single lines and groups of lines
US20050240735A1 (en) * 2004-04-27 2005-10-27 International Business Machines Corporation Location-aware cache-to-cache transfers
CN1858721A (zh) * 2005-05-03 2006-11-08 国际商业机器公司 用于处理多处理器系统中的存储器访问的方法和装置
US20090138660A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor snoop coherency protocol
US20110060880A1 (en) * 2009-09-04 2011-03-10 Kabushiki Kaisha Toshiba Multiprocessor
US20130179631A1 (en) * 2010-11-02 2013-07-11 Darren J. Cepulis Solid-state disk (ssd) management

Also Published As

Publication number Publication date
WO2015034667A1 (en) 2015-03-12
KR20160053966A (ko) 2016-05-13
EP3044683A1 (en) 2016-07-20
JP2016529639A (ja) 2016-09-23
US20150074357A1 (en) 2015-03-12

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Effective date of abandoning: 20190809