JP2016527718A5 - - Google Patents
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- JP2016527718A5 JP2016527718A5 JP2016527976A JP2016527976A JP2016527718A5 JP 2016527718 A5 JP2016527718 A5 JP 2016527718A5 JP 2016527976 A JP2016527976 A JP 2016527976A JP 2016527976 A JP2016527976 A JP 2016527976A JP 2016527718 A5 JP2016527718 A5 JP 2016527718A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG201305439-0 | 2013-07-16 | ||
| SG2013054390 | 2013-07-16 | ||
| PCT/SG2014/000335 WO2015009238A1 (en) | 2013-07-16 | 2014-07-16 | Method and apparatus for chip-to-wafer integration |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016527718A JP2016527718A (ja) | 2016-09-08 |
| JP2016527718A5 true JP2016527718A5 (ja) | 2017-08-24 |
| JP6446450B2 JP6446450B2 (ja) | 2018-12-26 |
Family
ID=52346559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016527976A Active JP6446450B2 (ja) | 2013-07-16 | 2014-07-16 | チップをウェハに対し集積する方法及びその装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9613928B2 (ja) |
| JP (1) | JP6446450B2 (ja) |
| SG (1) | SG11201600268YA (ja) |
| WO (1) | WO2015009238A1 (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190116198A (ko) * | 2019-09-24 | 2019-10-14 | 엘지전자 주식회사 | 마이크로 led를 이용한 디스플레이 장치 및 이의 제조 방법 |
| WO2021188042A1 (en) * | 2020-03-18 | 2021-09-23 | Airise Pte. Ltd. | Bonding apparatus, system, and method of bonding |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933042A (en) * | 1986-09-26 | 1990-06-12 | General Electric Company | Method for packaging integrated circuit chips employing a polymer film overlay layer |
| WO1988002551A1 (en) * | 1986-09-26 | 1988-04-07 | General Electric Company | Method and apparatus for packaging integrated circuit chips employing a polymer film overlay layer |
| US5352629A (en) * | 1993-01-19 | 1994-10-04 | General Electric Company | Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules |
| US5605547A (en) * | 1995-03-27 | 1997-02-25 | Micron Technology, Inc. | Method and apparatus for mounting a component to a substrate using an anisotropic adhesive, a compressive cover film, and a conveyor |
| JP2010153670A (ja) * | 2008-12-26 | 2010-07-08 | Panasonic Corp | フリップチップ実装方法と半導体装置 |
| JP2011124413A (ja) * | 2009-12-11 | 2011-06-23 | Murata Mfg Co Ltd | 電子部品モジュールの製造方法及び電子部品モジュール |
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2014
- 2014-07-16 US US14/904,670 patent/US9613928B2/en active Active
- 2014-07-16 SG SG11201600268YA patent/SG11201600268YA/en unknown
- 2014-07-16 JP JP2016527976A patent/JP6446450B2/ja active Active
- 2014-07-16 WO PCT/SG2014/000335 patent/WO2015009238A1/en active Application Filing