SG11201600268YA - Method and apparatus for chip-to-wafer integration - Google Patents

Method and apparatus for chip-to-wafer integration

Info

Publication number
SG11201600268YA
SG11201600268YA SG11201600268YA SG11201600268YA SG11201600268YA SG 11201600268Y A SG11201600268Y A SG 11201600268YA SG 11201600268Y A SG11201600268Y A SG 11201600268YA SG 11201600268Y A SG11201600268Y A SG 11201600268YA SG 11201600268Y A SG11201600268Y A SG 11201600268YA
Authority
SG
Singapore
Prior art keywords
chip
wafer integration
wafer
integration
Prior art date
Application number
SG11201600268YA
Other languages
English (en)
Inventor
Sunil Wickramanayaka
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Priority to SG11201600268YA priority Critical patent/SG11201600268YA/en
Publication of SG11201600268YA publication Critical patent/SG11201600268YA/en

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    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
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    • H01L2224/83909—Post-treatment of the layer connector or bonding area
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    • H01L2224/921—Connecting a surface with connectors of different types
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
SG11201600268YA 2013-07-16 2014-07-16 Method and apparatus for chip-to-wafer integration SG11201600268YA (en)

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SG11201600268YA SG11201600268YA (en) 2013-07-16 2014-07-16 Method and apparatus for chip-to-wafer integration
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US4933042A (en) * 1986-09-26 1990-06-12 General Electric Company Method for packaging integrated circuit chips employing a polymer film overlay layer
WO1988002551A1 (en) * 1986-09-26 1988-04-07 General Electric Company Method and apparatus for packaging integrated circuit chips employing a polymer film overlay layer
US5352629A (en) * 1993-01-19 1994-10-04 General Electric Company Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
US5605547A (en) * 1995-03-27 1997-02-25 Micron Technology, Inc. Method and apparatus for mounting a component to a substrate using an anisotropic adhesive, a compressive cover film, and a conveyor
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