JP2016501454A5 - - Google Patents

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JP2016501454A5
JP2016501454A5 JP2015540900A JP2015540900A JP2016501454A5 JP 2016501454 A5 JP2016501454 A5 JP 2016501454A5 JP 2015540900 A JP2015540900 A JP 2015540900A JP 2015540900 A JP2015540900 A JP 2015540900A JP 2016501454 A5 JP2016501454 A5 JP 2016501454A5
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cell
buffer status
available data
reporting
status value
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JP2015540900A
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JP6009686B2 (ja
JP2016501454A (ja
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Priority claimed from US13/915,583 external-priority patent/US9264930B2/en
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JP2015540900A 2012-11-07 2013-11-06 デュアル接続性におけるバッファステータス報告および論理チャネル優先度付け Active JP6009686B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261723698P 2012-11-07 2012-11-07
US61/723,698 2012-11-07
US13/915,583 US9264930B2 (en) 2012-11-07 2013-06-11 Buffer status reporting and logical channel prioritization in multiflow operation
US13/915,583 2013-06-11
PCT/US2013/068827 WO2014074656A2 (en) 2012-11-07 2013-11-06 Buffer status reporting and logical channel prioritization in multiflow operation

Related Child Applications (1)

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JP2016179663A Division JP6498642B2 (ja) 2012-11-07 2016-09-14 デュアル接続性におけるバッファステータス報告および論理チャネル優先度付け

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JP2016501454A JP2016501454A (ja) 2016-01-18
JP2016501454A5 true JP2016501454A5 (enExample) 2016-06-02
JP6009686B2 JP6009686B2 (ja) 2016-10-19

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JP2015540900A Active JP6009686B2 (ja) 2012-11-07 2013-11-06 デュアル接続性におけるバッファステータス報告および論理チャネル優先度付け
JP2016179663A Active JP6498642B2 (ja) 2012-11-07 2016-09-14 デュアル接続性におけるバッファステータス報告および論理チャネル優先度付け

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Country Status (8)

Country Link
US (2) US9264930B2 (enExample)
EP (2) EP2918120B1 (enExample)
JP (2) JP6009686B2 (enExample)
KR (2) KR102082162B1 (enExample)
CN (1) CN104871622B (enExample)
ES (2) ES2660049T3 (enExample)
HU (2) HUE046062T2 (enExample)
WO (1) WO2014074656A2 (enExample)

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