JP2016225556A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce compressive strain applied to a layer composed of semiconductor where an effectiveness mass of electrons which compose a channel layer is small.SOLUTION: A semiconductor device at least comprises a semiconductor laminated structure 26 including an electron transit layer 24 and an electron supply layer 25 above a substrate 10. The electron transit layer is made of group III-V compound semiconductor and has a structure where a first layer 13, a second layer 15 and a third layer 17 are sequentially laminated, in which the second layer is made of semiconductor with effective mass smaller than that of the first layer or the third layer; and conduction band energy of the second layer is lower than conduction band energy of the first layer or the third layer; and an interface of the first layer and the second layer, and an interface of the second layer and the third layer have mixed crystal areas 14, 16 where a group V element of the group III-V compound semiconductor is substituted by a group V element with an atomic radius larger than that of the group V element of the group III-V semiconductor, respectively.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

For example, there is a high electron mobility transistor (HEMT) as one of ultrahigh-speed transistors for communication that can operate in a millimeter wave band (about 30 to about 300 GHz) or a submillimeter wave band (about 300 GHz to about 3 THz). .
For example, as a HEMT using a group III-V compound semiconductor, for example, an InAlAs / InGaAs-based HEMT or AlGaAs using InGaAs for the channel layer (electron transit layer) and InAlAs or AlGaAs for the electron supply layer (barrier layer). / InGaAs-based HEMT, or AlGaAs / InGaP-based HEMT or InAlP / InGaP-based HEMT using InGaP for the channel layer and AlGaAs or InAlP for the electron supply layer.

In order to realize such high-speed HEMT by shortening the intrinsic delay time, there are methods such as reducing the gate length and increasing the electron velocity in the channel layer.
Among these, in order to increase the electron velocity in the channel layer, a semiconductor with a low effective mass of electrons may be used for the channel layer.

Therefore, there is a composite channel HEMT in which a layer made of a semiconductor having a low electron effective mass is provided in the channel layer of the HEMT.
For example, there is an InGaAs / InAs / InGaAs composite channel HEMT in which an InAs layer made of InAs, which is a semiconductor with a low effective electron mass, is provided in an InGaAs channel layer of InAlAs / InGaAs-based HEMT or AlGaAs / InGaAs-based HEMT. Further, for example, there is an InGaP / InP / InGaP composite channel HEMT in which an InP layer made of InP, which is a semiconductor having a low electron effective mass, is provided in an InGaP channel layer of an AlGaAs / InGaP-based HEMT or InAlP / InGaP-based HEMT.

JP 2002-313815 A JP-A-9-205197 Special table 2012-523712 gazette

By the way, in an InGaAs / InAs / InGaAs composite channel HEMT, for example, the channel layer has a structure in which an InGaAs layer, an InAs layer, and an InGaAs layer are stacked in order, and the InAs layer is made of a semiconductor having a lighter effective mass of electrons than the InGaAs layer. It is a layer.
In this case, since the lattice constant of InAs is larger than that of InGaAs, compressive strain is applied to the InAs layer constituting the channel layer.

The InAs layer to which compressive strain is applied has an effective electron mass that is higher than that of the unstrained InAs layer. As a result, the effectiveness of InAs, which is a semiconductor having a low effective electron mass, cannot be fully utilized. This is not preferable for speeding up the HEMT.
Further, when compressive strain is applied to the InAs layer, the crystal of the InAs layer is deteriorated. As a result, it is difficult to increase the thickness of the InAs layer. If the InAs layer cannot be increased, electrons cannot be sufficiently stored in the InAs layer, and electrons spread to the InGaAs layer sandwiching the InAs layer. become. This is not preferable for speeding up the HEMT.

In addition, although it demonstrated as a subject in InGaAs / InAs / InGaAs composite channel HEMT here, the same subject exists also in composite channel HEMT (for example, InGaP / InP / InGaP composite channel HEMT) of another material system.
Therefore, it is desired to reduce the compressive strain applied to the layer made of a semiconductor having a light effective mass of electrons constituting the channel layer.

  The semiconductor device includes a semiconductor stacked structure including at least an electron transit layer and an electron supply layer above a substrate, and the electron transit layer is made of a III-V group compound semiconductor, and includes a first layer, a second layer, and a third layer. Are stacked in order, the second layer is made of a semiconductor having a lighter effective mass of electrons than the first layer and the third layer, and the energy of the conduction band of the second layer is that of the first layer and the third layer. The group V element of the group III-V compound semiconductor is lower than the energy of the conduction band at the interface between the first layer and the second layer and the interface between the second layer and the third layer. It has a mixed crystal region substituted with a group V element having an atomic radius larger than that of a group V element.

  The method for manufacturing a semiconductor device includes a step of forming a semiconductor multilayer structure including at least an electron transit layer and an electron supply layer above a substrate, and the step of forming the electron transit layer includes a step of forming a group III-V compound semiconductor. Forming one layer, and forming on the first layer a second layer made of a III-V compound semiconductor having a lighter effective mass of electrons than that of the first layer and having a conduction band energy lower than that of the first layer; Forming a third layer made of a III-V group compound semiconductor having a larger effective mass of electrons than that of the second layer on the second layer and having a conduction band energy higher than that of the second layer; , Between the step of forming the first layer and the step of forming the second layer, and between the step of forming the second layer and the step of forming the third layer, a group V element of a III-V group compound semiconductor A step of irradiating a group V element having a larger atomic radius.

  Therefore, according to the semiconductor device and the manufacturing method thereof, there is an advantage that the compressive strain applied to the layer made of a semiconductor having a light effective mass of electrons constituting the channel layer can be reduced.

1 is a schematic cross-sectional view showing a configuration of a semiconductor device (InAlAs / InGaAs-based HEMT; InGaAs / InAs / InGaAs composite channel HEMT) according to an embodiment. It is a schematic diagram showing a conduction band structure of the semiconductor device (InAlAs / InGaAs-based HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of the present embodiment. It is typical sectional drawing which shows the structure of a general semiconductor device (InAlAs / InGaAs type | system | group HEMT; InGaAs / InAs / InGaAs composite channel HEMT). It is a schematic diagram showing a conduction band structure of a general semiconductor device (InAlAs / InGaAs-based HEMT; InGaAs / InAs / InGaAs composite channel HEMT). It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing for demonstrating the manufacturing method of the semiconductor device (InAlAs / InGaAs type HEMT; InGaAs / InAs / InGaAs composite channel HEMT) of this embodiment. It is typical sectional drawing which shows the structure of the semiconductor device (InAlP / InGaP type | system | group HEMT; InGaP / InP / InGaP composite channel HEMT) of the modification of this embodiment. It is a schematic diagram which shows the conduction band structure of the semiconductor device (InAlP / InGaP type HEMT; InGaP / InP / InGaP composite channel HEMT) of the modification of this embodiment. It is typical sectional drawing which shows the structure of a common semiconductor device (InAlP / InGaP type | system | group HEMT; InGaP / InP / InGaP composite channel HEMT). It is a schematic diagram showing a conduction band structure of a general semiconductor device (InAlP / InGaP-based HEMT; InGaP / InP / InGaP composite channel HEMT).

A semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.
The semiconductor device according to the present embodiment includes, for example, a HEMT using a III-V group compound semiconductor, that is, one of ultra-high speed transistors used for communication, that is, a HEMT having a III-V group compound semiconductor heterostructure.

  In the present embodiment, the semiconductor device is, for example, a HEMT having a semiconductor laminated structure using an InAlAs / InGaAs-based compound semiconductor as a III-V group compound semiconductor on a substrate, that is, InGaAs is used for an electron transit layer (channel layer). In use, the electron supply layer (barrier layer) includes an InAlAs / InGaAs-based HEMT (InGaAs channel HEMT) using InAlAs.

The HEMT is a transistor that can operate in a millimeter wave (about 30 to about 300 GHz) or submillimeter wave (about 300 GHz to about 3 THz) region, for example.
As shown in FIG. 1, the present InAlAs / InGaAs-based HEMT includes a substrate 10, a semiconductor stacked structure 26 provided on the substrate 10, a gate electrode 33, a source electrode 31 and a drain provided on the semiconductor stacked structure 26. And an electrode 32.

In the present embodiment, the substrate 10 is a semi-insulating InP substrate [for example, a semi-insulating (100) InP substrate; a semiconductor substrate]. As the substrate 10, a GaAs substrate or Si substrate can also be used.
The semiconductor multilayer structure 26 is a semiconductor multilayer structure including an electron transit layer 24 and an electron supply layer 25. Here, the semiconductor laminated structure 26 is a structure in which a buffer layer 11, a lower barrier layer 12, an electron transit layer (channel layer) 24, an electron supply layer (upper barrier layer) 25, an etching stop layer 21, and a cap layer 22 are laminated in this order. It has become. The cap layer 22 is also referred to as an ohmic contact cap layer.

In the present embodiment, the buffer layer 11 has a thickness of about 1000 nm, for example. The material used for the buffer layer 11 varies depending on the substrate 10. Note that the buffer layer 11 may be provided as necessary.
The lower barrier layer 12 is an InAlAs layer. Here, it is an undoped InAlAs layer. For example, an i-In _0.52 Al _0.48 As layer having a thickness of about 200 nm. When the buffer layer 11 is not provided, the lower barrier layer 12 functions as a buffer layer.

The electron transit layer 24 is made of an InGaAs-based compound semiconductor (III-V group compound semiconductor), and an InGaAs layer (first layer) 13, an InAs layer (second layer) 15, and an InGaAs layer (third layer) 17 are sequentially stacked. The structure (here, a three-layer structure) is provided. In this case, the InAs layer 15 is made of a semiconductor having a lighter effective mass than the InGaAs layers 13 and 17.
As described above, the InAlAs / InGaAs-based HEMT according to the present embodiment is an InGaAs / InAs / InGaAs composite in which an InAs layer made of InAs, which is a semiconductor having a low electron effective mass, is provided in the InGaAs channel layer of the InAlAs / InGaAs-based HEMT. Channel HEMT. The InGaAs / InAs / InGaAs composite channel HEMT is also referred to as an As-based composite channel HEMT.

The InGaAs / InAs / InGaAs composite channel HEMT semiconductor stacked structure 26 has a structure in which a lower barrier layer (InAlAs layer) 12, an electron transit layer 24, and an electron supply layer (InAlAs layer) 25 are stacked in this order.
As shown in the conduction band structure (vertical conduction band structure) in FIG. 2, the electron transit layer is formed in the quantum well constituted by the lower barrier layer 12, the electron transit layer 24, and the electron supply layer 25. The quantum well is composed of 24 first layers 13, second layers 15, and third layers 17, and has a conduction band energy deeper (lower) than this quantum well.

Further, as shown in the conduction band structure of FIG. 2, the energy of the conduction band of the first layer 13 and the third layer 17 (InGaAs layer) of the electron transit layer 24 is reduced by the lower barrier layer 12 and the electron supply layer 25 (InAlAs layer). ) And the energy of the conduction band of the second layer 15 (InAs layer) is lower than the energy of the conduction bands of the first layer 13 and the third layer 17.
That is, the energy of the conduction band decreases in the order of the lower barrier layer 12 and the electron supply layer 25, the first layer 13 and the third layer 17 of the electron transit layer 24, and the second layer 15 of the electron transit layer 24. The second layer 15 of the electron transit layer 24 with the lowest energy functions as a channel, and then the first layer 13 and the third layer 17 of the electron transit layer 24 with the lowest conduction band energy function as subchannels. It has become.

  As shown in FIG. 1, the electron transit layer 24 is formed at the interface between the InGaAs layer 13 and the InAs layer 15 and at the interface between the InAs layer 15 and the InGaAs layer 17. Has mixed crystal regions 14 and 16 substituted with Sb which is a group V element having a larger atomic radius than As which is a group V element of an InGaAs-based compound semiconductor.

That is, the electron transit layer 24 is an As group which is a group V element of a III-V group compound semiconductor that constitutes these quantum wells between a quantum well having a shallow conduction band energy and a quantum well having a deep conduction band energy. Has mixed crystal regions 14 and 16 substituted with Sb, which is a group V element having a larger atomic radius than As, which is a group V element of the III-V group compound semiconductor.
Thereby, the compressive strain added to the InAs layer 15 which consists of a semiconductor with the light effective mass of the electron which comprises the electron transit layer 24 can be reduced.

In this case, as shown in the conduction band structure of FIG. 2, the energy of the conductor in the mixed crystal regions 14 and 16 is lower than the energy of the conduction band of the InAs layer 15. Thereby, electrons can be further confined in the InAs layer 15 of the quantum well constituted by the InGaAs layer 13, the InAs layer 15, and the InGaAs layer 17 of the electron transit layer 24.
The InGaAs layer 13 is also referred to as a lower layer or a lower channel layer. The InAs layer 15 is also referred to as an intermediate layer or an intermediate channel layer. The InGaAs layer 17 is also referred to as an upper layer or an upper channel layer. The mixed crystal regions 14 and 16 are also referred to as a mixed crystal region containing Sb, a replacement region, an As / Sb replacement region, an Sb beam irradiation region, or a mixed crystal region due to an Sb atmosphere. The mixed crystal region 14 provided at the interface between the InGaAs layer 13 and the InAs layer 15 is also referred to as a lower mixed crystal region. The mixed crystal region 16 provided at the interface between the InAs layer 15 and the InGaAs layer 17 is also referred to as an upper mixed crystal region.

In this embodiment, as shown in FIG. 1, the electron transit layer 24 includes an undoped InGaAs layer 13, an Sb beam irradiation region 14, an undoped InAs layer 15, an Sb beam irradiation region 16, and an undoped InGaAs layer 17 from below. It has a structure prepared in order.
Here, the undoped InGaAs layer 13 is, for example, an i-In _0.53 Ga _0.47 As layer lattice-matched to InP, and has a thickness of about 3 nm. Further, the Sb beam irradiation region 14 is a very thin region of about one atomic layer, for example. The undoped InAs layer 15 has a thickness of about 5 nm, for example. Further, the Sb beam irradiation region 16 is a very thin region of about one atomic layer, for example. The undoped InGaAs layer 17 is, for example, an i-In _0.53 Ga _0.47 As layer lattice-matched to InP, and has a thickness of about 2 nm.

As described above, the electron transit layer 24 is made of a III-V group compound semiconductor and has a structure in which the first layer 13, the second layer 15, and the third layer 17 are sequentially laminated. It is made of a semiconductor having a lighter effective mass of electrons than the layer 13 and the third layer 17.
The energy of the conduction band of the second layer 15 is lower than the energy of the conduction bands of the first layer 13 and the third layer 17, and the interface between the first layer 13 and the second layer 15 and the second layer 15 and the third layer 15. At the interface with the layer 17, there are mixed crystal regions 14 and 16 in which the group V element of the group III-V compound semiconductor is substituted with a group V element having a larger atomic radius than the group V element of the group III-V compound semiconductor. .

In the present embodiment, the group V element of the III-V group compound semiconductor is As, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. The electron transit layer 24 has a structure in which an InGaAs layer as the first layer 13, an InAs layer as the second layer 15, and an InGaAs layer as the third layer 17 are sequentially stacked.
The electron supply layer 25 has a structure in which an InAlAs spacer layer 18, a Si-δ doping layer 19, and an InAlAs barrier layer 20 are sequentially stacked.

Here, the electron supply layer 25 is formed by sequentially laminating an undoped InAlAs spacer layer 18, an Si-δ doping layer 19 formed of InAlAs doped with Si to give n-type conductivity, and an undoped InAlAs barrier layer 20. Has a structure.
For example, the electron supply layer 25 includes an i-In _0.52 Al _0.48 As spacer layer 18 having a thickness of about 3 nm, and a Si-δ doping layer in which a δ doping amount of Si is about 1 × 10 ¹³ cm ^−2. 19. It has a structure in which an i-In _0.52 Al _0.48 As barrier layer 20 having a thickness of about 6 nm is sequentially laminated.

The etching stop layer 21 is an InP layer and is an etching stop layer for the cap layer 22.
Here, it is an undoped InP layer, that is, an i-InP layer, and its thickness is about 3 nm.
The etching stop layer 21 also has a function as a protective layer that prevents the InAlAs electron supply layer 25 from being oxidized.

The cap layer 22 is an InGaAs layer. Here, it is an n-InGaAs layer doped with Si to give n-type conductivity. For example, it is an n-In _0.53 Ga _0.47 As layer, its thickness is about 20 nm, and the Si doping amount is about 2 × 10 ¹⁹ cm ⁻³ . Note that an n-In _0.70 Ga _0.30 As layer may be stacked on the n-In _0.53 Ga _0.47 As layer to form a cap layer having a two-layer structure. In this case, the thickness of the n-In _0.53 Ga _0.47 As layer is about 20 nm, the thickness of the n-In _0.70 Ga _0.30 As layer is about 10 nm, and the Si doping amount is about 2 ×. What is necessary is just about 10 ¹⁹ cm ⁻³ . Alternatively, an n-type InGaAs layer and an n-type InAlAs layer may be stacked to form a cap layer having a two-layer structure.

The semiconductor multilayer structure 26 only needs to include at least the electron transit layer 24 and the electron supply layer 25 above the substrate 10, and may have another multilayer structure. The semiconductor stacked structure 26 is also referred to as a heterostructure semiconductor layer.
A gate electrode 33, a source electrode 31, and a drain electrode 32 are provided on the semiconductor multilayer structure 26 configured as described above, and the surface of the semiconductor multilayer structure 26 is covered with an SiO ₂ film (insulating film) 23. ing.

Here, a source electrode (metal electrode) 31 and a drain electrode (metal electrode) 32 using, for example, Ti / Pt / Au as electrode metals are provided on the cap layer 22.
That is, the source electrode 31 and the drain electrode 32 that are metal electrodes are provided on the cap layer 22 so that the contact between the cap layer 22 and the source electrode 31 and the drain electrode 32 that are metal electrodes is an ohmic contact. For this reason, the source electrode 31 and the drain electrode 32 are called ohmic electrodes.

Further, a gate electrode (metal electrode) 33 using, for example, Ti / Pt / Au as an electrode metal is provided on the i-InP layer 21.
By the way, in this embodiment, the reason why the electron transit layer 24 is configured as described above is as follows.
In order to increase the electron velocity in the channel layer in order to increase the speed of the HEMT, a semiconductor having a low electron effective mass may be used for the channel layer.

Here, examples of the semiconductor with a low effective mass of electrons include InAs (0.022 m ₀ ), InSb (0.014 m ₀ ), and InAsSb which is a mixed crystal thereof. Note that m ₀ is the static mass of electrons.
For example, InAs is used in HEMTs using Al (Ga) Sb as a barrier layer, or introduced as an ultrathin layer in an InGaAs channel layer of an InAlAs / InGaAs HEMT to form an InGaAs / InAs / InGaAs composite channel HEMT. It is used for.

Among these, when InAs is used for a HEMT having Al (Ga) Sb as a barrier layer, the lattice constant of InAs, AlSb, and GaSb is close to about 0.61 nm. can get.
On the other hand, the InGaAs / InAs / InGaAs composite channel HEMT has an electron transit layer (channel layer) 24 sandwiched between In _0.53 Ga _0.47 As layers 13 and 17 and an InAs layer 15 as shown in FIG. In _0.52 Al _0.48 As is used for the lower barrier layer 12 and the electron supply layer 25, the In _0.53 Ga _0.47 As of the electron transit layer 24, the lower barrier layer 12 and the electron supply layer 25 In _0.52 Al _0.48 As is lattice matched. In this case, the conduction band structure is as shown in FIG.

In the case of such an InGaAs / InAs / InGaAs composite channel HEMT, since the lattice constant of InAs is larger than that of InGaAs, compressive strain is applied to the InAs layer 15 introduced into the channel layer 24.
The InAs layer 15 to which compressive strain is applied has an effective electron mass that is greater than that of the unstrained InAs layer 15. As a result, the effectiveness of InAs, which is a semiconductor having a low effective electron mass, cannot be fully utilized. This is not preferable for speeding up the HEMT.

  In addition, when compressive strain is applied to the InAs layer 15, the crystal of the InAs layer 15 is deteriorated, so that it is difficult to increase the thickness of the InAs layer 15. If the InAs layer 15 is too thick, the crystal quality of the InAs layer 15 is deteriorated. If the InAs layer 15 cannot be made thick, electrons cannot be sufficiently stored in the InAs layer 15, and the electrons spread to the InGaAs layers 13 and 17 sandwiching the InAs layer 15. For example, the thickness at which the crystal quality is not deteriorated at present is about 2 nm. At this thickness, electrons cannot be sufficiently stored in the InAs layer 15, and the upper and lower InGaAs layers 13, 17 Electrons will spread to This is not preferable for speeding up the HEMT.

  Therefore, in the present embodiment, as described above, the electron transit layer 24 of the InGaAs / InAs / InGaAs composite channel HEMT is placed at the interface between the InGaAs layer 13 and the InAs layer 15 and the interface between the InAs layer 15 and the InGaAs layer 17. Mixed crystal regions 14 and 16 in which As, which is a group V element of an InGaAs-based compound semiconductor, is replaced by Sb, a group V element having a larger atomic radius than As, which is a group V element of an InGaAs-based compound semiconductor. It is supposed to have.

  In the mixed crystal regions 14 and 16, As contained in InGaAs or InAs, which are InGaAs-based compound semiconductors, is replaced with Sb, and mixed crystals containing Sb having a larger atomic radius than As, such as InSb, InAsSb, InGaSb, and InGaAsSb. It has become. These mixed crystals containing Sb having a larger atomic radius than As have a larger lattice constant than InAs (lattice magnitude relationship; mixed crystals containing InGaAs <InAs <Sb), so that the compressive strain applied to InAs is reduced. There is an effect.

  Thereby, the compressive strain applied to the InAs layer 15 made of a semiconductor having a light effective mass of electrons constituting the electron transit layer 24 of the InGaAs / InAs / InGaAs composite channel HEMT can be reduced. As a result, an increase in the effective mass of electrons in the InAs layer 15 is suppressed, and the original physical property of InAs, which is a semiconductor with a low effective electron mass, is fully utilized. In addition, deterioration of the crystal quality of the InAs layer 15 due to the application of compressive strain can be suppressed, and while maintaining high-quality crystals, the InAs layer 15 is made as thick as possible to sufficiently accumulate electrons in the InAs layer 15. It becomes possible to (confine). With these points, it is possible to realize a high speed InGaAs / InAs / InGaAs composite channel HEMT.

In this case, as shown in the conduction band structure of FIG. 2, the energy of the conductor in the mixed crystal regions 14 and 16 is lower than the energy of the conduction band of the InAs layer 15. As a result, electrons can be further confined in the InAs layer 15 of the quantum well constituted by the InGaAs layer 13, the InAs layer 15, and the InGaAs layer 17 of the electron transit layer 24.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.

The method for manufacturing a semiconductor device according to this embodiment includes a step of forming a semiconductor multilayer structure 26 including at least an electron transit layer 24 and an electron supply layer 25 above the substrate 10 (see FIG. 5).
The step of forming the electron transit layer 24 includes forming a first layer (here, InGaAs layer) 13 made of a III-V group compound semiconductor (here, InGaAs compound semiconductor), and forming a first layer 13 on the first layer 13. A second layer 15 (here, an InAs layer) 15 having a conduction band energy lower than that of the first layer is formed of a III-V group compound semiconductor having an effective electron mass lower than that of the first layer 13. In addition, a third layer (in this case, an InGaAs layer) 17 made of a III-V group compound semiconductor having a heavier effective mass of electrons than the second layer 15 and having a conduction band energy higher than that of the second layer 15 is formed. Including steps (see FIG. 5).

Further, between the step of forming the first layer 13 and the step of forming the second layer 15 and between the step of forming the second layer 15 and the step of forming the third layer 17, a III-V group compound This includes a step of irradiating a group V element (here, Sb) having a larger atomic radius than a group V element (here, As) of the semiconductor (see FIG. 5).
In the present embodiment, the semiconductor multilayer structure 26 further includes a lower barrier layer (here, an InAlAs layer) 12. Then, the step of forming the semiconductor multilayer structure 26 forms the lower barrier layer 12, and includes the first layer 13 and the third layer 17 whose conduction band energy is lower than that of the lower barrier layer 12 on the lower barrier layer 12. An electron transit layer 24 is formed, and an electron supply layer (here, an InAlAs layer) 25 having conduction band energy higher than that of the first layer 13 and the third layer 17 of the electron transit layer 24 is formed on the electron transit layer 24. , Including each step. That is, in the quantum well constituted by the lower barrier layer 12, the electron transit layer 24, and the electron supply layer 25, it is constituted by the first layer 13, the second layer 15 and the third layer 17 of the electron transit layer 24. A quantum well having a deeper (lower) conduction band energy than the quantum well is formed (see FIGS. 5 and 2).

In the present embodiment, in the step of irradiating a group V element having a larger atomic radius than the group V element of the group III-V compound semiconductor, the group V having a larger atomic radius than the group V element of the group III-V compound semiconductor. The energy of the conductor of the mixed crystal regions 14 and 16 formed by irradiating the element is lower than the energy of the conduction band of the second layer 15 (see FIGS. 5 and 2).
Hereinafter, a manufacturing method of an InAlAs / InGaAs-based HEMT (InGaAs / InAs / InGaAs composite channel HEMT) will be described as an example with reference to FIGS.

First, as shown in FIG. 5, a buffer layer 11 and an i-In _0.52 Al _0.48 As lower barrier layer are formed on a semi-insulating InP substrate 10 by, for example, molecular beam epitaxy (MBE). 12, i-In _0.53 Ga _0.47 As layer 13, Sb beam irradiation region 14, i-InAs layer 15, Sb beam irradiation region 16, i-In _0.53 Ga _{0. 47} As layer 17, i-In _0.52 Al _0.48 As spacer layer 18 constituting the electron supply layer 25, Si-δ doping layer 19, i-In _0.52 Al _0.48 As barrier layer 20, i The semiconductor stacked structure 26 is formed by sequentially stacking the -InP etching stop layer 21 and the n-In _0.53 Ga _0.47 As cap layer 22.

In this way, the semiconductor multilayer structure 26 including at least the electron transit layer 24 and the electron supply layer 25 is formed above the substrate 10.
In particular, in the step of forming the electron transit layer 24, the i-In _0.53 Ga _0.47 As layer 13, the Sb beam irradiation region 14, the i-InAs layer 15, the Sb beam irradiation region 16, as follows. The i-In _0.53 Ga _0.47 As layer 17 is formed.

That is, first, the i-In _0.53 Ga _0.47 As layer (first layer) 13 is formed on the i-In _0.52 Al _0.48 As lower barrier layer 12.
Next, the surface of the i-In _0.53 Ga _0.47 As layer 13 is irradiated with an Sb beam to form an Sb beam irradiation region 14. That is, on the surface of the i-In _0.53 Ga _0.47 As layer 13, the atomic radius is larger than that of As which is a group V element of an InGaAs-based compound semiconductor (III-V group compound semiconductor) constituting the electron transit layer 24. An Sb beam irradiation region 14 is formed by irradiating an Sb beam which is a large group V element.

Here, after the i-In _0.53 Ga _0.47 As layer 13 is formed and before the i-InAs layer 15 is formed, that is, the i-In _0.53 Ga _0.47 As layer 13 is formed. Between the step and the step of forming the i-InAs layer 15, the group III, As beam is stopped and the Sb beam is irradiated.
Thus, occur substitution of As and _Sb, on the surface of the i-In _{0.53 Ga 0.47} As layer 13, _i.e., thereafter the i-In _{0.53 Ga 0.47} As layer 13 on the Between the i-InAs layer 15 to be formed, an Sb beam irradiation region 14 which is an ultrathin (for example, about one atomic layer) mixed crystal region containing Sb such as InSb, InAsSb, InGaSb, InGaAsSb, or the like is formed.

Since the mixed crystal containing Sb having a larger atomic radius than As, which is formed in this way, has a larger lattice constant than InAs, the compressive strain applied to the i-InAs layer 15 can be reduced.
Here, the Sb beam is irradiated to form the Sb beam irradiation region 14, but the Sb beam irradiation region 14 which is a mixed crystal region by the Sb atmosphere may be formed in the Sb atmosphere.

Next, on the i-In _0.53 Ga _0.47 As layer 13, that is, on the Sb beam irradiation region 14 on the surface of the i-In _0.53 Ga _0.47 As layer 13, the i-InAs layer ( Second layer) 15 is formed. That is, on the i-In _0.53 Ga _0.47 As layer 13, it is made of InAs (III-V group compound semiconductor) having a lighter effective mass than the i-In _0.53 Ga _0.47 As layer 13. Then, the i-InAs layer 15 whose conduction band energy is lower than that of the i-In _0.53 Ga _0.47 As layer 13 is formed.

Next, the surface of the i-InAs layer 15 is irradiated with an Sb beam to form an Sb beam irradiation region 16. That is, on the surface of the i-InAs layer 15, an Sb beam that is a group V element having a larger atomic radius than As, which is a group V element of an InGaAs-based compound semiconductor (group III-V compound semiconductor) constituting the electron transit layer 24. To form an Sb beam irradiation region 16.
Here, after the i-InAs layer 15 is formed and before the i-In _0.53 Ga _0.47 As layer 17 is formed, that is, the step of forming the i-InAs layer 15 and the i-In _0.53. Between the step of forming the Ga _0.47 As layer 17, the group III, As beam is stopped and the Sb beam is irradiated.

As a result, substitution of As and Sb occurs, that is, on the surface of the i-InAs layer 15, that is, the i-InAs layer 15 and the i-In _0.53 Ga _0.47 As layer 17 formed _thereon. In between, an Sb beam irradiation region 16 which is an ultrathin (for example, about 1 atomic layer) mixed crystal region containing Sb such as InSb, InAsSb, InGaSb, InGaAsSb is formed.
Since the mixed crystal containing Sb having a larger atomic radius than As, which is formed in this way, has a larger lattice constant than InAs, the compressive strain applied to the i-InAs layer 15 can be reduced.

Although the Sb beam irradiation region 16 is formed here by irradiating the Sb beam, the Sb beam irradiation region 16 which is a mixed crystal region by the Sb atmosphere may be formed in the Sb atmosphere.
Next, an i-In _0.53 Ga _0.47 As layer (third layer) 17 is formed on the i-InAs layer 15, that is, on the Sb beam irradiation region 16 on the surface of the i-InAs layer 15. To do. That is, the i-InAs layer 15 is made of In _0.53 Ga _0.47 As (III-V group compound semiconductor) having a heavier effective mass of electrons than the i-InAs layer 15, and the energy of the conduction band is i−. An i-In _0.53 Ga _0.47 As layer 17 higher than the InAs layer 15 is formed.

In this way, the i-In _0.53 Ga _0.47 As layer 13, the Sb beam irradiation region 14, the i-InAs layer 15, the Sb beam irradiation region 16, and the i-In _0.53 Ga _0.47 As layer 17. Are formed in order.
Note that the crystal growth method is not limited to the MBE method, and for example, a metal organic chemical vapor deposition (MOCVD) method can also be used.

Here, the buffer layer 11 has a thickness of about 1000 nm. The i-In _0.52 Al _0.48 As lower barrier layer 12 has a thickness of about 200 nm. The i-In _0.53 Ga _0.47 As layer 13 has a thickness of about 3 nm. The Sb beam irradiation region 14 is an extremely thin layer of about 1 atomic layer. The i-InAs layer 15 has a thickness of about 5 nm. The Sb beam irradiation region 16 is a very thin layer of about 1 atomic layer. The i-In _0.53 Ga _0.47 As layer 17 has a thickness of about 2 nm. The i-In _0.52 Al _0.48 As spacer layer 18 has a thickness of about 3 nm. Further, the Si-δ doping layer 19 has a Si δ doping amount of about 1 × 10 ¹³ cm ⁻² . The i-In _0.52 Al _0.48 As barrier layer 20 has a thickness of about 6 nm. The i-InP etching stop layer 21 has a thickness of about 3 nm. The n-In _0.53 Ga _0.47 As cap layer 22 has a thickness of about 20 nm and an Si doping amount of about 2 × 10 ¹⁹ cm ⁻³ .

Next, after element isolation, as shown in FIG. 6, for example, a source electrode 31 and a drain electrode 32 having a three-layer structure of Ti / Pt / Au are formed. As a result, the source electrode 31 and the drain electrode 32 are formed on the n-In _0.53 Ga _0.47 As cap layer 22.
Next, as shown in FIG. 7, an SiO ₂ film 23 is formed on the cap layer 22 between the source electrode 31 and the drain electrode 32 by, for example, a plasma CVD (Chemical Vapor Deposition) method. Here, the thickness of the SiO ₂ film 23 is about 20 nm.

Next, as shown in FIGS. 8 to 14, a T-type gate electrode 33 is formed.
That is, first, as shown in FIG. 8, three-layer resist films 41 to 43 are formed. Here, a ZEP resist (manufactured by Nippon Zeon), a PMGI (Poly-dimethylglutarimide) resist, and a ZEP resist are sequentially applied, and a ZEP resist film 41, a PMGI resist film 42, and a ZEP resist film 43 are sequentially laminated. A resist film is formed.

  Next, as shown in FIG. 9, for example, an area for forming the head portion of the T-type gate electrode 33 is exposed by electron beam exposure to form openings in the ZEP resist film 43 and the PMGI resist film 42. Further, as shown in FIG. 10, for example, an area for forming the foot portion of the T-type gate electrode 33 is exposed by an electron beam exposure method, and an opening is formed in the lowermost ZEP resist film 41 in accordance with a desired gate length. Form.

Next, using the lowermost ZEP resist film 41 having an opening formed according to the gate length as a mask, for example, by reactive ion etching using CF ₄ as an etching gas, SiO _{2 as} shown in FIG. An opening is formed in the film 23.
In order to electrically separate the cap layer 22, for example, wet etching is performed using a mixed solution of citric acid (C ₆ H ₈ O ₇ ) and hydrogen peroxide (H ₂ O ₂ ) as an etchant. As shown in FIG. 12, a recess is formed.

Finally, as shown in FIG. 13, for example, Ti, Pt, and Au are deposited, and then lift-off is performed. As shown in FIG. 14, for example, a T-type gate electrode 33 having a three-layer structure of Ti / Pt / Au. Form. As a result, the T-type gate electrode 33 is formed on the i-InP etching stop layer 21.
In this way, the semiconductor device (InAlAs / InGaAs-based HEMT; InGaAs / InAs / InGaAs composite channel HEMT) according to the present embodiment can be manufactured.

Therefore, according to the semiconductor device of the present embodiment, there is an advantage that the compressive strain applied to the layer (in this case, the InAs layer 15) made of a semiconductor having a light effective mass of electrons constituting the channel layer 24 can be reduced. .
As a result, an increase in effective mass of electrons in the InAs layer 15 provided in the electron transit layer 24 is suppressed, and deterioration of the crystal quality of the InAs layer 15 due to the application of compressive strain can be suppressed. The thickness can be increased as much as possible, and the HEMT can be increased in speed.

In the above embodiment, the case where the present invention is applied to an InGaAs / InAs / InGaAs composite channel HEMT (InAlAs / InGaAs HEMT) using InAlAs as a barrier layer (electron supply layer 25 and lower barrier layer 12) is taken as an example. Although described in detail, the material system is not limited to this.
For example, the present invention can also be applied to an InGaAs / InAs / InGaAs composite channel HEMT (AlGaAs / InGaAs HEMT) using AlGaAs as a barrier layer (electron supply layer and lower barrier layer).

  That is, in the InGaAs / InAs / InGaAs composite channel HEMT (AlGaAs / InGaAs HEMT), the electron transit layer is divided into an InGaAs layer (first layer) and an InAs layer (second layer), as in the case of the above-described embodiment. The V group element (here As) of the InGaAs-based compound semiconductor (III-V group compound semiconductor) constituting the interface, and the interface between the InAs layer (second layer) and the InGaAs layer (third layer), It may have a mixed crystal region (Sb beam irradiation region) substituted by a group V element (here, Sb) having a larger atomic radius than the group V element of the InGaAs-based compound semiconductor.

  In this case, the manufacturing method includes a step between the step of forming the InGaAs layer (first layer) and the step of forming the InAs layer (second layer) included in the step of forming the electron transit layer and the InAs layer (second layer). Between the step of forming the layer) and the step of forming the InGaAs layer (third layer) having a larger atomic radius than the group V element (here As) of the InGaAs compound semiconductor (III-V compound semiconductor) What is necessary is just to include the process (Sb beam irradiation process) of irradiating a group V element (here Sb).

For example, the present invention is applied to an InGaP / InP / InGaP composite channel HEMT (AlGaAs / InGaP HEMT or InAlP / InGaP HEMT) using AlGaAs (or InAlP) as a barrier layer (electron supply layer and lower barrier layer). You can also.
For example, as shown in FIG. 17, an electron transit layer (channel layer) 24X has a structure in which an InP layer 15X is sandwiched between upper and lower InGaP layers 13X and 17X, and InAlP is used for the lower barrier layer 12X and the electron supply layer 25X. There is an InGaP / InP / InGaP composite channel HEMT in which the InGaP of the layer 24X is lattice-matched with the InAlP of the lower barrier layer 12X and the electron supply layer 25X, and its conduction band structure is as shown in FIG. Even in such an InGaP / InP / InGaP composite channel HEMT, since there is a problem similar to the InGaAs / InAs / InGaAs composite channel HEMT of the above-described embodiment, the present invention is applied as in the case of the above-described embodiment. Can do.

  Here, the InGaP / InP / InGaP composite channel HEMT using AlGaAs (or InAlP) as a barrier layer has a light effective mass of electrons in the InGaP channel layers 13X and 17X of the AlGaAs / InGaP HEMT or InAlP / InGaP HEMT. This is an InGaP / InP / InGaP composite channel HEMT provided with an InP layer 15X made of InP, which is a semiconductor.

  That is, in an InGaP / InP / InGaP composite channel HEMT (AlGaAs / InGaP-based HEMT or InAlP / InGaP-based HEMT), the electron transit layer 24X is formed of an InGaP layer (first layer) 13X and an InP layer (second layer) 15X. At the interface and the interface between the InP layer (second layer) 15X and the InGaP layer (third layer) 17X, a group V element (here, P) of the InGaP-based compound semiconductor (III-V compound semiconductor) constituting the interface is formed. Assuming that the mixed crystal regions (As beam irradiation region; Sb beam irradiation region) 14X and 16X are substituted by a group V element (here, As or Sb) having a larger atomic radius than the group V element of the InGaP-based compound semiconductor. Also good.

  In this case, the manufacturing method is performed between the step of forming the InGaP layer (first layer) 13X and the step of forming the InP layer (second layer) 15X included in the step of forming the electron transit layer 24X and the InP layer. Between the step of forming the (second layer) 15X and the step of forming the InGaP layer (third layer) 17X, from the group V element (here, P) of the InGaP-based compound semiconductor (III-V group compound semiconductor) May include a step (As beam irradiation step; Sb beam irradiation step) of irradiation with a group V element having a large atomic radius (here, As or Sb).

Hereinafter, an InGaP / InP / InGaP composite channel HEMT (InAlP / InGaP-based HEMT) using InAlP as a barrier layer (electron supply layer and lower barrier layer) will be described as an example.
Here, the InGaP / InP / InGaP composite channel HEMT (InAlP / InGaP-based HEMT) is formed on a GaAs substrate (semiconductor substrate) 10X, for example, as shown in FIG. 15, with a buffer layer 11X, an InAlP lower barrier layer 12X, an InGaP / A semiconductor multilayer structure 26X is provided in which an InP / InGaP electron transit layer (channel layer) 24X, an InAlP electron supply layer (upper barrier layer) 25X, and an InGaP cap layer 22X are sequentially stacked.

For example, the GaAs substrate 10X is a semi-insulating (100) GaAs substrate, for example. Further, the buffer layer 11X may be provided as necessary. The InAlP lower barrier layer 12X is an i-InAlP lower barrier layer and has a thickness of about 200 nm. The InGaP / InP / InGaP electron transit layer 24X has a structure in which an InGaP layer 13X, an InP layer 15X, and an InGaP layer 17X are sequentially stacked. The InAlP electron supply layer 25X includes an i-InAlP spacer layer 18X, a Si-δ doping layer 19X formed of InAlP doped with Si by δ doping to give n-type conductivity, and an i-InAlP barrier layer 20X. Has a structure. Here, the i-InAlP spacer layer 18X has a thickness of about 3 nm, the Si-δ doping layer 19X has a Si δ doping amount of about 1 × 10 ¹³ cm ⁻² , and the i-InAlP barrier layer 20X has a thickness of about 1 × 10 ¹³ cm ⁻² . The thickness is about 6 nm. The InGaP cap layer 22X is an n-InGaP layer doped with Si to give n-type conductivity. Here, the thickness of the n-InGaP layer 22X is about 20 nm, and the Si doping amount is about 2 × 10 ¹⁸ cm ⁻³ . Note that the composition ratio of the group III elements in the above InAlP layer and InGaP layer may be about 1: 1 (about 0.5 each).

Further, the semiconductor multilayer structure 26X may be any structure as long as it includes at least the electron transit layer 24X and the electron supply layer 25X above the substrate 10X, and may have another multilayer structure.
Then, the gate electrode 33X, the source electrode 31X, and the drain electrode 32X may be provided on the semiconductor stacked structure 26X, and the surface of the semiconductor stacked structure 26X may be covered with the SiO ₂ film (insulating film) 23X.

  As described above, the electron transit layer 24X is made of an InGaP compound semiconductor (III-V group compound semiconductor), and includes an InGaP layer (first layer) 13X, an InP layer (second layer) 15X, and an InGaP layer (first layer). 3 layers) are stacked in the order of 17X (here, a three-layer structure). In this case, the InP layer 15X is made of a semiconductor having a lighter effective mass than the InGaP layers 13X and 17X.

  As described above, the InAlP / InGaP-based HEMT of this modification example is an InGaP / InGaP / InGaP-based HEMT in which an InP layer 15X made of InP, which is a semiconductor with a low effective electron mass, is provided in the InGaP channel layers 13X and 17X of the InAlP / InGaP-based HEMT. InP / InGaP composite channel HEMT. The InGaP / InP / InGaP composite channel HEMT is also referred to as a P-based composite channel HEMT.

In the InGaP / InP / InGaP composite channel HEMT, the semiconductor stacked structure 26X has a structure in which a lower barrier layer (InAlP layer) 12X, an electron transit layer 24X, and an electron supply layer (InAlP layer) 25X are sequentially stacked.
That is, as shown in the conduction band structure (vertical conduction band structure) of FIG. 16, the electron transit layer is included in the quantum well composed of the lower barrier layer 12X, the electron transit layer 24X, and the electron supply layer 25X. A 24X first layer 13X, a second layer 15X, and a third layer 17X are provided, and a quantum well having a deeper (lower) conduction band energy than the quantum well is provided.

Further, as shown in the conduction band structure of FIG. 16, the energy of the conduction band of the first layer 13X and the third layer 17X (InGaP layer) of the electron transit layer 24X is the conduction band of the lower barrier layer 12X and the electron supply layer 25X. The energy of the conduction band of the second layer 15X (InP layer) is lower than the energy of the conduction bands of the first layer 13X and the third layer 17X.
That is, the energy of the conduction band decreases in the order of the lower barrier layer 12X and the electron supply layer 25X, the first layer 13X and the third layer 17X of the electron transit layer 24X, and the second layer 15X of the electron transit layer 24X. The second layer 15X of the electron transit layer 24X having the lowest energy functions as a channel, and then the first layer 13X and the third layer 17X of the electron transit layer 24X with the lowest conduction band energy function as subchannels. It has become.

  As shown in FIGS. 15 and 16, the electron transit layer 24X is formed of an InGaP-based compound semiconductor that forms the interface between the InGaP layer 13X and the InP layer 15X and the interface between the InP layer 15X and the InGaP layer 17X. The group V element P has mixed crystal regions 14X and 16X substituted with As or Sb which is a group V element having an atomic radius larger than that of the group V element P of the InGaP-based compound semiconductor.

That is, the electron transit layer 24X is formed of a group V element of a III-V group compound semiconductor that constitutes these quantum wells between a quantum well with a shallow conduction band energy and a quantum well with a deep conduction band energy. Has mixed crystal regions 14X and 16X substituted with As or Sb, which is a group V element having a larger atomic radius than P, which is a group V element of a III-V group compound semiconductor.
In the mixed crystal regions 14X and 16X, InGaP or InP, which is an InGaP compound semiconductor, is substituted with As or Sb, and InAs, InGaAs, InAsP, InGaAsP, or InSb, InPSb, InGaSb, InGaPSb, etc. It is a mixed crystal containing As or Sb having an atomic radius larger than that of P. These mixed crystals containing As or Sb having a larger atomic radius than P have a larger lattice constant than InP (lattice magnitude relationship: mixed crystals containing InGaP <InP <As or Sb), and compression applied to InP. It has the effect of reducing distortion.

  Thereby, it is possible to reduce the compressive strain applied to the InP layer 15X made of a semiconductor having a light effective mass of electrons constituting the electron transit layer 24X of the InGaP / InP / InGaP composite channel HEMT. As a result, an increase in the effective mass of electrons in the InP layer 15X is suppressed, and the original physical properties of InP, which is a semiconductor with a low effective electron mass, are fully utilized. In addition, deterioration of the crystal quality of the InP layer 15X due to the application of compressive strain can be suppressed, and while maintaining a high-quality crystal, the InP layer 15X is made as thick as possible to sufficiently accumulate electrons in the InP layer 15X. It becomes possible to (confine). With these points, it is possible to realize a high-speed InGaP / InP / InGaP composite channel HEMT.

In this case, as shown in the conduction band structure of FIG. 16, the energy of the conductors in the mixed crystal regions 14X and 16X is lower than the energy of the conduction band of the InP layer 15X. Thereby, electrons can be further confined in the InP layer 15X of the quantum well constituted by the InGaP layer 13X, the InP layer 15X, and the InGaP layer 17X of the electron transit layer 24X.
The InGaP layer 13X is also referred to as a lower layer or a lower channel layer. The InP layer 15X is also referred to as an intermediate layer or an intermediate channel layer. The InGaP layer 17X is also referred to as an upper layer or an upper channel layer. The mixed crystal regions 14X and 16X are also referred to as mixed crystal regions containing As or Sb, substitution regions, P / As or P / Sb substitution regions, As or Sb beam irradiation regions, and mixed crystal regions due to an As or Sb atmosphere. The mixed crystal region 14X provided at the interface between the InGaP layer 13X and the InP layer 15X is also referred to as a lower mixed crystal region. The mixed crystal region 16X provided at the interface between the InP layer 15X and the InGaP layer 17X is also referred to as an upper mixed crystal region.

In this modification, as shown in FIG. 15, the electron transit layer 24X includes an undoped InGaP layer 13X, an As or Sb beam irradiation region 14X, an undoped InP layer 15X, an As or Sb beam irradiation region 16X, and an undoped InGaP layer. 17X is provided in order from the bottom.
Here, the undoped InGaP layer 13X is, for example, an i-InGaP layer lattice-matched to GaAs and has a thickness of about 3 nm. Further, the As or Sb beam irradiation region 14X is an extremely thin region of about one atomic layer, for example. The undoped InAs layer 15X has a thickness of about 5 nm, for example. Further, the As or Sb beam irradiation region 16X is an extremely thin region of about one atomic layer, for example. The undoped InGaAs layer 17X is, for example, an i-InGaP layer lattice-matched to GaAs and has a thickness of about 2 nm.

  As described above, the electron transit layer 24X is made of a III-V group compound semiconductor, and has a structure in which the first layer 13X, the second layer 15X, and the third layer 17X are sequentially stacked, and the second layer 15X includes the first layer 15X. The layer 13X and the third layer 17X are made of a semiconductor having a lighter effective mass of electrons. The energy of the conduction band of the second layer 15X is lower than the energy of the conduction bands of the first layer 13X and the third layer 17X, and the interface between the first layer 13X and the second layer 15X and the second layer 15X and the third layer 15X. At the interface with the layer 17X, there are mixed crystal regions 14X and 16X in which the group V element of the group III-V compound semiconductor is substituted with the group V element having a larger atomic radius than the group V element of the group III-V compound semiconductor. .

In this modification, the group V element of the III-V group compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is As or Sb. The electron transit layer 24X has a structure in which an InGaP layer is stacked as the first layer 13X, an InP layer is stacked as the second layer 15X, and an InGaP layer is stacked as the third layer 17X.
Next, a method for manufacturing the semiconductor device (InAlP / InGaP-based HEMT; InGaP / InP / InGaP composite channel HEMT) according to this modification will be described.

  First, an InGaP layer 13X, an As or Sb beam irradiation region 14X constituting an buffer layer 11X, an InAlP lower barrier layer 12X, and an electron transit layer 24X are formed on the semi-insulating GaAs substrate 10X, for example, by MBE or MOCVD. 15X, As or Sb beam irradiation region 16X, InGaP layer 17X, InAlP spacer layer 18X constituting electron supply layer 25X, Si-δ doping layer 19X, InAlP barrier layer 20X, n-InGaP cap layer 22X are sequentially stacked, A semiconductor stacked structure 26X is formed (see FIG. 15).

In this manner, the semiconductor stacked structure 26X including at least the electron transit layer 24X and the electron supply layer 25X is formed above the substrate 10X (see FIG. 15).
In particular, in the step of forming the electron transit layer 24X, the InGaP layer 13X, As or Sb beam irradiation region 14X, the InP layer 15X, As or Sb beam irradiation region 16X, and the InGaP layer 17X are formed as follows (FIG. 15).

That is, first, an InGaP layer (first layer) 13X is formed on the InAlP lower barrier layer 12X.
Next, an As or Sb beam irradiation region 14X is formed by irradiating the surface of the InGaP layer 13X with an As or Sb beam. That is, an As or Sb beam which is a group V element having a larger atomic radius than P which is a group V element of an InGaP-based compound semiconductor (III-V group compound semiconductor) constituting the electron transit layer 24X on the surface of the InGaP layer 13X. To form an As or Sb beam irradiation region 14X.

Here, after the InGaP layer 13X is formed and before the InP layer 15X is formed, that is, between the step of forming the InGaP layer 13X and the step of forming the InP layer 15X, the group III and P beams are stopped. , As or Sb beam is irradiated.
As a result, substitution of P and As or Sb occurs. On the surface of the InGaP layer 13X, that is, between the InGaP layer 13X and the InP layer 15X subsequently formed thereon, InAs, InGaAs, InAsP, InGaAsP. Or an As or Sb beam irradiation region 14X which is an ultrathin (for example, about 1 atomic layer) mixed crystal region containing As or Sb such as InSb, InPSb, InGaSb, InGaPSb, or the like.

The mixed crystal containing As or Sb having an atomic radius larger than that of P formed in this manner has a lattice constant larger than that of InP, so that the compressive strain applied to the InP layer 15X can be reduced.
Here, the As or Sb beam irradiation region 14X is formed by irradiating the As or Sb beam, but the As or Sb beam irradiation region 14X which is a mixed crystal region in the As or Sb atmosphere under the As or Sb atmosphere. May be formed.

  Next, an InP layer (second layer) 15X is formed on the InGaP layer 13X, that is, on the As or Sb beam irradiation region 14X on the surface of the InGaP layer 13X. That is, on the InGaP layer 13X, an InP layer 15X made of InP (group III-V compound semiconductor) having a lighter effective mass than the InGaP layer 13X and having a conduction band energy lower than that of the InGaP layer 13X is formed.

  Next, the As or Sb beam irradiation region 16X is formed by irradiating the surface of the InP layer 15X with As or Sb beams. That is, an As or Sb beam which is a group V element having a larger atomic radius than P which is a group V element of an InGaP-based compound semiconductor (group III-V compound semiconductor) constituting the electron transit layer 24X on the surface of the InP layer 15X. To form an As or Sb beam irradiation region 16X.

Here, after the InP layer 15X is formed and before the InGaP layer 17X is formed, that is, between the step of forming the InP layer 15X and the step of forming the InGaP layer 17X, the group III and P beams are stopped. , As or Sb beam is irradiated.
As a result, substitution of P and As or Sb occurs. On the surface of the InP layer 15X, that is, between the InP layer 15X and the InGaP layer 17X subsequently formed thereon, InAs, InGaAs, InAsP, InGaAsP. Or an As or Sb beam irradiation region 16X which is an ultrathin (for example, about 1 atomic layer) mixed crystal region containing As or Sb such as InSb, InPSb, InGaSb, InGaPSb or the like.

The mixed crystal containing As or Sb having an atomic radius larger than that of P formed in this manner has a lattice constant larger than that of InP, so that the compressive strain applied to the InP layer 15X can be reduced.
Here, the As or Sb beam irradiation region 16X is formed by irradiating the As or Sb beam. However, the As or Sb beam irradiation region 16X which is a mixed crystal region in the As or Sb atmosphere under the As or Sb atmosphere. May be formed.

  Next, an InGaP layer (third layer) 17X is formed on the InP layer 15X, that is, on the As or Sb beam irradiation region 16X on the surface of the InP layer 15X. That is, on the InP layer 15X, an InGaP layer 17X made of InGaP (III-V group compound semiconductor) having a heavier effective mass of electrons than the InP layer 15X and having a conduction band energy higher than that of the InP layer 15X is formed.

In this way, the electron transit layer 24X including the InGaP layer 13X, the As or Sb beam irradiation region 14X, the InP layer 15X, the As or Sb beam irradiation region 16X, and the InGaP layer 17X in this order is formed.
Thereafter, similarly to the above-described embodiment, after element isolation, the source electrode 31X and the drain electrode 32X are formed, and the SiO ₂ film 23X is formed on the cap layer 22X between the source electrode 31X and the drain electrode 32X. Then, a T-type gate electrode 33X is formed.

In this way, the semiconductor device (InAlP / InGaP-based HEMT; InGaP / InP / InGaP composite channel HEMT) of this modification can be manufactured.
As described above, the manufacturing method of the semiconductor device according to this modification includes a step of forming the semiconductor stacked structure 26X including at least the electron transit layer 24X and the electron supply layer 25X above the substrate 10X (see FIG. 15).

  In addition, the step of forming the electron transit layer 24X is performed by forming a first layer (here InGaP layer) 13X made of a III-V group compound semiconductor (here InGaP-based compound semiconductor) and forming a first layer 13X on the first layer 13X. A second layer (here, InP layer) 15X having a conduction band energy lower than that of the first layer is formed of a III-V group compound semiconductor having an electron effective mass lighter than that of the first layer 13X. In addition, a third layer (in this case, an InGaP layer) 17X having a conduction band energy higher than that of the second layer 15X is formed of a III-V group compound semiconductor having an effective electron mass greater than that of the second layer 15X. Including steps (see FIG. 15).

Further, between the step of forming the first layer 13X and the step of forming the second layer 15X, and between the step of forming the second layer 15X and the step of forming the third layer 17X, a III-V group compound It includes a step of irradiating a group V element (As or Sb here) having a larger atomic radius than the group V element (here P) of the semiconductor (see FIG. 15).
In the present embodiment, the semiconductor stacked structure 26X further includes a lower barrier layer (InAlP layer here) 12X. The step of forming the semiconductor multilayer structure 26X includes the formation of the lower barrier layer 12X, and the first layer 13X and the third layer 17X having conduction band energy lower than that of the lower barrier layer 12X are formed on the lower barrier layer 12X. An electron transit layer 24X is formed, and an electron supply layer (here, an InAlP layer) 25X having conduction band energy higher than that of the first layer 13X and the third layer 17X of the electron transit layer 24X is formed on the electron transit layer 24X. , Including each step. That is, in the quantum well constituted by the lower barrier layer 12X, the electron transit layer 24X, and the electron supply layer 25X, the electron transit layer 24X is constituted by the first layer 13X, the second layer 15X, and the third layer 17X. A quantum well having a deeper (lower) conduction band energy than that of the quantum well is formed (see FIGS. 15 and 16).

In the present embodiment, in the step of irradiating a group V element having a larger atomic radius than the group V element of the group III-V compound semiconductor, the group V having a larger atomic radius than the group V element of the group III-V compound semiconductor. The energy of the conductor in the mixed crystal regions 14X and 16X formed by irradiating the element is lower than the energy of the conduction band of the second layer 15X (see FIGS. 15 and 16).
(Other)
Note that the present invention is not limited to the configurations described in the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the present invention.

Hereinafter, additional notes will be disclosed regarding the above-described embodiment and modifications.
(Appendix 1)
A semiconductor laminated structure including at least an electron transit layer and an electron supply layer above the substrate,
The electron transit layer is made of a III-V group compound semiconductor, and has a structure in which a first layer, a second layer, and a third layer are sequentially stacked, and the second layer includes the first layer and the third layer. A semiconductor having a lighter effective mass of electrons, wherein the energy of the conduction band of the second layer is lower than the energy of the conduction bands of the first layer and the third layer, and the first layer, the second layer, The group V element of the group III-V compound semiconductor has a larger atomic radius than the group V element of the group III-V compound semiconductor at the interface of the second layer and the third layer. A semiconductor device having a mixed crystal region substituted with an element.

(Appendix 2)
The semiconductor stacked structure further includes a lower barrier layer, and has a structure in which the lower barrier layer, the electron transit layer, and the electron supply layer are sequentially laminated, and the first layer and the third layer of the electron transit layer. The semiconductor device according to appendix 1, wherein energy of a conduction band of the layer is lower than energy of a conduction band of the lower barrier layer and the electron supply layer.

(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the energy of the conductor in the mixed crystal region is lower than the energy of the conduction band of the second layer.
(Appendix 4)
The group V element of the group III-V compound semiconductor is As, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. The semiconductor device according to any one of 1 to 3.

(Appendix 5)
The semiconductor device according to claim 4, wherein the electron transit layer has a structure in which an InGaAs layer as the first layer, an InAs layer as the second layer, and an InGaAs layer as the third layer are sequentially stacked. .
(Appendix 6)
The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is As. The semiconductor device according to any one of 1 to 3.

(Appendix 7)
The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. The semiconductor device according to any one of 1 to 3.
(Appendix 8)
The electron transit layer has a structure in which an InGaP layer as the first layer, an InP layer as the second layer, and an InGaP layer as the third layer are sequentially stacked. Semiconductor device.

(Appendix 9)
Forming a semiconductor multilayer structure including at least an electron transit layer and an electron supply layer above the substrate;
The step of forming the electron transit layer includes
Forming a first layer made of a III-V compound semiconductor;
On the first layer, a group III-V compound semiconductor having a lighter effective mass of electrons than the first layer is formed, and a second layer having a conduction band energy lower than that of the first layer is formed.
Each step of forming, on the second layer, a third layer made of a III-V group compound semiconductor having an electron effective mass heavier than that of the second layer and having a conduction band energy higher than that of the second layer. Including
Further, the III-V group between the step of forming the first layer and the step of forming the second layer and between the step of forming the second layer and the step of forming the third layer. A method of manufacturing a semiconductor device, comprising: irradiating a group V element having an atomic radius larger than that of a group V element of a compound semiconductor.

(Appendix 10)
The semiconductor multilayer structure further includes a lower barrier layer,
The step of forming the semiconductor stacked structure includes:
Forming the lower barrier layer;
Forming the electron transit layer including the first layer and the third layer having a conduction band energy lower than that of the lower barrier layer on the lower barrier layer;
Appendix 9 includes the steps of forming the electron supply layer on the electron transit layer having a conduction band energy higher than that of the first layer and the third layer of the electron transit layer. The manufacturing method of the semiconductor device of description.

(Appendix 11)
In the step of irradiating the group V element having a larger atomic radius than the group V element of the III-V group compound semiconductor, the group V element having a larger atomic radius than the group V element of the group III-V compound semiconductor. 11. The method of manufacturing a semiconductor device according to appendix 9 or 10, wherein the energy of the conductor in the mixed crystal region formed by irradiating is lower than the energy of the conduction band of the second layer.

(Appendix 12)
The group V element of the group III-V compound semiconductor is As, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. The manufacturing method of the semiconductor device of any one of 9-11.
(Appendix 13)
Note 12: In the step of forming the electron transit layer, an InGaAs layer is formed as the first layer, an InAs layer is formed as the second layer, and an InGaAs layer is formed as the third layer. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

(Appendix 14)
The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is As. The manufacturing method of the semiconductor device of any one of 9-11.
(Appendix 15)
The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. The manufacturing method of the semiconductor device of any one of 9-11.

(Appendix 16)
Note 14: In the step of forming the electron transit layer, an InGaP layer is formed as the first layer, an InP layer is formed as the second layer, and an InGaP layer is formed as the third layer. Or 15. A method of manufacturing a semiconductor device according to 15.

10 Substrate (InP substrate)
10X substrate (GaAs substrate)
11, 11X Buffer layer 12 InAlAs lower barrier layer 12X InAlP lower barrier layer 13 InGaAs layer (first layer)
13X InGaP layer (first layer)
14 Sb irradiation region (mixed crystal region)
14X As or Sb irradiation region (mixed crystal region)
15 InAs layer (second layer)
15X InP layer (second layer)
16 Sb irradiation region (mixed crystal region)
16X As or Sb irradiation region (mixed crystal region)
17 InGaAs layer (third layer)
17X InGaP layer (third layer)
18 InAlAs spacer layer 18X InAlP spacer layer 19, 19X Si-δ doping layer 20 InAlAs barrier layer 20X InAlP barrier layer 21 InP etching stop layer 22 n-InGaAs cap layer 22X n-InGaP cap layer 23, 23X SiO ₂ film 24, 24X Electronic travel layer (composite channel layer)
25, 25X Electron supply layer 26, 26X Semiconductor laminated structure 31, 31X Source electrode 32, 32X Drain electrode 33, 33X Gate electrode 41 Resist film (ZEP)
42 Resist film (PMGI)
43 Resist film (ZEP)

Claims (9)

A semiconductor laminated structure including at least an electron transit layer and an electron supply layer above the substrate,
The electron transit layer is made of a III-V group compound semiconductor, and has a structure in which a first layer, a second layer, and a third layer are sequentially stacked, and the second layer includes the first layer and the third layer. A semiconductor having a lighter effective mass of electrons, wherein the energy of the conduction band of the second layer is lower than the energy of the conduction bands of the first layer and the third layer, and the first layer, the second layer, The group V element of the group III-V compound semiconductor has a larger atomic radius than the group V element of the group III-V compound semiconductor at the interface of the second layer and the third layer. A semiconductor device having a mixed crystal region substituted with an element.   The semiconductor stacked structure further includes a lower barrier layer, and has a structure in which the lower barrier layer, the electron transit layer, and the electron supply layer are sequentially laminated, and the first layer and the third layer of the electron transit layer. 2. The semiconductor device according to claim 1, wherein the energy of the conduction band of the layer is lower than the energy of the conduction band of the lower barrier layer and the electron supply layer.   The semiconductor device according to claim 1, wherein the energy of the conductor in the mixed crystal region is lower than the energy of the conduction band of the second layer.   The group V element of the group III-V compound semiconductor is As, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. Item 4. The semiconductor device according to any one of Items 1 to 3.   5. The semiconductor according to claim 4, wherein the electron transit layer has a structure in which an InGaAs layer as the first layer, an InAs layer as the second layer, and an InGaAs layer as the third layer are sequentially stacked. apparatus.   The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is As. Item 4. The semiconductor device according to any one of Items 1 to 3.   The group V element of the group III-V compound semiconductor is P, and the group V element having an atomic radius larger than that of the group V element of the group III-V compound semiconductor is Sb. Item 4. The semiconductor device according to any one of Items 1 to 3.   The electron transit layer has a structure in which an InGaP layer as the first layer, an InP layer as the second layer, and an InGaP layer as the third layer are sequentially stacked. Semiconductor device. Forming a semiconductor multilayer structure including at least an electron transit layer and an electron supply layer above the substrate;
The step of forming the electron transit layer includes
Forming a first layer made of a III-V compound semiconductor;
On the first layer, a group III-V compound semiconductor having a lighter effective mass of electrons than the first layer is formed, and a second layer having a conduction band energy lower than that of the first layer is formed.
Each step of forming, on the second layer, a third layer made of a III-V group compound semiconductor having an electron effective mass heavier than that of the second layer and having a conduction band energy higher than that of the second layer. Including
Further, the III-V group between the step of forming the first layer and the step of forming the second layer and between the step of forming the second layer and the step of forming the third layer. A method of manufacturing a semiconductor device, comprising: irradiating a group V element having an atomic radius larger than that of a group V element of a compound semiconductor.

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