JP2016213838A5 - - Google Patents

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Publication number
JP2016213838A5
JP2016213838A5 JP2016093038A JP2016093038A JP2016213838A5 JP 2016213838 A5 JP2016213838 A5 JP 2016213838A5 JP 2016093038 A JP2016093038 A JP 2016093038A JP 2016093038 A JP2016093038 A JP 2016093038A JP 2016213838 A5 JP2016213838 A5 JP 2016213838A5
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JP
Japan
Prior art keywords
data
memory device
memory
vector
scrambled
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JP2016093038A
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English (en)
Japanese (ja)
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JP2016213838A (ja
JP6633967B2 (ja
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Priority claimed from US15/064,191 external-priority patent/US10121013B2/en
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Publication of JP2016213838A5 publication Critical patent/JP2016213838A5/ja
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JP2016093038A 2015-05-07 2016-05-06 Ｓｓｄ通信プロトコルのためのｘｏｒ基盤のスクランブリング及びディスクランブリング方法及びシステム Active JP6633967B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201562158420P 2015-05-07 2015-05-07
US62/158,420 2015-05-07
US201562209166P 2015-08-24 2015-08-24
US62/209,166 2015-08-24
US15/064,191 2016-03-08
US15/064,191 US10121013B2 (en) 2015-05-07 2016-03-08 XOR-based scrambler/descrambler for SSD communication protocols

Publications (3)

Publication Number Publication Date
JP2016213838A JP2016213838A (ja) 2016-12-15
JP2016213838A5 true JP2016213838A5 (cg-RX-API-DMAC7.html) 2019-05-16
JP6633967B2 JP6633967B2 (ja) 2020-01-22

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JP2016093038A Active JP6633967B2 (ja) 2015-05-07 2016-05-06 Ｓｓｄ通信プロトコルのためのｘｏｒ基盤のスクランブリング及びディスクランブリング方法及びシステム

Country Status (5)

Country Link
US (1) US10121013B2 (cg-RX-API-DMAC7.html)
JP (1) JP6633967B2 (cg-RX-API-DMAC7.html)
KR (1) KR102329307B1 (cg-RX-API-DMAC7.html)
CN (1) CN106155584B (cg-RX-API-DMAC7.html)
TW (1) TWI714579B (cg-RX-API-DMAC7.html)

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US10956259B2 (en) * 2019-01-18 2021-03-23 Winbond Electronics Corp. Error correction code memory device and codeword accessing method thereof
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KR20240062654A (ko) 2022-11-02 2024-05-09 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
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