JP2016213386A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of semiconductor device capable of improving the reliability.SOLUTION: A semiconductor device in an embodiment has a first substrate and a second substrate. The first substrate has a first electrode on the surface thereof. The second substrate has a second electrode which is connected to the first electrode on an insulator layer on the surface layer which is bonded to the first substrate, and has a barrier metal film in an enclosed area which encloses the second electrode on the surface of the insulator layer. In the first electrode, the surface area at the side which is connected to the second electrode is larger than the surface area of the second electrode which is connected to the first electrode.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art Conventionally, there is a semiconductor device in which an occupation area is reduced by laminating and bonding substrates on which semiconductor elements and integrated circuits are formed in multiple stages. The insulating layer on the surface side to which each substrate is bonded is provided with electrodes that are connected by bonding the substrates to each other.

  In such a semiconductor device, when misalignment occurs in the substrates to be bonded, the material of one electrode diffuses into the insulating layer of the other substrate, which causes leakage of current from the electrodes, In some cases, poor bonding may occur and reliability may be reduced.

JP 2013-168419 A

  An object of one embodiment is to provide a semiconductor device and a method of manufacturing the semiconductor device that can improve reliability.

  The semiconductor device according to the embodiment includes a first substrate and a second substrate. The first substrate includes a first electrode on the surface. The second substrate includes a second electrode connected to the first electrode in a surface insulating layer bonded to the first substrate, and encloses the second electrode on the surface of the insulating layer. A barrier metal film is provided in the region.

FIG. 1 is an explanatory diagram illustrating a cross-sectional structure of the semiconductor device according to the first embodiment. FIG. 2 is an explanatory view showing a manufacturing process of the second substrate according to the first embodiment. FIG. 3 is an explanatory diagram showing a manufacturing process of the second substrate according to the first embodiment. FIG. 4 is an explanatory view showing a manufacturing process of the first substrate according to the first embodiment. FIG. 5 is an explanatory diagram illustrating a cross-sectional structure of a semiconductor device according to a modification of the first embodiment. FIG. 6 is an explanatory view showing a cross-sectional structure of a semiconductor device according to the second embodiment. FIG. 7 is an explanatory view showing a manufacturing process of the second substrate according to the second embodiment. FIG. 8 is an explanatory diagram illustrating a manufacturing process of the second substrate according to the second embodiment. FIG. 9 is an explanatory diagram illustrating a cross-sectional structure of a semiconductor device according to a modification of the second embodiment. FIG. 10 is an explanatory view showing a cross-sectional structure of a semiconductor device according to the third embodiment. FIG. 11 is an explanatory view showing a manufacturing process of the second substrate according to the third embodiment.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is an explanatory diagram illustrating a cross-sectional structure of the semiconductor device 1 according to the first embodiment. As shown in FIG. 1A, the semiconductor device 1 includes a first substrate 10 and a second substrate 20, and is manufactured by stacking and bonding the first substrate 10 on the second substrate 20. The

  The first substrate 10 includes a semiconductor layer provided with a semiconductor element such as a back-illuminated image sensor. The second substrate 20 includes a semiconductor layer provided with an integrated circuit such as a logic circuit. In FIG. 1, illustration of such a semiconductor layer is omitted.

  The first substrate 10 includes an interlayer insulating film 12 below a semiconductor layer (not shown) on which a semiconductor element or the like is provided, an etching stopper film 13 on the lower surface of the interlayer insulating film 12, and a lower surface of the etching stopper film 13. Includes a first field layer 14.

  The interlayer insulating film 12 is formed of, for example, silicon oxide, and a wiring 11 connected to a semiconductor element or the like is provided therein. The wiring 11 is a so-called copper wiring formed of copper.

  The etching stopper film 13 is formed of, for example, silicon nitride, and is a film that prevents over-etching of the wiring 11 due to etching when a via hole 42 (see FIG. 4) for the first electrode 15 described later is formed by etching. .

  The first field layer 14 is an insulating layer formed of, for example, TEOS (tetraethoxysilane) and provided with the first electrode 15 therein. The first electrode 15 is formed of, for example, copper, and the peripheral surface except the lower surface is covered with the barrier metal film 16.

  The barrier metal film 16 is formed of, for example, titanium nitride, and is a film that suppresses diffusion of copper, which is the material of the first electrode 15, into the first field layer 14. Thus, the 1st board | substrate 10 is equipped with the 1st electrode 15 on the surface (here lower surface) used as the bonding surface with the 2nd board | substrate 20. As shown in FIG.

  In addition, the second substrate 20 includes an interlayer insulating film 22 above a semiconductor layer (not shown) on which an integrated circuit or the like is provided, an etching stopper film 23 on the upper surface of the interlayer insulating film 22, and the etching stopper film 23. A second field layer 24 is provided on the upper surface.

  The interlayer insulating film 22 is formed of, for example, silicon oxide, and a wiring 21 connected to an integrated circuit or the like is provided therein. The wiring 21 is a so-called copper wiring formed of copper.

  The etching stopper film 23 is formed of, for example, silicon nitride, and is a film that prevents over-etching of the wiring 21 due to etching when a via hole 41 for a second electrode 25 described later is formed by etching.

  The second field layer 24 is an insulating layer formed of, for example, TEOS and provided with the second electrode 25 therein. The second electrode 25 is formed of, for example, copper, and the peripheral surface except the upper surface is covered with the barrier metal film 26.

  The barrier metal film 26 is formed of titanium nitride, for example, and is a film that suppresses diffusion of copper, which is the material of the first electrode 15, into the second field layer 24. The barrier metal film 26 of the second substrate 20 extends to a region including the second electrode 25 on the surface of the second field layer 24.

  As described above, the second substrate 20 includes the second electrode 25 connected to the first electrode 15 on the second field layer 24 of the surface layer bonded to the first substrate 10, and the surface of the second field layer 24. A barrier metal film 26 is provided in a region including the second electrode 25 in FIG.

  Here, the portion of the barrier metal film 26 exposed on the surface of the second field layer 24 is the connection surface (lower surface) of the first electrode 15 when the first substrate 10 and the second substrate 20 are bonded. It has an area that can be included. That is, the sum of the area of the barrier metal film 26 on the surface (upper surface) side of the second field layer 24 and the area of the connection surface (upper surface) of the second electrode 25 is the connection surface (lower surface) of the first electrode 15. ) Larger than the area.

  Thereby, the semiconductor device 1 can prevent the copper of the first electrode 15 from diffusing into the second field layer 24 even when the first substrate 10 and the second substrate 20 to be bonded are misaligned. it can.

  Specifically, as shown in FIG. 1B, when the first substrate 10 and the second substrate 20 are bonded together, the semiconductor device 1 is slightly attached to the first substrate 10 and the second substrate 20. Misalignment may occur.

  Even in such a case, in the semiconductor device 1, the copper of the first electrode 15 is on the second field layer 24 side by the barrier metal film 26 interposed between the lower surface of the first electrode 15 and the second field layer 24. Can be prevented from diffusing.

  Therefore, in the semiconductor device 1, current leakage from the first electrode 15 to the second field layer 24 due to the diffusion of copper into the second field layer 24, or the bonding between the first substrate 10 and the second substrate 20. By preventing the occurrence of defects, reliability can be improved.

  Further, the surface area of the first electrode 15 of the semiconductor device 1 on the side connected to the second electrode 25 is larger than the surface area of the side of the second electrode 25 connected to the first electrode 15. As a result, in the semiconductor device 1, the upper surface of the second electrode 25 is within the lower surface of the first electrode 15 even when there is some misalignment between the first substrate 10 and the second substrate 20 to be bonded. Connected at any point.

  Thus, the semiconductor device 1 prevents the copper of the second electrode 25 from coming into contact with the first field layer 14 even if there is a slight misalignment between the first substrate 10 and the second substrate 20. Copper diffusion from the second electrode 25 to the first field layer 14 can be prevented.

  Therefore, in the semiconductor device 1, current leakage from the second electrode 25 to the first field layer 14 due to the diffusion of copper into the first field layer 14 or the bonding between the first substrate 10 and the second substrate 20. By preventing the occurrence of defects, reliability can be improved.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. In the manufacturing process of the semiconductor device 1, processes other than the process of forming the first electrode 15, the second electrode 25, and the barrier metal films 16 and 26 are the same as the manufacturing process of a general semiconductor device.

  Therefore, here, the step of forming the first electrode 15 and the barrier metal film 16 on the unfinished first substrate 10 and the formation of the second electrode 25 and the barrier metal film 26 on the unfinished second substrate 20 are performed. And the description of other manufacturing steps will be omitted. 2 and 3 are explanatory views showing a manufacturing process of the second substrate 20 according to the first embodiment, and FIG. 4 is an explanatory view showing a manufacturing process of the first substrate 10 according to the first embodiment. .

  When the second substrate 20 is manufactured, as shown in FIG. 2A, an interlayer insulating film 22, an etching stopper film 23, and a second field layer on which a wiring 21 is provided on a semiconductor layer (not shown). An incomplete second substrate 20 in which 24 are sequentially stacked is prepared.

  Subsequently, as shown in FIG. 2B, a resist 31 is applied to the surface of the second field layer 24, and the resist 31 is patterned by photolithography, whereby the resist 31 on the position where the second electrode 25 is formed. Is selectively removed.

  Thereafter, by performing anisotropic etching using the patterned resist 31 as a mask, via holes 41 reaching from the surface of the second field layer 24 to the surface of the wiring 21 are formed as shown in FIG. Form.

  Here, the surface of the etching stopper film 23 is exposed, for example, by performing anisotropic dry etching on the second field layer 24 where the resist 31 is removed. Thereafter, the etching stopper film 23 where the surface is exposed is removed by, for example, anisotropic wet etching, so that the surface of the wiring 21 is exposed, a via hole 41 is formed, and the resist 31 is removed.

  Subsequently, a resist 32 is applied again on the surface of the second field layer 24. Then, by patterning the resist 32 by photolithography, as shown in FIG. 3A, the resist 32 on the inclusion region E1 surrounding and enclosing the opening of the via hole 41 on the surface of the second field layer 24 is formed. Selectively remove.

  Thereafter, as shown in FIG. 3B, anisotropic etching using the resist 32 as a mask is performed, so that the surface of the inclusion region E1 in the surface of the second field layer 24 is changed to the inclusion region E1. Retreat from any other surface.

  Subsequently, as shown in FIG. 3C, a barrier metal film 26 is formed by, for example, forming a titanium nitride film on the inner surface of the via hole 41 and the surface of the second field layer 24. Thereafter, a copper layer 50 as a material of the second electrode 25 (see FIG. 1) is laminated in the via hole 41 in which the barrier metal film 26 is formed and on the second field layer 24.

  Finally, the second substrate 20 is thinned from the surface of the copper layer 50 by a thickness d1 by a planarization process such as CMP (Chemical Mechanical Polishing), and the surface of the barrier metal film 26 on the inclusion region E1. And the surface of the second field layer 24 other than the inclusion region E1 are flush with each other. Thereby, the second substrate 20 shown in FIG. 1 is completed.

  When the first substrate 10 is manufactured, as shown in FIG. 4A, the interlayer insulating film 12 provided with the wiring 11 on the semiconductor layer (not shown), the etching stopper film 13, and the first substrate An incomplete first substrate 10 on which field layers 14 are sequentially stacked is prepared.

  Then, a via hole 42 reaching from the surface of the first field layer 14 to the surface of the wiring 11 is formed by a process similar to the process of forming the via hole 41 in the second substrate 20 (see FIGS. 2A and 2B). To do. Here, a via hole 42 having the same shape and size as the via hole 41 of the second substrate 20 is formed.

  Subsequently, a resist 33 is applied again on the surface of the first field layer 14. Then, by patterning the resist 33 by photolithography, the resist 33 on the inclusion region E2 that surrounds and encloses the opening of the via hole 42 on the surface of the first field layer 14 is selectively removed.

  Thereafter, as shown in FIG. 4B, anisotropic etching using the resist 33 as a mask is performed, so that the surface of the inclusion region E2 in the surface of the first field layer 14 is changed to the inclusion region E2. Retreat from any other surface.

  Subsequently, after removing the resist 33, as shown in FIG. 4C, for example, a titanium nitride film is formed on the inner surface of the via hole 42 and the surface of the first field layer 14, thereby forming a barrier metal film. 16 is formed. Thereafter, a copper layer 50 as a material of the first electrode 15 (see FIG. 1) is laminated in the via hole 42 in which the barrier metal film 16 is formed and on the first field layer 14.

  Finally, the first substrate 10 is thinned from the surface of the copper layer 50 by a thickness d2 by a planarization process such as CMP. Thereby, as shown in FIG. 1, the first electrode 15 having the first electrode 15 having a larger surface area on the side connected to the second electrode 25 than the surface area on the side connected to the first electrode 15 of the second electrode 25. The substrate 10 is completed.

  In the first embodiment, a case where the surface area of the first electrode 15 on the side connected to the second electrode 25 is larger than the surface area of the second electrode 25 on the side connected to the first electrode 15 is taken as an example. However, the shape of the first electrode 15 is not limited to this.

  Here, with reference to FIG. 5, a semiconductor device 1a according to a modification of the first embodiment will be described. FIG. 5 is an explanatory diagram showing a cross-sectional structure of a semiconductor device 1a according to a modification of the first embodiment. Here, among the components shown in FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals as those shown in FIG.

  As shown in FIG. 5, the semiconductor device 1a is different from the semiconductor device 1 shown in FIG. 1 in the cross-sectional structure of the first substrate 10a. Specifically, the first substrate 10a of the semiconductor device 1a includes a first electrode 15a and a barrier metal film 16a having the same shape as the second substrate 20. Accordingly, the first field layer 14 a has the same shape as the second field layer 24.

  Here, the portion of the barrier metal film 26 exposed on the surface (upper surface) side of the second field layer 24 is the connection surface of the first electrode 15a when the first substrate 10a and the second substrate 20 are bonded. It has an area that can contain the (lower surface). That is, the sum of the area of the barrier metal film 26 on the surface (upper surface) side of the second field layer 24 and the area of the connection surface (upper surface) of the second electrode 25 is the connection surface (lower surface) of the first electrode 15a. ) Larger than the area.

  Similarly, the portion of the barrier metal film 16a exposed to the surface (lower surface) side of the first field layer 14a is the connection surface of the second electrode 25 when the second substrate 20 and the first substrate 10a are bonded. It has an area that can contain (upper surface). That is, the area obtained by adding the area of the barrier metal film 16a on the surface (lower surface) side of the first field layer 14a and the area of the connection surface (lower surface) of the first electrode 15a is the connection surface (upper surface) of the second electrode 25. ) Larger than the area.

  Therefore, as shown in FIG. 5, the semiconductor device 1 a has a gap between the first electrode 15 a and the second field layer 24 when the first substrate 10 a and the second substrate 20 to be bonded are misaligned. In this, a barrier metal film 26 is interposed. Further, a barrier metal film 16a is interposed between the second electrode 25 and the first field layer 14a.

  As a result, the semiconductor device 1a allows the copper diffusion from the first electrode 15a to the second field layer 24 and the first from the second electrode 25 when the first substrate 10a and the second substrate 20 are misaligned. Copper diffusion to the field layer 14a can be prevented.

  Therefore, the semiconductor device 1a can improve reliability by preventing current leakage due to copper diffusion into the first field layer 14a and the second field layer 24 and bonding failure between the first substrate 10a and the second substrate 20. Can be improved.

  The semiconductor device 1 shown in FIG. 1 and the semiconductor device 1a shown in FIG. 5 are examples of the semiconductor device according to the first embodiment, and can be further modified. For example, in the semiconductor device according to the first embodiment, the second substrate 20 includes the first electrode 15 and the barrier metal film 16 illustrated in FIG. 1, and the first substrate 10 includes the second electrode 25 and the barrier metal film 26. It may be.

  As described above, the semiconductor device according to the first embodiment includes the first substrate having the first electrode on the surface, the second electrode on the surface insulating layer bonded to the first substrate, and the surface of the insulating layer. And a second substrate having a barrier metal film in a region surrounding the periphery of the second electrode.

  Thereby, in the semiconductor device according to the first embodiment, the electrode material diffuses from the first electrode to the insulating layer on the surface of the second substrate when a misalignment occurs between the first substrate and the second substrate to be bonded. This can be prevented. Therefore, the semiconductor device according to the first embodiment can improve the reliability by preventing the leakage of current due to the diffusion of the electrode material into the insulating layer and the poor bonding of the substrates.

(Second Embodiment)
Next, a semiconductor device 1b according to the second embodiment will be described with reference to FIG. FIG. 6 is an explanatory diagram showing a cross-sectional structure of the semiconductor device 1b according to the second embodiment. Here, among the components shown in FIG. 6, the same components as those shown in FIG. 1 are given the same reference numerals as those shown in FIG.

  As shown in FIG. 6A, the semiconductor device 1b includes a first substrate 10 and a second substrate 20b, and is manufactured by laminating and bonding the first substrate 10 on the second substrate 20b. The In the semiconductor device 1b, the shapes of the second electrode 25b and the barrier metal film 26b of the second substrate 20b are different from those of the second substrate 20 shown in FIG.

  Specifically, the upper surface of the second electrode 25b is covered with the barrier metal film 26b in addition to the side surface and the bottom surface. Accordingly, the second electrode 25b is shorter in the thickness direction by the thickness of the barrier metal film 26b provided on the upper surface than the second electrode 25 shown in FIG.

  In addition, the barrier metal film 26b extends to the periphery of the portion covering the upper surface of the second electrode 25b. That is, the barrier metal film 26b is also provided in the inclusion region including the second electrode 25b on the surface of the second field layer 24, similarly to the barrier metal film 26 shown in FIG.

  Further, the portion of the barrier metal film 26b exposed on the surface (upper surface) side of the second field layer 24 is connected to the connection surface (first electrode 15) when the first substrate 10 and the second substrate 20b are bonded. It has an area that can contain the lower surface. That is, the area of the barrier metal film 26 b on the surface (upper surface) side of the second field layer 24 is larger than the area of the connection surface (lower surface) of the first electrode 15.

  For this reason, as shown in FIG. 6B, the semiconductor device 1b has a lower surface of the first electrode 15 and the first electrode 15 when the first substrate 10 and the second substrate 20b to be bonded are misaligned. The barrier metal film 26b is interposed between the two field layers 24.

  According to the semiconductor device 1b, it is possible to prevent the copper of the first electrode 15 from diffusing into the second field layer 24 when the first substrate 10 and the second substrate 20b are misaligned. Therefore, in the semiconductor device 1b, current leakage from the first electrode 15 to the second field layer 24 due to the diffusion of copper into the second field layer 24, or the bonding between the first substrate 10 and the second substrate 20b. By preventing the occurrence of defects, reliability can be improved.

  Next, a method for manufacturing the semiconductor device 1b will be described with reference to FIGS. Of the manufacturing process of the semiconductor device 1b, processes other than the manufacturing process of the second substrate 20b are the same as the manufacturing process of the semiconductor device 1 of the first embodiment. For this reason, the manufacturing process of the 2nd board | substrate 20b is demonstrated here, The description is abbreviate | omitted about another manufacturing process.

  7 and 8 are explanatory views showing a manufacturing process of the second substrate 20b according to the second embodiment. When manufacturing the second substrate 20b, as shown in FIG. 7A, an interlayer insulating film 22, an etching stopper film 23, and a second field layer on which a wiring 21 is provided on a semiconductor layer (not shown). An incomplete second substrate 20b in which 24 is sequentially stacked is prepared.

  Subsequently, via holes 41 reaching from the surface of the second field layer 24 to the surface of the wiring 21 are formed by a process similar to the process shown in FIG. Thereafter, a barrier metal film 26 b is formed on the inner surface of the via hole 41 and the surface of the second field layer 24.

  Subsequently, as shown in FIG. 7B, a copper layer 50, which is a material of the second electrode 25b (see FIG. 6), is laminated inside the via hole 41 and on the second field layer 24. Thereafter, as shown in FIG. 7C, the surface of the second field layer 24 is exposed by a planarization process such as CMP. Thereby, the second electrode 25b is formed.

  Subsequently, as shown in FIG. 8A, a thickness of the second field layer 24 is increased by laminating a TEOS film on the second field layer 24. Thereafter, a resist 34 is applied to the surface of the second field layer 24, the resist 34 is patterned by photolithography, and the resist on the inclusion region E3 that includes the region on the second electrode 25b on the surface of the second field layer 24. 34 is selectively removed.

  Subsequently, as shown in FIG. 8B, anisotropic etching using the patterned resist 34 as a mask is performed, so that the surface of the inclusion region E3 among the surface of the second field layer 24 is obtained. , Retreat from the surface other than the inclusion region E3. Thereafter, as shown in FIG. 8C, a barrier metal film 26b is formed on the second field layer 24 and the second electrode 25b.

  Finally, the second substrate 20b is thinned by a thickness d3 from the upper surface side by a planarization process such as CMP, for example, and the surface of the barrier metal film 26b on the inclusion region E3 and the inclusion in the second field layer 24 The surface of the region other than the region E3 is flush with the surface. Thereby, the second substrate 20b shown in FIG. 6 is completed.

  In the second embodiment, the case where the surface area of the first electrode 15 connected to the second electrode 25b is larger than the surface area of the second electrode 25b connected to the first electrode 15 is taken as an example. However, the shape of the first electrode 15 is not limited to this.

  Here, with reference to FIG. 9, a semiconductor device 1c according to a modification of the second embodiment will be described. FIG. 9 is an explanatory diagram showing a cross-sectional structure of a semiconductor device 1c according to a modification of the second embodiment. Here, among the components shown in FIG. 9, the same components as those shown in FIG. 6 are given the same reference numerals as those shown in FIG.

  As shown in FIG. 9, the semiconductor device 1c is different from the semiconductor device 1b shown in FIG. 6 in the cross-sectional structure of the first substrate 10c. Specifically, the first substrate 10c of the semiconductor device 1c includes a first electrode 15c and a barrier metal film 16c having the same shape as the second substrate 20b. Accordingly, the first field layer 14 c has the same shape as the second field layer 24.

  Here, the portion of the barrier metal film 26b exposed on the surface (upper surface) side of the second field layer 24 is the connection surface of the first electrode 15c when the first substrate 10c and the second substrate 20b are bonded. It has an area that can contain the (lower surface). That is, the area of the barrier metal film 26b on the surface (upper surface) side of the second field layer 24 is larger than the area of the connection surface (lower surface) of the first electrode 15c.

  Similarly, the portion of the barrier metal film 16c exposed on the surface (lower surface) side of the first field layer 14c is the connection surface of the second electrode 25b when the second substrate 20b and the first substrate 10c are bonded. It has an area that can contain (upper surface). That is, the area of the barrier metal film 16c on the surface (lower surface) side of the first field layer 14c is larger than the area of the connection surface (upper surface) of the second electrode 25b.

  For this reason, as shown in FIG. 9, the semiconductor device 1c has a gap between the first electrode 15c and the second field layer 24 when the first substrate 10c and the second substrate 20b to be bonded are misaligned. In this, barrier metal films 16c and 26b are interposed. Also, the barrier metal films 16c and 26b are interposed between the second electrode 25b and the first field layer 14c.

  As a result, in the semiconductor device 1c, when the first substrate 10c and the second substrate 20b are misaligned, the diffusion of copper from the first electrode 15c to the second field layer 24 and the first from the second electrode 25b are first performed. Copper diffusion into the field layer 14c can be prevented.

  Therefore, the semiconductor device 1c can improve reliability by preventing current leakage due to copper diffusion into the first field layer 14c and the second field layer 24 and bonding failure between the first substrate 10c and the second substrate 20b. Can be improved.

  The semiconductor device 1b shown in FIG. 6 and the semiconductor device 1c shown in FIG. 9 are examples of the semiconductor device according to the second embodiment, and can be further modified. For example, in the semiconductor device according to the second embodiment, the first substrate 15 includes the first electrode 15 and the barrier metal film 16 illustrated in FIG. 6, and the first substrate 10 includes the second electrode 25b and the barrier metal film 26b. It may be.

  As described above, the semiconductor device according to the second embodiment includes the first substrate having the first electrode on the surface, the second electrode on the surface insulating layer bonded to the first substrate, and the surface of the insulating layer. And a second substrate having a barrier metal film on the surface of the second electrode and the surface surrounding the second electrode.

  Thereby, in the semiconductor device according to the second embodiment, the electrode material diffuses from the first electrode to the insulating layer on the surface of the second substrate when a misalignment occurs between the first substrate and the second substrate to be bonded. This can be prevented.

  In the semiconductor device according to the second embodiment, since the second electrode is covered with the barrier metal film, the material of the second electrode can be prevented from leaking outside the barrier metal film. Therefore, the semiconductor device according to the second embodiment can improve the reliability by preventing the leakage of current due to the diffusion of the electrode material into the insulating layer and the poor bonding of the substrates.

(Third embodiment)
Next, a semiconductor device 1d according to the third embodiment will be described with reference to FIG. FIG. 10 is an explanatory diagram showing a cross-sectional structure of a semiconductor device 1d according to the third embodiment. Here, among the components shown in FIG. 10, the same components as those shown in FIG. 1 are given the same reference numerals as those shown in FIG.

  As shown in FIG. 10A, the semiconductor device 1d includes a first substrate 10d and a second substrate 20d, and is manufactured by laminating and bonding the first substrate 10d on the second substrate 20d. The The first electrode 15 provided on the first substrate 10d of the semiconductor device 1d and the second electrode 25d provided on the second substrate 20d have the same shape as the first electrode 15 shown in FIG.

  That is, the first electrode 15 is wider at the portion on the second electrode 25d side than the portion on the wiring 11 side from the central position in the thickness direction inside the first field layer 14d. Similarly, the portion of the second electrode 25d on the first electrode 15 side is wider than the portion on the wiring 21 side from the central position in the thickness direction inside the second field layer 24d. Thereby, the semiconductor device 1d can reduce the connection resistance between the first electrode 15 and the second electrode 25d by expanding the connection surface between the first electrode 15 and the second electrode 25d.

  Further, the barrier metal film 16d on the first substrate 10d side covers the peripheral surface except the lower surface of the first electrode 15, and extends to a region surrounding and including the first electrode 15 on the lower surface of the first field layer 14d. Exists. Similarly, the barrier metal film 26d on the second substrate 20d side covers the peripheral surface except the upper surface of the second electrode 25d, and extends to a region surrounding and including the second electrode 25d on the upper surface of the second field layer 24d. Extend.

  Here, the portion of the barrier metal film 26d exposed to the surface (upper surface) side of the second field layer 24d is the connection surface of the first electrode 15 when the first substrate 10d and the second substrate 20d are bonded. It has an area that can contain the (lower surface). That is, the sum of the area of the barrier metal film 26d on the surface (upper surface) side of the second field layer 24d and the area of the connection surface (upper surface) of the second electrode 25d is the connection surface (lower surface) of the first electrode 15. ) Larger than the area.

  Similarly, the portion of the barrier metal film 16d exposed on the surface (lower surface) side of the first field layer 14d is the connection surface of the second electrode 25d when the second substrate 20d and the first substrate 10d are bonded. It has an area that can contain (upper surface). That is, the sum of the area of the barrier metal film 16d on the surface (lower surface) side of the first field layer 14d and the area of the connection surface (lower surface) of the first electrode 15 is the connection surface (upper surface) of the second electrode 25d. ) Larger than the area.

  For this reason, as shown in FIG. 10B, the semiconductor device 1d has the first electrode 15 and the second field layer when a misalignment occurs between the first substrate 10d and the second substrate 20d to be bonded. A barrier metal film 26d is interposed between 24d and 24d. A barrier metal film 16d is interposed between the second electrode 25d and the first field layer 14d.

  As a result, the semiconductor device 1d causes the copper diffusion from the first electrode 15 to the second field layer 24d and the first from the second electrode 25d to the first when the misalignment occurs between the first substrate 10d and the second substrate 20d. Copper diffusion to the field layer 14d can be prevented.

  Accordingly, the semiconductor device 1d can improve reliability by preventing current leakage due to copper diffusion into the first field layer 14d and the second field layer 24d and a junction failure between the first substrate 10d and the second substrate 20d. Can be improved.

  Next, with reference to FIG. 11, a method for manufacturing the semiconductor device 1d according to the third embodiment will be described. In the manufacturing process of the semiconductor device 1d, processes other than the process of forming the first electrode 15, the second electrode 25d, and the barrier metal films 16d and 26d are the same as the manufacturing process of the semiconductor device 1 according to the first embodiment. It is.

  The first electrode 15 and the barrier metal film 16d, and the second electrode 25d and the barrier metal film 26d can be formed by the same manufacturing process. Therefore, here, a manufacturing process for forming the second electrode 25d and the barrier metal film 26d will be described.

  When forming the second electrode 25d and the barrier metal film 26d on the second substrate 20d, as shown in FIG. 11A, the via hole 42 is formed in the second field layer 24d. Here, by the same process as shown in FIGS. 4A and 4B, the second field layer 24d is widened from the upper surface of the second field layer 24d to the center position in the thickness direction of the second field layer 24d. A via hole 42 having a narrow width from the center in the thickness direction to the lower surface is formed.

  Subsequently, the surface of the region surrounding and including the upper opening of the via hole 42 on the uppermost surface of the second field layer 24d is receded by, for example, selective anisotropic etching, thereby being shown in FIG. Thus, the width of the upper portion of the via hole 42 is expanded.

  Thereafter, as shown in FIG. 11C, a barrier metal film 26d is formed on the surfaces of the via hole 42 and the second field layer 24d, and then a copper layer 50 is laminated on the barrier metal film 26d. Finally, the second substrate 20d is thinned from the surface of the copper layer 50 by a thickness d4 by a planarization process such as CMP. Thereby, the second substrate 20d including the second electrode 25d and the barrier metal film 26d as shown in FIG. 10 is completed.

  As described above, the semiconductor device according to the third embodiment includes electrodes on the surface insulating layers to which the first substrate and the second substrate are bonded. Each electrode is provided in the position which opposes, and the dimension of the connection surface side connected by bonding a 1st board | substrate and a 2nd board | substrate is larger than the dimension of a board | substrate inside side. Thereby, the semiconductor device according to the third embodiment can reduce the connection resistance between the electrode on the first substrate side and the electrode on the second substrate side.

  Furthermore, the semiconductor device according to the third embodiment includes a barrier metal film that covers a peripheral surface excluding the surface of each electrode and a surface of a region surrounding and surrounding the electrode on the surface of the insulating layer. Thereby, in the semiconductor device according to the third embodiment, even if a misalignment occurs between the first substrate and the second substrate to be bonded, the electrode on the first substrate side to the insulating layer on the second substrate side, and It is possible to prevent the electrode material from diffusing from the electrode on the second substrate side to the insulating layer on the first substrate side.

  Therefore, according to the semiconductor device according to the third embodiment, the reliability can be improved by preventing the leakage of current due to the diffusion of the electrode material into the insulating layer and the poor bonding of the substrates.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 1a, 1b, 1c, 1d semiconductor device, 10, 10a, 10c, 10d first substrate, 11, 21 wiring, 12, 22 interlayer insulation film, 13, 23 etching stopper film, 14, 14a, 14c, 14d first 1 field layer, 15, 15a, 15c, 15d first electrode, 16, 16a, 16c, 16d, 26, 26b, 26d barrier metal film, 20, 20b, 20d second substrate, 24, 24d second field layer, 25 , 25b, 25d second electrode, 31, 32, 33, 34 resist, 41, 42 via hole, 50 copper layer, E1, E2, E3 inclusion region.

Claims (5)

A first substrate comprising a first electrode on the surface;
The insulating layer of the surface layer bonded to the first substrate includes a second electrode connected to the first electrode, and a barrier metal is provided in an inclusion region surrounding and enclosing the second electrode on the surface of the insulating layer. A semiconductor device comprising: a second substrate comprising a film. The first electrode is
2. The semiconductor device according to claim 1, wherein a surface area of a side connected to the second electrode is larger than a surface area of a side of the second electrode connected to the first electrode. The barrier metal film is
The semiconductor device according to claim 1, wherein a surface of the second electrode connected to the first electrode is covered. Forming a via hole from the surface of the insulating layer of the substrate surface toward the inside of the substrate;
Retreating the surface of the inclusion region surrounding and including the opening of the via hole in the surface of the insulating layer from the surface of the region other than the inclusion region;
Forming a barrier metal film on the inner surface of the via hole and the surface of the insulating layer;
Laminating an electrode material in the via hole in which the barrier metal film is formed and on the insulating layer;
And a step of planarizing the surface of the barrier metal film on the inclusion region and the surface of the region other than the inclusion region in the insulating layer. . Forming a via hole from the surface of the insulating layer of the substrate surface toward the inside of the substrate;
Forming a barrier metal film on the inner surface of the via hole and the surface of the insulating layer;
Laminating an electrode material in the via hole in which the barrier metal film is formed and on the insulating layer;
A step of exposing the surface of the insulating layer to form an electrode by planarization;
Forming an insulating film on the insulating layer after the planarization treatment;
Retreating the surface of the inclusion region surrounding and enclosing the region on the electrode on the surface of the insulating film from the surface of the region other than the inclusion region to expose the electrode material;
Forming a barrier metal film on the surface of the insulating film exposing the electrode material;
And a step of planarizing the surface of the barrier metal film on the inclusion region and the surface of the region other than the inclusion region in the insulating film. .

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