JP2016208452A - Divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a frequency divider that can suppress the occurrence of glitch even if the timing of the control signal is shifted.SOLUTION: The frequency divider of the present invention includes a divide-by-2 circuit for dividing a frequency of an input clock signal by two and outputting four frequency-divided signals having different phases, a selection circuit for selecting one divide-by-two signal from the four divide-by-two signals outputted from the divide-by-two circuit and switching between the first division operation and the second division operation, and a control circuit for outputting a control signal for causing the selection circuit to select the divide-by-two signal in the period of the divide-by-two signal in which the signal levels before and after selection by the selection circuit are the same, and controlling the first frequency dividing operation and the second frequency dividing operation.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a frequency divider used in a PLL circuit or the like.

  The dual modulus prescaler is a circuit that divides an input clock signal, and is a frequency divider that can switch between two division ratios. Since the dual modulus prescaler can set only two values as the frequency division ratio, the dual modulus prescaler is often used for applications that require high-speed clock frequency division because of its high operation speed.

  For example, as a conventional dual modulus prescaler, Non-Patent Document 1 discloses a 2/3 dual modulus prescaler that can switch between frequency division by 2 and frequency division by 3. Here, 2/3 means switching between frequency division by 2 and frequency division by 3.

  FIG. 8 is a diagram showing a configuration of a conventional dual modulus prescaler. This dual modulus prescaler includes a divide-by-2 circuit 1, a selection circuit 2, and a control circuit 3. The divide-by-2 circuit 1 divides the clock signal input from IN by 2, and outputs a divide-by-2 signal having a phase difference of 180 °. The selection circuit 2 is a selection circuit that selects one of the frequency-divided signals output from the frequency-dividing circuit 1 by the control signal cnt from the control circuit 3. The control circuit 3 is a control circuit that receives the signal MOD for switching the frequency dividing operation and outputs cnt for controlling the frequency dividing operation or the frequency dividing operation to the selection circuit 2.

  FIG. 9 is an operation timing chart of a conventional dual modulus prescaler. When MOD is input to the control circuit 3, the control circuit 3 outputs cnt to the selection circuit 2 in order to switch between the divide-by-2 operation and the divide-by-3 operation. When cnt for controlling the selection circuit 2 changes from “L” to “H”, or from “H” to “L”, an operation of dividing by 3 is performed, and when cnt remains “L” or “H”, 2 changes. Dividing operation is performed. In FIG. 9, the thick line is a divide-by-2 signal selected by the selection circuit 2. This circuit can switch the division ratio by controlling the phase of the divide-by-2 signal, and can operate at high speed.

B. Chi, B. Shi, “New implementation of phase-switching technology and it's applications to GHz dual-modulus prescalers. IE Proc.-Circ.

  However, the conventional dual modulus prescaler has a problem that a glitch occurs. Due to this glitch, a device connected to the frequency divider erroneously recognizes the frequency division ratio and malfunctions. A case where the timing of cnt output from the control circuit 3 is slightly shifted will be described. At this time, since the selection timing of the selection circuit 2 is also shifted, it can be seen in FIG. 9 that a glitch has occurred in the output signal of the selection circuit 2. In a general circuit, a signal is recognized by the rising edge of the signal, and the frequency division ratio is determined by the number of edges. Therefore, when a glitch occurs, the next-stage circuit connected to this circuit may erroneously recognize the frequency division ratio and cause a malfunction. For this reason, the occurrence of glitches must be avoided. In the conventional dual modulus prescaler, since a highly accurate timing is required for the control of the selection circuit, it is difficult to actually configure the circuit in consideration of timing variations due to variations in semiconductor element characteristics.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a frequency divider that can suppress the occurrence of glitches even when the timing of control signals is deviated.

  The frequency divider of the present invention divides an input clock signal by two and outputs four divide-by-2 signals having different phases, and four divide-by-2 signals output by the divide-by-2 circuit A selection circuit that selects one of the two frequency-divided signals and switches between the first frequency-dividing operation and the second frequency-dividing operation, and a period of the frequency-divided signal that has the same signal level before and after selection by the selecting circuit. A control circuit is provided that outputs a control signal that causes the selection circuit to select the frequency-divided signal by two and controls the first frequency-dividing operation and the second frequency-dividing operation.

  According to the present invention, this frequency divider does not switch the output signal when performing the frequency division operation, and when the frequency division operation is performed, the frequency division signal having the same signal level before and after selection by the selection circuit. In this period, since the selection circuit selects the output signal, the effect of suppressing the occurrence of glitches can be obtained even if the timing of the control signal is deviated from the selection circuit.

3 is a diagram illustrating a configuration example of a 2/3 dual modulus prescaler according to Embodiment 1. FIG. 3 is an operation timing chart of the 2/3 dual modulus prescaler according to the first exemplary embodiment. 3 is an operation timing chart of the 3/4 dual modulus prescaler according to the first embodiment. FIG. 10 is a diagram illustrating another configuration example of the dual modulus prescaler according to the first embodiment. 6 is a diagram illustrating a configuration example of a 2/3 dual modulus prescaler according to Embodiment 2. FIG. 6 is an operation timing chart of the 2/3 dual modulus prescaler according to the second exemplary embodiment. It is another structural example of the dual modulus prescaler based on Embodiment 2 using a signal delay circuit. It is a figure which shows the structure of the conventional dual modulus prescaler. It is a figure which shows the operation | movement timing chart of the conventional dual modulus prescaler.

Embodiment 1
FIG. 1 is a diagram showing a configuration example of a 2/3 dual modulus prescaler according to Embodiment 1 of the present invention.
This dual modulus prescaler includes a divide-by-2 circuit 1 (an example of a divide-by-2 circuit), a selection circuit 6 (an example of a selection circuit), and a control circuit 7 (an example of a control circuit). The example of the frequency division operation) and the frequency division operation of 3 (an example of the second frequency division operation) are switched. Here, it is assumed that a binary signal represented by High (hereinafter referred to as “H”) or Low (hereinafter referred to as “L”) is handled. The state where the signal level is lower than the predetermined signal level is “L”, and the state where the signal level is higher than the predetermined signal level is “H”. Since it is determined as “L” if the signal level is lower than the predetermined signal level, the output of “L” not only means that a signal lower than the predetermined signal level is output. This includes the case where no signal is output.

  The divide-by-2 circuit 1 is a divide-by circuit that divides a clock signal by two and outputs four divide-by-2 signals having phases different by 90 degrees. The divide-by-2 circuit 1 includes data latch circuits 4 and 5. In FIG. 1, the data latch circuit is represented as Dlatch. The data latch circuit is a circuit that outputs the input data as it is when the clock signal is “H”, and holds and outputs the previous input data when it is “L”. In data latch circuits 4 and 5 in FIG. 1,> is a terminal to which a clock signal is input (hereinafter referred to as a clock terminal), and D is a data terminal to which a data signal is input (hereinafter referred to as D terminal). Q is a data signal output terminal (hereinafter referred to as Q terminal), and Q bar (a symbol with a line on Q) is an inverted output terminal (inverted output terminal for outputting a signal obtained by inverting Q output signal). (Hereinafter referred to as -Q terminal). For example, when the clock signal is “H” and D is “H”, Q is “H” and −Q is “L”.

  In the data latch circuit 5 in FIG. 1, the circle in front of the clock terminal means that the signal is inverted. Normally, the data latch circuit holds data when the clock signal falls from “H” to “L”. However, when there is a circle, the signal is inverted, so that the data is held when the clock signal rises from “L” to “H”. For example, in the data latch circuit 5, when the clock signal rises from “L” to “H”, if D is “H”, Q is held at “H” and −Q is held at “L”. The

  In the divide-by-2 circuit 1, the clock terminal of the data latch circuit 4 and the clock terminal of the data latch circuit 5 are connected. The −Q terminal of the data latch circuit 5 is connected to the D terminal of the data latch circuit 4. The output terminals of the divide-by-2 circuit 1 are the Q terminal of the data latch circuit 4, the Q terminal of the data latch circuit 5, the -Q terminal of the data latch circuit, and the -Q terminal of the data latch circuit 5. With this configuration, the divide-by-2 circuit 1 can output four signals having phases different by 90 degrees.

  The selection circuit 6 selects one signal from the four signals output from the divide-by-2 circuit 1 by the control signals cnt <0> and cnt <1> output from the control circuit 7, and performs a divide-by-2 operation. This is a selection circuit for switching between the three-frequency division operation. In FIG. 1, 00, 01, 10, and 11 in the selection circuit 6 indicate the values of control signals (cnt <1> and cnt <0>) output from the control circuit 7. Here, “L” = 0 and “H” = 1. The selection circuit 6 determines and outputs a signal to be selected according to the value of (cnt <1>, cnt <0>). The selection circuit 6 selects a signal of 0 ° when (cnt <1>, cnt <0>) = (“L”, “L”) = (0, 0), and selects (cnt <1>, cnt When <0>) = (“L”, “H”) = (0, 1), a 90 ° signal is selected, and (cnt <1>, cnt <0>) = (“H”, “H “) = (1, 1), a signal of 180 ° is selected, and when (cnt <1>, cnt <0>) = (“ H ”,“ L ”) = (1, 0), 270 Select the signal at °. For the selection circuit 6, for example, a multiplexer or an analog switch is used.

  The control circuit 7 is a control circuit that outputs control signals cnt <0> and cnt <1> indicating signals to be selected by the selection circuit 6 to the selection circuit 6. The control circuit 7 is composed of a logic circuit, and outputs a control signal for causing the selection circuit 6 to select the divided signal by 2 during the period of the divided signal by 2 with the same signal level before and after selection by the selection circuit 6. Controls the circumferential operation and the previous divide-by-3 operation.

Next, the operation of the dual modulus prescaler according to the first embodiment will be described.
When this circuit performs a frequency-dividing operation by 2, the selection circuit 6 outputs a signal of 0 ° or 180 ° without switching the output signal.

  On the other hand, when this circuit performs the frequency division operation by 3, the selection circuit 6 switches the output signal twice. For example, the selection circuit 6 switches the output signal so that the signal of 0 ° → the signal of 90 ° → the signal of 180 °. The cycle for switching the output signal is 7/4 × T⇒1 / 2 × T⇒3 / 4 × T. In the above example, the selection circuit 6 outputs a 0 ° signal for 7/4 × T, and then outputs a 90 ° signal for 1/2 × T, and then 3/4 × T. During this time, a 180 ° signal is output. As will be described later, the selection circuit 6 switches the signal at a cycle of 7/4 × T⇒1 / 2 × T⇒3 / 4 × T, so that even if the switching timing is shifted by 1/4 × T before and after, The selection circuit 6 can switch signals within a period in which the front and rear signal levels are the same, thereby preventing the occurrence of glitches. In other words, by switching signals at a cycle of 7/4 × T⇒1 / 2 × T⇒3 / 4 × T, a margin amount before and after a shift in switching timing can be secured.

FIG. 2 is an operation timing chart of the 2/3 dual modulus prescaler according to the first exemplary embodiment.
In FIG. 2, MOD is a signal that instructs the control circuit 7 to switch the frequency division ratio. IN is a clock signal input to the divide-by-2 circuit. T is the period of the clock signal. 0 °, 90 °, 180 °, and 270 ° are signals output from the divide-by-2 circuit 1. At 0 °, 90 °, 180 °, and 270 °, the thick line is a signal selected by the selection circuit 6. cnt <0> and cnt <1> are control signals for the selection circuit 6. OUT is an output signal of the selection circuit 6.

  Here, as shown in FIG. 2, the operation in the case where the control circuit 7 changes the frequency division ratio in the order of frequency division / 2, frequency division 3, frequency division 3, and frequency division 2 will be described. The period for performing each frequency division operation is 2T⇒3T⇒3T⇒2T.

  In FIG. 2, when MOD = “H” is not input to the control circuit 7 during the time A to A−1, the control circuit 7 determines that the frequency dividing operation is performed during the time A to B. In that case, the control circuit 7 outputs the control signals (cnt <1>, cnt <0>) = (“L”, “L”) to the selection circuit 6. The MOD input to the control circuit 7 is “L” when the frequency is divided by 2, and is “H” when the frequency is divided by 3.

  It is assumed that the initial state of the selection circuit 6 is 0 °. The selection circuit 6 selects a 0 ° signal according to the control signals (cnt <1>, cnt <0>) = (“L”, “L”) input to the selection circuit 6, and outputs the 0 ° signal. Output. In this way, in the case of the divide-by-2 operation, the selection circuit 6 outputs the same signal without changing the signal to be selected. In the case of performing the divide-by-2 operation, the selection circuit 6 may select and output a 180 ° signal instead of a 0 ° signal. Further, the initial state of the selection circuit 6 is not 0 ° but may be a signal of another phase.

  Next, the operation of this circuit from time B to time C will be described. When MOD = “H” is input to the control circuit 7 during the time B to B−1, the control circuit 7 determines that the frequency division operation is performed during the time B to C. When switching from the divide-by-2 operation to the divide-by-3 operation, when the time is B-1, the control circuit 7 selects (cnt <1>, cnt <0>) = (“L”, “H”) Output to circuit 6.

  The selection circuit 6 selects and outputs a 90 ° signal according to (cnt <1>, cnt <0>) = (“L”, “H”) output from the control circuit 7.

  Thereafter, the control circuit 7 outputs (cnt <1>, cnt <0>) = (“H”, “H”) to the selection circuit 6 at B-2.

  The selection circuit 6 selects and outputs a 180 ° signal according to (cnt <1>, cnt <0>) = (“H”, “H”) output from the control circuit 7.

  As described above, when the frequency division operation is switched from the frequency division 2 operation to the frequency division 3 operation, the selection circuit 6 outputs a 0 ° signal from B to B-1, and from B-1. A 90 ° signal is output during B-2, and a 180 ° signal is output between B-2 and C. That is, when performing the divide-by-3 operation, the selection circuit 6 switches the output signal twice.

  Next, the operation of this circuit from time C to D will be described. In this case, the circuit continues to divide by 3 from the divide by 3 operation. If MOD = “H” is input to the control circuit 7 during the time period from C to C−1, it is determined that the control circuit 7 performs the divide-by-3 operation during the time period from C to D. When the time is C−1, the control circuit 7 outputs (cnt <1>, cnt <0>) = (“H”, “L”) to the selection circuit 6.

The selection circuit 6 outputs (cnt <1>, cnt <0>) = (“H”, “
In accordance with L ″), a 270 ° signal is selected and output.

  Thereafter, the control circuit 7 outputs (cnt <1>, cnt <0>) = (“L”, “L”) to the selection circuit 6 when the time is C−2.

  The selection circuit 6 selects and outputs a 0 ° signal in accordance with (cnt <1>, cnt <0>) = (“L”, “L”) output from the control circuit 7. Thus, in the case of performing the divide-by-3 operation, the selection circuit 6 switches the output signal twice.

  Next, the operation of this circuit from time D to E will be described. In this case, the circuit switches from the divide-by-3 operation to the divide-by-2 operation. If MOD = “L” is input to the control circuit 7 during the time period from D to D−1, the control circuit 7 determines that the frequency division operation is performed during the time period D to E.

  The control circuit 7 outputs (cnt <1>, cnt <0>) = (“L”, “L”) to the selection circuit 6 during the time from D to D−1.

  The selection circuit 6 selects a 0 ° signal according to (cnt <1>, cnt <0>) = (“L”, “L”) output from the control circuit 7 and outputs a 0 ° signal.

  When the selection circuit 6 performs the above operation, the circuit can switch between the divide-by-2 operation and the divide-by-3 operation.

  Furthermore, this circuit has a margin of 1/4 × T before and after the timing shift when the selection circuit 6 selects the output signal. In the case of the divide-by-3 operation, the selection circuit 6 selects the output signal in the period of the divide-by-2 signal in which the signal levels before and after selection by the selection circuit 6 are the same as described above. Even if the timing for selecting is shifted by 1/4 × T time before and after, the signal level of “L” or “H” does not change and no glitch occurs. Since signals are switched between signals that differ by 90 °, the signal level before switching and the signal level after switching are the same for 1/4 × T before and after switching. For example, when the time is B−1, the signal of 0 ° before switching is “L” for 1/4 × T before and after switching, and the signal of 90 ° after switching is “L”. Further, when the time is B-2, the signal of 90 ° before switching is “L” for 1/4 × T before and after switching, and the signal of 180 ° after switching is “L”. Thus, in this circuit, since the signal level does not change for a certain period before and after the selection circuit 6 selects a signal, no glitch occurs even when the selection timing of the selection circuit 6 is shifted.

  The timing at which the control circuit 7 determines whether the frequency dividing operation is the frequency dividing operation or the frequency dividing operation is 3 is as follows. The control circuit 7 determines whether the frequency dividing operation is the frequency dividing operation or the frequency dividing operation of 3 based on the value of the MOD input from the start of the frequency dividing operation until 7/4 × T. For example, in FIG. 2, the frequency dividing operation between A and B is determined by the value of MOD input between A and A-1, and in FIG. 2, MOD = “L”. 7 is determined to perform a divide-by-2 operation. The frequency dividing operation between B and C is determined by the value of MOD inputted between B and B−1. In FIG. 2, MOD = “H”. It is decided to move. As described above, the control circuit 7 determines whether the frequency dividing operation is the frequency dividing operation or the frequency dividing operation of 3 based on the value of the MOD input until 7/4 × T has elapsed since the start of the frequency dividing operation. The control circuit 7 determines that the divide-by-3 operation is performed if MOD = “H” is input even once between the start of the divide operation and 7/4 × T, and the MOD = “L”. For example, it is determined that the operation is divided by two.

  As described above, this dual modulus prescaler does not switch the output signal when performing the divide-by-2 operation, and does not switch the output signal when performing the divide-by-3 operation. Since the selection circuit 6 selects the output signal during this period, the effect of suppressing the occurrence of glitches can be obtained even if the timing of the control signal is deviated from the selection circuit 6. In addition, since two states can be switched using one divide-by-2 circuit, an effect of operating at high speed can be obtained.

  Although the dual modulus prescaler that switches between the divide-by-2 operation and the divide-by-3 operation has been described here, the present invention is not limited to this. For example, a dual modulus prescaler (hereinafter, referred to as a 3/4 dual modulus prescaler) that switches between a frequency division operation and a frequency division operation of 4 can be realized.

  FIG. 3 is an operation timing chart of the 3/4 dual modulus prescaler according to the first exemplary embodiment. The notation in FIG. 3 is the same as FIG.

The operation of the 3/4 dual modulus prescaler will be described below.
In FIG. 3, the frequency dividing operation from A to B is performed by 3, and the frequency dividing operation from B to C is performed by 4.

  When performing the divide-by-3 operation, the selection circuit 6 switches the output signal twice. In FIG. 3, the selection circuit 6 switches output signals between A-1 and A-2 between A and B. For example, the selection circuit 6 switches the output signal such that 0 ° signal ⇒ 90 ° signal when A-1 and 90 ° signal ⇒ 180 ° signal when A-2. The cycle of switching the output signal is 7/4 × T from A to A-1, 1/2 × T from A-1 to A-2, and 3/4 × T from A-2 to B.

  When the divide-by-4 operation is performed, the selection circuit 6 switches the output signal four times. In FIG. 3, the selection circuit 6 switches output signals at B-1, B-2, B-3, and B-4 between B and C that perform the frequency division operation. For example, when the selection circuit 6 is B-1, the 180 ° signal ⇒ 270 ° signal, the B-2 270 ° signal ⇒ 0 ° signal, and the B-3 signal 0 ° signal ⇒ When the signal is 90 ° and B-4, the output signal is switched as follows: 90 ° signal ⇒ 180 ° signal. The cycle for switching the output signal is 7/4 × T from B to B-1, 1/2 × T from B-1 to B-2, 1/2 × T from B-2 to B-3, B-3 To B-4 is 1/2 × T, and B-4 to C is 3/4 × T.

  By switching the output signals in this way, a 3/4 dual modulus prescaler can be realized with the same configuration as the 2/3 dual modulus prescaler.

  In the case of the 3/4 dual modulus prescaler, the timing at which the control circuit 7 determines whether the frequency division operation is 3 or 4 is as follows. The control circuit 7 determines whether the frequency dividing operation is the frequency dividing operation by 3 or the frequency dividing operation by 4 based on the MOD value input from the start of the frequency dividing operation to 11/4 × T. For example, in FIG. 3, the frequency dividing operation between A and B is determined by the value of MOD input between A and A-3, and in FIG. 3, MOD = “L”. 7 is determined to perform the divide-by-3 operation. The frequency dividing operation between B and C is determined by the value of MOD input between B and B-3. In FIG. 3, MOD = “H”, so that the control circuit 7 divides by 4 It is decided to move. The control circuit 7 determines that the divide-by-4 operation is performed if MOD = “H” is input even once between the start of the dividing operation and 11/4 × T, and the MOD = “L”. For example, it is determined that the operation is divided by three.

  The 3/4 dual modulus prescaler has been described above. In the case of the N / N + 1 dual modulus prescaler, the following is obtained. Here, N is an integer of 3 or more.

  In the case of N frequency division operation, the selection circuit 6 switches the output signal N−1 times. The cycle for switching is 7/4 × T⇒1 / 2 × T⇒.. .⇒1 / 2 × T⇒3 / 4 × T. Here, ½ × T is repeated 2N−5 times.

  As described above, even in the case of the N / N + 1 dual modulus prescaler, as in the 2/3 dual modulus prescaler, the first period is 7/4 × T and the last period is 3/4 × T. The frequency division ratio changes depending on how many times the ½ × T period is repeated during that period.

  In the case of N + 1 frequency division operation, the selection circuit 6 switches the output signal N times. The cycle for switching is 7/4 × T⇒1 / 2 × T⇒.. .⇒1 / 2 × T⇒3 / 4 × T. Here, 1/2 × T is repeated 2N-3 times.

  In the case of the N / N + 1 dual modulus prescaler, the timing at which the control circuit 7 determines whether the N frequency dividing operation or the N + 1 frequency dividing operation is as follows. The control circuit 7 determines whether the N frequency dividing operation or the N + 1 frequency dividing operation is performed based on the MOD value input between the start time of the frequency dividing operation and (N−1) / 4 × T. The control circuit 7 determines that the N + 1 frequency dividing operation is performed if MOD = “H” is input even once between the start of the frequency dividing operation and (N−1) / 4 × T, and the MOD = “ If “L”, it is determined that the N-dividing operation is performed.

  As described above, this dual modulus prescaler can switch between the N frequency dividing operation and the N + 1 frequency dividing operation.

The dual modulus prescaler according to the first embodiment may be configured as follows.
FIG. 4 is a diagram illustrating another configuration example of the dual modulus prescaler according to the first embodiment.
Compared with FIG. 3, a signal delay circuit 8 is provided between the divide-by-2 circuit 1 and the selection circuit 6, and the difference is that the divide-by-2 circuit 1 and the control circuit 7 are connected.

  The signal delay circuit 8 is a signal delay circuit that delays the output signal of the divide-by-2 circuit 1 and outputs the delayed signal to the selection circuit 6. An inverter or a buffer is used for the signal delay circuit 8. A desired delay time can be obtained by connecting a plurality of inverters or buffers in series. The signal delay circuit 8 may be an amplifier.

  As described in the description of the 2/3 dual modulus prescaler, according to the present invention, even if the control timing of the selection circuit 6 slightly varies, the frequency dividing operation is not affected and no glitch is generated. It should be noted that the center value itself of the control timing of the selection circuit 6 is preferably synchronized with the timing of the output signal of the divide-by-2 circuit 1. This is because the margin amount with respect to the timing shift of the selection circuit 6 is reduced if they are not synchronized. Therefore, in this circuit, the control circuit 7 outputs the control signal to the selection circuit 6 in synchronization with the timing of the output signal of the divide-by-2 circuit 1.

  However, even if the control circuit 7 is synchronized with the timing of the output signal of the divide-by-2 circuit 1, if the control signal (cnt <1>, cnt <0>) is delayed by the processing of the control circuit 7, the control timing The variation margin decreases, and in some cases, normal operation cannot be performed. This problem is particularly noticeable when the input clock frequency is high.

  In order to avoid this situation, in the present circuit in which the signal delay circuit 8 is added, the signal delay circuit 8 delays the input signal to the selection circuit 6 by the processing time of the control circuit 7 and is output from the divide-by-2 circuit 1. The timing at which the signal is input to the selection circuit 6 and the timing at which the control signal output from the control circuit 7 is input to the selection circuit 6 are matched. As a result, it is possible to operate even with an input clock having a high frequency.

Embodiment 2
In the second embodiment, a configuration example of the control circuit 7 will be described.
FIG. 5 is a diagram illustrating a configuration example of a 2/3 dual modulus prescaler according to the second embodiment.
In FIG. 5, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and the description thereof is omitted.

  The control circuit 7 includes a logic circuit, and includes a selection circuit 9 (an example of a first selection circuit), a selection circuit 10 (an example of a second selection circuit), an AND gate 11 (an example of a second gate circuit), AND gate 12 (an example of a third gate circuit), AND gate 15 (a first gate circuit), DFF 13 (an example of a third flip-flop), DFF 14 (an example of a fourth flip-flop), DFF 16 (a first gate circuit) And a DFF 17 (an example of a second flip-flop).

  The selection circuit 9 is a selection circuit that selects and outputs one signal from the four signals output from the divide-by-2 circuit 1 in accordance with the output signal of the DFF 16 and the output signal of the DFF 17. The selection circuit 9 is connected to the divide-by-2 circuit 1 in parallel with the selection circuit 6. The 0 ° signal line of the divide-by-2 circuit 1 is connected to the 00 terminal of the selection circuit 9, and the 90 ° signal line of the divide-by-2 circuit 1 is connected to the 01 terminal of the selection circuit 9. The 1 180 ° signal line is connected to the 11 terminal of the selection circuit 9, and the 270 ° signal line of the divide-by-2 circuit 1 is connected to the 10 terminal of the selection circuit 9.

  The selection circuit 10 is a selection circuit that selects and outputs one signal from the four signals output from the divide-by-2 circuit 1 in accordance with the output signal of the DFF 16 and the output signal of the DFF 17. Similar to the selection circuit 9, the selection circuit 10 is connected to the divide-by-2 circuit 1 in parallel with the selection circuit 6. However, the connection relationship between the four output terminals of the divide-by-2 circuit 1 and the four terminals of the selection circuit 10 is different from that of the selection circuit 9. The 0 ° signal line of the divide-by-2 circuit 1 is connected to the 01 terminal of the selection circuit 10, and the 90 ° signal line of the divide-by-2 circuit 1 is connected to the 11 terminal of the selection circuit 10. The 1 180 ° signal line is connected to the 10 terminal of the selection circuit 10, and the 270 ° signal line of the divide-by-2 circuit 1 is connected to the 00 terminal of the selection circuit 9.

  The AND gate 11 is an AND gate that receives the output signal of the selection circuit 9 and the output signal of the AND gate 15 and outputs the logical product of the two input signals to the DFF 13.

  The AND gate 12 is an AND gate that receives the output signal of the selection circuit 10 and the output signal of the AND gate 15 and outputs the logical product of the two input signals to the DFF 14.

  The AND gate 15 receives the signal MOD for instructing the frequency dividing operation, inverts the signal output from the selection circuit 6, and inputs the logical product of the two input signals to the AND gates 11 and 12. This is an AND gate to output.

  The DFF 13 is a flip-flop that holds 1-bit data, the output signal of the AND gate 11 is input to the clock terminal, and the −Q terminal and the D terminal are connected.

  The DFF 14 is a flip-flop that holds 1-bit data, the output signal of the AND gate 12 is input to the clock terminal, and the −Q terminal and the D terminal are connected.

  The DFF 16 is a flip-flop that holds 1-bit data, the output signal of the selection circuit 6 is input to the clock terminal, the output signal of the DFF 13 is input to the D terminal, and the signal is output from the Q terminal.

  The DFF 17 is a flip-flop that holds 1-bit data, the output signal of the selection circuit 6 is input to the clock terminal, the output signal of the DFF 13 is input to the D terminal, and the signal is output from the Q terminal.

Next, the operation of the dual modulus prescaler of the second exemplary embodiment will be described.
Since the operation as the dual modulus prescaler is the same as that of the first embodiment, the description thereof is omitted.
The operation of the control circuit 7 will be described.
FIG. 6 is an operation timing chart of the 2/3 dual modulus prescaler according to the second exemplary embodiment.

  In FIG. 6, cnt2 <0> is a control signal output from the Q terminal of the DFF 17 to the selection circuits 9 and 10. Similarly, cnt2 <1> is a control signal output from the Q terminal of the DFF 16 to the selection circuits 9 and 10. sel2 <0> is a signal output from the selection circuit 10 to the AND gate 12. sel2 <1> is a signal output from the selection circuit 9 to the AND gate 11. tmask is a signal output from the AND gate 15 to the AND gates 11 and 12. tclk <0> is a signal output from the AND gate 12 to the DFF 14. tclk <1> is a signal output from the AND gate 11 to the DFF 13. cnt <0> is a control signal to the selection circuit 6 output from the D terminal of the DFF 14. Similarly, cnt <1> is a control signal to the selection circuit 6 output from the D terminal of the DFF 13.

  As shown in FIG. 6, the operation when the control circuit 7 changes the frequency division ratio in the order of frequency division → division 3 → division 3 → division 3 → division is described. The period for performing each frequency division operation is 2T⇒3T⇒3T⇒2T.

  First, a case where the frequency dividing operation is performed from A to B will be described. When the frequency division operation is performed, MOD = “L” is input to the control circuit 7. The control circuit 7 outputs (cnt <1>, cnt <0>) = (“L”, “L”) to the selection circuit 6. The selection circuit 6 selects a signal of 0 ° from among the signals output from the divide-by-2 circuit 1 according to (cnt <1>, cnt <0>) = (“L”, “L”). Is output.

  Next, a case where the frequency division operation is performed from B to C will be described. When switching from the divide-by-2 operation to the divide-by-3 operation, MOD = “H” is input to the AND gate 15 of the control circuit 7. In FIG. 6, when B, MOD = “H” is input to the AND gate 15 of the control circuit 7. Further, the inverted signal of the signal output from the selection circuit 6 is input to the AND gate 15. In FIG. 6, after the divide-by-2 operation is completed, that is, when B, the selection circuit 6 outputs out = “H”, and then outputs B = “L” when B−1.

  Therefore, when the selection circuit 6 outputs out = “L”, that is, when B−1, the AND gate 15 sets tmask = “H” to one terminal of the AND gate 11 and one terminal of the AND gate 12. Output to. Sel2 <0> is input from the selection circuit 9 to the other input terminal of the AND gate 11.

When the time is B-2, the selection circuit 10 selects the signal of 270 °, so sel2 <0> changes from “L” to “H”. At that timing, both inputs of the AND gate 12 become “H”, and the AND gate 12 outputs tclk <0> = “H” to the DFF 14. The DFF 14 receives tclk <0> = “H” and outputs cnt <0> = “H” to the selection circuit 6. At this time, cnt <1> = “L”.
Upon receiving cnt <0> = “H” and cnt <1> = “L”, the selection circuit 6 changes the signal to be selected from a 0 ° signal to a 90 ° signal, and outputs a 90 ° signal. To do.

  Since the selection circuit 9 selects the 0 ° signal when the time is B-3, sel2 <1> = “H” is input from the selection circuit 9 to the other input terminal of the AND gate 11. Is done. At that timing, both inputs of the AND gate 11 become “H”, and the AND gate 11 outputs tclk <1> = “H” to the DFF 13. The DFF 13 receives tclk <1> = “H” and outputs cnt <1> = “H” to the selection circuit 6.

  Since the signals cnt <0> = “H” and cnt <1> = “H” are input to the selection circuit 6, the selection circuit 6 changes the signal to be selected from the 90 ° signal to 180 °. The signal is changed to and output. Since the selection circuit 6 switches the output signal twice between B and C, the selection circuit 6 performs a divide-by-3 operation.

  Next, a case where the frequency division operation is performed from C to D will be described. During the previous divide-by-3 operation, cnt <1> = “H” is input to the D terminal of the DFF 16, and cnt <1> = “H” is input to the D terminal of the DFF 17. Yes. After the previous divide-by-3 operation is completed, that is, when the time is C, the output signal of the selection circuit 6 changes from “L” to “H”, and the signal is applied to the clock terminal of the DFF 16 and the clock terminal of the DFF 17. Is output. Then, the DFF 16 outputs cnt2 <1> = “H” to the selection circuits 9 and 10. Similarly, the DFF 17 outputs cnt2 <0> = “H” to the selection circuits 9 and 10.

  In response to the control signal cnt2 <1> = “H” from the DFF 16 and the control signal cnt2 <0> = “H” from the DFF 17, the selection circuit 9 selects a signal from 0 ° to 180 °. And the signal is output to the AND gate 11.

  Similarly, in response to the control signal cnt2 <1> = “H” from the DFF 16 and the control signal cnt2 <0> = “H” from the DFF 17, the selection circuit 10 changes the signal from 270 ° to the signal 90 °. The signal to be selected is changed and the signal is output to the AND gate 12.

  When the time is C−1, out = “H” is changed to out = “L”. Therefore, the AND gate 15 sets tmask = “H” to one terminal of the AND gate 11 and one terminal of the AND gate 12. Output to.

  Since sel2 <0> = “H” and tmask = “H” are input to the AND gate 12 when the time is C−2, the AND gate 12 outputs tclk <0> = “H” to the DFF 14. To do.

  When tclk <0> = “H” is input to the DFF 14, the input signal of the DFF 14 is switched from “L” to “H”. Therefore, the DFF 14 changes the output signal cnt <0> from “H” to “L”. Then, cnt <0> = “L” is output to the selection circuit 6.

  Since the signals input to the selection circuit 6 are cnt <1> = “H” and cnt <0> = “L”, the selection circuit 6 switches the signal to be selected from the 180 ° signal to the 270 ° signal. A 270 ° signal is output.

  When the time is C-3, sel2 <1> = “H” and tmask = “H” are input to the AND gate 11. Therefore, the AND gate 11 outputs tclk <1> = “H” to the DFF 13.

  When tclk <1> = “H” is input to the DFF 13, the input signal of the DFF 13 is switched from “L” to “H”. Therefore, the DFF 13 changes the output signal cnt <1> from “H” to “L”. Then, cnt <1> = “L” is output to the selection circuit 6.

  Since the signals input to the selection circuit 6 are cnt <1> = “L” and cnt <0> = “L”, the selection circuit 6 switches the signal to be selected from the 270 ° signal to the 0 ° signal. , A 0 ° signal is output.

  As described above, since the selection circuit 6 switches the output signal twice during the time period from C to D, the selection circuit 6 performs the divide-by-3 operation.

  Next, a case where the frequency dividing operation is performed from D to E will be described. When the time is D, MOD = “L” is input to the AND gate 14. As a result, the AND gate 14 outputs tmask = “L” to the AND gates 11 and 12. Since one signal input to the AND gates 11 and 12 is “L”, the signal tclk <1> output from the AND gate 11 and the signal tclk <0> output from the AND gate 12 are both “L”. become.

  Since the values of tclk <1> and tclk <0> have not changed from the time when the previous divide-by-3 operation, that is, D, has occurred, the DFF 13 sets cnt <1> = “L” to the selection circuit 6. The DFF 14 continues to output cnt <0> = “L” to the selection circuit 6. The selection circuit 6 continues to output the 0 ° signal in accordance with cnt <0> = “L” and cnt <1> = “L”.

  Thus, since the selection circuit 6 does not switch the output signal during the time from D to E, the selection circuit 6 performs the frequency division operation by two.

  As described above, according to the second embodiment, the output signal of the selection circuit 6 and the output signal of the divide-by-2 circuit 1 are input to the control circuit 7, and the control circuit 7 uses the both signals to select the selection circuit 6. Since the control signal is generated with respect to the divide-by-2 signal output from the divide-by-2 circuit 1, the control signal output from the selection circuit 7 to the selection circuit 6 can be synchronized. Thereby, it is possible to prevent the timing at which the selection circuit 6 selects the frequency-divided signal by 2 based on the control signal from being shifted. Further, the control circuit 7 of the second embodiment can be configured by two selection circuits, three AND gates, and four DFFs, and is controlled in a simple configuration at high speed in synchronization with the output signal of the divide-by-2 circuit 1. A signal can be generated.

In the second embodiment, the signal delay circuit 8 may be used.
FIG. 7 is another configuration example of the dual modulus prescaler according to the second exemplary embodiment using a signal delay circuit. Compared with FIG. 5, a signal delay circuit 8 is provided between the divide-by-2 circuit and the selection circuit 6. With such a configuration, the delay time due to the processing of the control circuit 7 can be compensated by the signal delay circuit 8, so that the timing at which the output signal of the divide-by-2 circuit 1 reaches the selection circuit 6 and the control circuit 7 The timing for outputting the control signal to the selection circuit 6 can be matched. As a result, even when the frequency of the input clock signal increases, the occurrence of glitches due to timing shifts can be prevented. Here, the signal delay circuit 8 compensates for delays of the selection circuits 9 and 10, the AND gates 11 and 12, and the DFFs 13 and 14.

1 2 frequency divider circuit, 2 6 9 10 selection circuit, 3 7 control circuit, 8 signal delay circuit, 11 12 15 AND gate, 13 14 16 17 DFF.

Claims (5)

A divide-by-2 circuit that divides the input clock signal by 2 and outputs four divide-by-2 signals with different phases;
A selection circuit that selects one of the two frequency-divided signals from the four frequency-divided signals output by the frequency-dividing circuit and switches between a first frequency-dividing operation and a second frequency-dividing operation;
A control signal for causing the selection circuit to select the divided-by-2 signal is output during the period of the divided-by-2 signal in which the signal levels before and after selection by the selection circuit are the same, and the first divided operation and the second divided signal are output. And a control circuit for controlling the frequency dividing operation of the frequency divider.   The frequency divider according to claim 1, wherein the four frequency-divided signals output from the frequency-divided-by-2 circuit are signals having phases different by 90 degrees.   The control circuit receives four divided signals output from the two divider circuit and the two divided signals selected by the selection circuit as input signals, and outputs the divided signal and the selection circuit to the selection circuit. 2. The frequency divider according to claim 1, comprising a logic circuit that synchronizes the control signal. The control circuit includes first to second selection circuits, first to third gate circuits, and first to second flip-flops,
The first gate circuit receives a signal instructing the first frequency division operation or the second frequency division operation and an inverted signal of the output signal of the selection circuit, and outputs a logical product of both signals.
In the first flip-flop, the control signal to the selection circuit is input to a data terminal, the output signal of the selection circuit is input to a clock terminal, and the control signal from the output terminal to the first selection circuit and Outputting a control signal to the second selection circuit;
In the second flip-flop, the control signal to the selection circuit is input to a data terminal, the output signal of the selection circuit is input to a clock terminal, and the control signal from the output terminal to the first selection circuit and Outputting a control signal to the second selection circuit;
The first selection circuit is configured to select one of four divide-by-2 signals output from the divide-by-2 circuit according to a control signal output from the first flip-flop and a control signal output from the second flip-flop. Select the two divide-by-2 signals,
In accordance with the control signal output from the first flip-flop and the control signal output from the second flip-flop, the second selection circuit uses the four frequency-divided signals output from the frequency-divided-by-2 circuit according to the control signal output from the second flip-flop. Selecting one of the two frequency-divided signals different from the frequency-divided signal selected by the first selection circuit;
The second gate circuit receives the frequency-divided signal selected by the first selection circuit and the signal output by the first gate circuit, and outputs a logical product of both signals.
The third gate circuit receives the divide-by-2 signal selected by the second selection circuit and the signal output by the first gate circuit, and outputs a logical product of both signals.
In the third flip-flop, the signal output from the second gate circuit is input to the clock terminal, the data terminal and the inverted output terminal are connected, and the control signal from the output terminal to the selection circuit is output.
The fourth flip-flop receives a signal output from the third gate circuit at a clock terminal, is connected to a data terminal and an inverted output terminal, and outputs a control signal from the output terminal to the selection circuit. The frequency divider according to Item 3.   5. The frequency divider according to claim 1, further comprising a signal delay circuit that delays the four frequency-divided signals output from the frequency-divided-by-2 circuit.

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