JP2012222793A - Variable frequency division device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable frequency division device that is compliant with a fast clock signal.SOLUTION: A variable frequency division circuit 101 inputs a clock signal Clk_a, and outputs a signal Do1 that is a frequency division of the clock signal Clk_a by a factor of P (P is an integer of two or greater) or P+1. A variable frequency division circuit 102 inputs a clock signal Clk_b having the opposite phase to the clock signal Clk_a, and outputs a signal Do2 that is a frequency division of the clock signal Clk_b by a factor of P or P+1. A path switching circuit 103 inputs the signals Do1, Do2 and selectively outputs either of the signals Do1, Do2 according to a path selection signal MuxCont.

Description

  The present invention relates to a variable frequency dividing device for switching between integer frequency division and fractional frequency division used in a frequency synthesizer or the like.

As one of variable frequency dividers, for example, a circuit described in Non-Patent Document 1 is known.
FIG. 7 is a block diagram of such a conventional variable frequency dividing device.
Dividing the clock signal Clk with a duty ratio of 50% and the frequency division number control signal DivCont1 as input and switching the frequency division number to 1 or 1.5 by the frequency division number control signal DivCont1, and outputting the divided signal Da A circuit 201 and a frequency dividing circuit 202 that receives the signal Da and outputs the signal Db after frequency division by the frequency dividing number P. Here, the frequency division number P is a positive integer.

Next, the operation of the conventional variable frequency dividing device configured as described above will be described. Here, as an example, a case where P = 8 and frequency division by 8 and frequency division by 8.5 will be described. FIG. 8 shows an example of time waveforms of the clock signal Clk, the signals Da and Db, and the frequency division number control signal DivCont1.
The frequency dividing number control signal DivCont1 sets the frequency dividing number of the frequency dividing circuit 201 to 1 when it is Low, and sets the frequency dividing of the frequency dividing circuit 201 to 1.5 when it is High. Further, the frequency dividing circuit 202 is an input signal.

Since the frequency division number control signal DivCont1 is Low during the period from the time Ta to the time Tb, the frequency division number of the frequency dividing circuit 201 is 1. Therefore, the output signal Da of the frequency dividing circuit 201 is equal to the clock signal Clk. Since the frequency dividing circuit 202 outputs a signal obtained by dividing the input signal by 8, the output signal Db of the frequency dividing circuit 202 is a signal obtained by dividing the clock signal Clk by 8.
In the period from time Tb to time Tc, the frequency division number control signal DivCont1 becomes High only during the period from time Tb1 to time Tb2, so the frequency division number of the frequency dividing circuit 201 is set to 1.5. Therefore, between time Tb1 and time Tb2, the output signal Da of the frequency dividing circuit 201 is a signal obtained by dividing the clock signal Clk by 1.5. That is, as shown in FIG. 8, the frequency dividing circuit 201 outputs a signal longer than the clock signal Clk by 0.5 clocks.

  The frequency dividing circuit 202 counts the rising edge of the input signal Da eight times, and outputs a frequency divided signal. During the period from time Tb to time Tc, the rising edge of the signal Da is counted eight times. Since the time is 8.5 clocks, the frequency dividing circuit 202 outputs a signal divided by 8.5.

Yu-Che Yang, Shih-An Yu, Yu-Hsuan Liu, Tao Wang, and Shey-Shi Lu, “A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

  However, the frequency division number control signal DivCont1 operates differently from the set value unless the switching from Low to High is performed within 1 clock and switching from High to Low is performed within 1 clock. The control signal DivCont1 needs to be switched within a predetermined time.

  As described above, the switching time of the frequency division number control signal DivCont1 is limited, and in the conventional configuration, it is necessary to change the control signal within one clock. Therefore, when the clock signal is accelerated, the frequency division number control signal DivCont1 Is difficult to generate with high time accuracy, and a variable frequency divider cannot be realized.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a variable frequency dividing device that can cope with a case where a clock signal is increased in speed.

  A variable frequency dividing device according to the present invention receives a first clock signal and outputs a P (P is an integer equal to or greater than 2) or P + 1 frequency divided signal for the first clock signal. And a second variable frequency dividing circuit for inputting a second clock signal having a phase opposite to that of the first clock signal and outputting a P or P + 1 frequency divided signal for the second clock signal, and a first variable An output of the frequency divider and the output of the second variable frequency divider are input, and a path switching circuit that selects and outputs either one based on the path selection signal is provided.

  The variable frequency dividing device according to the present invention is provided with two variable frequency dividing circuits for outputting a P or P + 1 frequency divided signal with respect to an input clock signal, and each has a first clock signal and an opposite phase to the first clock signal. Since the second clock signal is input and the path switching circuit selects and outputs the outputs of these two variable frequency dividers, the variable can sufficiently cope even when the clock signal speed increases. A frequency divider can be obtained.

It is a block diagram which shows the variable frequency dividing apparatus by Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the variable frequency divider by Embodiment 1 of this invention. It is a block diagram which shows the variable frequency dividing apparatus by Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the variable frequency-dividing apparatus by Embodiment 2 of this invention. It is a block diagram which shows the variable frequency divider by Embodiment 3 of this invention. It is a timing chart which shows operation | movement of the variable frequency-dividing apparatus by Embodiment 4 of this invention. It is a block diagram which shows the conventional variable frequency divider. It is a timing chart which shows operation | movement of the conventional variable frequency divider.

Embodiment 1 FIG.
1 is a block diagram showing a variable frequency dividing apparatus according to Embodiment 1 of the present invention.
The illustrated variable frequency dividing device includes a variable frequency dividing circuit 101 (first variable frequency dividing circuit), a variable frequency dividing circuit 102 (second variable frequency dividing circuit), and a path switching circuit 103. The variable frequency dividing circuit 101 can set binary continuous integer frequency dividing numbers P (where P ≧ 2) and P + 1 by using a frequency dividing number control signal DivCont1, and a differential clock signal Clk_a having a duty ratio of 50%. This is a variable frequency dividing circuit that receives the clock signal Clk_a from among the (first clock signal) and Clk_b (second clock signal) and outputs the divided signal Do1. Further, the variable frequency dividing circuit 102 can set binary continuous integer frequency dividing numbers P and P + 1 by a frequency dividing number control signal DivCont2, and a clock signal of the differential clocks Clk_a and Clk_b having a duty ratio of 50%. This is a variable frequency dividing circuit that receives Clk_b and outputs a divided signal Do2. Further, the path switching circuit 103 is a circuit that selects and outputs one of the input signals Do1 and Do2 by the path selection signal MuxCont. Note that the circuit configurations of the variable frequency dividing circuit 101 and the variable frequency dividing circuit 102 are the same, and only the phase of the clock signal that is the input signal is different. The path switching circuit 103 outputs a signal Do1 when the path selection signal MuxCont is Low, and the path switching circuit 103 outputs a signal Do2 when the path selection signal MuxCont is High.

Next, the operation of the variable frequency dividing device of the first embodiment will be described. Here, for explanation, the case of P = 8 will be described.
FIG. 2 shows the clock signals Clk_a, Clk_b, frequency division number control signals DivCont1, DivCont2, path selection signal MuxCont, signals Do1, Do2, and output signal Do when dividing by 8, 8.5, and 8 are performed. It is an example of a time waveform.

In this example, when the frequency dividing number control signal DivCont1 is Low, the variable frequency dividing circuit 101 performs a frequency dividing operation, and when the frequency dividing number control signal DivCont1 is High, the variable frequency dividing circuit 101 performs a frequency dividing operation. Further, when the frequency division number control signal DivCont2 is Low, the variable frequency divider circuit 102 performs a frequency division operation, and when the frequency division number control signal DivCont2 is High, the variable frequency divider circuit 102 performs a frequency division operation.
In addition, the variable frequency dividing circuit 101 and the variable frequency dividing circuit 102 output a High signal for 4 clocks when the frequency dividing operation is performed, output a Low signal for the remaining 4 clocks, and output a High signal for only 4 clocks when the frequency dividing operation is performed. Is output, and the remaining 5 clocks output the Low signal.

From time T0 to time T1 is an operation period for obtaining a frequency-divided signal of 8.
Since the frequency division number control signal DivCont1 is Low, the variable frequency dividing circuit 101 outputs a frequency divided signal of 8 of the clock signal Clk_a. Further, since the frequency dividing number control signal DivCont2 is Low, the variable frequency dividing circuit 102 outputs a frequency divided signal of 8 of the clock signal Clk_b. Since the route selection signal MuxCont is Low, the route switching circuit 103 outputs the signal Do1. Therefore, the output signal Do is a signal obtained by dividing the clock signal Clk_a by 8.

From time T1 to time T4 is a period for obtaining 8.5 frequency division.
Since the frequency dividing number control signal DivCont1 is High, the variable frequency dividing circuit 101 performs the frequency dividing operation by 9. Therefore, the output signal Do1 of the variable frequency dividing circuit 101 outputs a signal obtained by dividing the clock signal Clk_a by 9. On the other hand, since the frequency dividing number control signal DivCont2 does not change from Low, the variable frequency dividing circuit 102 performs a frequency dividing operation. Therefore, the output signal Do2 of the variable frequency dividing circuit 102 outputs a signal obtained by dividing the clock signal Clk_b by 8.

  Focusing on the route selection signal MuxCont, the time T1 to the time T2 is Low, and the time T2 to the time T4 is High. Therefore, the output signal Do of the path switching circuit 103 outputs the signal Do1 from the time T1 to the time T2, and outputs the signal Do2 from the time T2 to the time T4.

  Since the clock signals Clk_a and Clk_b are differential signals, the signal Do1 has a rising edge earlier than the signal Do2 by 0.5 clock. Further, since the signal Do1 is a signal obtained by dividing the clock signal Clk_a by 9 and the signal Do2 is a signal obtained by dividing the clock signal Clk_b by 8 from the time T1 to the time T4, the signal Do2 is 0.5 clock earlier than the signal Do1. The rising edge of the signal appears. Therefore, when the output signal of the path switching circuit 103 is switched from the signal Do1 to the signal Do2 during time T3 (3.5 clocks) before the falling edge of the signal Do1 is output from the path switching circuit 103 from time T1 ′. An 8.5 divided signal can be obtained.

From time T4 to time T5 is a period for obtaining a frequency-divided signal of 8.
The variable frequency dividing circuits 101 and 102 both divide the frequency by 8 because the frequency dividing number control signals DivCont1 and DivCont2 are Low. Therefore, the variable frequency dividing circuit 101 outputs a signal obtained by dividing the clock signal Clk_a by 8, and the variable frequency dividing circuit 102 outputs a signal obtained by dividing the clock signal Clk_b by 8. Since the route selection signal MuxCont is High, the route switching circuit 103 outputs the signal Do2.

In this way, in the period (time T2 to time T4) for obtaining the fractionally divided signal, the route selection signal MuxCont only needs to be switched from Low to High once within 3.5 clocks, and the route selection signal which is a control signal. MuxCont switch time can be extended longer than the previous configuration.
Therefore, even when the clock signal speeds up, the control signal can be generated with high time accuracy, so that the variable frequency dividing device can be reliably realized.
The operations of the variable frequency dividing circuits 101 and 102 and the path switching circuit 103 shown here are merely examples, and the present invention is not limited to this.

  As described above, according to the variable frequency dividing device of the first embodiment, the first clock signal is input, and P (P is an integer equal to or greater than 2) or P + 1 frequency-divided signal with respect to the first clock signal. A first variable frequency dividing circuit to output and a second clock signal having a phase opposite to that of the first clock signal are input, and a second variable frequency signal that outputs a P or P + 1 frequency divided signal with respect to the second clock signal is output. A frequency divider, and a path switching circuit that inputs the output of the first variable frequency divider and the output of the second variable frequency divider, and selects and outputs one of them based on the path selection signal. Therefore, it is possible to obtain a variable frequency dividing device that can sufficiently cope even when the clock signal speed is increased.

Embodiment 2. FIG.
FIG. 3 is a configuration diagram illustrating the variable frequency dividing device according to the second embodiment.
The variable frequency dividing device according to the second embodiment includes variable frequency dividing circuits 111 and 112 and a path switching circuit 103. The variable frequency dividing circuit 111 receives the clock signal Clk_a, the frequency division number control signal DivCont1, and the current control signal DivPS1 (first current control signal) as input signals, and is an integer frequency division set by the frequency division number control signal DivCont1. This is a variable frequency dividing circuit that outputs a frequency-divided signal Do1 that performs a frequency dividing operation of the number P or the frequency dividing number P + 1. The variable frequency dividing circuit 112 receives the clock signal Clk_b, the frequency division number control signal DivCont2, and the current control signal DivPS2 (second current control signal) as input signals, and is an integer frequency division number set by the frequency division number control signal DivCont2. This is a variable frequency dividing circuit that outputs a frequency-divided signal Do2 that performs a frequency dividing operation of P or frequency dividing number P + 1. The path switching circuit 103 is the same as in the first embodiment, and is a selection circuit that selects and outputs one of the signals Do1 and Do2 input by the path selection signal MuxCont.

  As in the first embodiment, the circuit configurations of the variable frequency dividing circuit 111 and the variable frequency dividing circuit 112 are the same, and only the phase of the clock signal that is the input signal is different. The path switching circuit 103 outputs the signal Do1 when the path selection signal MuxCont is Low, and outputs the signal Do2 when the path selection signal MuxCont is High.

  When the current control signal DivPS1 is Low, the variable frequency dividing circuit 111 is brought into a current reduction state, and when it is High, the variable frequency dividing circuit 111 is operated. Further, when the current control signal DivPS2 is Low, the variable frequency dividing circuit 112 is brought into a current reduction state, and when it is High, the variable frequency dividing circuit 112 is operated.

  The current control signal DivPS1 rises N clocks earlier than the falling edge of the path selection signal MuxCont and falls M clocks later than the rising edge of the path selection signal MuxCont. The current control signal DivPS2 rises N clocks earlier than the rising edge of the path selection signal MuxCont and falls M clocks later than the falling edge of the path selection signal MuxCont. That is, according to the current control signals DivPS1 and DivPS2, one of the variable frequency dividing circuits 111 and 112 whose output is not selected by the path switching circuit 103 is set in the current reduction state. The N clock and the M clock are safety margins for returning from the current reduction state when the variable frequency dividing circuits 111 and 112 operate.

Next, the operation of the variable frequency divider of Embodiment 2 will be described using FIG. As an example, here, P = 8, M = 6.5, and N = 1.5. FIG. 4 shows time waveforms of the output signal, clock signal, and control signal of the circuit shown in the second embodiment.
The time waveforms of the clock signals Clk_a, Clk_b, signals Do1, Do2, output signal Do, frequency division number control signals DivCont1, DivCont2, and path selection signal MuxCont shown in FIG. The current control signals DivPS1 and DivPS2 will be described below.
The variable frequency dividing circuits 111 and 112 output a high signal for only 4 clocks during the frequency division operation, output a low signal for the remaining 4 clocks, and output a high signal for only 4 clocks during the frequency division operation. The remaining 5 clocks perform an operation of outputting a Low signal.

  From time T0 to time T1, the path selection signal MuxCont is Low, the path switching circuit 103 outputs the output signal Do1 of the variable frequency dividing circuit 111, and the output signal Do2 of the variable frequency dividing circuit 112 is the output side of the path switching circuit 103. Is not output. At this time, the current control signal DivPS2 is Low, and the variable frequency dividing circuit 112 is brought into a current reduction state.

  The period from time T1 to time T4 is a period for obtaining the 8.5 frequency-divided signal. The current control signals DivPS1 and DivPS2 become High, and the variable frequency dividing circuits 111 and 112 perform a frequency dividing operation according to the frequency dividing number control signals DivCont1 and DivCont2.

  Since the path selection signal MuxCont is High from time T4 to time T5, the path switching circuit 103 outputs the output signal Do2 of the variable frequency dividing circuit 112, and the output signal Do1 of the variable frequency dividing circuit 111 is the output of the path switching circuit 103. Is not output to the side. At this time, the current control signal DivPS1 is Low, and the variable frequency dividing circuit 111 is brought into a current reduction state.

  Thus, by controlling the variable frequency dividing circuits 111 and 112 by the current control signals DivPS1 and DivPS2, the variable frequency dividing circuit that outputs a signal that is not selected by the path switching circuit 103 can be put into a current reduction state. Thus, current reduction of the entire variable frequency divider can be realized.

  In this example, the case of P = 8, M = 6.5, and N = 1.5 has been described, but the present invention is not limited to this. The operations of the variable frequency divider and the path switching circuit used here are only examples, and the present invention is not limited to this.

  As described above, according to the variable frequency divider of the second embodiment, the variable divider whose output is not selected by the path switching circuit among the first variable divider circuit and the second variable divider circuit. Since the peripheral circuit is set in the current reduction state, the current reduction of the entire variable frequency divider can be realized.

  Further, according to the variable frequency dividing device of the second embodiment, the first variable frequency dividing circuit and the second variable frequency dividing circuit have the first current control signal and the second current control signal respectively inputted thereto. The path switching circuit selects the output of the first variable frequency dividing circuit when the path selection signal is at the low level. The output of the second variable frequency dividing circuit is selected at the high level, and the first current control signal rises N clocks earlier than the falling edge of the path selection signal and M from the rising edge of the path selection signal. The second current control signal rises N clocks earlier than the rising edge of the path selection signal and falls M clocks later than the falling edge of the path selection signal. Since, it is possible to realize the current reduction of the entire variable frequency device with high accuracy.

Embodiment 3 FIG.
FIG. 5 is a configuration diagram illustrating the variable frequency dividing device according to the third embodiment.
The variable frequency dividing device according to the third embodiment includes variable frequency dividing circuits 111 and 112, a path switching circuit 103, and a single-phase differential conversion circuit 113. Here, since the configurations of the variable frequency dividing circuits 111 and 112 and the path switching circuit 103 are the same as those in the second embodiment, description thereof will be omitted.

The single-phase differential conversion circuit 113 is a circuit that receives a single-phase clock signal and outputs a clock signal Clk_a that is in phase with the input signal and a clock signal Clk_b that is opposite in phase to the input signal. In the third embodiment, even if the input clock signal is single-phase, a differential clock signal can be obtained by using the single-phase differential conversion circuit 113. Therefore, the same effect as in the second embodiment can be obtained. Obtainable.
In this example, the signal having the same phase as the single-phase clock signal is referred to as the clock signal Clk_a and the signal having the opposite phase is referred to as Clk_b. However, the signal having the opposite phase from the single-phase clock signal is referred to as the clock signal Clk_a, The clock signal Clk_b may be used.

  As described above, according to the variable frequency dividing device of the third embodiment, the single-phase differential conversion circuit that converts the single-phase clock signal into the differential clock signal is provided, and one of the differential clock signals is the first. Since one clock signal is used as the second clock signal and the other is used as the second clock signal, current reduction of the entire variable frequency divider can be realized even if the input clock signal is a single phase.

Embodiment 4 FIG.
In the fourth embodiment, the integer A is set to a value larger than the integer P, the P dividing operation is performed X times, the P + 1 dividing operation is performed Y times, the P + 0.5 dividing operation is performed once, and the A + 0.5 divided signal is obtained. The variable frequency dividing device obtained will be described. The configuration on the drawing is the same as that in FIGS. 1, 3, and 5 in the first to third embodiments, and thus the description on the configuration is omitted.
The operation of the fourth embodiment will be described below using the configuration of FIG. 3 or FIG.

  FIG. 6 shows clock signals Clk_a and Clk_b, frequency division number control signals DivCont 1 and DivCont2, path selection signal MuxCont, signals Do1 and Do2, output signal Do, current control signal DIVPS1 (first current control signal), DIVPS2 (first 2 is an example of a time waveform of current control signal 2). Here, a case where A = 50, P = 8, X = 3, and Y = 2 will be described as an example.

  Since the frequency division number control signal DivCont1 is Low during the period from time T0 to time T1, the variable frequency dividing circuit 111 outputs a frequency divided signal of 8. Since the route selection signal MuxCont is Low, the route switching circuit 103 outputs a divided by 8 signal. Since the current control signal DivPS2 is Low, the variable frequency dividing circuit 112 is in a current reduction state.

  Since the frequency division number control signal DivCont1 is High from time T1 to time T2, the variable frequency dividing circuit 111 outputs a frequency divided signal of 9. Since the route selection signal MuxCont is Low, the route switching circuit 103 outputs a 9-frequency divided signal. Since the current control signal DivPS2 is Low, the variable frequency dividing circuit 112 is in a current reduction state.

  The 8.5 frequency division signal is output from the path switching circuit 103 during the period from time T2 to time T3. The details of the operation are the same as those in the period for obtaining the 8.5 frequency-divided signal in the first embodiment, and the description thereof is omitted here.

  As described above, during the period from the time T0 to the time T3, the path switching circuit 103 outputs the frequency-divided 8 signal three times, the frequency-divided 9 signal twice, and the frequency-divided 8.5 signal once. At this time, connected to the output terminal of the path switching circuit 103, the rising edge of the input signal is counted 6 times, High is output while counting the first 3 times, and Low is output while counting the remaining 3 times. Since the counter circuit (not shown) outputs the 50.5 frequency-divided signal, the 50.5 frequency-divided signal can be obtained in the period from time T0 to time T3.

  The two variable frequency dividing circuits 111 and 112 operate simultaneously during a period from time T2 to T3, and only the variable frequency dividing circuit 111 operates from time T0 to T2, and the variable frequency dividing circuit 112 is in a current reduction state. Therefore, even when a signal with a large frequency division number is obtained, the current reduction of the entire variable frequency divider can be realized.

  As described above, by appropriately setting the frequency dividing operation number of the variable frequency dividing device, the P + 0.5 frequency dividing period is only one in the period for obtaining the A + 0.5 frequency divided signal. The period during which the peripheral circuits 111 and 112 are simultaneously operated is minimized, and the maximum current reduction of the entire variable frequency divider can be realized.

  In the present embodiment, A = 50, P = 8, X = 3, and Y = 2 have been described, but the present invention is not limited to this.

  As described above, according to the variable frequency dividing device of the fourth embodiment, the first variable frequency dividing circuit or the second variable frequency dividing circuit outputs the P frequency divided signal X (X is an arbitrary integer) times. The first variable frequency dividing circuit or the second variable frequency dividing circuit outputs the P + 1 frequency divided signal Y (Y is an arbitrary integer) times, and the path switching circuit is connected to the first variable frequency dividing circuit and the second variable frequency dividing circuit. The P + 0.5 frequency dividing signal is output once by selecting the output of the variable frequency dividing circuit based on the path selection signal, and A (A is A based on the frequency dividing signal of X times, Y times, and 1 time. Since an integer larger than P) +0.5 frequency division signal is obtained, even when a signal with a large frequency division number is obtained, current reduction of the entire variable frequency divider can be realized.

  In the present invention, within the scope of the invention, the embodiments can be freely combined, any component of each embodiment can be modified, or any component can be omitted in each embodiment. .

  101, 111 Variable frequency dividing circuit (first variable frequency dividing circuit), 102, 112 Variable frequency dividing circuit (second variable frequency dividing circuit), 103 Path switching circuit.

Claims (5)

A first variable frequency dividing circuit that inputs a first clock signal and outputs a divided signal of P (P is an integer of 2 or more) or P + 1 with respect to the first clock signal;
A second variable frequency dividing circuit for inputting a second clock signal having a phase opposite to that of the first clock signal and outputting a P or P + 1 frequency dividing signal for the second clock signal;
A variable frequency divider comprising a path switching circuit that inputs the output of the first variable frequency divider circuit and the output of the second variable frequency divider circuit, and selects and outputs either one based on a path selection signal. apparatus. A single-phase differential conversion circuit that converts a single-phase clock signal into a differential clock signal is provided.
2. The variable frequency dividing device according to claim 1, wherein one of the differential clock signals is a first clock signal, and the other is a second clock signal.   2. The variable frequency dividing circuit, the output of which is not selected by the path switching circuit among the first variable frequency dividing circuit and the second variable frequency dividing circuit, is set in a current reduction state. 2. The variable frequency dividing device according to 2. The first variable frequency dividing circuit and the second variable frequency dividing circuit operate when the first current control signal and the second current control signal inputted thereto are at a low level, respectively, and when they are at a high level. And the path switching circuit selects the output of the first variable frequency dividing circuit when the path selection signal is low level, and the second variable frequency dividing circuit when the path selection signal is high level. Select the output of
And,
The first current control signal rises N clocks earlier than the falling edge of the path selection signal, falls M clocks later than the rising edge of the path selection signal,
4. The variable frequency dividing device according to claim 3, wherein the second current control signal rises N clocks earlier than a rising edge of the path selection signal and falls M clocks later than a falling edge of the path selection signal. . The first variable frequency dividing circuit or the second variable frequency dividing circuit outputs the P frequency division signal X (X is an arbitrary integer) times,
The first variable frequency dividing circuit or the second variable frequency dividing circuit outputs a P + 1 frequency divided signal Y (Y is an arbitrary integer) times,
The path switching circuit outputs the P + 0.5 frequency divided signal once by selecting the outputs of the first variable frequency dividing circuit and the second variable frequency dividing circuit based on the path selection signal,
5. The frequency division signal of A (A is an integer larger than P) +0.5 is obtained on the basis of the frequency-divided signal of X times, Y times, and 1 time. The variable frequency dividing device according to claim 1.

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