JP2016207908A - Method of manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon carbide semiconductor device capable of suppressing difference in loads required for cutting in different directions.SOLUTION: A substrate 12 formed of a silicon carbide single crystal of a hexagonal system and provided with a principal surface 12a inclined to a c-plane of the hexagonal system, is prepared. The substrate 12 is cut along a first virtual surface vertical to the principal surface 12a and the c-plane. The substrate 12 is cut along a second virtual surface 7a vertical to the first virtual surface and the c-plane.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device, and more particularly, to a method for manufacturing a silicon carbide semiconductor device having a substrate made of a hexagonal silicon carbide single crystal, and a hexagonal carbonization. The present invention relates to a silicon carbide semiconductor device having a substrate made of a silicon single crystal.

  A silicon carbide semiconductor device has attracted attention as a power device excellent in heat resistance, voltage resistance, and power saving. As a silicon carbide (SiC) substrate used for the manufacture, a substrate having a principal surface inclined with respect to a hexagonal c-plane, in other words, a substrate having an off angle, is widely used. In the manufacture of a semiconductor device, generally, after a plurality of semiconductor elements are formed on a substrate, a plurality of chips are cut out by cutting the substrate. Since SiC has the second highest hardness after diamond and boron nitride, the cutting process of the SiC substrate is more burdensome than the Si substrate or the like. When the substrate is completely cut in the thickness direction by cutting with a tool using a rotating thin-blade grindstone (hereinafter referred to as blade dicing), the tool tends to be consumed, and its frequent replacement is usually required.

  According to Japanese Patent Laying-Open No. 2012-146874 (Patent Document 1), laser machining is proposed instead of blade dicing. This laser processing is intended to accurately cut a plate-like workpiece including a hexagonal SiC substrate having a c-plane and a main surface having an off angle θ along a planned cutting line. Specifically, the processing object is irradiated with the laser beam along the planned cutting line with the focusing point set inside the SiC substrate. Thereby, a modified region serving as a starting point of cutting is formed inside the SiC substrate along the planned cutting line. The workpiece is cut along the scheduled cutting line starting from the modified region. The modified region is a region where the physical characteristics are different from the surroundings.

  According to the description of the embodiment in the above publication, the a-plane is inclined at an angle θ with respect to the thickness direction of the SiC substrate, and the m-plane is not inclined with respect to the thickness direction of the SiC substrate. As the line to be cut, a line extending in a direction parallel to the surface and the a-plane and a line extending in a direction parallel to the surface and the m-plane are set. In forming the planned cutting line, by changing the distance from the surface to the position of the condensing point each time, a plurality of rows of modified regions are formed for one cutting planned line so as to be aligned in the thickness direction of the SiC substrate. It is formed.

JP 2012-146874 A

  According to the technique described in the above publication, between cleaving along a line extending in a direction parallel to the surface and the a-plane and cleaving along a line extending in a direction parallel to the surface and the m-plane, The necessary load is greatly different, and the former line is less likely to break along the former line.

  Moreover, since the edge of the surface of the chip | tip obtained after isolation | separation is formed by cleaving material, linearity is bad and the chip | tip of an edge is also large. Further, the separation end face has large unevenness due to the presence of the modified region formed by the laser beam. For this reason, compared with the technique of blade dicing, the bending strength of the cut-out chip | tip becomes low. The bending strength is an index indicating the resistance of the semiconductor element chip to the bending force. The bending force is caused by, for example, thermal stress generated when the semiconductor element chip is used.

  In addition, since a plurality of rows of modified regions are formed corresponding to one scheduled cutting line, it is necessary to repeat scanning of the laser light along the scheduled cutting line. For this reason, the advantage of laser processing, which has a higher processing speed than blade dicing, is at least somewhat impaired.

  The present invention has been made in view of the problems as described above, and an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device capable of suppressing a difference in loads necessary for cleaving in different directions. Is to provide.

  The method for manufacturing a silicon carbide semiconductor device of the present invention includes the following steps. A substrate made of a hexagonal silicon carbide single crystal and provided with a principal surface inclined with respect to the hexagonal c-plane is prepared. The substrate is cleaved along the first imaginary plane perpendicular to the main surface and the c-plane. The substrate is cleaved along the first virtual plane and the second virtual plane perpendicular to the c-plane.

  The silicon carbide semiconductor device of the present invention has a substrate and a semiconductor element structure. The substrate is made of a hexagonal silicon carbide single crystal, and has a principal surface inclined with respect to the hexagonal c-plane, a first surface perpendicular to the principal surface and the c-plane, and a first surface And a second side surface perpendicular to the c-plane. The semiconductor element structure is provided on the main surface.

  According to the present invention, cutting a chip as a silicon carbide semiconductor device from a substrate having an off-angle with respect to the c-plane, cutting to form a first side surface along the first virtual plane, And cleaving to form the second side surface along the virtual surface. Since the first and second imaginary planes are both perpendicular to the c-plane, the difference in load necessary for each cleaving can be suppressed.

1 is a perspective view schematically showing a configuration of a semiconductor element chip as a silicon carbide semiconductor device in a first embodiment of the present invention. It is a perspective view explaining the crystal structure of the material of the wafer substrate used for the manufacturing method of the semiconductor element chip | tip as a silicon carbide semiconductor device in Embodiment 1 of this invention. 1 is a perspective view schematically showing a configuration of a wafer substrate used in a method for manufacturing a semiconductor element chip as a silicon carbide semiconductor device in Embodiment 1 of the present invention. It is a perspective view which shows roughly the process of forming a semiconductor element structure on a wafer substrate in the manufacturing method of the semiconductor element chip | tip as a silicon carbide semiconductor device in Embodiment 1 of this invention. FIG. 5 is a perspective view schematically showing a cutting line in the wafer cutting step of FIG. 4. FIG. 6 is a partial cross-sectional view of FIG. 5 with a cross section perpendicular to the cutting line 6 m of FIG. 5. 6 is a partial cross-sectional view of FIG. 5 with a cross section perpendicular to the cutting line 6a of FIG. FIG. 7 is a partial cross-sectional view schematically showing a groove forming step on the opposite surface in the wafer cutting step, with the same field of view as FIG. 6. FIG. 8 is a partial cross-sectional view schematically showing a groove forming step on the opposite surface in the wafer cutting step, with the same field of view as FIG. 7. FIG. 7 is a partial cross-sectional view schematically showing a groove forming process on the main surface in a wafer cutting process with the same field of view as FIG. 6. FIG. 8 is a partial cross-sectional view schematically showing a groove forming step on the main surface in a wafer cutting step with the same field of view as FIG. 7. FIG. 7 is a partial cross-sectional view schematically showing a configuration of a wafer in which grooves are formed on the opposite surface and the main surface in the same field of view as FIG. 6. FIG. 8 is a partial cross-sectional view schematically showing a configuration of a wafer in which grooves are formed on the opposite surface and the main surface, with the same field of view as FIG. 7. FIG. 7 is a partial cross-sectional view schematically showing a process of cleaving a wafer having grooves formed on the opposite surface and the main surface, with the same field of view as FIG. 6. FIG. 8 is a partial cross-sectional view schematically showing a process of cleaving a wafer having grooves formed on the opposite surface and the main surface, with the same field of view as FIG. 7. It is a graph which shows the breaking load of the wafer board | substrate in the Example in Embodiment 1 of this invention, and a comparative example. It is a graph which shows the bending strength of the semiconductor element chip | tip as a silicon carbide semiconductor device in the Example and comparative example in Embodiment 1 of this invention. It is a perspective view which shows roughly the process of forming a semiconductor element structure on a wafer substrate in the manufacturing method of the semiconductor element chip | tip as a silicon carbide semiconductor device in Embodiment 2 of this invention. It is a perspective view which shows roughly the structure of the semiconductor element chip | tip as a silicon carbide semiconductor device in Embodiment 2 of this invention. It is a perspective view which shows schematically one process of the manufacturing method of the semiconductor element chip | tip as a silicon carbide semiconductor device in Embodiment 3 of this invention. It is a partial front view which shows roughly the dicing apparatus as a manufacturing apparatus which performs the process of FIG.

  In this specification, the crystallographic terms “c-plane”, “m-plane” and “a-plane” are used for hexagonal silicon carbide single crystals. The c-plane is a {0001} plane in a comprehensive manner using an index. More specifically, the {0001} plane is a (0001) plane that is a silicon plane or a (000-1) plane that is a carbon plane. The m-plane is a {1-100} plane in a comprehensive manner using an index. The a-plane is a {11-20} plane in a comprehensive manner using an index. In the present specification, the minus sign added before the integer value of the exponent corresponds to the bar added on the integer value of the exponent in crystallography.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
(Silicon carbide semiconductor device)
Referring to FIG. 1, a semiconductor element chip 90 a (silicon carbide semiconductor device) of the present embodiment has a chip substrate 11 (substrate), a semiconductor element structure 4, and an ohmic electrode 5.

  Chip substrate 11 is made of a hexagonal silicon carbide single crystal. The chip substrate 11 has a main surface 12a (upper surface in the drawing), a side surface 15m (first side surface), and a side surface 15a (second side surface). The chip substrate 11 has an opposite surface 12b (lower surface in the drawing) opposite to the main surface 12a, a side surface opposite to the side surface 15a, and a side surface opposite to the side surface 15m. The main surface 12a and the opposite surface 12b are parallel to each other. Further, the side surface 15a and the opposite side surface are parallel to each other. The side surface 15m and the opposite side surface are parallel to each other. The chip substrate 11 includes an edge portion 28m between the opposite surface 12b and the side surface 15m, an edge portion 38m between the main surface 12a and the side surface 15m, an edge portion 28a between the opposite surface 12b and the side surface 15a, It has the edge part 38a between the main surface 12a and the side surface 15a. Each of the edge portions 28m, 38m, 28a, and 38a extends linearly.

  The main surface 12a is inclined with respect to the hexagonal c-plane, and is preferably inclined at 2 ° or more and 8 ° or less. In other words, the main surface 12a has an off angle θ of 2 ° or more and 8 ° or less with respect to the c-plane. The off angle θ is, for example, about 4 °.

  The side surface 15m is perpendicular to the main surfaces 12a and c. The side surface 15a is perpendicular to the side surfaces 15m and the c-plane, and is inclined with respect to the main surface 12a corresponding to the off angle θ. Preferably, the side surface 15a is a hexagonal a-plane or m-plane, and in the present embodiment, the side surface 15a is described as being the a-plane. When the side surface 15a is a-plane, the side surface 15m is m-plane.

  The semiconductor element structure 4 is provided on the main surface 12a. The ohmic electrode 5 is provided on the opposite surface 12b. The semiconductor element structure 4 is, for example, a power transistor element structure or a power diode element structure. The transistor element structure is, for example, a MIS (Metal Insulator Semiconductor) structure or a JFET (Junction Field Effect Transistor) structure. The diode element structure is, for example, an SBD (Schottky Barrier Diode) structure or a pn diode structure. When the semiconductor element structure 4 is a MIS structure, the semiconductor element chip 90a is, for example, a MISFET element chip having an ohmic electrode 5 as a drain electrode and a source electrode and a gate electrode included in the semiconductor element structure 4. In this case, if the collector region is provided on the opposite surface 12b of the chip substrate 11, the semiconductor element chip 90a may be an IGBT (Insulated Gate Bipolar Transistor) element chip. When the semiconductor element structure 4 has an SBD structure, the semiconductor element chip 90 a is an SBD element chip having a Schottky electrode included in the semiconductor element structure 4. When the semiconductor element structure 4 has a pn diode structure, the semiconductor element chip 90a is, for example, a pn diode element chip having an ohmic electrode 5 as a cathode electrode and an anode electrode included in the semiconductor element structure 4. The semiconductor element structure 4 has a size of about several mm to 10 mm square, for example. The ohmic electrode 5 is a multilayer metal film made of titanium, nickel, gold, or the like, for example.

(Production method)
Next, a method for manufacturing the semiconductor element chip 90a will be described. Broadly divided, a wafer level process and a cutting process are performed.

  First, the wafer level process will be described below.

  2 and 3, a wafer substrate 12 (substrate) made of a hexagonal silicon carbide single crystal is prepared. The wafer substrate 12 is finally cleaved into the chip substrate 11 (FIG. 1), and is provided with the main surface 12a and the opposite surface 12b described above. The main surface 12a has the above-described off angle θ. In other words, the surface orientation of the principal surface 12a is inclined with respect to the off angle θ with respect to the hexagonal c-axis as the crystal axis CA. The off direction of the off angle θ is the a-axis direction in the present embodiment. Therefore, the m-plane is parallel to the direction perpendicular to the main surface 12a, that is, the thickness direction, and the a-plane is inclined by an off angle θ.

  In the figure, the main surface 12a of the wafer substrate 12 is approximately circular, and has a diameter of, for example, about 75 mm (3 inches), about 100 mm (4 inches), or about 150 mm (6 inches). The thickness of the wafer substrate 12 is, for example, about 350 μm.

  The main surface 12a is provided with an orientation flat 2 (first orientation flat) and an orientation flat 3 (second orientation flat). The orientation flats 2 and 3 can grasp the direction in which the wafer substrate 12 is to be cut. Each of the orientation flats 2 and 3 has a straight portion parallel to the m-plane and the a-plane. The orientation flats 2 and 3 preferably have different lengths from each other, so that the front and back of the wafer substrate 12 can be distinguished.

  Referring to FIG. 4, a plurality of semiconductor element structures 4 are formed in a matrix on main surface 12a. The ohmic electrode 5 is formed on the opposite surface 12b by, for example, a vapor deposition method. Note that, after forming the semiconductor element structure 4 and before forming the ohmic electrode 5, the opposite surface 12b may be ground to reduce the thickness of the wafer substrate 12 to about 300 μm or less, for example. As described above, the wafer 80a having the wafer substrate 12, the semiconductor element structure 4 on the main surface 12a, and the ohmic electrode 5 on the opposite surface 12b is obtained.

  Referring to FIG. 5, wafer substrate 12 is cut along cutting lines 6m and 6a on main surface 12a. The cutting lines 6m and 6a are located in a portion where the element structure is not formed between the semiconductor element structures 4 formed in a matrix. The cutting lines 6m and 6a are along the orientation flats 2 and 3, respectively. Therefore, the cutting lines 6m and 6a are parallel to the m-plane and the a-plane on the main surface 12a.

  Next, an outline of the cutting process will be described. 6 and 7 are partial cross-sectional views perpendicular to the cutting lines 6m and 6a (FIG. 5), respectively.

  Referring to FIG. 6, cutting along cutting line 6m is performed by cleaving wafer substrate 12 along virtual surface 7m (first virtual surface) perpendicular to main surfaces 12a and c. . In the present embodiment, the virtual surface 7m is an m-plane. Since the virtual surface 7m is perpendicular to the main surface 12a, the cutting line 6m on the main surface 12a and the corresponding cutting line 6mp on the opposite surface 12b overlap in plan view.

  Referring to FIG. 7, cutting along cutting line 6a is performed by cleaving wafer substrate 12 along virtual surface 7m (FIG. 6) and virtual surface 7a perpendicular to c-plane. In the present embodiment, the virtual surface 7a is a-plane. Since the virtual surface 7a is not perpendicular to the main surface 12a but is inclined, the corresponding cutting line 6ap on the opposite surface 12b is shifted in plan view with respect to the cutting line 6a on the main surface 12a. In other words, on the opposite surface 12b, the cutting line 6ap is displaced from the virtual surface 7c that includes the cutting line 6a and is perpendicular to the main surface 12a. This deviation amount is calculated by T × tan θ, where T is the thickness of the substrate. The direction of deviation is the direction toward the orientation flat 3 when the crystal axis CA is tilted in the opposite direction to the direction toward the orientation flat 3. On the contrary, when the crystal axis CA is inclined in the direction toward the orientation flat 3, the direction in which the shift is directed is the opposite direction to the direction toward the orientation flat 3.

  Next, a more specific method of the cutting process will be described with reference to FIGS. 8, 10, 12, and 14 correspond to the visual field of FIG. 6, and FIGS. 9, 11, 13, and 15 correspond to the visual field of FIG. 7.

  Referring to FIG. 8, a groove 8m (first groove) located on imaginary surface 7m is formed on opposite surface 12b. In other words, the groove 8m is formed along the cutting line 6mp. In this embodiment, groove 8m is formed by laser light. This laser beam has a focal point on the opposite surface 12 b of the wafer substrate 12. In other words, this laser beam has a focal point at the boundary between the wafer substrate 12 and the ohmic electrode 5.

  Referring to FIG. 9, a groove 8a (second groove) located on virtual surface 7a is formed on opposite surface 12b. In other words, the groove 8a is formed along the cutting line 6ap. In this embodiment, groove 8a is formed by a laser beam. This laser beam has a focal point on the opposite surface 12 b of the wafer substrate 12. In other words, this laser beam has a focal point at the boundary between the wafer substrate 12 and the ohmic electrode 5.

  Referring to FIG. 10, a groove 18m (third groove) located on imaginary surface 7m is formed on main surface 12a. In other words, the groove 18m is formed along the cutting line 6m. The groove 18m is formed by a laser beam having a focal point on the main surface 12a of the wafer substrate 12.

  Referring to FIG. 11, a groove 18a (fourth groove) located on imaginary surface 7a is formed on main surface 12a. In other words, the groove 18a is formed along the cutting line 6a. The groove 18 a is formed by a laser beam having a focal point on the main surface 12 a of the wafer substrate 12.

  With reference to FIGS. 12 and 13, grooves 8m, 8a, 18m and 18a are provided in wafer substrate 12 as described above. As the above-described processing apparatus using laser light, the support base that supports the wafer 80a, the laser head that emits the laser light, the function of controlling the focal depth of the laser light, and the focal position in a plan view are scanned. What has a function can be used. The function of scanning the focal position may be provided with a moving mechanism for enabling the relative position of the support base and the laser head to be displaced.

  Next, the wafer substrate 12 is cleaved by applying a load. Specifically, wafer substrate 12 is cleaved along a plane connecting the ridge lines at the bottom of each of grooves 8m and 18m. In other words, the wafer substrate 12 is cleaved along the virtual surface 7m. Wafer substrate 12 is cleaved along the plane connecting the ridge lines at the bottom of each of grooves 8a and 18a. In other words, the wafer substrate 12 is cleaved along the virtual surface 7a.

  Further, referring to FIG. 14 and FIG. 15, the semiconductor element chip 90 a having the chip substrate 11 described with reference to FIG. 1 is obtained from the wafer 80 a having the wafer substrate 12 by the cleaving. The portions that were the respective grooves 8m, 8a, 18m, and 18a are divided into edge portions 28m, 28a, 38m, and 38a.

(Example)
FIG. 16 is a graph showing the results of measuring the load necessary for cleaving along the cutting lines 6m and 6a (FIG. 5) for each of the example and the comparative example 1. In the figure, error bars represent the maximum and minimum values of the measurement data, and the circular plot represents the average value of the measurement data.

  In Comparative Example 1, a step of locally modifying the wafer substrate 12 using laser light was performed before cleaving. The laser beam was scanned along each of the cutting lines 6m and 6a (FIG. 5) in plan view. Further, a plurality of times of scanning of the laser beam corresponding to each cutting line was performed while changing the focal position of the laser beam in the thickness direction of the wafer substrate 12. As a result, a plurality of rows of modified regions were formed in the wafer substrate 12 so as to be aligned in the thickness direction of the wafer substrate 12 corresponding to each scheduled cutting line. Therefore, all the cleaving in the comparative example 1 was performed along the surface perpendicular | vertical to the main surface 12a. Specifically, cleaving along the m-plane and cleaving along a plane inclined by an off angle θ from the a-plane were performed.

  As a result of the measurement, in the example, the load was almost the same between the cutting lines 6m and 6a. In contrast, in the comparative example, the load necessary for the cleaving along the cutting line 6m is substantially the same as that in the embodiment, but the load necessary for the cleaving along the cutting line 6a is about 1.5 times that. Met. Thus, the reason why only the cleaving along the cutting line 6a in the comparative example requires a large load is that this cleaving is not along the direction perpendicular to the c-plane, more specifically, the m-plane and a This is thought to be due to the fact that it is not along any of the faces.

  FIG. 17 is a graph showing the results of measuring the chip bending strength of Comparative Example 2 in which cutting in the entire thickness direction is performed by blade dicing in addition to the above-described Example and Comparative Example 1. In the figure, error bars represent the maximum and minimum values of the measurement data, and the circular plot represents the average value of the measurement data. As a result of the measurement, according to the example, the same chip bending strength as in Comparative Example 2 by blade dicing was obtained. On the other hand, the chip bending strength of Comparative Example 1 was lower.

  This is because the edges 28m, 28a, 38m and 38a (FIG. 1) in the embodiment are defined by the grooves 8m, 8a, 18m and 18a (FIGS. 12 and 13), respectively. On the other hand, it is considered that the edge portion in Comparative Example 1 is caused by cleaving. The former has linearity defined by the grooves 8m, 8a, 18m and 18a, whereas the latter has linearity disturbance due to variation in the cleaving direction. The portion where the linearity is disturbed can be a starting point of chip cracking.

  Secondly, the side surfaces 15m and 15a (FIG. 1) in the example are not modified by the laser beam, whereas the side surface in the comparative example 1 is considered to be partially modified. . The former has a relatively flat surface formed by cleaving, whereas the latter has unevenness due to the presence of a partially formed modified region. A portion having large unevenness can be a starting point for chip cracking.

(effect)
According to the present embodiment, the cutting of the chip as the semiconductor element chip 90a from the wafer substrate 12 (FIG. 3) having an off angle with respect to the c-plane is performed on the side surface 15m along the virtual surface 7m (FIG. 6). And cleaving to form the side surface 15a along the virtual surface 7a (FIG. 7). Since both the virtual surface 7m and the virtual surface 7a are perpendicular to the c-plane, the difference in load necessary for each cleaving can be suppressed.

  The side surface 15a is a hexagonal a-plane or m-plane, and is an a-plane in the present embodiment. Corresponding to this, the virtual surface 7a is a hexagonal a-plane or m-plane, and is an a-plane in the present embodiment. Thereby, each of the virtual surface 7m and the virtual surface 7a is parallel to one and the other of the a-plane and the m-plane. Therefore, the difference in load necessary for each cleaving can be suppressed.

  By forming the grooves 8m and 8a, the cutting position on the opposite surface 12b can be defined. Further, by forming the grooves 18m and 18a, the cutting position on the main surface 12a can be defined. Thereby, the boundary between the split surface and each of the main surface 12a and the opposite surface 12b, that is, the edge of the chip, can be made highly linear and have few chips.

  The grooves 8m and 8a are formed by a laser beam having a focal point on the opposite surface 12b of the wafer substrate 12, and the grooves 18m and 18a are formed by a laser beam having a focal point on the main surface 12a of the wafer substrate 12. Thereby, the location where the wafer substrate 12 is altered by the irradiation of the laser beam can be kept near the main surface 12a and the opposite surface 12b. Therefore, the flatness of the cut section can be improved. Further, the number of scans of the laser beam necessary for forming each of the cutting lines 6m and 6a (FIG. 5) can be suppressed to two. Thus, the laser beam irradiation process is required as compared with the method that requires multiple laser beam scans while changing the focal position of the laser beam in the thickness direction of the wafer substrate 12 as in Comparative Example 1. Time can be shortened.

  The main surface 12a of the wafer substrate 12 is inclined at 2 ° or more and 8 ° or less with respect to the c-plane. Thereby, the off-angle of the wafer substrate 12 can be set to a value of 2 ° or more and 8 ° or less widely used for semiconductor devices.

  In the present embodiment, the case where the second side surface and the second virtual surface are a-planes has been described. However, the second side surface and the second virtual surface are not limited to the a-plane. For example, It may be an m-plane. In this case, the first side surface and the first virtual surface are a-planes.

<Embodiment 2>
Referring to FIG. 18, in the present embodiment, unlike wafer 80a (FIG. 4), wafer 80b has semiconductor element structure 4 formed on opposite surface 12b of wafer substrate 12, and on main surface 12a. It is obtained by forming the ohmic electrode 5. With reference to the cutting line 6ap on the opposite surface 12b, the corresponding cutting line 6a (not shown in FIG. 18) on the main surface 12a is displaced in plan view. This deviation amount itself is calculated by T × tan θ as in the first embodiment. The direction in which the deviation is directed is the direction opposite to the direction toward the orientation flat 3 when the crystal axis CA is inclined in the direction opposite to the direction toward the orientation flat 3. On the contrary, when the crystal axis CA is inclined in the direction toward the orientation flat 3, the direction in which the shift is directed is the direction toward the orientation flat 3.

  Referring to FIG. 19, semiconductor element chip 90b obtained by the above method differs from semiconductor element chip 90a in that semiconductor element structure 4 provided on main surface 12a and ohmic electrode provided on opposite surface 12b. And 5.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated. Also according to the present embodiment, substantially the same effect as in the first embodiment can be obtained.

<Embodiment 3>
Referring to FIG. 20, in the present embodiment, grooves 8m, 8a, 18m and 18a (FIGS. 12 and 13) are formed by machining instead of laser machining. This machining can be performed by dicing using the dicing apparatus 20.

  Referring to FIG. 21, the dicing apparatus 20 includes, for example, a spindle shaft 16, a thin blade grindstone (blade) 17, a flange 18, and a fixing screw 19. The spindle shaft 16 is configured to be rotatable by air and ball bearings. The blade 17 has diamond particles as a main component. The flange 18 is made of metal. The blade 17 is sandwiched between flanges 18 and held by a fixing screw 19 with respect to the spindle shaft 16. The dicing apparatus 20 performs a cutting process by scanning while rotating the blade 17 while keeping the blade 17 at a constant height. Thereby, grooves 8m, 8a, 18m and 18a (FIGS. 12 and 13) are formed.

  The tip of the blade 17 for cutting is not particularly limited in its angle, but preferably has a V shape. Thereby, the starting point of the cleaving of the wafer substrate 12 can be easily determined by the groove tip.

  Since the configuration other than the above is substantially the same as the configuration of the first or second embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated. According to the present embodiment, substantially the same effect as in the first or second embodiment can be obtained. Although not as fast as laser processing, the processing speed can be increased as compared with the case where the wafer substrate 12 is cut in the entire thickness direction by the blade 17. This is because the processing load is reduced by reducing the contact area between the wafer substrate 12 and the blade 17.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  2 orientation flat (first orientation flat), 3 orientation flat (second orientation flat), 4 semiconductor element structure, 5 ohmic electrode, 6a, 6m, 6ap, 6mp cutting line, 7m virtual plane (first virtual plane) ), 7a virtual surface (second virtual surface), 8m groove (first groove), 8a groove (second groove), 18m groove (third groove), 18a groove (fourth groove), 11 Chip substrate (substrate), 12 wafer substrate (substrate), 12a main surface, 12b opposite surface, 15m side surface (first side surface), 15a side surface (second side surface), 28a, 28m, 38a, 38m edge portion, 80a , 80b Wafer, 90a, 90b Semiconductor element chip (silicon carbide semiconductor device).

Claims (9)

Preparing a substrate made of a hexagonal silicon carbide single crystal and provided with a principal surface inclined with respect to the hexagonal c-plane;
Cleaving the substrate along a first imaginary plane perpendicular to the main surface and the c-plane;
And a step of cleaving the substrate along a second virtual plane perpendicular to the first virtual plane and the c plane.   2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the second virtual plane is one of the hexagonal a-plane and m-plane.   3. The silicon carbide semiconductor device according to claim 2, wherein a first orientation flat and a second orientation flat parallel to each of the m-plane and the a-plane are provided on the main surface of the substrate. Production method. The substrate is provided with an opposite surface opposite to the main surface,
Forming a first groove located on the first virtual surface on the opposite surface;
Forming a second groove located on the second virtual surface on the opposite surface;
Forming a third groove located on the first virtual surface on the main surface;
Forming a fourth groove located on the second virtual surface on the main surface; and
The manufacturing method of the silicon carbide semiconductor device of any one of Claim 1 to 3.   The step of forming the first groove and the second groove is performed by a laser beam having a focal point on the opposite surface of the substrate, and the step of forming the third groove and the fourth groove The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the method is performed by laser light having a focal point on the main surface of the substrate.   6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein said main surface of said substrate is inclined at 2 ° or more and 8 ° or less with respect to said c-plane. A main surface made of a hexagonal silicon carbide single crystal and inclined with respect to the hexagonal c-plane; a first side surface perpendicular to the main surface and the c-plane; A substrate having a side surface and a second side surface perpendicular to the c-plane;
A silicon carbide semiconductor device comprising: a semiconductor element structure provided on the main surface.   The silicon carbide semiconductor device according to claim 7, wherein the second side surface is one of the hexagonal a-plane and m-plane.   9. The silicon carbide semiconductor device according to claim 7, wherein the main surface of the substrate is inclined by 2 ° or more and 8 ° or less with respect to the c-plane.

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