JP2016204201A - Nitride semiconductor epitaxial wafer and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of an obtained nitride semiconductor device by reducing warpage.SOLUTION: A nitride semiconductor epitaxial wafer comprises a substrate for epitaxial growth and nitride semiconductor layers (3-12) formed by epitaxial crystal growth on the substrate (1) for epitaxial growth, and the substrate (1) for epitaxial growth is substantially circular having a radius R. A difference value between an overall X-ray rocking curve half value of GaN(10-12) in a circular area from the center of the substrate (1) for epitaxial growth to a circle having a radius (1/5)R and an overall X-ray rocking curve half value of GaN(10-12) in a torus area from the center of a circle having a radius (4/5)R to a circle having a radius (R-5 mm) is equal to or larger than 100 arcsec and less than 200 arcsec.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a nitride semiconductor epitaxial wafer and a method for manufacturing the same.

The nitride semiconductor is represented by a general formula In _x Al _y Ga _1-xy N (0 ≦ x <1, 0 ≦ y <1, 0 ≦ x + y <1). Since the nitride semiconductor can change the band gap in the range of 1.95 eV to 6 eV depending on the composition, it is researched and developed as a light emitting device material in a wide wavelength range from the ultraviolet region to the infrared region. Has been put to practical use.

  Moreover, the device using the nitride semiconductor is used for a power element or the like that operates at a high frequency and a high output. In particular, field effect transistors (FETs) such as high electron mobility transistors (HEMTs) are known as semiconductor devices suitable for amplification in a high frequency band.

  In an electronic device using the nitride semiconductor, an Si substrate is generally used as a method for suppressing the price of the device.

  However, since the crystal growth of the nitride semiconductor is performed at a high temperature around 1000 ° C., an epitaxial substrate (hereinafter referred to as a nitride semiconductor) on which the nitride semiconductor is epitaxially grown due to the difference in thermal expansion coefficient between Si and the nitride semiconductor. A large warp occurs in an epitaxial wafer).

  As a method for reducing the warpage of the nitride semiconductor epitaxial wafer, it is conceivable to devise a layer structure of the nitride semiconductor layer that is epitaxially grown. For example, as a layer structure of a nitride semiconductor layer for an electronic device, warpage may be reduced by reducing the number of pairs in a superlattice layer formed by repeating pairs of an AlN layer and an AlGaN layer.

  Further, there is a semiconductor bulk crystal disclosed in Japanese Patent Application Laid-Open No. 2012-197218 (Patent Document 1). In this semiconductor bulk crystal, the compound semiconductor single crystal is epitaxially grown by forming a cavity in such a manner that the base substrate and the compound semiconductor single crystal are in direct contact with each other or by forming irregularities on the main surface of the base substrate. The generation of cracks in the middle is suppressed.

  In this way, the epitaxial growth substrate is preliminarily roughened to grow a nitride semiconductor, thereby relaxing the strain of the epitaxial growth substrate and suppressing warpage and cracks at the edges.

JP 2012-197218 A

  However, the conventional method for reducing the warpage of the epitaxial substrate has the following problems.

  That is, in the layer structure of the nitride semiconductor layer for electronic devices in which the number of pairs in the superlattice layer formed by repeating pairs of the AlN layer and the AlGaN layer is reduced, the warp of the nitride semiconductor epitaxial wafer is warped. May be reduced. However, as a compensation, problems such as a reduction in breakdown voltage, which is a device characteristic after completion of the process, occur.

  As described above, when restrictions are imposed on the layer structure of the nitride semiconductor layer in the nitride semiconductor epitaxial wafer, there is a problem that other characteristics may be deteriorated.

  Further, the “semiconductor bulk crystal” disclosed in Patent Document 1 is not preferable from the viewpoint of manufacturing because it takes time and cost for the irregularity processing step of the base substrate.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor epitaxial wafer that can reduce warpage and improve the characteristics of the obtained nitride semiconductor device, and a method for manufacturing the same.

In order to solve the above problems, the nitride semiconductor epitaxial wafer of the present invention is
An epitaxial growth substrate;
A nitride semiconductor layer epitaxially grown on the epitaxial growth substrate;
The epitaxial growth substrate has a substantially circular shape with a radius R,
The full width at half maximum of the X-ray rocking curve of GaN (10-12) in the circular area from the center of the substrate for epitaxial growth to the circle of radius (1/5) R, and from the circle of radius (4/5) R to radius (R- A difference value between the full width at half maximum of X-ray rocking curve of GaN (10-12) in a torus area up to a circle of 5 mm) is 100 arcsec or more and less than 200 arcsec.

In the nitride semiconductor epitaxial wafer of one embodiment,
The substrate for epitaxial growth is any one of Si, SiC, ZnO, and sapphire.

In the nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth substrate has a diameter of 3 inches or more and a thickness of 1500 μm or more.

In addition, the method of manufacturing the nitride semiconductor epitaxial wafer of the present invention is as follows:
An epitaxial growth step of epitaxially growing a nitride semiconductor on the epitaxial growth substrate;
Regarding the nitride semiconductor epitaxial wafer obtained in the epitaxial growth step, the full width at half maximum of the X-ray rocking curve of GaN (10-12) in the circular area from the center of the substrate for epitaxial growth of radius R to the circle of radius (1/5) R And the difference value between the full width at half maximum of X-ray rocking curve of GaN (10-12) in the torus area from the circle with radius (4/5) R to the circle with radius (R-5mm) is 100 arcsec or more and less than 200 arcsec As described above, the epitaxial growth step is performed.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth step includes a step of epitaxially growing an AlN underlayer on the epitaxial growth substrate and a step of epitaxially growing the nitride semiconductor on the AlN underlayer.

  As is apparent from the above, the present invention can control the density of dislocations, nanopipes, and the like and the bending in the crystal by causing a difference in crystallinity between the central portion and the outer peripheral portion.

  Therefore, for the stress due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth, the transmission of the stress from the epitaxial growth substrate between the central portion and the outer peripheral portion is varied, dispersed, suppressed, changed, The nitride semiconductor epitaxial wafer as a whole can be balanced, and the effect of suppressing warpage can be given.

It is a cross-sectional schematic diagram in the nitride semiconductor for HEMTs using the nitride semiconductor epitaxial wafer of this invention. It is explanatory drawing of the area (A) on the substrate for epitaxial growth. It is explanatory drawing of an area (B). It is explanatory drawing of an area (C). It is explanatory drawing of an area (D).

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a schematic sectional view of a nitride semiconductor for HEMT using the nitride semiconductor epitaxial wafer of the present embodiment.

  In FIG. 1, the nitride semiconductor for HEMT is formed by laminating an AlN layer 2, an AlGaN buffer layer 5, a superlattice buffer layer 10, an undoped GaN layer 11 and an AlGaN barrier layer 12 in this order on a Si (111) substrate 1. Configured.

The AlGaN buffer layer 5 is composed of an Al _0.50 Ga _0.50 N layer 3 and a GaN layer 4 laminated on the Al _0.50 Ga _0.50 N layer 3. The superlattice buffer layer 10 is composed of an AlN layer 6, an Al _0.05 Ga _0.95 N layer 7, an Al _0.90 Ga _0.10 N layer 8 and an Al _0.10 Ga _0.90 N layer 9 repeatedly. It is configured by stacking.

  Next, a method for producing a nitride semiconductor epitaxial wafer used for producing a nitride semiconductor for HEMT having the above configuration will be described.

  First, the Si (111) substrate 1 having a thickness of 800 μm is treated with diluted hydrofluoric acid to remove the natural oxide film on the surface. Next, the Si substrate 1 is introduced into a reactor of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.

In the MOCVD apparatus, after raising the substrate temperature from room temperature to 1100 ° C., H ₂ , N ₂ , NH ₃ (ammonia) and TMA (trimethylaluminum) are supplied to the main surface of the Si substrate 1. The AlN layer 2 is grown to a thickness of 150 nm.

Next, the substrate temperature is changed to 1050 ° C., H ₂ , N ₂ , NH ₃ , TMA and TMG (trimethylgallium) are supplied, and Al _0.50 Ga _0.50 with a layer thickness of 300 nm is formed on the AlN layer 2. N layer 3 is grown. Further, a GaN layer 4 having a layer thickness of 20 nm is grown. Thus, the Al GaN buffer layer 5 in which the Al _0.50 Ga _0.50 N layer 3 and the GaN layer 4 are laminated is formed.

After that, while maintaining the substrate temperature at 1050 ° C., H ₂ , N ₂ , NH ₃ and TMA are supplied to grow the AlN layer 6 having a layer thickness of 3.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.05 Ga _0.95 N layer 7 having a layer thickness of 1.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.90 Ga _0.10 N layer 8 having a layer thickness of 1.5 nm. Further, H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied to grow an Al _0.10 Ga _0.90 N layer 9 having a layer thickness of 23.5 nm. Thereafter, the formation of the AlN layer 6 to Al _0.10 Ga _0.90 N layer 9 is repeated 60 times to form the superlattice buffer layer 10.

Thereafter, the substrate temperature is changed to 1040 ° C., H ₂ , N ₂ , NH ₃ and TMG are supplied to grow the undoped GaN layer 11 having a layer thickness of 1200 nm. After that, the growth temperature is changed to 1020 ° C., and H ₂ , N ₂ , NH ₃ , TMA and TMG are supplied, and an Al _0.20 Ga _0.80 N AlGaN barrier with a layer thickness of 30.0 nm. Layer 12 is grown.

  After that, by cooling to room temperature, the AlN layer 2, the AlGaN buffer layer 5, the superlattice buffer layer 10, the undoped GaN layer 11, and the AlGaN barrier layer 12 are stacked on the Si (111) substrate 1 for HEMT. The nitride semiconductor epitaxial wafer is obtained.

  Furthermore, an electrode, an insulating film, and the like are formed on the stacked nitride semiconductor epitaxy structure on the Si (111) substrate 1 in the nitride semiconductor epitaxial wafer by using a photolithography technique. A nitride semiconductor for HEMT is formed by grinding, polishing and dicing. Further, the HEMT device is completed through processes such as die bonding and mounting.

  Hereinafter, in the nitride semiconductor epitaxial wafer formed as described above, the correlation between the crystallinity and warpage of the nitride semiconductor layer formed of the AlGaN buffer layer 5 to the AlGaN barrier layer 12 is examined.

(In-plane control of crystallinity)
The in-wafer adjustment of the crystallinity of the nitride semiconductor layer was performed by adjusting the flow rate of a carrier gas such as H ₂ and N ₂ and the flow rate of a material gas such as NH ₃ in the undoped GaN layer 11.

  The correlation between various crystallinities adjusted as described above and warpage is as follows.

  2 to 5 show the respective areas on the surface of the epitaxial growth substrate with respect to the nitride semiconductor epitaxial wafer.

  2 to 5, the surface of the epitaxial growth substrate 21 having a substantially circular shape has a substrate center O, a substrate radius R, a length 1/5 of the substrate radius R (1/5) R, and a substrate radius R of 4. / 5 length (4/5) R, 3/5 length (3/5) R of substrate radius R, and length r 5mm shorter than substrate radius R (up to 5mm inside of substrate periphery) To do.

  Then, when the nitride semiconductor layer is formed on the epitaxial growth substrate 21, a nitride semiconductor epitaxial wafer in which the in-plane crystallinity is controlled as described above is manufactured. Based on the lengths from the set substrate center O, the “warp” was evaluated for each area provided in the nitride semiconductor epitaxial wafer as follows.

  First, each area will be described.

Area (A) ... Circle area within circle 22 with radius (1/5) R (see Fig. 2)
Area (B): Torus (doughnut) area from circle 22 with radius (1/5) R to circle 23 with radius (3/5) R (see FIG. 3)
Area (C): Torus (doughnut) area from circle 23 with radius (3/5) R to circle 24 with radius (4/5) R (see FIG. 4)
Area (D): Torus (doughnut) area from circle 24 with radius (4/5) R to circle 25 with radius r (see FIG. 5)

  Next, the relationship between the full width at half maximum of X-ray rocking curve (hereinafter referred to as XRC-FWHM) and warpage of GaN (10-12) in the areas (A) to (D) was investigated. As a result, a relationship was found between the difference value and the warpage of “GN (10-12) XRC-FWHM” between area (A) and area (D).

  That is, in the nitride semiconductor epitaxial wafer in which the (maximum value−minimum value) / maximum value of the film thickness distribution is suppressed to 5% or less, from “XRC-FWHM of GaN (10-12)” in area (A) The value obtained by subtracting “XRC-FWHM of GaN (10-12)” in area (D) (hereinafter simply referred to as a difference value) and BOW, which is an index of warpage, were measured. Here, the “BOW” refers to the amount of warpage evaluated at the center of the wafer, and is the amount of displacement of irregularities on the intermediate surface connecting equidistant points from the front surface and the back surface of the wafer.

  In this case, the difference values are classified as follows.

Difference value (1) ... 0 arcsec or more and less than 15 arcsec Difference value (2) ... 15 arcsec or more and less than 50 arcsec Difference value (3) ... 50 arcsec or more and less than 100 arcsec Difference value (4) ... 100 arcsec or more and less than 200 arcsec Difference value (5) ... 200 arcsec or more and less than 300 arcsec Difference value (6) ... 300 arcsec or more

  Further, the average value of the BOW corresponding to the above-described category of each difference value is as follows.

BOW (1)… -121μm
BOW (2)… -121.3μm
BOW (3)… -63.5μm
BOW (4)… -34.1μm
BOW (5)… -45.2μm
BOW (6) ... -58.6 μm.

  Here, the physical model causing a difference in crystallinity between the central portion (area (A)) and the outer peripheral portion ((area (D)) in the nitride semiconductor epitaxial wafer is the crystal of the wafer central portion and the outer peripheral portion. By controlling the density of the dislocations, nanopipes, etc. and the bending in the crystal by making a difference in the properties, it is possible to control the stress against the stress due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth. By varying / dispersing, suppressing, and changing the way the stress is transmitted from the epitaxial growth substrate 21 between the central portion and the outer peripheral portion, the entire nitride semiconductor epitaxial wafer is balanced and effective in suppressing warpage. is there.

  In the above physical model, if the BOW is controlled to -50 μm or more, the stress generated in the nitride semiconductor layer composed of the AlGaN buffer layer 5 to the AlGaN barrier layer 12 can be reduced. Accordingly, the difference value of the nitride semiconductor epitaxial wafer is preferably the difference value (4). That is, the difference value of the nitride semiconductor epitaxial wafer is desirably 100 arcsec or more and less than 200 arcsec.

  However, when the difference value is 200 arcsec or more, the in-plane distribution of device characteristics in a device manufactured using the nitride semiconductor epitaxial wafer becomes too large. Therefore, the difference value is desirably less than 200 arcsec.

  In addition, in the difference value of “GN (10-12) XRC-FWHM” between the above-mentioned area (A) and area (D), nitride having good crystallinity near the center (area (a)) There are many semiconductor epitaxial wafers. However, conversely, even when the crystallinity of the outer peripheral portion (area (D)) is better, the same idea as described above can be applied.

  As a result, the circular area (A) in the circle 22 with radius (1/5) R and the torus (doughnut) area (D) from the circle 24 with radius (4/5) R to the circle 25 with radius r The difference value of “XRC-FWHM of GaN (10-12)” is preferably 100 arcsec or more and less than 200 arcsec.

  As described above, it is possible to control the warpage of the nitride semiconductor epitaxial wafer by adjusting the crystallinity balance in the wafer plane in the crystallinity of the nitride semiconductor layer. Therefore, it is possible to obtain a device having desirable characteristics while increasing the degree of freedom of the layer structure of the nitride semiconductor layer, which has conventionally limited the layer thickness and layer structure.

Second Embodiment The second embodiment relates to the type of substrate in the nitride semiconductor epitaxial wafer in the first embodiment.

  When Si, SiC, ZnO, or sapphire is used as the epitaxial growth substrate, the difference in thermal expansion coefficient between the epitaxial growth substrate and the nitride semiconductor is usually large. A large strain stress is generated when the temperature is lowered after the growth is completed.

  Therefore, in the present embodiment, as in the case of the first embodiment, the circle area (A) in the circle 22 having the radius (1/5) R and the circle having the radius (4/5) R are used. The central portion of the wafer is obtained by setting a difference value of “XRC-FWHM of GaN (10-12)” in the torus (doughnut) area (D) from 24 to circle 25 of radius r to 100 arcsec or more and less than 200 arcsec. And a difference in crystallinity between the outer peripheral portion and the outer peripheral portion.

  Thus, by controlling the density in the dislocations and nanopipes and the bending in the crystal, the stress due to the difference in thermal expansion coefficient resulting from the temperature change during epitaxial crystal growth can be controlled from the epitaxial growth substrate with respect to the central portion and the outer peripheral portion. The effect of changing how the stress is transmitted can be achieved. As a result, it is possible to greatly influence the warpage control in the nitride semiconductor epitaxial wafer.

Third Embodiment The third embodiment relates to the configuration of the substrate in the nitride semiconductor epitaxial wafer in the first embodiment.

  In the present embodiment, the size of the epitaxial growth substrate is made as large as possible, and the substrate thickness is made as thick as possible. Thus, as the substrate size is increased or the substrate thickness is increased, the rate of volume change due to relaxation of the rate of temperature rise and fall of the crystal growth temperature can be further reduced, and the generation of defects can be more effectively suppressed. An effect can be obtained.

  Therefore, for example, by setting the diameter of the epitaxial growth substrate to 3 inches or more and the thickness to 1500 μm or more, the manner of transmission of stress due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth is changed, dispersed, suppressed, and changed. Thus, warpage in the nitride semiconductor epitaxial wafer can be suppressed.

Fourth Embodiment The fourth embodiment relates to the effect of the AlN buffer layer in the method for manufacturing a nitride semiconductor epitaxial wafer in the first embodiment.

  In the manufacture of a nitride semiconductor epitaxial wafer, when the substrate for epitaxial growth is Si, the AlN layer 2 is used as a base buffer layer in order to suppress the reaction between Si and GaN which is a nitride semiconductor. Then, defects of an appropriate size (for example, about several nanometers to several tens of nanometers) such as nanopipes are generated in the AlN layer 2 in contact with the interface with the Si substrate 1.

  Therefore, the reaction between the Si substrate 1 and GaN, which is a nitride semiconductor, can be more effectively suppressed by defects of an appropriate size such as the nanopipe, and the device characteristics can be improved.

  In each of the above embodiments, a nitride semiconductor epitaxial wafer for producing a nitride semiconductor for HEMT has been described as an example. However, the present invention is not limited to a nitride semiconductor epitaxial wafer for producing a nitride semiconductor for HEMT, and can also be applied to a nitride semiconductor epitaxial wafer for a light emitting element.

In summary, the nitride semiconductor epitaxial wafer of the present invention is
Epitaxial growth substrates 1, 21;
Nitride semiconductor layers 3 to 12 grown epitaxially on the epitaxial growth substrates 1 and 21, and
The epitaxial growth substrates 1 and 21 are substantially circles having a radius R,
The full width at half maximum of the X-ray rocking curve of GaN (10-12) in the circular area (A) from the center of the epitaxial growth substrate 1, 21 to the circle 22 of radius (1/5) R, and radius (4/5) R The difference value between the full width at half maximum of X-ray rocking curve of GaN (10-12) in the torus area (D) from the circle 24 to the circle 25 with radius (R-5 mm) is 100 arcsec or more and less than 200 arcsec. It is said.

  According to the above configuration, by causing a difference in crystallinity between the central portion and the outer peripheral portion of the nitride semiconductor epitaxial wafer, it is possible to control the density in the dislocations, the nanopipes, etc., and the bending in the crystal. Therefore, the way in which the stress is transmitted from the epitaxial growth substrates 1 and 21 between the central portion and the outer peripheral portion is changed, dispersed, suppressed, and changed with respect to the stress due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth. Thus, the entire nitride semiconductor epitaxial wafer can be balanced, and the effect of suppressing warpage can be provided.

In the nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth substrates 1 and 21 are any one of Si, SiC, ZnO, and sapphire.

  When Si, SiC, ZnO or sapphire having a large difference in thermal expansion coefficient from the nitride semiconductor layers 3 to 12 is used as the epitaxial growth substrates 1 and 21, the crystal growth temperature rise rate and the temperature fall rate, particularly the crystal A large strain stress is generated due to a difference in thermal expansion coefficient between the epitaxial growth substrates 1 and 21 and the nitride semiconductor layers 3 to 12 when the temperature is lowered after the growth is completed.

  According to this embodiment, the crystallinity of the nitride semiconductor epitaxial wafer is controlled by controlling the density of dislocations and nanopipes and the bending in the crystal by causing a difference in crystallinity between the central portion and the outer peripheral portion. It is possible to vary, suppress, and change the way the stress is transmitted from the epitaxial growth substrates 1 and 21 between the central portion and the outer peripheral portion with respect to the stress due to the difference in thermal expansion coefficient resulting from the temperature change during growth. it can.

  Therefore, even when Si, SiC, ZnO or sapphire having a large difference in thermal expansion coefficient from the nitride semiconductor layers 3 to 12 is used as the epitaxial growth substrates 1 and 21, it is effective in suppressing warpage. Can do.

In the nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth substrates 1, 21 have a diameter of 3 inches or more and a thickness of 1500 μm or more.

  According to this embodiment, the epitaxial growth substrates 1 and 21 have a diameter of 3 inches or more and a thickness of 1500 μm or more. Therefore, by increasing the substrate size and increasing the substrate thickness, it is possible to vary, suppress, and change the way stress is transmitted due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth.

In addition, the method of manufacturing the nitride semiconductor epitaxial wafer of the present invention is as follows:
An epitaxial growth step of epitaxially growing a nitride semiconductor on the epitaxial growth substrates 1, 21;
With respect to the nitride semiconductor epitaxial wafer obtained in the epitaxial growth step, GaN (10-12) in a circular area (A) from the center of the epitaxial growth substrate 1, 21 having a radius R to a circle 22 having a radius (1/5) R. Full width at half maximum of X-ray rocking curve and full width at half maximum of X-ray rocking curve at GaN (10-12) in torus area (D) from circle 24 with radius (4/5) R to circle 25 with radius (R-5mm) The epitaxial growth step is performed so that the difference value between the first and second electrodes is 100 arcsec or more and less than 200 arcsec.

  According to the above configuration, by causing a difference in crystallinity between the central portion and the outer peripheral portion of the nitride semiconductor epitaxial wafer, it is possible to control the density in the dislocations, the nanopipes, etc., and the bending in the crystal. Therefore, the way in which the stress is transmitted from the epitaxial growth substrates 1 and 21 between the central portion and the outer peripheral portion is changed, dispersed, suppressed, and changed with respect to the stress due to the difference in thermal expansion coefficient resulting from the temperature change during crystal growth. Thus, the entire nitride semiconductor epitaxial wafer can be balanced, and the effect of suppressing warpage can be provided.

Further, in the method of manufacturing a nitride semiconductor epitaxial wafer of one embodiment,
The epitaxial growth step includes a step of epitaxially growing an AlN underlayer on the epitaxial growth substrates 1 and 21, and a step of epitaxially growing the nitride semiconductor on the AlN underlayer.

  According to this embodiment, when the epitaxial growth substrates 1 and 21 are Si, AlN is used as a base buffer layer in order to suppress the reaction between Si and GaN. In that case, a defect of an appropriate size such as a nanopipe occurs in the AlN layer 2 in contact with the Si interface. Therefore, the reaction between the Si substrate and GaN, which is the nitride semiconductor, can be more effectively suppressed by a defect of an appropriate size such as the nanopipe, and the device characteristics can be improved.

1 Si (111) substrate 2 AlN layer 3 Al _0.50 Ga _0.50 N layer 4 GaN layer 5 AlGaN buffer layer 6 AlN layer 7 Al _0.05 Ga _0.95 N layer 8 Al _0.90 Ga _0.10 N layer 9 Al _0.10 Ga _0.90 N layer 10 Superlattice buffer layer 11 Undoped GaN layer 12 AlGaN barrier layer 21 Epitaxial growth substrate 22 Radius (1/5) R circle 23 Radius (3/5) R circle 24 Circle of radius (4/5) R 25 Circle of radius r
(A), (B), (C), (D) area

Claims (5)

An epitaxial growth substrate;
A nitride semiconductor layer epitaxially grown on the epitaxial growth substrate;
The epitaxial growth substrate has a substantially circular shape with a radius R,
The full width at half maximum of the X-ray rocking curve of GaN (10-12) in the circular area from the center of the substrate for epitaxial growth to the circle of radius (1/5) R, and from the circle of radius (4/5) R to radius (R- A nitride semiconductor epitaxial wafer characterized in that a difference value between the full width at half maximum of X-ray rocking curve of GaN (10-12) in a torus area up to a circle of 5 mm) is 100 arcsec or more and less than 200 arcsec. The nitride semiconductor epitaxial wafer according to claim 1,
The nitride semiconductor epitaxial wafer, wherein the substrate for epitaxial growth is any one of Si, SiC, ZnO and sapphire. In the nitride semiconductor epitaxial wafer according to claim 1 or 2,
A nitride semiconductor epitaxial wafer, wherein the epitaxial growth substrate has a diameter of 3 inches or more and a thickness of 1500 μm or more. An epitaxial growth step of epitaxially growing a nitride semiconductor on the epitaxial growth substrate;
Regarding the nitride semiconductor epitaxial wafer obtained in the epitaxial growth step, the full width at half maximum of the X-ray rocking curve of GaN (10-12) in the circular area from the center of the substrate for epitaxial growth of radius R to the circle of radius (1/5) R The difference value between the full width at half maximum of X-ray rocking curve of GaN (10-12) in the torus area from the circle of radius (4/5) R to the circle of radius (R-5mm) is 100 arcsec or more and less than 200 arcsec Thus, a method of manufacturing a nitride semiconductor epitaxial wafer, wherein the epitaxial growth step is performed. In the manufacturing method of the nitride semiconductor epitaxial wafer according to claim 4,
The epitaxial growth step includes a step of epitaxially growing an AlN underlayer on the epitaxial growth substrate and a step of epitaxially growing the nitride semiconductor on the AlN underlayer. Manufacturing method of semiconductor epitaxial wafer.

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