JP2016197619A - Semiconductor element formation substrate, manufacturing method of semiconductor element formation substrate and manufacturing method of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element formation substrate, a manufacturing method of a semiconductor element formation substrate, and a manufacturing method of a semiconductor element, which can inhibit metal diffusion to the inside of a semiconductor layer.SOLUTION: A semiconductor element formation substrate 1 comprises: a support substrate 2; a semiconductor laminate 4 provided on a principal surface 2a of the support substrate 2 and has first semiconductor layers 21, 22 functioning as collectors, a second semiconductor layer 23 functioning as a base and third semiconductor layers 24, 25 functioning as emitters which are sequentially laminated from the support substrate 2 side; and an alignment mark 5 composed of a resin filled in a first opening 4a which pierces the first semiconductor layers, the second semiconductor layer and the third semiconductor layers. The semiconductor element formation substrate 1 further comprises second openings different from the first opening 4a in part of the first semiconductor layers, and a resin is filled in the second openings.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor element forming substrate, a method for manufacturing a semiconductor element forming substrate, and a method for manufacturing a semiconductor element.

  In recent years, there has been a demand for semiconductor elements capable of high-speed operation as communication equipment and the like increase in speed. As one of such semiconductor elements, for example, a heterojunction bipolar transistor (HBT) is known. For example, in the following Patent Document 1, an n-type GaAs collector layer, a p-type GaAs base layer, an emitter layer composed of an n-type InGaP layer and an n-type AlGaAs layer are sequentially arranged on a semi-insulating GaAs substrate. HBT provided in is disclosed.

JP-A-5-36713

  A semiconductor element such as the above-described HBT is formed by patterning a semiconductor layer stacked on a substrate a plurality of times. In order to suppress misalignment of these patterning, metal or alloy alignment marks may be used. In this case, metal atoms constituting the alignment mark may be diffused into the semiconductor layer during the manufacture of the semiconductor element, which may affect the electrical characteristics of the semiconductor element.

  An object of the present invention is to provide a substrate for forming a semiconductor element, a method for manufacturing the substrate for forming a semiconductor element, and a method for manufacturing the semiconductor element that can suppress metal diffusion into the semiconductor layer.

  A substrate for forming a semiconductor element according to one aspect of the present invention is a first substrate that functions as a collector, which is provided on a main surface of a support substrate and a support substrate, and is stacked in order from the support substrate side. A semiconductor stack having a layer, a second semiconductor layer functioning as a base, and a third semiconductor layer functioning as an emitter, and in a first opening penetrating the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer An alignment mark made of filled resin, and a second opening different from the first opening is provided in a part of the first semiconductor layer, and the second opening is filled with resin. Become.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor element forming substrate, comprising: a first semiconductor layer that functions as a collector; a second semiconductor layer that functions as a base; and a third semiconductor that functions as an emitter. A first step of forming a semiconductor stacked body in which layers are sequentially stacked; a second step of bonding a first support substrate on a first main surface of the semiconductor stacked body opposite to the semiconductor substrate; and a semiconductor substrate Forming a first etching mask on the second main surface opposite to the first main surface of the semiconductor stacked body, and then etching the first semiconductor layer, the second semiconductor layer, And a fourth step of forming an opening penetrating the third semiconductor layer, a fifth step of removing the first etching mask, and forming the second etching mask on the second main surface, and then opening the opening by etching. Expand In addition, a sixth step of forming a void by removing a part of the first semiconductor layer, and a seventh step of forming an alignment mark in the opening by filling the opening with a resin and filling the void in the resin And comprising.

  A method for manufacturing a semiconductor device according to another aspect of the present invention includes a method for manufacturing a substrate for forming a semiconductor device described in the above paragraph, and a second support on a second main surface after removing the second etching mask. An eighth step of bonding the substrate; a ninth step of forming a collector layer, a base layer, and an emitter layer by etching the semiconductor laminate; a collector electrode on the collector layer; and a base electrode on the base layer A tenth step of forming an emitter electrode on the emitter layer, an alignment mark, a collector layer, a base layer, an emitter layer, a resin filled in the air gap, a collector element, a base electrode, and a semiconductor element having the emitter electrode And an eleventh step of cutting the second support substrate so as to divide the substrate, wherein the relative dielectric constant of the resin contained in the semiconductor element is smaller than the relative dielectric constant of the collector layer. .

  ADVANTAGE OF THE INVENTION According to this invention, the metal element formation substrate which can suppress metal diffusion in a semiconductor layer and can reduce a parasitic capacitance, the manufacturing method of a semiconductor element formation substrate, and the manufacturing method of a semiconductor element can be provided.

FIG. 1 is a sectional view showing a semiconductor element forming substrate according to the present embodiment. 2A to 2C are views for explaining a method for manufacturing a semiconductor element formation substrate according to this embodiment. FIGS. 3A to 3C are views for explaining a method for manufacturing a semiconductor element formation substrate according to this embodiment. 4A to 4C are views for explaining a method of manufacturing a semiconductor element formation substrate according to this embodiment. 5A to 5C are views for explaining a method for manufacturing a semiconductor element formation substrate according to the present embodiment. FIGS. 6A to 6C are views for explaining a method for manufacturing a semiconductor element using the semiconductor element forming substrate according to the present embodiment. 7A and 7B are views for explaining a method of manufacturing a semiconductor element using the semiconductor element forming substrate according to the present embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described. One embodiment of the present invention is a support substrate, and a semiconductor stacked body provided on the main surface of the support substrate, which is sequentially stacked from the support substrate side, and functions as a base and a first semiconductor layer that functions as a collector. A semiconductor stacked body having a second semiconductor layer and a third semiconductor layer functioning as an emitter, and a first semiconductor layer, a second semiconductor layer, and a resin filled in a first opening penetrating the third semiconductor layer A semiconductor element forming substrate in which a second opening different from the first opening is provided in a part of the first semiconductor layer, and the second opening is filled with a resin. It is.

  According to this semiconductor element forming substrate, the alignment mark is made of resin. Thereby, compared with the case where the alignment mark made of a metal or an alloy is used, the metal directly in contact with the semiconductor stacked body is reduced, so that metal diffusion into the first to third semiconductor layers can be suppressed. In addition, by filling the second opening provided in a part of the first semiconductor layer with resin, the parasitic capacitance of the semiconductor element formation substrate can be reduced.

  The alignment mark may have a first recess that is recessed from the support substrate side toward the third semiconductor layer, and the first recess may form a first gap. When the resin constituting the alignment mark is thermally expanded at the time of manufacturing the semiconductor element forming substrate, the resin can expand into the first gap formed by the first recess. Thereby, damage to the semiconductor element forming substrate can be suppressed.

  The resin in the second opening may have a relative dielectric constant smaller than that of the first semiconductor layer.

  According to another embodiment of the present invention, a semiconductor stacked structure in which a first semiconductor layer functioning as a collector, a second semiconductor layer functioning as a base, and a third semiconductor layer functioning as an emitter are sequentially stacked on a semiconductor substrate. A first step of forming a body, a second step of bonding the first support substrate on the first main surface opposite to the semiconductor substrate side in the semiconductor laminate, and a third step of removing the semiconductor substrate from the semiconductor laminate. And an opening penetrating the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by etching after forming a first etching mask on the second main surface opposite to the first main surface of the semiconductor stacked body A fourth step of forming a portion, a fifth step of removing the first etching mask, and forming a second etching mask on the second main surface, then expanding the opening by etching, and forming the first semiconductor layer Partly A semiconductor element forming substrate comprising: a sixth step of forming a void to leave and a seventh step of forming an alignment mark in the opening by filling the opening with a resin and filling the void in the resin It is a manufacturing method.

  According to this manufacturing method, the alignment mark provided in the opening can be formed of resin. Thereby, compared with the case where the alignment mark made of a metal or an alloy is used, the metal directly in contact with the semiconductor stacked body is reduced, so that metal diffusion into the first to third semiconductor layers can be suppressed. In addition, by filling the void into which the first semiconductor layer is partially removed, the parasitic capacitance of the semiconductor element forming substrate can be reduced.

  Another embodiment of the present invention includes a method for manufacturing a substrate for forming a semiconductor element described in the above paragraph, and an eighth step of bonding a second support substrate to a second main surface after removing the second etching mask, The ninth step of forming the collector layer, the base layer, and the emitter layer by etching the semiconductor laminate, the collector electrode on the collector layer, the base electrode on the base layer, and the emitter electrode on the emitter layer The tenth step of forming each, the alignment mark, the collector layer, the base layer, the emitter layer, the resin filled in the air gap, the semiconductor element having the collector electrode, the base electrode, and the emitter electrode are separated from each other. An eleventh step of cutting the support substrate, wherein the relative dielectric constant of the resin contained in the semiconductor element is smaller than the relative dielectric constant of the collector layer. A.

  According to this manufacturing method, the alignment mark can be formed of resin. Thereby, compared with the case where the alignment mark made of a metal or an alloy is used, the metal directly in contact with the semiconductor stacked body is reduced, so that metal diffusion into the first to third semiconductor layers can be suppressed. In addition, since the semiconductor element manufactured by the above manufacturing method has a resin having a relative dielectric constant smaller than that of the collector layer, the parasitic capacitance of the semiconductor element can be reduced.

[Details of the embodiment of the present invention]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description is omitted.

(Embodiment)
FIG. 1 is a sectional view showing a semiconductor element forming substrate according to the present embodiment. As shown in FIG. 1, a semiconductor element forming substrate 1 of this embodiment includes a support substrate (second support substrate) 2, a metal layer 3 provided on the main surface 2 a of the support substrate 2, and a metal layer. 3, a semiconductor laminate 4 provided on 3, an alignment mark 5 provided in an opening (first opening) 4 a penetrating the semiconductor laminate 4, and a region where a part of the semiconductor laminate 4 is removed is filled A region 6 to be processed.

  The support substrate 2 is a substrate having high thermal conductivity, such as an AlN substrate (aluminum nitride substrate), a Si substrate (silicon substrate), a SiC substrate (silicon carbide substrate), or a diamond substrate. The thickness of the support substrate 2 is, for example, 20 μm to 200 μm. The thermal conductivity of the support substrate 2 is preferably higher than that of, for example, an InP substrate (indium phosphorous substrate). The thermal conductivity of the support substrate 2 is, for example, 100 W / (m · K) or more and 2000 W / (m · K) or less. Moreover, the thermal expansion coefficient of the support substrate 2 is about 1-5 ppm / degrees C, for example.

  The metal layer 3 is provided between the support substrate 2 and the semiconductor stacked body 4 and is a layer for bonding the support substrate 2 and the semiconductor stacked body 4 to each other. The metal layer 3 is made of, for example, a metal or alloy containing at least one of tungsten, molybdenum, and tantalum. The thickness of the metal layer 3 is 10 nm to 60 nm. When the thickness of the metal layer 3 is 10 nm or more, it can suppress that the semiconductor laminated body 4 peels from the support substrate 2. FIG. When the thickness of the metal layer 3 is 60 nm or less, the heat of the semiconductor stacked body 4 is sufficiently transferred to the support substrate 2. The thickness of the metal layer 3 is preferably 50 nm or less, more preferably 45 nm or less, and further preferably 40 nm or less.

  The metal layer 3 includes a first metal layer 11 and a second metal layer 12 that are stacked on each other. The first metal layer 11 and the second metal layer 12 may be made of the same material or different materials. A gap (third gap) 13 is provided between the first metal layer 11 and the second metal layer 12 overlapping the alignment mark 5 in the stacking direction of the semiconductor stacked body 4 (hereinafter simply referred to as the stacking direction). ing. Similarly, a gap 14 is provided between the first metal layer 11 and the second metal layer 12 that overlap the region 6 in the stacking direction. These voids 13 and 14 may be filled with air, or the voids 13 and 14 may be in a vacuum state.

  The semiconductor stacked body 4 is made of, for example, a III-V group compound semiconductor. The semiconductor stacked body 4 includes semiconductor layers 21 to 25 that are sequentially stacked from the support substrate 2 side. For example, when the HBT is formed by the semiconductor element forming substrate 1, the semiconductor layers (first semiconductor layers) 21 and 22 function as collectors, the semiconductor layer (second semiconductor layer) 23 functions as a base, and the semiconductor layers (Third semiconductor layer) 24 and 25 function as emitters.

The semiconductor layer 21 is a layer in contact with the metal layer 3 and is, for example, an n-type InP layer. The thickness of the semiconductor layer 21 is, for example, 300 nm. The concentration of Si (silicon) in the semiconductor layer 21 is, for example, about 2 × 10 ¹⁹ atoms / cm ³ . The relative dielectric constant of InP forming the semiconductor layer 21 is 12.4, and the thermal expansion coefficient of InP is 4.5 ppm / ° C.

The semiconductor layer 22 is in contact with a part of the semiconductor layer 21 and is, for example, a stacked body of an n-type InP layer and an n-type InAlGaAs layer. The n-type InP layer is located on the semiconductor layer 21 side, and the n-type InAlGaAs layer is located on the semiconductor layer 23 side. The thickness of the InP layer is 200 nm, for example, and the thickness of the InAlGaAs layer is 50 nm, for example. The concentration of Si in the InP layer in the semiconductor layer 22 is, for example, about 3 × 10 ¹⁶ atoms / cm ³ . The concentration of Si in the InAlGaAs layer in the semiconductor layer 22 is, for example, about 1 × 10 ¹⁷ atoms / cm ³ .

The semiconductor layer 23 is in contact with the semiconductor layer 22 and is, for example, a p-type InGaAs layer. The thickness of the semiconductor layer 23 is, for example, 400 nm. The concentration of C (carbon) in the semiconductor layer 23 is, for example, about 5 × 10 ¹⁹ atoms / cm ³ .

The semiconductor layer 24 is in contact with a partial region of the semiconductor layer 23 and is, for example, an n-type InP layer. The thickness of the semiconductor layer 24 is, for example, 150 nm. The concentration of Si in the semiconductor layer 24 is, for example, about 2 × 10 ¹⁸ atoms / cm ³ .

The semiconductor layer 25 is in contact with the semiconductor layer 24 and is, for example, an n-type InGaAs layer. The thickness of the semiconductor layer 25 is, for example, 250 nm. The concentration of Si in the semiconductor layer 25 is, for example, about 2 × 10 ¹⁹ atoms / cm ³ .

  One or more alignment marks 5 are provided, for example, at the end of the support substrate 2, and are made of a resin filled in the opening 4 a that penetrates the semiconductor layers 21 to 25 of the semiconductor stacked body 4. This resin has an insulating property. Further, the relative dielectric constant of this resin is at least smaller than the relative dielectric constant of the semiconductor layer 21 (that is, the relative dielectric constant of InP), for example, 2 to 6. The relative dielectric constant of the resin is preferably smaller than the relative dielectric constant of the semiconductor layers 21 to 25. In the present embodiment, for example, benzocyclobutene (BCB) having a relative dielectric constant of 2.6 is used as the resin. The relative dielectric constant of the benzocyclobutene is smaller than that of the semiconductor layers 21 to 25, and the coefficient of thermal expansion is 52 ppm / ° C.

  The alignment mark 5 has a recess (first recess) 5a that is recessed from the support substrate 2 side toward the semiconductor layer 25 side in the stacking direction. The recess 5a forms a gap (first gap), and the gap 13 is formed by forming the gap. Further, the exposed portion 5 b on the opposite side of the alignment mark 5 from the support substrate 2 is in contact with the surface of the semiconductor layer 25. The intermediate portion 5c of the alignment mark 5 is sandwiched between the semiconductor layer 23 and the semiconductor layer 25 in the stacking direction.

  The region 6 is made of a resin filled in an opening (second opening) 26 formed by removing a part of the semiconductor layers 21 and 22 in the semiconductor stacked body 4. The resin constituting the region 6 is the same as the resin constituting the alignment mark 5. The region 6 that is the resin has a recess 6 a that is recessed from the support substrate 2 side toward the semiconductor layer 25 side. The recess 6a forms a void, and the void 14 is formed by forming the void.

  Next, a method for manufacturing a semiconductor element formation substrate according to the present embodiment will be described with reference to FIGS. (A) to (c) in FIG. 2, (a) to (c) in FIG. 3, (a) to (c) in FIG. 4, and (a) to (c) in FIG. It is a figure explaining the manufacturing method of the board | substrate for semiconductor element formation which concerns.

  First, as shown in FIG. 2A, as a first step, a protective layer 32, a semiconductor laminate 4, a protective layer 33, an adhesive layer 34, and a support substrate (first support substrate) 35 are sequentially stacked. A semiconductor substrate 31 is prepared. In the first step, first, the protective layer 32, the semiconductor stacked body 4, and the protective layer 33 are formed on the semiconductor substrate 31. Then, the metal layer provided on the protective layer 33 and the metal layer provided on the support substrate 35 are adhered to each other to form the adhesive layer 34. As a result, the support substrate 35 is bonded to the protective layer 33 on the first main surface 4 b opposite to the semiconductor substrate 31 in the semiconductor stacked body 4 via the adhesive layer 34. The adhesion between the metal layers is performed, for example, by atomic diffusion bonding.

  The semiconductor substrate 31 is made of, for example, a III-V group compound semiconductor. The semiconductor substrate 31 is, for example, an InP substrate. The protective layer 32 is a semiconductor layer having high etching selectivity with respect to the semiconductor layer 21 of the semiconductor stacked body 4. The protective layer 32 is an InGaAs layer of about 200 nm, for example. The protective layer 32 is formed by an epitaxial growth method. Similarly, the semiconductor layers 21 to 25 included in the semiconductor stacked body 4 are formed by, for example, an epitaxial growth method.

  The protective layer 33 is a stacked body in which a semiconductor layer 33a having a high etching selectivity with respect to the semiconductor layer 25 of the semiconductor stacked body 4 and a semiconductor layer 33b having a high etching selectivity with respect to the semiconductor layer 33a are sequentially stacked. . The semiconductor layer 33a is an InP layer of about 200 nm, for example. The semiconductor layer 33b is an InGaAs layer of about 200 nm, for example. The semiconductor layers 33a and 33b are formed by an epitaxial growth method. The adhesive layer 34 is a tungsten layer or the like, and is grown by sputtering, for example.

  Next, as shown in FIG. 2B, as a second step, the semiconductor substrate 31 is removed from the semiconductor stacked body 4. For example, the semiconductor substrate 31 is removed by dry etching or wet etching. Then, the protective layer 32 is removed from the semiconductor stacked body 4.

  Next, as shown in FIG. 2C, as a third step, a patterned first etching mask is formed on the second main surface 4 c facing the first main surface 4 b of the exposed semiconductor stacked body 4. 36 is formed. The first etching mask 36 is made of, for example, a silicon compound (SiN layer or SiOx layer) and has an opening 36a. A part of the second main surface 4c is exposed through the opening 36a.

  Next, as shown in FIG. 3A, as a fourth step, a part of the semiconductor stacked body 4 is etched using the first etching mask 36. Specifically, the openings 4a penetrating the semiconductor layers 21 to 25 are formed by wet etching the semiconductor layers 21 to 25 of the semiconductor stacked body 4 exposed through the openings 36a. The wet etching of the semiconductor layers 21 to 25 is performed using, for example, a plurality of etchants. By adjusting the wet etching time, the maximum width of the opening 4 a is larger than the width of the opening 36 a provided in the first etching mask 36. The wet etching time may be several minutes to several tens of minutes, for example.

  Next, as a fifth step, first, the first etching mask 36 is first removed by various etchings, and then, as shown in FIG. 3B, a second etching mask patterned on the second main surface 4c. 37 is formed. The second etching mask 37 has an opening 37a that does not overlap the opening 4a in the stacking direction, and an opening 37b that overlaps the opening 4a in the stacking direction. In this fifth step, before the second etching mask 37 is formed, the flat second etching mask 37 can be formed by filling the opening 4a with, for example, a resin. In this case, the resin filled in the opening 4a is removed by various etchings through the opening 37b after the opening 37b is formed in the second etching mask 37.

  Next, as shown in FIG. 3C, as a sixth step, a part of the semiconductor stacked body 4 is removed using the second etching mask 37. Specifically, a part of the semiconductor layers 21 and 22 of the semiconductor stacked body 4 exposed by the opening 37a is etched to form the opening 26 that forms a gap. More specifically, the InP that forms the semiconductor layer 21 and the n-type InP layer that forms the semiconductor layer 22 are wet-etched using hydrochloric acid having a adjusted concentration, whereby the opening 26 is formed in the semiconductor stacked body 4. Form. Simultaneously with the formation of the opening 26, the opening 4a is expanded by etching through the opening 37b and a part of the semiconductor layer 33a is removed. Specifically, an InP layer as the semiconductor layer 21, an n-type InP layer as the semiconductor layer 22, an n-type InP layer as the semiconductor layer 24, and an InP layer as the semiconductor layer 33a are formed using the hydrochloric acid. By wet etching, a part of the opening 4a is expanded and a part of the semiconductor layer 33a is removed.

  Next, as shown in FIG. 4A, as a seventh step, a resin layer 39 is formed on the second etching mask 37 and is formed by the opening 4 a and the opening 26 of the semiconductor stacked body 4. Fill the gaps with resin. For example, the resin layer 39 is formed by a coating method or an inkjet method, and the opening 4a and the opening 26 are filled with resin.

  Next, as shown in FIG. 4B, as an eighth step, the resin layer 39 is removed. For example, the resin layer 39 is removed by CMP (Chemical Mechanical Polishing). Thereby, at least the resin filled in the opening 4a and the opening 26 remains, and the alignment mark 5 and the region 6 of the present embodiment are formed. Further, the exposed surface of the resin forming the alignment mark 5 and the region 6 and the surface of the second etching mask 37 are substantially flush with each other. The exposed surface of the resin may be recessed by dishing.

Next, as shown in FIG. 4C, as a ninth step, a part of the resin of the alignment mark 5 and a part of the resin that is the region 6 are removed, whereby the recess 5a is formed in the alignment mark 5. And a recess 6 a is formed in the region 6. Specifically, the recesses 5 a and 6 a are formed by dry etching a part of the resin using the second etching mask 37. This dry etching is reactive ion etching using, for example, CF ₄ gas and O ₂ gas, and is performed until the recesses of the recesses 5a and 6a reach at least the second main surface 4c toward the support substrate 35. For example, the reactive ion etching is performed under the conditions of a CF ₄ gas flow rate of 10 sccm, an O ₂ gas flow rate of 5 sccm, a pressure of 20 Pa, and 100 W.

  Next, as shown in FIG. 5A, as a tenth step, the second etching mask 37 is removed. For example, the second etching mask 37 is removed by various etchings.

  Next, as shown in FIG. 5B, as an eleventh step, a support substrate (second support substrate) 2 provided with the first metal layer 11 on the main surface 2a is prepared. Further, the second metal layer 12 is formed on the second main surface 4 c of the semiconductor stacked body 4, the exposed surface of the alignment mark 5, and the exposed surface of the region 6.

  Next, as shown in FIG. 5C, as a twelfth step, the support substrate 2 is bonded onto the second main surface 4 c of the semiconductor stacked body 4. Specifically, the metal substrate 3 is formed by bonding the first metal layer 11 and the second metal layer 12 to each other, so that the support substrate 2 is bonded onto the second main surface 4 c of the semiconductor stacked body 4. . Adhesion between the first metal layer 11 and the second metal layer 12 is performed by, for example, atomic diffusion bonding. Here, the first metal layer 11 and the second metal layer 12 that overlap the recess 5a of the alignment mark 5 as viewed from the stacking direction do not adhere to each other, form a gap 13 and the first metal layer 11 that overlaps the recess 6a of the region 6. The metal layer 11 and the second metal layer 12 do not adhere to each other and form a gap 14. Next, the support substrate 35 is removed from the semiconductor stacked body 4. For example, the support substrate 35 is removed by dry etching or wet etching. Then, the adhesive layer 34 and the protective layer 33 are removed. Thus, the semiconductor element forming substrate 1 is completed (see FIG. 2).

  The alignment mark 5 of the semiconductor element forming substrate 1 formed by the manufacturing method according to this embodiment described above is made of resin. Thereby, compared with the case where the alignment mark made from a metal or an alloy is used, since the metal which touches the semiconductor laminated body 4 reduces, the metal diffusion to the semiconductor layers 21-25 can be suppressed. In addition, by filling the opening 26 provided in a part of the semiconductor layers 21 and 22 with resin, the parasitic capacitance of the semiconductor element forming substrate 1 can be reduced.

  The alignment mark 5 may have a recess 5a that is recessed from the support substrate 2 side toward the semiconductor layer 25, and the recess 5a may form a gap. When the resin constituting the alignment mark 5 is thermally expanded at the time of manufacturing the semiconductor element forming substrate 1 or the like, the resin can be expanded into the gap formed by the recess 5a. Thereby, damage to the semiconductor element forming substrate 1 can be suppressed.

  Further, the resin in the opening 26 may have a relative dielectric constant smaller than that of the semiconductor layer 21.

  In addition, the region 6 that is a resin filled in the opening 26 has a recess 6a that is recessed from the support substrate 2 side toward the semiconductor layer 25 side, and even if a void is formed in the recess 6a. Good. When the resin thermally expands at the time of manufacturing the semiconductor element forming substrate 1, the resin can expand into the gap formed by the recess 6a. Thereby, damage to the semiconductor element forming substrate 1 can be suppressed.

  The semiconductor element forming substrate 1 may be further provided with a metal layer 3 that is provided between the semiconductor stacked body 4 and the support substrate 2 and that joins the semiconductor stacked body 4 and the support substrate 2 to each other. In this case, the heat generated in the semiconductor stacked body 4 is favorably released to the support substrate 2 through the metal layer 3 in contact with the support substrate 2 and the semiconductor stacked body 4.

  In addition, the metal layer 3 includes a first metal layer 11 and a second metal layer 12 that are stacked on each other, and between the first metal layer 11 and the second metal layer 12 that overlap the alignment mark 5 in the stacking direction, A gap 13 may be provided. In this case, thermal stress generated when the semiconductor element forming substrate 1 is heated can be relaxed.

  Next, an example of a method for manufacturing a semiconductor element (HBT) formed using the semiconductor element formation substrate according to the present embodiment will be described with reference to FIGS. FIGS. 6A to 6C and FIGS. 7A and 7B are views for explaining a method for manufacturing a semiconductor element using the semiconductor element forming substrate according to the present embodiment.

  As a 21st step, a part of the semiconductor laminated body 4 of the semiconductor element forming substrate 1 is removed. In the twenty-first step, first, as shown in FIG. 6A, the emitter contact layer 51 is formed by patterning the semiconductor layer 25. For example, the emitter contact layer 51 is formed by wet etching. Next, after forming a third etching mask 41 covering at least the emitter contact layer 51 and the alignment mark 5, the semiconductor layers 23 and 24 are wet-etched. Thereby, the emitter layer 52 and the base layer 53 are formed on the region 6. In the twenty-first step, the semiconductor layer 22 is etched until the region 6 formed outside the base layer 53 is exposed. In the 21st step, the semiconductor layers 22 to 25 are etched using the alignment mark 5 and a third etching mask 41 is formed at a predetermined position.

  Next, as a 22nd step, as shown in FIG. 6B, the semiconductor layers 21 and 22 and the metal layer 3 are patterned to thereby collect the collector layer 54 including the sub-collector layer 54a and the main collector layer 54b. Then, the mesa structure semiconductor stacked body 50 having the base layer 53, the emitter layer 52, and the emitter contact layer 51 is formed. The semiconductor stacked body 50 is provided so as to be separated from the alignment mark 5 and include the region 6. In addition, since the alignment mark 5 and the region 6 are covered with the etching mask during the patterning, the shapes of the alignment mark 5 and the region 6 do not change. Next, an electrode 55 that functions as an emitter electrode on the emitter contact layer 51 of the semiconductor stacked body 50, an electrode 56 that functions as a base electrode on the base layer 53, and an electrode 57 that functions as a collector electrode on the subcollector layer 54a. Respectively. Thereby, the semiconductor element 100 which is HBT is formed. After forming the semiconductor element 100, an insulating film 58 that covers the alignment mark 5 and the semiconductor element 100 is formed. The insulating film 58 is, for example, a silicon nitride film. In the twenty-second step, the semiconductor layers 21 and 22 and the metal layer 3 are etched using the alignment mark 5 and the electrodes 55 to 57 are formed at predetermined positions.

  Next, as shown in FIG. 6C, as a twenty-third step, interlayer films 59a and 59b, a wiring 60 connected to the electrode 55, and a wiring 61 connected to the electrode 57 are formed. The interlayer films 59a and 59b may be referred to as planarization films, and are layers formed of, for example, a resin such as polyimide. Moreover, the wirings 60 and 61 are made of a conductive material including a metal or an alloy. Although not shown in FIG. 6C, a wiring connected to the electrode 56 is also formed in the 23rd step.

  Next, as shown in FIG. 7A, as a 24th step, a part of the main surface 2a of the support substrate 2 is exposed by removing a part of the insulating film 58 and the interlayer films 59a and 59b. A groove G to be formed is formed. For example, the groove G is formed by removing the insulating film 58 and the interlayer films 59a and 59b by various etchings. The grooves G are formed, for example, in a lattice shape when viewed from the stacking direction. The region exposed by the groove G is a region through which a dicing saw described later passes.

  Next, as shown in FIG. 7B, after the thinning of the support substrate 2 is performed as a twenty-fifth step, the semiconductor element 100 is formed on the surface 2b facing the main surface 2a of the support substrate 2. A conductive layer 62 functioning as a back electrode is formed. After the formation of the conductive layer 62, the support substrate 2 is cut along the grooves G formed on the support substrate 2 to divide the alignment mark 5 and the semiconductor element 100. For example, the support substrate 2 is cut using a dicing saw.

The region 6 is provided in the semiconductor element 100 formed using the semiconductor element forming substrate 1 according to this embodiment described above. The resin in this region 6 is at least smaller than the relative dielectric constant of the semiconductor layer 21. Thereby, a partial region of the semiconductor stacked body 50 included in the semiconductor element 100 is replaced with a resin having a relative dielectric constant smaller than that, so that the parasitic capacitance of the semiconductor element 100 can be reduced.

  The semiconductor element forming substrate, the semiconductor element forming substrate manufacturing method, and the semiconductor element manufacturing method formed using the semiconductor element forming substrate according to the present invention are not limited to the above-described embodiments and modifications. Various other modifications are possible. For example, the semiconductor element 100 according to the embodiment is not limited to the HBT, and may be, for example, a high electron mobility transistor (HEMT).

  Moreover, in the said embodiment and modification, you may combine mutually in the possible range. For example, the region 6 embedded in the semiconductor stacked body 4 may be provided only in the semiconductor layer 21. Further, the region may not be filled with resin, and a gap may be formed in the subcollector layer 54 a of the semiconductor element 100.

  In the embodiment and the modification, the semiconductor stacked body 4 may include an etch stop layer. For example, the etch stop layer is included between the semiconductor layer 21 and the semiconductor layer 22 in the semiconductor stacked body 4, and the etching selectivity with respect to the semiconductor layer 22 is very low. In this case, the etch stop layer can suppress excessive etching of the semiconductor layer 22 and can suppress a change in characteristics of the semiconductor element. For example, InGaAs is used as the etch stop layer. This etch stop layer is etched using, for example, a liquid obtained by diluting a mixed solution of phosphoric acid and hydrogen peroxide with water as an etchant.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor element formation board | substrate, 2 ... Support substrate, 2a ... Main surface, 3 ... Metal layer, 4 ... Semiconductor laminated body, 4a ... Opening part, 5 ... Alignment mark, 5a ... Recessed part, 6 ... Area, 6a ... Recessed part 11 ... 1st metal layer, 12 ... 2nd metal layer, 13, 14 ... gap | interval, 21-25 ... semiconductor layer, 26 ... opening part, 31 ... semiconductor substrate, 35 ... support substrate, 36 ... 1st etching mask, 37 ... second etching mask, 51 ... emitter contact layer, 52 ... emitter layer, 53 ... base layer, 54 ... collector layer, 54a ... sub-collector layer, 54b ... main collector layer, 55-57 ... electrode, 100 ... semiconductor element , G ... groove.

Claims (5)

A support substrate;
A semiconductor stacked body provided on the main surface of the support substrate, which is stacked in order from the support substrate side, and functions as a first semiconductor layer functioning as a collector, a second semiconductor layer functioning as a base, and an emitter. A semiconductor laminate having a third semiconductor layer;
An alignment mark made of a resin filled in a first opening that penetrates the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and
A substrate for forming a semiconductor element, wherein a second opening different from the first opening is provided in a part of the first semiconductor layer, and the second opening is filled with a resin. The alignment mark has a first recess recessed from the support substrate side toward the third semiconductor layer side,
The substrate for forming a semiconductor element according to claim 1, wherein the first recess forms a first gap.   The substrate for forming a semiconductor element according to claim 1, wherein the resin in the second opening has a relative dielectric constant smaller than that of the first semiconductor layer. Forming a semiconductor stacked body in which a first semiconductor layer functioning as a collector, a second semiconductor layer functioning as a base, and a third semiconductor layer functioning as an emitter are sequentially stacked on a semiconductor substrate;
A second step of bonding a first support substrate on a first main surface opposite to the semiconductor substrate side in the semiconductor laminate;
A third step of removing the semiconductor substrate from the semiconductor stack;
A first etching mask is formed on a second main surface opposite to the first main surface of the semiconductor multilayer body, and then penetrates through the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by etching. A fourth step of forming an opening to be
A fifth step of removing the first etching mask;
A sixth step of forming a second etching mask on the second main surface, expanding the opening by etching, and removing a portion of the first semiconductor layer to form a void;
Forming an alignment mark in the opening by filling the opening with resin, and filling the gap with the resin;
A method for manufacturing a substrate for forming a semiconductor element. A method for manufacturing a substrate for forming a semiconductor element according to claim 4,
An eighth step of bonding a second support substrate to the second main surface after removing the second etching mask;
A ninth step of forming a collector layer, a base layer, and an emitter layer by etching the semiconductor stack;
A tenth step of forming a collector electrode on the collector layer, a base electrode on the base layer, and an emitter electrode on the emitter layer;
The alignment mark is separated from the collector layer, the base layer, the emitter layer, the resin filled in the gap, the collector electrode, the base electrode, and the semiconductor element having the emitter electrode. An eleventh step of cutting the second support substrate;
With
The relative dielectric constant of the resin contained in the semiconductor element is smaller than the relative dielectric constant of the collector layer,
A method for manufacturing a semiconductor device.

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