JP2016197194A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device with which it is possible to reduce the number of transistors for composing a logic circuit even when an enable signal dividing circuit is installed, and an electronic apparatus equipped with the electro-optic device.SOLUTION: In a data line drive circuit 101 formed on the element substrate 10 of the electro-optic device, first enable signals ENBs1, ENBs2 are active-low pulse signals, and an enable signal dividing circuit 130 generates active-high second enable signals ENBx1, ENBx2, ENBx3, ENBx4 by only four NOR circuits 131 and outputs the generated signals to a sampling signal output circuit 150. The sampling signal output circuit 150 generates active-high sampling signals Q1, Q2, Q3, Q4 by the active-high second enable signals ENBx1, ENBx2, ENBx3, ENBx4 and active-high transfer signals P1, P2 outputted from a shift register 140.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an electro-optical device in which an enable signal dividing circuit is provided on an element substrate, and an electronic apparatus including the electro-optical device.

  In an electro-optical device such as a liquid crystal device, a plurality of data lines, a plurality of scanning lines extending in a direction intersecting with the plurality of data lines, and a crossing of the data lines and the scanning lines are provided on one side of the element substrate. A plurality of correspondingly provided pixels are configured. In such an electro-optical device, the sampling circuit samples an image signal based on the sampling signal output from the data line driving circuit and supplies the data line to the data line.

  In such an electro-optical device, it has been proposed to provide an enable signal dividing circuit 130 on the element substrate 10 as shown in FIG. As shown in FIGS. 10 and 11, the enable signal dividing circuit 130 includes a positive logic first enable signal ENBs1 input through the selection circuit 120 by the NAND circuit 138 and the NOT circuit 139 (inverter), ENBs2 is divided for each series, and a plurality of series of positive logic second enable signals ENBx1, ENBx2, ENBx3, ENBx4 having a pulse width narrower than the pulse width of the transfer signal output from shift register 140 are generated. On the other hand, when supplying image signals in six phases to n data lines, the shift register 140 receives positive logic transfer signals P1, P2,... From each stage by a start pulse DX, a clock signal CLX, and a reverse phase clock signal CLXINV. -Pn / 12 is output (patent document 1).

  Accordingly, the sampling signal output circuit 150 receives, for example, the NAND circuit 158 to which the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 and the positive logic transfer signals P1 and P2 are input, and the output of the NAND circuit 158, for example. And an AND circuit 159 to which a positive logic control signal NRG is input. As a result, positive logic sampling signals Q 1, Q 2, Q 3, Q 4... Qn / 6 can be output to the selection signal line 109 for a predetermined period defined by the control signal NRG. Here, the control signal NRG is inverted by the NOT circuit 156 and input to the AND circuit 159. The sampling signals Q1, Q2, Q3, Q4,... Qn output from the AND circuit 159 are output to the sampling circuit via two NOT circuits 154, 155 connected in series.

JP 2009-180969 A

  However, when the circuit configuration shown in FIG. 10 is adopted, the number of transistors for configuring the logic circuit is increased by the provision of the enable signal dividing circuit 130, so that a signal delay occurs. As a result, in the sampling circuit, the sampling signals Q1, Q2, Q3, Q4... Qn / 2 and the image signal are out of timing and the image quality is lowered.

  In view of the above problems, an object of the present invention is to provide an electro-optical device that can reduce the number of transistors for forming a logic circuit even when an enable signal dividing circuit is provided, and the electro-optical device. The object is to provide an electronic device equipped.

  In order to solve the above-described problems, an aspect of the electro-optical device according to the present invention includes a plurality of data lines and a plurality of scans extending in a direction intersecting the plurality of data lines on one surface side of the element substrate. Line, a plurality of pixels provided corresponding to each intersection of the data line and the scanning line, a shift register for sequentially outputting a transfer signal from each of the plurality of stages, and an input via the terminal of the element substrate An enable signal dividing circuit that divides the generated first enable signal to generate a plurality of second enable signals having a pulse width narrower than the pulse width of the transfer signal, and the second enable signal for each of the plurality of sequences. A sampling signal output circuit that shapes the transfer signal and outputs a sampling signal in which a pulse width of the transfer signal is limited to a pulse width of the second enable signal; And a sampling circuit for sampling the image signal and supplying the sampling signal to the data line, the first enable signal is a negative logic pulse signal, and the enable signal dividing circuit is positive logic by a NOR circuit. The second enable signal is generated and output to the sampling signal output circuit.

  In the present invention, the first enable signal is a negative logic pulse signal, and the enable signal dividing circuit generates a positive logic second enable signal by the NOR circuit and outputs the second enable signal to the sampling signal output circuit. For this reason, since the number of transistors for forming the logic circuit is smaller than when the first enable signal of positive logic is used and the NAND circuit and NOT circuit are used as the enable signal dividing circuit, the second enable Signal delay in signals and sampling signals can be suppressed. Therefore, in the sampling circuit, it is possible to suppress a timing shift between the sampling signal and the image signal, and it is possible to suppress a deterioration in image quality caused by the shift. Further, since the number of transistors for forming the logic circuit is small, power consumption can be reduced.

  In this case, it is preferable that the shift register outputs the positive logic transfer signal, and the sampling signal output circuit generates the positive logic sampling signal by the second enable signal and the transfer signal.

  Another aspect of the electro-optical device according to the invention includes a plurality of data lines, a plurality of scanning lines extending in a direction intersecting the plurality of data lines, the data lines, and the data lines on one surface side of the element substrate. Dividing a plurality of pixels provided corresponding to each intersection with a scanning line, a shift register for sequentially outputting a transfer signal from each of a plurality of stages, and a first enable signal input via a terminal of the element substrate An enable signal dividing circuit for generating a plurality of second enable signals having a pulse width narrower than a pulse width of the transfer signal, and shaping the transfer signal based on the second enable signal for each of the plurality of sequences. A sampling signal output circuit that outputs a sampling signal in which the pulse width of the transfer signal is limited to the pulse width of the second enable signal; and an image signal based on the sampling signal And the first enable signal is a positive logic pulse signal, and the enable signal dividing circuit is a negative logic second enable signal by a NAND circuit. And output to the sampling signal output circuit.

  In the present invention, the first enable signal is a positive logic pulse signal, and the enable signal dividing circuit generates a negative logic second enable signal by the NAND circuit and outputs the second enable signal to the sampling signal output circuit. For this reason, since the number of transistors for forming the logic circuit is smaller than when the first enable signal of positive logic is used and the NAND circuit and NOT circuit are used as the enable signal dividing circuit, the second enable Signal delay in signals and sampling signals can be suppressed. Therefore, in the sampling circuit, it is possible to suppress a timing shift between the sampling signal and the image signal, and it is possible to suppress a deterioration in image quality caused by the shift.

  In this case, it is preferable that the shift register outputs the negative logic transfer signal, and the sampling signal output circuit generates the positive logic sampling signal based on the second enable signal and the transfer signal. According to this configuration, a positive logic sampling signal can be generated even if the second enable signal is negative logic.

  According to another aspect of the present invention, the sampling signal output circuit receives a first NOR circuit to which the second enable signal and the transfer signal are input, an output signal of the first NOR circuit and a positive logic control signal. The second NOR circuit is preferably provided. According to this configuration, the number of NOT circuits provided in the sampling signal output circuit can be reduced, so that signal delay in the sampling signal can be suppressed. Therefore, in the sampling circuit, it is possible to suppress a timing shift between the sampling signal and the image signal, and it is possible to suppress a deterioration in image quality caused by the shift.

  The electro-optical device according to the present invention can be used in electronic devices such as a mobile phone, a mobile computer, and a projection display device. Among these electronic apparatuses, the projection display device includes a light source unit for supplying light to the electro-optical device and a projection optical system that projects light modulated by the electro-optical device.

FIG. 3 is an explanatory diagram of a liquid crystal panel of the electro-optical device according to the first embodiment of the invention. FIG. 3 is an explanatory diagram showing an electrical configuration of an element substrate of the electro-optical device according to Embodiment 1 of the invention. 3 is an explanatory diagram of a data line driving circuit of the electro-optical device according to the first embodiment of the invention. FIG. FIG. 4 is an explanatory diagram showing an enlarged part of the data line driving circuit shown in FIG. 3. 4 is a timing chart of signals and the like generated by the data line driving circuit shown in FIG. 7 is an explanatory diagram of a data line driving circuit of an electro-optical device according to a second embodiment of the invention. FIG. FIG. 7 is an explanatory diagram showing an enlarged part of the data line driving circuit shown in FIG. 6. 7 is a timing chart of signals and the like generated by the data line driving circuit shown in FIG. It is a schematic block diagram of the projection type display apparatus (electronic device) and optical unit to which this invention is applied. FIG. 4 is an explanatory diagram showing an enlarged part of a data line driving circuit of an electro-optical device according to a reference example of the invention. 11 is a timing chart of signals and the like generated by the data line driving circuit shown in FIG.

  Hereinafter, a liquid crystal device which is a typical electro-optical device will be described as an embodiment of the present invention. In the following description, portions common to the configurations described with reference to FIGS. 10 and 11 are described with the same reference numerals.

[Embodiment 1]
FIG. 1 is an explanatory diagram of a liquid crystal panel of an electro-optical device according to Embodiment 1 of the present invention. FIGS. 1 (a) and 1 (b) show the liquid crystal panel together with the respective components from the counter substrate side. FIG. 6 is a plan view and a sectional view taken along the line HH ′.

  As shown in FIGS. 1A and 1B, the electro-optical device 100 according to this embodiment is a liquid crystal device, and includes a liquid crystal panel 100p. In the liquid crystal panel 100p, the element substrate 10 and the counter substrate 20 are bonded to each other with a sealant 107 through a predetermined gap, and the sealant 107 is provided in a frame shape along the outer edge of the counter substrate 20. The sealing material 107 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is mixed with a gap material 107a such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. In the liquid crystal panel 100p, a liquid crystal layer 50 (electro-optical material layer) made of various liquid crystal materials (electro-optical materials) is formed in a region surrounded by the sealing material 107 between the element substrate 10 and the counter substrate 20. Is provided. In this embodiment, the sealing material 107 is formed with a discontinuous portion used as the liquid crystal injection port 107c. The liquid crystal injection port 107c is sealed with a sealing material 107d after the liquid crystal material is injected.

  In the liquid crystal panel 100p having such a configuration, both the element substrate 10 and the counter substrate 20 are quadrangular, and an image display region 10a is provided as a quadrangular region substantially at the center of the liquid crystal panel 100p. The outer side of the image display area 10a is a rectangular frame-shaped outer peripheral area 10c.

  In the element substrate 10, in the outer peripheral region 10 c, the data line driving circuit 101 and the plurality of terminals 102 are formed along the side 10 e located on one side of the element substrate 10 in the Y-axis direction. A sampling circuit 103 is configured between the image display area 10a. In the element substrate 10, in the outer peripheral region 10c, the scanning line driving circuit 104 is formed along each of the other sides 10g and 10h adjacent to the side 10e. A flexible wiring board (not shown) is connected to the terminal 102, and various potentials and various signals are input to the element substrate 10 from an external control circuit via the flexible wiring board.

  Of the one surface 10 s and the other surface 10 t of the element substrate 10, on the one surface 10 s side facing the counter substrate 20, the pixel electrode 9 a in the image display region 10 a and a pixel transistor 30 described later with reference to FIG. Etc. are arranged in a matrix, and an alignment film 16 is formed on the upper layer side of the pixel electrode 9a. On the one surface 10s side of the element substrate 10, out of the outer peripheral region 10c outside the image display region 10a, a rectangular frame-shaped peripheral region 10b sandwiched between the image display region 10a and the sealing material 107 has a pixel electrode 9a. The dummy pixel electrode 9b formed at the same time is formed.

  A common electrode 21 is formed on the side of the one surface 20 s facing the element substrate 10 out of the one surface 20 s and the other surface 20 t of the counter substrate 20. The common electrode 21 is formed across the plurality of pixels 100a as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes. In this embodiment, the common electrode 21 is formed on substantially the entire surface of the counter substrate 20. On one side 20 s of the counter substrate 20, a light shielding layer 29 is formed on the lower layer side of the common electrode 21, and an alignment film 26 is laminated on the surface of the common electrode 21. The light shielding layer 29 is formed as a frame portion 29 a extending along the outer peripheral edge of the image display area 10 a, and the image display area 10 a is defined by the inner peripheral edge of the light shielding layer 29. The light shielding layer 29 is also formed as a black matrix portion 29b that overlaps an inter-pixel region sandwiched between adjacent pixel electrodes 9a.

  In the liquid crystal panel 100p, inter-substrate conduction electrodes 25 are formed on the four corners on the one surface 20s side of the counter substrate 20 outside the sealing material 107, and on the one surface 10s side of the element substrate 10. The inter-substrate conduction electrodes 19 are formed at positions facing the four corners of the counter substrate 20 (inter-substrate conduction electrodes 25). In this embodiment, the inter-substrate conduction electrode 25 is composed of a part of the common electrode 21. A common potential Vcom is applied to the inter-substrate conduction electrode 19. An inter-substrate conducting material 19 a containing conductive particles is disposed between the inter-substrate conducting electrode 19 and the inter-substrate conducting electrode 25, and the common electrode 21 of the counter substrate 20 is the inter-substrate conducting electrode 19. The element substrate 10 is electrically connected through the inter-substrate conductive material 19a and the inter-substrate conductive electrode 25. Therefore, the common potential Vcom is applied to the common electrode 21 from the element substrate 10 side.

  In this embodiment, the electro-optical device 100 is a transmissive liquid crystal device, and the pixel electrode 9a and the common electrode 21 are formed of a light-transmitting conductive film such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. Has been. In such a transmissive liquid crystal device (electro-optical device 100), for example, light incident from the counter substrate 20 side is modulated while being emitted from the element substrate 10 side, and an image is displayed. When the electro-optical device 100 is a reflective liquid crystal device, the common electrode 21 is formed of a light-transmitting conductive film such as an ITO film or an IZO film, and the pixel electrode 9a is a reflective conductive film such as an aluminum film. It is formed by. In such a reflective liquid crystal device (electro-optical device 100), light incident from the counter substrate 20 side is modulated while being reflected by the element substrate 10 and emitted to display an image.

  The electro-optical device 100 can be used as a color display device of an electronic device such as a mobile computer or a mobile phone. In this case, a color filter (not shown) is formed on the counter substrate 20. The electro-optical device 100 can be used as electronic paper. Further, in the electro-optical device 100, a polarizing film, a retardation film, a polarizing plate, and the like are predetermined with respect to the liquid crystal panel 100p according to the type of the liquid crystal layer 50 to be used and the normally white mode / normally black mode. Arranged in the direction. Furthermore, the electro-optical device 100 can be used as a light valve for RGB in a projection display device (liquid crystal projector) described later. In this case, each of the RGB electro-optical devices 100 receives light of each color separated through RGB color separation dichroic mirrors as projection light, so that no color filter is formed. .

(Electrical configuration of the element substrate 10)
FIG. 2 is an explanatory diagram showing an electrical configuration of the element substrate 10 of the electro-optical device 100 according to the first embodiment of the present invention. FIGS. 2 (a) and 2 (b) are circuits and wirings of the element substrate 10. FIG. FIG. 5 is an explanatory diagram showing a planar layout of the pixel and an explanatory diagram showing an electrical configuration of a pixel. In the following description, the same alphabet symbol is given to the signal name and signal wiring input to the element substrate 10 via the terminal 102 after the signal and the wiring L, respectively. For example, for the signal name “clock signal CLX”, the corresponding signal wiring is “wiring LCLX”. In the following description, the same alphabetical symbol is given to the signal name and the signal terminal input to the element substrate 10 via the terminal 102 after the signal and the terminal T, respectively. For example, the terminal 102 corresponding to the signal name “clock signal CLX” is “terminal TCLX”.

  As shown in FIGS. 2A and 2B, in the electro-optical device 100, a pixel electrode array region 10p in which a plurality of pixels 100a are arrayed in a matrix is provided in the central region of the element substrate 10. Of the pixel electrode array region 10p, the region surrounded by the inner edge of the frame portion 29a shown in FIG. 1B is the image display region 10a. In the element substrate 10, a plurality of scanning lines 3a extending in the X direction and a plurality of data lines 6a extending in the Y direction are formed inside the pixel electrode array region 10p, and correspond to the intersections thereof. A pixel 100a is formed at each position. In each of the plurality of pixels 100a, a pixel transistor 30 (switching element) made of a TFT or the like and a pixel electrode 9a are formed. The data line 6 a is electrically connected to the source of the pixel transistor 30, the scanning line 3 a is electrically connected to the gate of the pixel transistor 30, and the pixel electrode 9 a is electrically connected to the drain of the pixel transistor 30. Has been.

  In the element substrate 10, a scanning line driving circuit 104, a data line driving circuit 101, a sampling circuit 103, an inter-substrate conduction electrode 19, a terminal 102, and the like are configured in the outer peripheral region 10 c outside the pixel electrode arrangement region 10 p. A plurality of wirings 105 extend from the terminal 102 toward the scanning line driving circuit 104, the data line driving circuit 101, the sampling circuit 103, and the inter-substrate conduction electrode 19.

  In each pixel 100a, the pixel electrode 9a is opposed to the common electrode 21 formed on the counter substrate 20 described with reference to FIG. 1 via the liquid crystal layer 50, thereby forming a liquid crystal capacitor 50a. Each pixel 100a is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuations in the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, a constant potential line 8a (capacitance line) extending across the plurality of pixels 100a is formed, and a common potential Vcom is applied to the constant potential line 8a.

  The terminal 102 is composed of a plurality of terminal groups that are roughly classified into four applications, ie, for common potential lines, for scanning line driving circuits, for image signals, and for data line driving circuits. Specifically, the terminal 102 includes a terminal TVcom for the common potential line LVcom, and includes a terminal TDY, a terminal TVSSY, a terminal TVDDY, a terminal TCLY, and a terminal TCLYINV for the scanning line driving circuit 104. The terminal 102 includes terminals TVID1 to TVID6 for the image signals VID1 to VID6. For the data line driving circuit 101, the terminal TVSSX, the terminal TDX, the terminal TVDDX, the terminal TCLX, the terminal TCLXINV, the terminals TENBs1, TENBs2, and the terminal TVSSX is provided. In this embodiment, the image signals VID1 to VID6 are serial-parallel expanded (that is, phase expanded) in, for example, an external circuit and input to a sampling circuit 103 described later via the six image signal lines LVID1 to LVID6. Is done. Note that the number of phase expansions of the image signal is not limited to six phases. For example, image signals expanded in a plurality of phases such as 9 phases, 12 phases, 24 phases, and 48 phases correspond to the number of expansions. Supplied to a set of data lines 6a whose number is one set.

(Configuration of data line driving circuit 101 and the like)
FIG. 3 is an explanatory diagram of the data line driving circuit 101 of the electro-optical device 100 according to Embodiment 1 of the present invention. 4 is an explanatory diagram showing an enlarged part of the data line driving circuit 101 shown in FIG. 3. FIGS. 4A and 4B show four sampling signals Q1 in the data line driving circuit 101. FIG. , Q2, Q3, and Q4 are enlarged explanatory views showing the NOR circuit 131 used in the enable signal dividing circuit 130. FIG. FIG. 5 is a timing chart of signals and the like generated by the data line driving circuit 101 shown in FIG.

  As shown in FIGS. 2, 3, 4, and 5, the data line driving circuit 101 includes a selection circuit 120, an enable signal dividing circuit 130, a shift register 140, and a sampling signal output circuit 150.

  In the data line driving circuit 101, the enable signal dividing circuit 130 includes a first enable signal supplied from the external control circuit via the terminal 102 (terminals TENBs1, TENBs2), the wiring 105 (wiring LENBs1, LENBs2), and the selection circuit 120. ENBs1 and ENBs2 are divided for each series to generate second enable signals ENBx1, ENBx2, ENBx3, and ENBx4. At that time, the enable signal dividing circuit 130 is supplied with the clock signal CLX from the external control circuit via the terminal 102 (terminal TCLX), the wiring 105 (wiring LCLX), and the selection circuit 120, and is generated by the selection circuit 120. Alternatively, the selected antiphase clock signal CLXINV is supplied.

  The shift register 140 uses the negative power supply VSSX and the positive power supply VDDX supplied from the external control circuit via the terminal 102 (terminals TVSSX, TVDDX) and the wiring 105 (wiring LVSSX, LVDDX) as power supplies, and the terminal 102 from the external control circuit. The transfer operation is started based on the start pulse DX supplied via the (terminal TDX) and the wiring 105 (wiring LDX). More specifically, the shift register 140 is connected to each stage based on the clock signal CLX and the antiphase clock signal CLXINV supplied via the terminal 102 (terminals TCLX, TCLXINV) and the wiring 105 (wiring LCLX, LCLXINV). The transfer signals P1, P2,..., Pn / 12 are sequentially output to the sampling signal output circuit 150. Here, the pulse widths of the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 are narrower than the pulse widths of the transfer signals P1, P2,... Pn / 12. Note that an end pulse generation circuit 180 that generates an end pulse EP is formed at the final stage of the shift register 140.

  The sampling signal output circuit 150 uses the second enable signals ENBx1, ENBx2, ENBx3 generated by the enable signal dividing circuit 130 to generate the pulse widths of the transfer signals P1, P2,..., Pn / 12 sequentially output from the shift register 140. , And ENBx4 pulse width. As a result, the sampling signal output circuit 150 outputs sampling signals Q1, Q2, Q3, Q4... Qn / 6 that define each sampling period in the sampling circuit 103.

  As shown in FIG. 2, the sampling circuit 103 includes a plurality of switching elements 108 for sampling an image signal. In this embodiment, the switching element 108 is composed of a field effect transistor such as an N-channel TFT, for example. The data line 6 a is electrically connected to the drain of the switching element 108. The wiring 105 (image signal lines LVID 1 to LVID 6) is connected to the source of the switching element 108 via the wiring 106, and the switching element 108. The selection signal line 109 connected to the sampling signal output circuit 150 of the data line driving circuit 101 is connected to the gate of the first line. The image signals VID1 to VID6 supplied to the wiring 105 (image signal lines LVID1 to LVID6) via the terminal 102 (terminals TVID1 to TVID6) are sampled signals supplied from the sampling signal output circuit 150 through the selection signal line 109. Sampling is performed by the sampling circuit 103 based on Q1, Q2, Q3, Q4... Qn / 6. As a result, the image signals S1, S2, S3,... Sn are supplied to each data line 6a. The switching element 108 may be composed of a complementary field effect transistor.

  The scanning line driving circuit 104 includes a shift register circuit and a buffer circuit as components, and starts a transfer operation of the built-in shift register circuit in response to the start pulse DY, and generates a clock signal CLY and an antiphase clock signal CLYINV. Based on this, a scanning signal is applied to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

(Detailed configuration and operation of the data line driving circuit 101 and the like)
As shown in FIG. 4, in the electro-optical device 100 of the present embodiment, the first enable signals ENBs1 and ENBs2 are both negative logic pulse signals. The enable signal dividing circuit 130 also receives two NOR circuits 131 (the NOR circuit 131a and the NOR circuit 131c) to which the first series of first enable signals ENBs1 are input and the second series of the first enable signals ENBs2. 2 NOR circuits 131 (NOR circuit 131b and NOR circuit 131d).

  Among the four NOR circuits 131, the first enable signal ENBs1 and the clock signal CLX are input to the NOR circuit 131a that generates the second enable signal ENBx1 from the first series of first enable signals ENBs1. The first enable signal ENBs1 and the antiphase clock signal CLXINV are input to the NOR circuit 131c that generates the second enable signal ENBx3 from the first enable signal ENBs1 of the first series.

  The first enable signal ENBs2 and the clock signal CLX are input to the NOR circuit 131b that generates the second enable signal ENBx2 from the second series of first enable signals ENBs2. The first enable signal ENBs2 and the antiphase clock signal CLXINV are input to the NOR circuit 131d that generates the second enable signal ENBx4 from the second series of first enable signals ENBs2.

  Therefore, as shown in FIG. 5, the enable signal dividing circuit 130 generates the positive logic second enable signals ENBx1, ENBx2, ENBx3, and ENBx4 and outputs them to the sampling signal output circuit 150.

  As shown in FIG. 4B, in the enable signal dividing circuit 130, the NOR circuit 131 is composed of two N-type field effect transistors 171 and 172 and two P-type field effect transistors 173 and 174. It is configured. Specifically, a P-type field effect transistor 173 and an N-type field effect transistor 171 are electrically connected in series between the high voltage Vddx and the low voltage Vssx. A clock signal (clock signal CLX or antiphase clock signal CLXINV) is applied to the gate of the n-type field effect transistor 173 and the gate of the n-type field effect transistor 171. A P-type field effect transistor 174 is connected in series between the P-type field effect transistor 173 and the N-type field effect transistor 171, and the N-type field effect transistor 171 includes N Type field effect transistors 172 are connected in parallel.

  A first enable signal (first enable signal ENBs1 or first enable signal ENBs2) is applied to the gates of the P-type field effect transistor 174 and the N-type field effect transistor 172. Further, from the connection point between the P-type field effect transistor 174 and the N-type field effect transistor 172, a second enable signal (second enable signal ENBx1, second enable signal ENBx2, second enable signal ENBx3, or The second enable signal ENBx4) is output.

  3, 4, and 5 again, in this embodiment, the shift register 140 outputs the positive logic transfer signals P 1 and P 2, and the sampling signal output circuit 150 outputs the positive logic second enable signals ENBx 1, ENBx 2, ENBx 3. , ENBx4 and positive logic transfer signals P1, P2 generate positive logic sampling signals Q1, Q2, Q3, Q4.

  More specifically, the odd-numbered stage of the shift register 140 includes a first clocked inverter 141 that operates based on the clock signal CLX, and a first inverter 142 that is electrically connected in series to the first clocked inverter 141. And a second clocked inverter 143 electrically connected in parallel to the first inverter 142, and the second clocked inverter 143 operates based on the anti-phase clock signal CLXINV. Therefore, a positive logic transfer signal P 1 is output from the first inverter 142 to the sampling signal output circuit 150. Further, the even-numbered stage of the shift register 140 includes a third clocked inverter 144 that operates based on the anti-phase clock signal CLXINV, a second inverter 145 that is electrically connected in series to the third clocked inverter 144, And a fourth clocked inverter 146 electrically connected in parallel to the second inverter 145, and the fourth clocked inverter 146 operates based on the clock signal CLX. Accordingly, the positive inverter transfer signal P2 is output from the second inverter 145 to the sampling signal output circuit 150 at a timing shifted by a half cycle with respect to the transfer signal P1.

  The sampling signal output circuit 150 includes a NAND circuit 158 for each series to which any one of the second enable signals ENBx1, ENBx2, ENBx3, and ENBx4 and any one of the transfer signals P1 and P2 are input. And an AND circuit 159 for each series to which an inverted output signal and a positive logic control signal NRG are input. At this time, the transfer signal P1 is input to the two NAND circuits 158a and 158b to which the second enable signals ENBx1 and ENBx2 are input at adjacent positions among the four NAND circuits 158, and the transfer signal P2 is the four NAND circuits. In the circuit 158, the second enable signals ENBx3 and ENBx4 are input to adjacent two NAND circuits 158c and 158d at adjacent positions.

  As a result, the transfer signals P1 and P2 are shaped by the NAND circuit 158 based on the waveforms of the second enable signals ENBx1, ENBx2, ENBx3, and ENBx4 having a narrow pulse width, and the second enable signals ENBx1, ENBx2, and ENBx3 for each series. , ENBx4, and output to the sampling circuit 103 as positive logic sampling signals Q1, Q2, Q3, Q4,.

  Here, the control signal NRG is inverted by the NOT circuit 156 and input to the AND circuit 159. The sampling signals Q1, Q2, Q3, Q4,... Qn output from the AND circuit 159 are output to the sampling circuit 103 via two NOT circuits 154 and 155 connected in series.

(Main effects of this form)
As described above, in the present embodiment, the first enable signals ENBs1 and ENBs2 are negative logic pulse signals, and the enable signal dividing circuit 130 has the positive logic second enable signals ENBx1, ENBx2, ENBx3, ENBx4 is generated and output to the sampling signal output circuit 150. For this reason, the number of transistors for forming the logic circuit is small as compared with the case where the positive logic first enable signal is used and the NAND circuit and the NOT circuit are used as the enable signal dividing circuit. Therefore, signal delay in the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 and sampling signals Q1, Q2, Q3, Q4,. Therefore, in the sampling circuit 103, timing deviation between the sampling signals Q1, Q2, Q3, Q4... And the image signals VID1 to VID6 can be suppressed, and deterioration in image quality due to such deviation can be suppressed. Can do. Further, since the number of transistors for forming the logic circuit is small, power consumption can be reduced.

[Embodiment 2]
FIG. 6 is an explanatory diagram of the data line driving circuit 101 of the electro-optical device 100 according to Embodiment 2 of the present invention. FIG. 7 is an explanatory diagram showing an enlarged part of the data line driving circuit 101 shown in FIG. FIG. 8 is a timing chart of signals and the like generated by the data line driving circuit 101 shown in FIG. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIGS. 6, 7, and 8, also in this embodiment, the data line driving circuit 101 includes a selection circuit 120, an enable signal dividing circuit 130, a shift register 140, and a sampling signal output, as in the first embodiment. A circuit 150 is provided.

  In the electro-optical device 100 of this embodiment, the first enable signals ENBs1 and ENBs2 are both positive logic pulse signals. The enable signal dividing circuit 130 also receives two NAND circuits 132 (NAND circuit 132a and NAND circuit 132c) to which the first series of first enable signals ENBs1 are input and the second series of first enable signals ENBs2. 2 NAND circuits 132 (NAND circuit 132b and NAND circuit 132d).

  Among the four NAND circuits 132, the first enable signal ENBs1 and the antiphase clock signal CLXINV are input to the NAN circuit 132a that generates the second enable signal ENBx1 from the first series of first enable signals ENBs1. The first enable signal ENBs1 and the clock signal CLX are input to the NAND circuit 132c that generates the second enable signal ENBx3 from the first enable signal ENBs1 of the first series.

  The first enable signal ENBs2 and the antiphase clock signal CLXINV are input to the NAND circuit 132b that generates the second enable signal ENBx2 from the second series of first enable signals ENBs2. The first enable signal ENBs2 and the clock signal CLX are input to the NOR circuit 132d that generates the second enable signal ENBx4 from the second series of first enable signals ENBs2.

  Therefore, as shown in FIG. 8, the enable signal dividing circuit 130 generates negative enable second enable signals ENBx1, ENBx2, ENBx3, and ENBx4 and outputs them to the sampling signal output circuit 150.

  In this embodiment, the shift register 140 outputs the negative logic transfer signals P1 and P2 to the sampling signal output circuit 150, and the sampling signal output circuit 150 outputs the negative logic second enable signals ENBx1, ENBx2, ENBx3, ENBx4, and Positive logic sampling signals Q1, Q2, Q3, and Q4 are generated by the negative logic transfer signals P1 and P2.

  More specifically, the odd-numbered stage of the shift register 140 includes a first clocked inverter 141 that operates based on the clock signal CLX, and a first inverter 142 that is electrically connected in series to the first clocked inverter 141. And a second clocked inverter 143 electrically connected in parallel to the first inverter 142, and the second clocked inverter 143 operates based on the anti-phase clock signal CLXINV. Therefore, the first clocked inverter 141 outputs a negative logic transfer signal P1 to the sampling signal output circuit 150. Further, the even-numbered stage of the shift register 140 includes a third clocked inverter 144 that operates based on the anti-phase clock signal CLXINV, a second inverter 145 that is electrically connected in series to the third clocked inverter 144, And a fourth clocked inverter 146 electrically connected in parallel to the second inverter 145, and the fourth clocked inverter 146 operates based on the clock signal CLX. Therefore, the third clocked inverter 144 outputs the negative logic transfer signal P2 to the sampling signal output circuit 150 at a timing shifted by a half cycle with respect to the transfer signal P1.

  The sampling signal output circuit 150 includes a first NOR circuit 152 and a first NOR circuit for each series to which any one of the second enable signals ENBx1, ENBx2, ENBx3, ENBx4, and any one of the transfer signals P1, P2 are input. And a second NOR circuit 153 for each series to which a positive logic control signal NRG is input. At that time, the transfer signal P1 is input to the two first NOR circuits 152a and 152b to which the second enable signals ENBx1 and ENBx2 are input at adjacent positions among the four first NOR circuits 152, and the transfer signal P2 is 4 Among the first NOR circuits 152, the second enable signals ENBx3 and ENBx4 are input to the two first NOR circuits 152c and 152d that are input at adjacent positions.

  As a result, the transfer signals P1 and P2 are shaped by the first NOR circuit 152 based on the waveforms of the second enable signals ENBx1, ENBx2, ENBx3, and ENBx4 having a narrow pulse width, and the second enable signals ENBx1, ENBx2, The positive logic sampling signals Q1, Q2, Q3, Q4... Qn limited to the pulse widths of ENBx3 and ENBx4 are output to the sampling circuit 103.

  Here, the control signal NRG is input to the second NOR circuit 153 as positive logic. Also, the sampling signals Q1, Q2, Q3, Q4... Qn output from the second NOR circuit 153 are output to the sampling circuit 103 via one NOT circuit 155.

(Main effects of this form)
As described above, in the present embodiment, the first enable signals ENBs1 and ENBs2 are positive logic pulse signals, and the enable signal dividing circuit 130 is connected to the negative logic second enable signals ENBx1, ENBx2, ENBx3, ENBx4 is generated and output to the sampling signal output circuit 150. For this reason, the number of transistors for forming the logic circuit is small as compared with the case where the positive logic first enable signal is used and the NAND circuit and the NOT circuit are used as the enable signal dividing circuit. Therefore, signal delay in the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 and sampling signals Q1, Q2, Q3, Q4,. Therefore, in the sampling circuit 103, timing deviation between the sampling signals Q1, Q2, Q3, Q4... And the image signals VID1 to VID6 can be suppressed, and deterioration in image quality due to such deviation can be suppressed. Can do. Further, since the number of transistors for forming the logic circuit is small, power consumption can be reduced.

  The shift register 140 outputs negative logic transfer signals P1 and P2. The sampling signal output circuit 150 outputs negative logic second enable signals ENBx1, ENBx2, ENBx3 and ENBx4, and negative logic transfer signals P1 and P2. To generate positive logic sampling signals Q1, Q2, Q3, Q4. Therefore, even if the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 are negative logic, the positive logic sampling signals Q1, Q2, Q3, Q4,... Can be generated.

  In this embodiment, the sampling signal output circuit 150 includes the first NOR circuit 152 to which the second enable signals ENBx1, ENBx2, ENBx3, ENBx4 and the transfer signals P1 and P2 are input, and the output signal of the first NOR circuit 152 and the positive signal. And a second NOR circuit 153 to which a logical control signal NRG is input. For this reason, since the number of NOT circuits provided in the sampling signal output circuit 150 can be reduced, signal delay in the sampling signals Q1, Q2, Q3, Q4. Therefore, in the sampling circuit 103, timing deviations between the sampling signals Q1, Q2, Q3, Q4... And the image signals VID1 to VID6 can be suppressed, and deterioration in image quality due to such deviations can be suppressed. it can.

[Other electro-optical devices]
In the above-described embodiment, the liquid crystal device has been described as an example of the electro-optical device, but the present invention is not limited to this, and an organic electroluminescence display device, a plasma display, an FED (Field Emission Display), an SED (Surface-) The present invention may be applied to electro-optical devices such as a Conduction Electron-Emitter Display (LED), an LED (light emitting diode) display device, and an electrophoretic display device.

[Example of mounting on electronic devices]
(Configuration example of projection display device and optical unit)
FIG. 9 is a schematic configuration diagram of a projection display device (electronic device) and an optical unit to which the present invention is applied.

  A projection display device 110 shown in FIG. 9 is a so-called projection type projection display device that irradiates light onto a screen 111 provided on the viewer side and observes light reflected by the screen 111. The projection display device 110 includes a light source unit 230 including a light source 112, dichroic mirrors 113 and 114, liquid crystal light valves 115 to 117, a projection optical system 118, a cross dichroic prism 119 (synthetic optical system), and a relay. The electro-optical device 100 and the cross dichroic prism 119 constitute an optical unit 200.

  The light source 112 is composed of an ultrahigh pressure mercury lamp that supplies light including red light R, green light G, and blue light B. The dichroic mirror 113 is configured to transmit the red light R from the light source 112 and reflect the green light G and the blue light B. The dichroic mirror 114 is configured to transmit the blue light B and reflect the green light G out of the green light G and the blue light B reflected by the dichroic mirror 113. Thus, the dichroic mirrors 113 and 114 constitute a color separation optical system that separates the light emitted from the light source 112 into red light R, green light G, and blue light B.

  Here, between the dichroic mirror 113 and the light source 112, an integrator 121 and a polarization conversion element 122 are arranged in order from the light source 112. The integrator 121 is configured to uniformize the illuminance distribution of the light emitted from the light source 112. Further, the polarization conversion element 122 is configured to change the light from the light source 112 into polarized light having a specific vibration direction such as s-polarized light.

  The liquid crystal light valve 115 is a transmissive liquid crystal device that modulates red light transmitted through the dichroic mirror 113 and reflected by the reflection mirror 123 in accordance with an image signal. The liquid crystal light valve 115 includes a λ / 2 phase difference plate 115a, a first polarizing plate 115b, an electro-optical device 100 (red liquid crystal panel 100R), and a second polarizing plate 115d. Here, the red light R incident on the liquid crystal light valve 115 remains as s-polarized light because the polarization of the light does not change even if it passes through the dichroic mirror 113.

  The λ / 2 phase difference plate 115a is an optical element that converts s-polarized light incident on the liquid crystal light valve 115 into p-polarized light. The first polarizing plate 115b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (the red liquid crystal panel 100R) is configured to convert p-polarized light into s-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. Furthermore, the second polarizing plate 115d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Therefore, the liquid crystal light valve 115 is configured to modulate the red light R according to the image signal and emit the modulated red light R toward the cross dichroic prism 119.

  Note that the λ / 2 phase difference plate 115a and the first polarizing plate 115b are disposed in contact with a light-transmitting glass plate 115e that does not convert the polarization, and the λ / 2 phase difference plate 115a and the first polarization plate 115b are arranged in contact with each other. It is possible to avoid the polarizing plate 115b from being distorted by heat generation.

  The liquid crystal light valve 116 is a transmissive liquid crystal device that modulates green light G reflected by the dichroic mirror 114 after being reflected by the dichroic mirror 113 in accordance with an image signal. Similar to the liquid crystal light valve 115, the liquid crystal light valve 116 includes a first polarizing plate 116b, an electro-optical device 100 (green liquid crystal panel 100G), and a second polarizing plate 116d. Green light G incident on the liquid crystal light valve 116 is s-polarized light that is reflected by the dichroic mirrors 113 and 114 and then incident. The first polarizing plate 116b is a polarizing plate that blocks p-polarized light and transmits s-polarized light. The electro-optical device 100 (green liquid crystal panel 100G) is configured to convert s-polarized light into p-polarized light (circularly polarized light or elliptically polarized light in the case of halftone) by modulation according to an image signal. The second polarizing plate 116d is a polarizing plate that blocks s-polarized light and transmits p-polarized light. Therefore, the liquid crystal light valve 116 is configured to modulate the green light G in accordance with the image signal and emit the modulated green light G toward the cross dichroic prism 119.

  The liquid crystal light valve 117 is a transmissive liquid crystal device that modulates the blue light B reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114 and then through the relay system 220 in accordance with an image signal. Like the liquid crystal light valves 115 and 116, the liquid crystal light valve 117 includes a λ / 2 phase difference plate 117a, a first polarizing plate 117b, an electro-optical device 100 (blue liquid crystal panel 100B), and a second polarizing plate 117d. I have. Here, the blue light B incident on the liquid crystal light valve 117 is reflected by two reflecting mirrors 125a and 125b (to be described later) of the relay system 220 after being reflected by the dichroic mirror 113 and transmitted through the dichroic mirror 114. It has become.

  The λ / 2 phase difference plate 117a is an optical element that converts s-polarized light incident on the liquid crystal light valve 117 into p-polarized light. The first polarizing plate 117b is a polarizing plate that blocks s-polarized light and transmits p-polarized light. The electro-optical device 100 (blue liquid crystal panel 100B) is configured to convert p-polarized light to s-polarized light (circularly polarized light or elliptically polarized light if it is a halftone) by modulation according to an image signal. Furthermore, the second polarizing plate 117d is a polarizing plate that blocks p-polarized light and transmits s-polarized light. Therefore, the liquid crystal light valve 117 is configured to modulate the blue light B according to the image signal and emit the modulated blue light B toward the cross dichroic prism 119. The λ / 2 phase difference plate 117a and the first polarizing plate 117b are arranged in contact with the glass plate 117e.

  The relay system 220 includes relay lenses 124a and 124b and reflection mirrors 125a and 125b. The relay lenses 124a and 124b are provided to prevent light loss due to the long optical path of the blue light B. Here, the relay lens 124a is disposed between the dichroic mirror 114 and the reflection mirror 125a. The relay lens 124b is disposed between the reflection mirrors 125a and 125b. The reflection mirror 125a is disposed so as to reflect the blue light B transmitted through the dichroic mirror 114 and emitted from the relay lens 124a toward the relay lens 124b. The reflection mirror 125b is disposed so as to reflect the blue light B emitted from the relay lens 124b toward the liquid crystal light valve 117.

  The cross dichroic prism 119 is a color combining optical system in which two dichroic films 119a and 119b are arranged orthogonally in an X shape. The dichroic film 119a is a film that reflects blue light B and transmits green light G, and the dichroic film 119b is a film that reflects red light R and transmits green light G. Therefore, the cross dichroic prism 119 is configured to combine the red light R, the green light G, and the blue light B modulated by each of the liquid crystal light valves 115 to 117 and emit the resultant light toward the projection optical system 118. Yes.

  Note that light incident on the cross dichroic prism 119 from the liquid crystal light valves 115 and 117 is s-polarized light, and light incident on the cross dichroic prism 119 from the liquid crystal light valve 116 is p-polarized light. Thus, by making the light incident on the cross dichroic prism 119 into different types of polarized light, the light incident from the liquid crystal light valves 115 to 117 in the cross dichroic prism 119 can be synthesized. Here, in general, the dichroic films 119a and 119b are excellent in s-polarized reflection transistor characteristics. For this reason, red light R and blue light B reflected by the dichroic films 119a and 119b are s-polarized light, and green light G transmitted through the dichroic films 119a and 119b is p-polarized light. The projection optical system 118 has a projection lens (not shown) and is configured to project the light combined by the cross dichroic prism 119 onto the screen 111.

(Other projection display devices)
In the projection type display device, the transmission type electro-optical device 100 is used. However, the reflection type electro-optical device 100 may be used to form the projection type display device. In the projection display device, an LED light source that emits light of each color may be used as the light source unit, and the color light emitted from the LED light source may be supplied to another liquid crystal device. .

(Other electronic devices)
As for the electro-optical device 100 to which the present invention is applied, in addition to the electronic devices described above, mobile phones, personal digital assistants (PDAs), digital cameras, liquid crystal televisions, car navigation devices, video phones, POS terminals In addition, it may be used as a direct-view display device in an electronic device such as a device provided with a touch panel.

6a ... Data line, 9a ... Pixel electrode, 10 ... Element substrate, 10a ... Image display area, 100 ... Electro-optical device, 100a ... Pixel, 101 ... Data line drive circuit, 102 ... Terminal, 103..Sampling circuit 104..Scanning line driving circuit 108..Switching element 109 ... Selection signal line 110 ... Projection type display device 120 ... Selection circuit 130 ... Enable signal dividing circuit 131 131a to 131d, NOR circuit, 132, 132a to 132d, NAND circuit, 140, shift register, 141, first clocked inverter, 142, first inverter, 143, second clocked inverter, 144 ··· Third clocked inverter, 145 ··· Second inverter, 146 ··· Fourth clocked inverter 150..Sampling signal output circuit, 152, 152a to 152d..First NOR circuit, 153..Second NOR circuit, 154,155,156..NOT circuit, 158,158a to 158d..NAND circuit, 159..AND Circuits 171, 172, N-type field effect transistors, 173, 174, P-type field effect transistors, 200, Optical unit, 230, Light source, CLX, Clock signal, CLKINV, Reverse Phase clock signal, DX ··· Start pulse, ENBs1, 2 ··· First enable signal, ENBx1 to 4 ··· Second enable signal, LVID1 to 6 ·· Image signal line, NRG ··· Control signal, P1, P2 to Pn / 12 ・ ・ Transfer signal, Q1, Q2 to Qn / 6 ・ ・ Sampling signal, S1, S2 to Sn ・ ・ Image signal

Claims (6)

On one side of the element substrate,
Multiple data lines,
A plurality of scanning lines extending in a direction intersecting with the plurality of data lines;
A plurality of pixels provided corresponding to each intersection of the data line and the scanning line;
A shift register that sequentially outputs transfer signals from each of the plurality of stages;
An enable signal dividing circuit that divides a first enable signal input via a terminal of the element substrate to generate a plurality of second enable signals having a pulse width narrower than a pulse width of the transfer signal;
A sampling signal output circuit that shapes the transfer signal based on the second enable signal for each of a plurality of series and outputs a sampling signal in which the pulse width of the transfer signal is limited to the pulse width of the second enable signal;
A sampling circuit that samples an image signal based on the sampling signal and supplies the image signal to the data line;
Have
The first enable signal is a negative logic pulse signal,
The electro-optical device, wherein the enable signal dividing circuit generates a positive enable second enable signal by a NOR circuit and outputs the second enable signal to the sampling signal output circuit. The shift register outputs the positive logic transfer signal,
The electro-optical device according to claim 1, wherein the sampling signal output circuit generates the positive logic sampling signal based on the second enable signal and the transfer signal. On one side of the element substrate,
Multiple data lines,
A plurality of scanning lines extending in a direction intersecting with the plurality of data lines;
A plurality of pixels provided corresponding to each intersection of the data line and the scanning line;
A shift register that sequentially outputs transfer signals from each of the plurality of stages;
An enable signal dividing circuit that divides a first enable signal input via a terminal of the element substrate to generate a plurality of second enable signals having a pulse width narrower than a pulse width of the transfer signal;
A sampling signal output circuit that shapes the transfer signal based on the second enable signal for each of a plurality of series and outputs a sampling signal in which the pulse width of the transfer signal is limited to the pulse width of the second enable signal;
A sampling circuit that samples an image signal based on the sampling signal and supplies the image signal to the data line;
Have
The first enable signal is a positive logic pulse signal;
The electro-optical device, wherein the enable signal dividing circuit generates a negative enable second enable signal by a NAND circuit and outputs the second enable signal to the sampling signal output circuit. The shift register outputs the transfer signal of negative logic,
4. The electro-optical device according to claim 3, wherein the sampling signal output circuit generates the positive logic sampling signal based on the second enable signal and the transfer signal. 5.   The sampling signal output circuit includes a first NOR circuit to which the second enable signal and the transfer signal are input, and a second NOR circuit to which an output signal of the first NOR circuit and a positive logic control signal are input. The electro-optical device according to claim 4.   An electronic apparatus comprising the electro-optical device according to claim 1.

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