JP2016174055A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with reduced wiring inductance and reduced wiring resistance.SOLUTION: A semiconductor device according to an embodiment comprises: a case that has a frame section including a first portion and a second portion, and a bottom section; first wiring that has a first wiring section encapsulated by the first portion and having a first external terminal, and a second wiring section encapsulated by the second portion and having a first terminal; second wiring that has a third wiring section encapsulated by the first portion and having a second external terminal, and a fourth wiring section encapsulated by the second portion and having a fourth terminal adjacent to the first terminal; a first semiconductor element provided on the bottom section, and that has a first electrode at the bottom section side, and a second electrode at an opposite side to the bottom section, the first electrode being electrically connected with the first terminal; and a fourth semiconductor element provided on the bottom section, and that has a seventh electrode at the bottom section side, and an eighth electrode at an opposite side to the bottom section, the seventh electrode being electrically connected with the second electrode, and the eighth electrode being electrically connected with the fourth terminal.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  In a semiconductor device used for switching in applications such as power control, it is necessary to increase the speed of the semiconductor element in order to reduce the switching loss of the semiconductor element provided therein. The surge voltage ΔV when the semiconductor element is turned off is represented by ΔV = −di / dt × Ls (di / dt: hourly current change rate, Ls: wiring inductance).

  However, the rate of change in current (di / dt) in the above equation increases as the speed of the semiconductor element increases. As a result, the surge voltage ΔV increases as the speed of the semiconductor element increases. When the surge voltage ΔV exceeds a predetermined voltage, the semiconductor element may be destroyed. Accordingly, in order to reduce the surge voltage ΔV, how to reduce Ls is important. On the other hand, in such a semiconductor device, there is a case where wiring is routed in the semiconductor device and wiring resistance is increased. When the wiring resistance increases, energy loss and heat generation in the semiconductor device may be caused.

  Thus, in a semiconductor device used for switching, it is desirable that the wiring inductance and wiring resistance be reduced.

Japanese Patent No. 5555206

  The problem to be solved by the present invention is to provide a semiconductor device with reduced wiring inductance and wiring resistance.

  The semiconductor device according to the embodiment includes a first portion extending in a first direction and a second direction that intersects the first direction, and the length in the second direction is the first portion in the first direction. A case having a frame portion including a second portion longer than the length of the one portion, and a bottom portion connected to the frame portion; a first wiring sealed by the first portion and having a first external terminal; And a first wiring having a first terminal which is sealed by the second part and has a first terminal extending from the frame part to the inside of the frame part, and sealed by the first part A third wiring portion that is stopped and has a second external terminal; and a fourth terminal that is sealed by the second portion, extends from the frame portion to the inside of the frame portion, and is adjacent to the first terminal. A second wiring having a fourth wiring portion; provided on the bottom portion; on the bottom portion side; A first semiconductor element having a first electrode disposed on the opposite side of the bottom, and a first semiconductor element electrically connected to the first terminal; and the bottom A seventh electrode provided on the bottom side, and an eighth electrode provided on the opposite side of the bottom, and the seventh electrode is electrically connected to the second electrode. A fourth semiconductor element connected, wherein the eighth electrode is electrically connected to the fourth terminal.

FIG. 1A is a schematic plan view showing the main part of the semiconductor device according to the first embodiment, and FIG. 1B is a schematic view at a position along the line A1-A2 of FIG. FIG. 1C is a schematic cross-sectional view at a position along line B1-B2 in FIG. 2A and 2B are enlarged plan views of the semiconductor device according to the first embodiment, and FIG. 2C is an equivalent circuit of a main part of the semiconductor device according to the first embodiment. FIG. FIG. 3A is a schematic perspective view showing the wiring sealed in a part of the resin case of the semiconductor device according to the first embodiment, and FIG. 3B is the semiconductor according to the first embodiment. It is a typical side view showing the wiring sealed by a part of resin case of an apparatus. It is a schematic diagram showing the waveform of the voltage and current at the time of turn-off in which an IGBT element shifts from an on state to an off state. FIG. 5A is a schematic plan view of a semiconductor device according to a reference example, and FIG. 5B is an equivalent circuit diagram of the semiconductor device according to the reference example. FIG. 6A is a diagram illustrating an example of a current flowing in the semiconductor device according to the reference example, and FIG. 6B is a diagram illustrating an example of a current flowing in the semiconductor device according to the first embodiment. is there. FIG. 7A and FIG. 7B are schematic diagrams for explaining inductance canceling by magnetic coupling. FIG. 8A and FIG. 8B are a schematic diagram and a table for explaining the wiring resistance of the semiconductor device according to the reference example. FIG. 9A and FIG. 9B are a schematic diagram and a table for explaining the wiring resistance of the semiconductor device according to the first embodiment. FIG. 10A is a schematic plan view showing the main part of the semiconductor device according to the second embodiment, and FIG. 10B is an equivalent circuit diagram of the semiconductor device according to the second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate.

(First embodiment)
FIG. 1A is a schematic plan view showing the main part of the semiconductor device according to the first embodiment, and FIG. 1B is a schematic view at a position along the line A1-A2 of FIG. FIG. 1C is a schematic cross-sectional view at a position along line B1-B2 in FIG.

  2A and 2B are enlarged plan views of the semiconductor device according to the first embodiment, and FIG. 2C is an equivalent circuit of a main part of the semiconductor device according to the first embodiment. FIG.

  FIG. 3A is a schematic perspective view showing the wiring sealed in a part of the case of the semiconductor device according to the first embodiment, and FIG. 3B is the semiconductor device according to the first embodiment. It is a typical side view showing the wiring sealed by a part of case.

  A semiconductor device 1 shown in FIGS. 1A to 1C includes a case 100, a first wiring (hereinafter, for example, a P-side wiring 101), and a second wiring (hereinafter, for example, an N-side wiring 102). A first electrode layer (hereinafter, for example, electrode layer 111), a second electrode layer (hereinafter, for example, electrode layer 112), a third electrode layer (hereinafter, for example, electrode layer 113), and a first semiconductor An element (hereinafter, for example, semiconductor element 121), a second semiconductor element (hereinafter, for example, semiconductor element 122), a third semiconductor element (hereinafter, for example, semiconductor element 123), and a fourth electrode layer (hereinafter, for example, for example) , Electrode layer 114), fifth electrode layer (hereinafter, for example, electrode layer 115), sixth electrode layer (hereinafter, for example, electrode layer 116), and fourth semiconductor element (hereinafter, for example, semiconductor element 124). And a fifth semiconductor element (hereinafter, for example, a semiconductor element 125 Comprising the sixth semiconductor device (hereinafter, for example, a semiconductor device 126) and, the. The semiconductor device 1 may be called a semiconductor package, a power module, or a semiconductor module. The semiconductor device 1 is a 6 in 1 package including six switching elements in one module.

  The semiconductor elements 121 to 126 are switching elements. For example, the semiconductor elements 121 to 126 are IGBT (Insulated Gate Bipolar Transistor) elements, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) elements, and the like. Hereinafter, the semiconductor elements 121 to 126 will be described using an IGBT element as an example.

  The case 100 has a resin frame portion 100f and a bottom portion 100b connected to the frame portion 100f. The bottom 100b includes a metal plate such as copper (Cu). Case 100 further has a lid (not shown). The frame portion 100f includes a first portion 100fa and a second portion 100fb. The first portion 100fa extends in the first direction (hereinafter, for example, the X direction). The second portion 100fb extends in a second direction that intersects the X direction (hereinafter, for example, the Y direction). The length of the second portion 100fb in the Y direction is longer than the length of the first portion 100fa in the X direction.

  The size of the case 100 is, for example, a length in the X direction of 60 mm and a length in the Y direction of 152 mm. Further, the inside of the case 100 may be filled with a resin such as silicone.

  The P-side wiring 101 includes a first wiring part 101x extending in the X direction and a second wiring part 101y extending in the Y direction. The P-side wiring 101 is a P-side bus bar. The first wiring portion 101x of the P-side wiring 101 is sealed with the first portion 100fa. The second wiring portion 101y of the P-side wiring 101 is sealed with the second portion 100fb.

  Here, in this embodiment, “A is sealed with B” means that at least a part of A is sealed with B.

  The second wiring portion 101y of the P-side wiring 101 has a first terminal 101a, a second terminal 101b, and a third terminal 101c. The first terminal 101a, the second terminal 101b, and the third terminal 101c are arranged in the Y direction. The second terminal 101b is located between the first terminal 101a and the third terminal 101c in the Y direction. The first terminal 101a, the second terminal 101b, and the third terminal 101c extend in the X direction. The first terminal 101a, the second terminal 101b, and the third terminal 101c extend from the frame part 100f to the inside of the frame part 100f.

  The N-side wiring 102 is separated from the P-side wiring 101. For example, the P-side wiring 101 is separated from the N-side wiring 102 in a third direction (hereinafter, for example, the Z direction) that intersects the Y direction and the X direction.

  The N-side wiring 102 includes a third wiring portion 102x extending in the X direction and a fourth wiring portion 102y extending in the Y direction. The N-side wiring 102 is an N-side bus bar. The third wiring portion 102x of the N-side wiring 102 is sealed with the first portion 100fb. The fourth wiring portion 102y of the N-side wiring 102 is sealed with the second portion 100fb.

  The fourth wiring portion 102y of the N-side wiring 102 includes a fourth terminal 102a, a fifth terminal 102b, and a sixth terminal 102c. The fourth terminal 102a, the fifth terminal 102b, and the sixth terminal 102c are arranged in the Y direction. The fifth terminal 102b is located between the fourth terminal 102a and the sixth terminal 102c in the Y direction. The fourth terminal 102a, the fifth terminal 102b, and the sixth terminal 102c extend in the X direction. The fourth terminal 102a, the fifth terminal 102b, and the sixth terminal 102c extend from the frame portion 100f to the inside of the frame portion 100f.

  For example, when the semiconductor device 1 is viewed from the top, that is, viewed from the Z direction, the fourth terminal 102a is adjacent to the first terminal 101a in the Y direction. The fifth terminal 102b is adjacent to the second terminal 101b in the Y direction. The sixth terminal 102c is adjacent to the third terminal 101c in the Y direction. Here, “adjacent” does not mean directly contacting, but means adjoining in a non-contact state. Further, “adjacent” is used to mean “close” as close as possible in a non-contact state.

  3A and 3B show the frame portion 100f, the P-side wiring 101, the N-side wiring 102, and the AC terminal 140U in the vicinity of the first terminal 101a and the fourth terminal 102a.

  The P-side wiring 101 is provided above the N-side wiring 102. The second wiring part 101y of the P-side wiring 101 and the fourth wiring part 102y of the N-side wiring 102 are sealed with a frame part 100f. In the X direction, the first terminal 101a extends from the second wiring portion 101y. In the X direction, the fourth terminal 102a extends from the fourth wiring portion 102y. Since a part of the frame portion 100f is interposed between the P-side wiring 101 and the N-side wiring 102, insulation between the P-side wiring 101 and the N-side wiring 102 is maintained.

  In the semiconductor device 1, the P-side wiring 101 and the N-side wiring 102 are arranged vertically, the P-side wiring 101 and the N-side wiring 102 are accommodated in the case 100, and a plurality of semiconductor elements It is arranged sideways. The P-side wiring 101 and the N-side wiring 102 include, for example, copper (Cu).

  As shown in FIGS. 1B and 1C, an insulating layer 100 d is provided on the bottom 100 b of the case 100. A base substrate including a bottom 100b that is a metal plate and an insulating layer 100d is a DBC (Direct Bonded Copper) substrate.

  As shown in FIG. 1A, the electrode layer 111 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 111 is electrically connected to the first terminal 101a via the wire W11. The wire of the embodiment includes, for example, aluminum (Al), gold (Au), and the like.

  The electrode layer 112 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 112 is electrically connected to the second terminal 101b via the wire W12.

  The electrode layer 113 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 113 is electrically connected to the third terminal 101c through the wire W13.

  The electrode layer 111, the electrode layer 112, and the electrode layer 113 are arranged in the Y direction in this order. Each of the electrode layer 111, the electrode layer 112, and the electrode layer 113 contains copper (Cu). Each shape of the electrode layer 111, the electrode layer 112, and the electrode layer 113 in the XY plane is similar, for example, and has the same area.

  As shown in FIG. 1B, the semiconductor element 121 includes a first electrode on the bottom 100b side (hereinafter, for example, a collector electrode 121c) and a side opposite to the collector electrode 121c through the first semiconductor layer 121s. That is, it has the 2nd electrode (henceforth, emitter electrode 121e) on the opposite side to the bottom part 100b. A collector electrode 121c is electrically connected to the electrode layer 111. Hereinafter, the collector electrode of the IGBT is provided on the bottom 110b side, and the emitter electrode 121e is provided on the side opposite to the collector electrode.

  The semiconductor element 122 includes a third electrode (hereinafter, for example, a collector electrode 122c) on the side of the bottom portion 100b and a fourth electrode (on the opposite side to the bottom portion 100b) through the second semiconductor layer 122s (that is, a side opposite to the bottom portion 100b). Hereinafter, for example, an emitter electrode 122e) is included. A collector electrode 122c is electrically connected to the electrode layer 112.

  The semiconductor element 123 includes a fifth electrode (hereinafter, for example, a collector electrode 123c) on the bottom 100b side and a sixth electrode (on the opposite side to the bottom 100b) via the third semiconductor layer 123s. Hereinafter, for example, an emitter electrode 123e) is included. A collector electrode 123c is electrically connected to the electrode layer 113.

  Further, as illustrated in FIG. 2C, the semiconductor element 121 includes a gate electrode G1. The semiconductor element 122 has a gate electrode G2. The semiconductor element 123 has a gate electrode G3.

  As shown in FIG. 1A, the electrode layer 114 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 114 is electrically connected to the emitter electrode 121e via the wire W14.

  As shown in FIG. 1A, the electrode layer 115 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 115 is electrically connected to the emitter electrode 122e via the wire W15.

  The electrode layer 116 is provided on the bottom 100b of the case 100 via the insulating layer 100d. The electrode layer 116 is electrically connected to the emitter electrode 123e via the wire W16.

  The electrode layer 114, the electrode layer 115, and the electrode layer 116 are arranged in the Y direction in this order. Each of the electrode layer 114, the electrode layer 115, and the electrode layer 116 contains copper (Cu). A part of the electrode layer 114 and a part of the electrode layer 111 are arranged in the X direction. A part of the electrode layer 115 and a part of the electrode layer 112 are arranged in the X direction. A part of the electrode layer 116 and a part of the electrode layer 113 are arranged in the X direction. Each shape of the electrode layer 114, the electrode layer 115, and the electrode layer 116 in the XY plane is similar, for example, and has the same area.

  In addition, an electrode layer 117, an electrode layer 118, and an electrode layer 119 are provided on the bottom 100b of the case 100 via an insulating layer 100d. The electrode layer 117, the electrode layer 118, and the electrode layer 119 are arranged in the Y direction in this order. Each of the electrode layer 117, the electrode layer 118, and the electrode layer 119 contains copper (Cu). The shapes of the electrode layer 117, the electrode layer 118, and the electrode layer 119 in the XY plane are similar, for example, and have the same area. Each of the electrode layer 117, the electrode layer 118, and the electrode layer 119 is an electrode layer serving as a relay point for electrical connection, and may be removed as appropriate. In the present embodiment, the embodiment will be described on the assumption that the electrode layer 117, the electrode layer 118, and the electrode layer 119 exist.

  A part of the electrode layer 114, a part of the electrode layer 111, and the electrode layer 117 are arranged in the X direction. A part of the electrode layer 115, a part of the electrode layer 112, and the electrode layer 118 are arranged in the X direction. A part of the electrode layer 116, a part of the electrode layer 113, and the electrode layer 119 are arranged in the X direction.

  As shown in FIG. 1C, the semiconductor element 124 includes a seventh electrode (hereinafter, for example, a collector electrode 124c) on the bottom 100b side and an opposite side through the fourth semiconductor layer 124s, that is, the bottom 100b. And an eighth electrode (hereinafter, for example, an emitter electrode 124e) provided on the opposite side. A collector electrode 124 c is electrically connected to the electrode layer 114. The emitter electrode 124e is electrically connected to the fourth terminal 102a through the wire W21, the electrode layer 117, and the wire W22.

  The semiconductor element 125 includes a ninth electrode (hereinafter, for example, a collector electrode 125c) on the bottom 100b side and a tenth electrode (on the opposite side to the bottom 100b) via the fifth semiconductor layer 125s. Hereinafter, for example, an emitter electrode 125e) is included. A collector electrode 125c is electrically connected to the electrode layer 115. The emitter electrode 125e is electrically connected to the fifth terminal 102b through the wire W23, the electrode layer 118, and the wire W24.

  The semiconductor element 126 includes an eleventh electrode (hereinafter, for example, a collector electrode 126c) on the side of the bottom 100b and a twelfth electrode (on the opposite side of the bottom 100b) via the sixth semiconductor layer 126s. Hereinafter, for example, an emitter electrode 126e) is included. A collector electrode 126c is electrically connected to the electrode layer 116. The emitter electrode 126e is electrically connected to the sixth terminal 102c through the wire W25, the electrode layer 119, and the wire W26.

  Further, as illustrated in FIG. 2C, the semiconductor element 124 includes a gate electrode G4. The semiconductor element 125 has a gate electrode G5. The semiconductor element 126 has a gate electrode G6.

  Further, as illustrated in FIGS. 1A and 1C, a semiconductor element 131 is provided on the electrode layer 111. The semiconductor element 131 is, for example, an FWD (Free Wheeling Diode) element. The semiconductor element 131 has a cathode electrode 131c on the bottom 100b side and an anode electrode 131a provided on the opposite side via the semiconductor layer 131s. A cathode electrode 131 c is electrically connected to the electrode layer 111. The anode electrode 131a is electrically connected to the electrode layer 114 via the wire W31.

  A semiconductor element 132 is provided on the electrode layer 112. The semiconductor element 132 is, for example, an FWD element. The semiconductor element 132 includes a cathode electrode 132c on the bottom 100b side and an anode electrode 132a provided on the opposite side through the semiconductor layer 132s. A cathode electrode 132c is electrically connected to the electrode layer 112. The anode electrode 132a is electrically connected to the electrode layer 115 via the wire W32.

  A semiconductor element 133 is provided on the electrode layer 113. The semiconductor element 133 is, for example, an FWD element. The semiconductor element 133 includes a cathode electrode 133c on the bottom 100b side and an anode electrode 133a provided on the opposite side through the semiconductor layer 133s. A cathode electrode 133c is electrically connected to the electrode layer 113. The anode electrode 133a is electrically connected to the electrode layer 116 through the wire W33.

  A semiconductor element 134 is provided on the electrode layer 114. The semiconductor element 134 is, for example, an FWD element. The semiconductor element 134 has a cathode electrode 134c on the bottom 100b side and an anode electrode 134a provided on the opposite side through the semiconductor layer 134s. A cathode electrode 134c is electrically connected to the electrode layer 114. The anode electrode 134a is electrically connected to the fourth terminal 102a via the wire W34, the electrode layer 117, and the wire W22.

  A semiconductor element 135 is provided on the electrode layer 115. The semiconductor element 135 is, for example, an FWD element. The semiconductor element 135 has a cathode electrode 135c on the bottom 100b side and an anode electrode 135a provided on the opposite side through the semiconductor layer 135s. A cathode electrode 135c is electrically connected to the electrode layer 115. The anode electrode 135a is electrically connected to the fifth terminal 102b via the wire W35, the electrode layer 118, and the wire W24.

  A semiconductor element 136 is provided on the electrode layer 116. The semiconductor element 136 is, for example, an FWD element. The semiconductor element 136 includes a cathode electrode 136c on the bottom 100b side and an anode electrode 136a provided on the opposite side through the semiconductor layer 136s. A cathode electrode 136 c is electrically connected to the electrode layer 116. The anode electrode 136a is electrically connected to the sixth terminal 102c through the wire W36, the electrode layer 119, and the wire W26.

  The second portion 100fb of the case 100 seals a part of each of the AC terminal 140U, the AC terminal 140V, and the AC terminal 140W. A part of each of the AC terminal 140U, the AC terminal 140V, and the AC terminal 140W extends from the second portion 100fb in the X direction. The AC terminal 140U, the AC terminal 140V, and the AC terminal 140W are arranged in this order in the Y direction. When viewed from the Z direction, the AC terminal 140U is provided beside the first terminal 101a and the fourth terminal 102a, the AC terminal 140V is provided beside the second terminal 101b and the fifth terminal 102b, and the AC terminal 140W is It is provided beside the third terminal 101c and the sixth terminal 102c.

  The AC terminal 140U is electrically connected to the electrode layer 114 through the wire W40U. The AC terminal 140V is electrically connected to the electrode layer 115 via the wire W40V. The AC terminal 140W is electrically connected to the electrode layer 116 via the wire W40W.

  The first wiring portion 101x of the P-side wiring 101 has a first external terminal (hereinafter, for example, a P-side DC external terminal 101p). The third wiring portion 102x of the N-side wiring 102 has a second external terminal (hereinafter, for example, an N-side DC external terminal 102n). A part of the P-side DC external terminal 101p and a part of the N-side DC external terminal 102n are sealed by the first part 100fa. The P-side DC external terminal 101p and the N-side DC external terminal 102n are arranged in the X direction. In the X direction, the length of the first wiring portion 101x is shorter than the length of the third wiring portion 102x. The position of the P-side DC external terminal 101p is closer to the second wiring part 101y and the fourth wiring part 102y than the position of the N-side DC external terminal 102n. The P-side DC external terminal 101p and the N-side DC external terminal 102n extend from the case 100 in the Z direction.

  In the semiconductor device 1, the distance between the first terminal 101 a and the semiconductor element 121 is the same as the distance between the second terminal 101 b and the semiconductor element 122. Here, the distance between members in the embodiment is defined as the shortest distance among the straight lines connecting the members.

  The distance between the third terminal 101 c and the semiconductor element 123 is the same as the distance between the second terminal 101 b and the semiconductor element 122.

  The distance between the fourth terminal 102 a and the semiconductor element 124 is the same as the distance between the fifth terminal 102 b and the semiconductor element 125.

  The distance between the sixth terminal 102 c and the semiconductor element 126 is the same as the distance between the fifth terminal 102 b and the semiconductor element 125.

  The distance between the semiconductor element 121 and the semiconductor element 124 is the same as the distance between the semiconductor element 122 and the semiconductor element 125.

  The distance between the semiconductor element 123 and the semiconductor element 126 is the same as the distance between the semiconductor element 122 and the semiconductor element 125.

  In the semiconductor device 1, at least a part of the semiconductor element 124 is disposed on the region 100 ba between the N-side wiring 102 and the semiconductor element 121 in the bottom 100 b of the case 100 when viewed from the Z direction.

  As viewed from the Z direction, at least a part of the semiconductor element 125 is disposed on the region 100bb between the N-side wiring 102 and the semiconductor element 122 at the bottom 100b of the case 100.

  As viewed from the Z direction, at least a part of the semiconductor element 126 is disposed on the region 100bc between the N-side wiring 102 and the semiconductor element 123 at the bottom 100b of the case 100.

Such a semiconductor device 1 is, for example, a three-phase inverter device as shown in FIG. In the semiconductor device 1, a DC voltage is input between the P-side DC external terminal 101p and the N-side DC external terminal 102n, and the application voltage, application time, and the like to the respective gate electrodes G1 to G6 are controlled. AC voltage is output from AC terminals 140U, 140V, and 140W.
FIG. 2A shows a plan view of one phase of the three-phase inverter device. FIG. 2 (a) shows the leftmost one phase of FIG. 1 (a).
When viewed from the Z direction, the distance L1 between the first terminal 101a and the fourth terminal 102a in the Y direction is not less than 0.8 mm and not more than 20 mm. Each planar shape of the electrode layer 111 and the electrode layer 114 is a rectangle. Each of the electrode layer 111 and the electrode layer 114 has a portion extending in the X direction and a portion extending in the Y direction. In the Y direction, at least part of the electrode layer 114 is aligned with at least part of the electrode layer 111.
FIG. 2A shows a one-phase plan view of the three-phase inverter device. In the semiconductor device 1, the other two-phase plan structure is similar to the plan structure shown in FIG. It has become.
That is, as viewed from the Z direction, the distance between the second terminal 101b and the fifth terminal 102b in the second direction is not less than 0.8 mm and not more than 20 mm.
In the Y direction, at least part of the electrode layer 115 is aligned with at least part of the electrode layer 112. In the Y direction, at least part of the electrode layer 116 is aligned with at least part of the electrode layer 113.
Further, the planar shapes of the electrode layer 111 and the electrode layer 114 are not limited to the shape shown in FIG. For example, as illustrated in FIG. 2B, the electrode layer 111 may extend in the X direction. The electrode layer 114 may be provided along the electrode layer 111 extending in the X direction. Note that when viewed from the Z direction, the distance between the third terminal 101c and the sixth terminal 102c in the second direction is not less than 0.8 mm and not more than 20 mm.

The operation of the semiconductor device 1 will be described.
FIG. 4 is a schematic diagram showing waveforms of voltage and current at the turn-off time when the IGBT element shifts from the on state to the off state.

  FIG. 4 shows changes in the time axis of the voltage Vce between the collector electrode and the emitter electrode and the current Ic flowing between the collector electrode and the emitter electrode in the IBGT element at the time of turn-off.

  The switching loss of the IGBT element decreases as the switching speed increases. However, when the IGBT element is switched at high speed, the surge voltage of the IGBT element is affected by the wiring inductance of the semiconductor device in which the IGBT element is incorporated.

For example, the surge voltage ΔV at the time of turn-off is represented by the product of the current change rate (di / dt) and the wiring inductance (Ls). That is,
ΔV = − (di / dt) × Ls (1)
It is. If the surge voltage ΔV exceeds the maximum rated voltage of the IGBT element, the IGBT element may be destroyed.

  As the speed of the IGBT element increases, the slope of (di / dt) increases. This increases the current change rate (di / dt). That is, the surge voltage ΔV increases as the speed of the IGBT element increases. However, the surge voltage ΔV can be lowered by reducing the wiring inductance (Ls).

  FIG. 5A is a schematic plan view of a semiconductor device according to a reference example, and FIG. 5B is an equivalent circuit diagram of the semiconductor device according to the reference example.

  In the semiconductor device 5 according to the reference example, the same case 100 as that of the semiconductor device 1 is used. The semiconductor device 5 is a three-phase inverter device. In the semiconductor device 5, the P-side wiring 101 and the N-side wiring 102 provided in the semiconductor device 1 are not provided. On the bottom 100b of the case 100, an insulating layer 100d is provided. In the description of the reference example, the description of the insulating layer 100d is omitted.

  In the semiconductor device 5, the electrode layer 511 and the electrode layer 514 are arranged in the X direction. The electrode layer 511 and the electrode layer 515 are arranged in the X direction. The electrode layer 513 and the electrode layer 516 are arranged in the X direction. In the semiconductor device 5, the electrode layer 511 is electrically connected to the P-side DC external terminal 101p through the wire W51. The electrode layer 513 is electrically connected to the electrode layer 511 through the wire W52. The electrode layer 511 and the electrode layer 513 are arranged in the Y direction. Note that the electrode layer 513 may be connected to the electrode layer 511 without using the wire W52.

  A collector electrode 121 c of the semiconductor element 121 is electrically connected to the electrode layer 511. A collector electrode 122 c of the semiconductor element 122 is electrically connected to the electrode layer 511. A collector electrode 123 c of the semiconductor element 123 is electrically connected to the electrode layer 513.

  In the semiconductor device 5, an N-side electrode layer 502 a and an N-side electrode layer 502 b are provided on the bottom 100 b of the case 100. The N-side electrode layer 502a and the N-side electrode layer 502b are arranged in the X direction.

  The N-side electrode layer 502a is electrically connected to the N-side DC external terminal 102n through the wire W53. The N-side electrode layer 502b is electrically connected to the N-side electrode layer 502a through the wire W54. Note that the N-side electrode layer 502b may be connected to the N-side electrode layer 502a without using the wire W54.

  The electrode layer 514 is electrically connected to the emitter electrode 121e of the semiconductor element 121 via the wire W55. The electrode layer 515 is electrically connected to the emitter electrode 122e of the semiconductor element 122 via the wire W56. The electrode layer 516 is electrically connected to the emitter electrode 123e of the semiconductor element 123 via the wire W57. The electrode layer 514, the electrode layer 515, and the electrode layer 516 are arranged in the Y direction.

  A collector electrode 124 c of the semiconductor element 124 is electrically connected to the electrode layer 514. The emitter electrode 124e of the semiconductor element 124 is electrically connected to the N-side electrode layer 502a through a wire W58.

  A collector electrode 125 c of the semiconductor element 125 is electrically connected to the electrode layer 515. The emitter electrode 125e of the semiconductor element 125 is electrically connected to the N-side electrode layer 502a through a wire W59.

  A collector electrode 126 c of the semiconductor element 126 is electrically connected to the electrode layer 516. The emitter electrode 126e of the semiconductor element 126 is electrically connected to the N-side electrode layer 502b through the wire W60.

  A semiconductor element 131 is provided on the electrode layer 511. A cathode electrode 131 c of the semiconductor element 131 is electrically connected to the electrode layer 511. The anode electrode 131a of the semiconductor element 131 is electrically connected to the AC terminal 140U via the wire W61, and is electrically connected to the emitter electrode 121e of the semiconductor element 121 via the wire W61.

  A semiconductor element 132 is provided over the electrode layer 511. The cathode layer 132c of the semiconductor element 132 is electrically connected to the electrode layer 511. The anode electrode 132a of the semiconductor element 132 is electrically connected to the AC terminal 140V via the wire W62, and is electrically connected to the emitter electrode 122e of the semiconductor element 122 via the wire W62.

  A semiconductor element 133 is provided over the electrode layer 513. A cathode electrode 133 c of the semiconductor element 133 is electrically connected to the electrode layer 513. The anode electrode 133a of the semiconductor element 133 is electrically connected to the AC terminal 140W via the wire W63, and is electrically connected to the emitter electrode 123e of the semiconductor element 123 via the wire W63.

  A semiconductor element 134 is provided over the electrode layer 514. A cathode electrode 134c of the semiconductor element 134 is electrically connected to the electrode layer 514. The anode electrode 134a of the semiconductor element 134 is electrically connected to the emitter electrode 124e of the semiconductor element 124 via the wire W64.

  A semiconductor element 135 is provided on the electrode layer 515. The cathode layer 135 c of the semiconductor element 135 is electrically connected to the electrode layer 515. The anode electrode 135a of the semiconductor element 135 is electrically connected to the emitter electrode 125e of the semiconductor element 125 via the wire W65.

  A semiconductor element 136 is provided over the electrode layer 516. The cathode layer 136c of the semiconductor element 136 is electrically connected to the electrode layer 516. The anode electrode 136a of the semiconductor element 136 is electrically connected to the emitter electrode 126e of the semiconductor element 126 via the wire W66.

  In the semiconductor device 5, the electrode layer 511 and the electrode layer 513 correspond to the P-side wiring 101 of the semiconductor device 1. Further, the N-side electrode layer 502 a and the N-side electrode layer 502 b correspond to the N-side wiring 102 of the semiconductor device 1. Here, the electrode layers 511 and 513 and the N-side electrode layers 502a and 502b are not arranged vertically. A plurality of electrode layers and a plurality of semiconductor elements are sandwiched between the electrode layers 511 and 513 and the N-side electrode layers 502a and 502b in the X direction.

  FIG. 6A is a diagram illustrating an example of a current flowing in the semiconductor device according to the reference example, and FIG. 6B is a diagram illustrating an example of a current flowing in the semiconductor device according to the first embodiment. is there.

  In the semiconductor device 5 of the reference example shown in FIG. 6A, a current path 5IU, a current path 5IV, and a current path flowing between the P-side DC external terminal 101p and the N-side DC terminal 101n during the operation The current path 5IW is raised. In FIGS. 6A and 6B, the currents flowing from the AC terminals 140U, 140V, and 140W to the external load are not shown.

  Here, the current path 5IV is longer than the current path 5IU, and the current path 5IW is longer than the current path 5IV. Further, for example, when a broken line A is drawn between the P-side DC external terminal 101p and the N-side DC terminal 101n, the area surrounded by the broken line A and the current path 5IV is determined by the broken line A and the current path 5IU. It is larger than the enclosed area. The area surrounded by the broken line A and the current path 5IW is larger than the area surrounded by the broken line A and the current path 5IV.

  On the other hand, in the semiconductor device 1 of the first embodiment shown in FIG. 6B, the P-side DC external terminal 101p has a first terminal 101a, a second terminal 101b, and a third terminal 101c, and an N-side DC terminal. 101n includes a fourth terminal 102a, a fifth terminal 102b, and a sixth terminal 102c.

Therefore, in the semiconductor device 1 of the first embodiment, the current path during operation includes the current path 1IU flowing between the first terminal 101a and the fourth terminal 102a, and the second terminal 101b and the fifth terminal 102b. And a current path 1IW flowing between the third terminal 101c and the sixth terminal 102c.
In the semiconductor device 1, the current path 1IU between the first terminal 101a and the fourth terminal 102a provided in the same frame portion 100f is folded at the bottom portion 100. The current path before being folded back and the current path after being folded back are closer than in the reference example. Similarly, the current path 1IV between the second terminal 101b and the fifth terminal 102b provided in the same frame portion 100f, and between the third terminal 101c and the sixth terminal 102c provided in the same frame portion 100f. The current path 1IW is also folded within the bottom portion 100b.

  Here, in the semiconductor device 1, the lengths of the current path 1IU, the current path 1IV, and the current path 1IW are the same. Further, in the semiconductor device 1, broken lines B are provided between the first terminal 101a and the fourth terminal 102a, between the second terminal 101b and the fifth terminal 102b, and between the third terminal 101c and the sixth terminal 102c. When drawn, the area surrounded by the broken line B and the current path 1IU, the area surrounded by the broken line B and the current path 1IV, and the area surrounded by the broken line B and the current path 1IW are the same. .

  The total of the area surrounded by the broken line B and the current path 1IU, the area surrounded by the broken line B and the current path 1IV, and the area surrounded by the broken line B and the current path 1IW in the semiconductor device 1 is as follows. It is smaller than the total of the area surrounded by the broken line A and the current path 5IV, the area surrounded by the broken line A and the current path 5IU, and the area surrounded by the broken line A and the current path 5IW.

  FIG. 7A and FIG. 7B are schematic diagrams for explaining inductance canceling by magnetic coupling.

For example, when an alternating current flows between the P-side terminal and the N-side terminal, as shown in FIG. 7A, if the area SA surrounded by the broken line A and the current path increases, the periphery of the current path The magnetic flux B ₁ emitted from the magnetic flux B ₁ is separated from the magnetic flux B ₂ opposite to the magnetic flux B ₁ . That is, in the example of FIG. 7 (a), the magnetic flux _{B 1} and the magnetic flux _{B 2} is less likely to cancel each other. Therefore, in the current path shown in FIG. 7A, the wiring inductance becomes high.

That is, in the semiconductor device 5 according to the reference example, the current path 5IV current path 5 IU, and the magnetic flux respectively and the magnetic flux _{B 1} which emits the periphery of the current path 5IW _{B 2} Togazu 7 cancel each other as represented in (a) It becomes difficult. Accordingly, the wiring inductance is increased, and the respective surge voltages (ΔV) of the semiconductor elements 121 to 126 are increased.

On the other hand, as depicted in FIG. 7 (b), the area SB surrounded by a broken line B and the current path becomes small, and approaching the magnetic flux B ₁ and the magnetic flux B ₂ emanating around the current path, the magnetic flux by the magnetic coupling B ₁ and magnetic flux B ₂ can easily cancel each other. Therefore, in the current path shown in FIG. 7B, the wiring inductance is reduced. That is, by adopting the current path shown in FIG. 7B in the semiconductor device, the surge voltage (ΔV) of the IGBT element can be set low.

In the semiconductor device 1 according to the first embodiment, the current path 1 IU, a current path 1IV, and so on represent the magnetic flux _{B 1} and the magnetic flux _{B 2} Togazu 7 (b) emitting the respective periphery of the current path 1IW cancel each other The Accordingly, the wiring inductance is reduced, and the surge voltage (ΔV) of each of the semiconductor elements 121 to 126 is reduced.

  Further, in the semiconductor device 5 according to the reference example, the electrode layer 511 and the electrode layer 513 (corresponding to the P-side wiring 101) are the N-side electrode layer 502a and the N-side electrode layer 502b (corresponding to the N-side wiring 102) in the X direction. is seperated. Therefore, the magnetic fluxes generated around the electrode layer 511 and the electrode layer 513 and the N-side electrode layer 502a and the N-side electrode layer 502b are difficult to cancel each other.

  In contrast, in the semiconductor device 1 according to the first embodiment, the P-side wiring 101 and the N-side wiring 102 overlap in the Z direction. Therefore, the magnetic flux generated around each of the P-side wiring 101 and the N-side wiring 102 can be easily canceled. Thereby, the wiring inductance is further reduced, and the surge voltage (ΔV) of each of the semiconductor elements 121 to 126 is further reduced.

  FIG. 8A and FIG. 8B are a schematic diagram and a table for explaining the wiring resistance of the semiconductor device according to the reference example.

  The wiring resistance in the semiconductor device causes energy loss of the semiconductor device due to the voltage drop. Furthermore, the inside of the apparatus may generate heat due to a voltage drop.

  The wiring resistances shown in FIG. 8A and FIG. 8B approximate the respective resistances of a plurality of wires and set the resistance as R1. Further, the resistance of each of the plurality of electrode layers provided on the insulating layer 100d is approximated to be a resistance R2.

  When the resistance R1 and the resistance R2 are 0.1Ω, the resistance between the P-side DC external terminal 101p and the AC terminal 140U shown in FIG. 8A, the P-side DC external terminal 101p and the AC terminal 140V The average value of the resistance between the P-side DC external terminal 101p and the AC terminal 140W is 0.53Ω.

  Further, the resistance between the N-side DC external terminal 102n and the AC terminal 140U, the resistance between the N-side DC external terminal 102n and the AC terminal 140V, and the N-side DC external terminal 102n and the AC shown in FIG. The average value of the resistance with the terminal 140W is 0.73Ω. In the reference example, the average value of the wiring resistance varies between the P side and the N side. For this reason, there is a possibility of locally generating heat in the semiconductor device.

  FIG. 9A and FIG. 9B are a schematic diagram and a table for explaining the wiring resistance of the semiconductor device according to the first embodiment.

  In the semiconductor device 1, as shown in FIG. 9A, the resistance between the P-side wiring 101 and the AC terminal 140U, the resistance between the P-side wiring 101 and the AC terminal 140V, and the P-side wiring 101 and the AC The average value of resistance with the terminal 140W is 0.5Ω.

  9B, the resistance between the N-side wiring 102 and the AC terminal 140U, the resistance between the N-side wiring 102 and the AC terminal 140V, and the resistance between the N-side wiring 102 and the AC terminal 140W. The average value of the resistance is 0.4Ω. That is, the wiring resistance of the semiconductor device 1 according to the first embodiment is reduced compared to the wiring resistance of the semiconductor device 5 according to the reference example. For example, the average value of the wiring resistance shown in FIG. 9B is about 55% of the average value of the wiring resistance shown in FIG.

  In the first embodiment, the average value of the wiring resistance is balanced between the P side and the N side. For this reason, even if heat is generated in the semiconductor device, the heat is easily dispersed in the semiconductor device.

  The case 100 in which the P-side wiring 101 and the N-side wiring 102 are sealed is manufactured by so-called insert resin molding in which the metal wiring is sealed with resin. Mass productivity of insert resin molding is generally high. Therefore, the semiconductor device 1 can be manufactured at low cost.

  Here, there is a semiconductor device in which the P-side wiring 101 and the N-side wiring 102 are arranged inside the case 100. In such a semiconductor device, when a resin such as silicone is filled inside the case 100, the P-side wiring 101 and the N-side wiring 102 may approach each other due to the pressure of resin sealing. Further, due to the presence of the P-side wiring 101 and the N-side wiring 102, silicone may not sufficiently wrap around the case 100. In the semiconductor device 1, since the P-side wiring 101 and the N-side wiring 102 are sealed in the frame portion 100 f of the case 100, such a problem is difficult to occur.

  In the semiconductor device 1, the P-side wiring 101 and the N-side wiring 102 are not arranged inside the case 100. Thereby, the freedom degree of arrangement | positioning of an electrode layer, a semiconductor element, a wire, etc. inside the case 100 increases.

  Moreover, even if the size of the case 100 is standardized in the market, according to the first embodiment, the wiring inductance and the wiring resistance can be lowered without changing the standard.

(Second Embodiment)
FIG. 10A is a schematic plan view showing the main part of the semiconductor device according to the second embodiment, and FIG. 10B is an equivalent circuit diagram of the semiconductor device according to the second embodiment.

  The semiconductor device 2 according to the second embodiment is a 2-in-1 package including two switching elements in one module. The semiconductor device 2 is one phase of a three-phase inverter device.

  As shown in FIG. 10, the P-side wiring 101 has two first terminals 101a. The N-side wiring 102 has two fourth terminals 102a.

  The electrode layer 111 a is provided on the bottom 100 b of the case 100. The electrode layer 111a is electrically connected to the first terminal 101a via the wire W11.

  A collector electrode 121c of the semiconductor element 121 is electrically connected to the electrode layer 111a.

  The electrode layer 114 a is provided on the bottom 100 b of the case 100. The electrode layer 114a is electrically connected to the emitter electrode 121e of the semiconductor element 121 through the wire W14.

  A part of the electrode layer 114a and a part of the electrode layer 111a are arranged in the X direction. An electrode layer 117 a is provided on the bottom 100 b of the case 100. A part of the electrode layer 114a, a part of the electrode layer 111a, and the electrode layer 117a are arranged in the X direction.

  A collector electrode 124c of the semiconductor element 124 is electrically connected to the electrode layer 114a. The emitter electrode 124e is electrically connected to the fourth terminal 102a via the wire W21, the electrode layer 117a, and the wire W22.

  A semiconductor element 131 is provided on the electrode layer 111a. The cathode layer 131c of the semiconductor element 131 is electrically connected to the electrode layer 111a. The anode 131a is electrically connected to the electrode layer 114a through the wire W31.

  A semiconductor element 134 is provided on the electrode layer 114a. A cathode electrode 134c of the semiconductor element 134 is electrically connected to the electrode layer 114a. The anode electrode 134a is electrically connected to the fourth terminal 102a via the wire W34, the electrode layer 117a, and the wire W22.

  The first portion 100fa of the case 100 seals a part of the AC terminal 140U.

  AC terminal 140U is electrically connected to electrode layer 114a through wire W40U.

  Further, in the semiconductor device 2, at least a part of the semiconductor element 124 is disposed on the region 100 ba between the N-side wiring 102 and the semiconductor element 121 in the bottom 100 b of the case 100 when viewed from the Z direction.

  A collector electrode 121c of the semiconductor element 121 is electrically connected to the electrode layer 111b.

  The electrode layer 114 b is provided on the bottom 100 b of the case 100. The electrode layer 114b is electrically connected to the electrode layer 114a through a wire W67. The electrode layer 114b is electrically connected to the emitter electrode 121e of the semiconductor element 121 via the wire W14.

  A part of the electrode layer 114b and a part of the electrode layer 111b are arranged in the X direction. An electrode layer 117 b is provided on the bottom 100 b of the case 100. The electrode layer 117b is electrically connected to the electrode layer 117a through a wire W68. A part of the electrode layer 114b, a part of the electrode layer 111b, and the electrode layer 117b are arranged in the X direction.

  A collector electrode 124c of the semiconductor element 124 is electrically connected to the electrode layer 114b. The emitter electrode 124e is electrically connected to the fourth terminal 102a through the wire W21, the electrode layer 117b, and the wire W22.

  A semiconductor element 131 is provided over the electrode layer 111b. The cathode layer 131c of the semiconductor element 131 is electrically connected to the electrode layer 111b. The anode 131a is electrically connected to the electrode layer 114b through the wire W31.

  A semiconductor element 134 is provided over the electrode layer 114b. A cathode electrode 134c of the semiconductor element 134 is electrically connected to the electrode layer 114b. The anode electrode 134a is electrically connected to the fourth terminal 102a via the wire W34, the electrode layer 117a, and the wire W22.

  The electrode layer 111a and the electrode layer 111b are arranged in the Y direction in this order. The electrode layer 114a and the electrode layer 114b are arranged in this order in the Y direction.

  In the semiconductor device 2, the semiconductor elements, electrode layers, and wires arranged in the region A and the semiconductor elements, electrode layers, and wires arranged in the region B are connected to the P-side wiring 101 and the N-side wiring 102. Are connected in parallel. In the semiconductor device 2, the semiconductor elements and electrode layers arranged in the region A and the semiconductor elements and electrode layers arranged in the region B are arranged symmetrically with respect to the boundary between the region A and the region B. Has been.

  Also in the semiconductor device 2, the P-side wiring 101 and the N-side wiring 102 overlap vertically in the Z direction. Therefore, the magnetic flux generated around each of the P-side wiring 101 and the N-side wiring 102 can be easily canceled.

  Further, the area surrounded by the broken line B and the current path 1IU is reduced. Magnetic fluxes generated around the current path 1IU cancel each other. Accordingly, the wiring inductance is reduced, and the surge voltage (ΔV) of each of the semiconductor elements 121 to 126 is reduced.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 2, 5 Semiconductor device, 1IU, 1IV, 1IW, 5IU, 5IV, 5IW Current path, 100 case, 100b bottom part, 100ba, 100bb, 100bc region, 100f frame part, 100fa first part, 100fb second part, 100d Insulating layer, 101 first wiring, 101a first terminal, 101b second terminal, 101c third terminal, 101p first external terminal, 101x first wiring section, 101y second wiring section, 102 second wiring, 102a fourth terminal , 102b fifth terminal, 102c sixth terminal, 102n second external terminal, 102x third wiring portion, 102y fourth wiring portion, 111 first electrode layer, 112 second electrode layer, 113 third electrode layer, 114 fourth Electrode layer, 115 fifth electrode layer, 116 sixth electrode layer, 11a, 111b, 114a, 114b, 117, 117a, 117b, 118, 119 electrode layer, 121 first semiconductor element, 121c first electrode, 121e second electrode, 122 second semiconductor element, 122c third electrode, 122e fourth Electrode, 123 third semiconductor element, 123c fifth electrode, 123e sixth electrode, 124 fourth semiconductor element, 124c seventh electrode, 124e eighth electrode, 125 fifth semiconductor element, 125c ninth electrode, 125e tenth electrode, 126 sixth semiconductor element, 126c eleventh electrode, 126e twelfth electrode, 131 semiconductor element, 131a anode electrode, 131c cathode electrode, 132 semiconductor element, 132a anode electrode, 132c cathode electrode, 133 semiconductor element, 133a a Cathode electrode, 133c cathode electrode, 134 semiconductor element, 134a anode electrode, 134c cathode electrode, 135 semiconductor element, 135a anode electrode, 135c cathode electrode, 136 semiconductor element, 136a anode electrode, 136c cathode electrode, 140U, 140V, 140W AC Terminal, 502a, 502b N side electrode layer, 511, 513, 514, 515, 516 electrode layer, G1-G6 gate electrode, W11, W12, W13, W14, W15, W16, W21, W22, W23, W24, W25, W26, W31, W32, W33, W34, W35, W36 Wire, W40U, W40V, W40W, W51, W52, W53, W54, W55, W56, W57, W58, W59, W60, W61 W62, W63, W64, W65, W66, W67, W68 wire

Claims (10)

A first portion extending in the first direction and a length extending in the second direction intersecting the first direction and having a length in the second direction that is longer than a length of the first portion in the first direction A case having a frame part including a second part and a bottom part connected to the frame part;
A first wiring portion sealed by the first portion and having a first external terminal; and a first wiring portion sealed by the second portion and having a first terminal extending from the frame portion to the inside of the frame portion. A first wiring having two wiring parts;
A third wiring portion sealed by the first portion and having a second external terminal, and sealed by the second portion, extending from the frame portion to the inside of the frame portion, and adjacent to the first terminal A second wiring having a fourth terminal having a fourth terminal,
A first electrode provided on the bottom and provided on the side of the bottom; and a second electrode provided on a side opposite to the bottom, and the first electrode is electrically connected to the first terminal. Connected first semiconductor elements;
A seventh electrode provided on the bottom and provided on the side of the bottom; and an eighth electrode provided on a side opposite to the bottom; and the seventh electrode is electrically connected to the second electrode. A fourth semiconductor element connected to the fourth terminal, wherein the eighth electrode is electrically connected to the fourth terminal;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first wiring is separated from the second wiring in a third direction intersecting the first direction and the second direction. A first electrode layer and a fourth electrode layer provided on the bottom;
The first electrode layer is electrically connected to the first terminal, the first semiconductor element is provided on the first electrode layer, and the first electrode is electrically connected to the first electrode layer. Connected to
The fourth electrode layer is electrically connected to the second electrode, the fourth semiconductor element is provided on the fourth electrode layer, and the seventh electrode is electrically connected to the fourth electrode layer. Connected to
3. The semiconductor device according to claim 1, wherein at least a part of the fourth electrode layer is aligned with at least a part of the first electrode layer in the second direction. In the second direction,
The semiconductor device according to claim 3, wherein a distance between the first terminal and the fourth terminal is 0.8 mm or more and 20 mm or less.   5. The device according to claim 1, wherein at the bottom portion, at least a part of the fourth semiconductor element is disposed on a region between the second wiring and the first semiconductor element. Semiconductor device. The second wiring portion of the first wiring further includes a second terminal and a third terminal,
The first terminal, the second terminal, and the third terminal are arranged in the second direction,
The second terminal is located between the first terminal and the third terminal;
The second terminal and the third terminal extend from the frame part to the inside of the frame part,
The fourth wiring portion of the second wiring further includes a fifth terminal and a sixth terminal,
The fourth terminal, the fifth terminal, and the sixth terminal are arranged in the second direction,
The fifth terminal is located between the fourth terminal and the sixth terminal;
The fifth terminal and the sixth terminal extend from the frame portion to the inside of the frame portion,
The fifth terminal is adjacent to the second terminal;
The sixth terminal is adjacent to the third terminal;
A third electrode provided on the bottom, arranged in the first semiconductor element in the second direction, provided on the side of the bottom, and a fourth electrode provided on the side opposite to the bottom. A second semiconductor element having the second electrode electrically connected to the second terminal;
A fifth electrode provided on the bottom, arranged in the second semiconductor element in the second direction, provided on the bottom, and a sixth electrode provided on the opposite side of the bottom; A third semiconductor element in which the fifth electrode is electrically connected to the third terminal;
A ninth electrode provided on the bottom and arranged in the second semiconductor element in the second direction, provided on the side of the bottom, and a tenth electrode provided on the opposite side of the bottom; A fifth semiconductor element having the ninth electrode electrically connected to the fourth electrode and the tenth electrode electrically connected to the fifth terminal;
An eleventh electrode provided on the bottom and arranged in the second direction in the second direction and provided on the bottom, and a twelfth electrode provided on the opposite side of the bottom; A sixth semiconductor element having the eleventh electrode electrically connected to the sixth electrode and the twelfth electrode electrically connected to the sixth terminal;
The semiconductor device according to claim 1, further comprising: A second electrode layer, a third electrode layer, a fifth electrode layer, and a sixth electrode layer provided on the bottom;
The second electrode layer is electrically connected to the second terminal, the second electrode layer is aligned with the first electrode layer in the second direction, and the second semiconductor element is the second electrode layer The third electrode is electrically connected to the second electrode layer;
The third electrode layer is electrically connected to the third terminal, the third electrode layer is aligned with the second electrode layer in the second direction, and the third semiconductor element is the third electrode layer And the fifth electrode is electrically connected to the third electrode layer,
The fifth electrode layer is electrically connected to the fourth electrode, the fifth electrode layer is aligned with the fourth electrode layer in the second direction, and the fifth semiconductor element includes the fifth electrode layer The ninth electrode is electrically connected to the fifth electrode layer;
The sixth electric layer is electrically connected to the sixth electrode, the sixth electrode layer is aligned with the fifth electrode layer in the second direction, and the sixth semiconductor element is the sixth electrode layer The eleventh electrode is electrically connected to the sixth electrode layer;
In the second direction,
At least a part of the fifth electrode layer is aligned with at least a part of the second electrode layer,
The semiconductor device according to claim 6, wherein at least a part of the sixth electrode layer is aligned with at least a part of the third electrode layer. In the second direction,
The distance between the second terminal and the fifth terminal is 0.8 mm or more and 20 mm or less,
The semiconductor device according to claim 6, wherein a distance between the third terminal and the sixth terminal is 0.8 mm or more and 20 mm or less.   The said bottom part WHEREIN: At least one part of the said 5th semiconductor element is arrange | positioned on the area | region between the said 2nd wiring and the said 2nd semiconductor element. Semiconductor device.   10. The device according to claim 6, wherein at the bottom, at least a part of the sixth semiconductor element is disposed on a region between the second wiring and the third semiconductor element. Semiconductor device.

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