JP2016171281A - Semiconductor light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which can improve reliability.SOLUTION: A semiconductor light emitting device 110 comprises a first metal pillar 21P, a second metal pillar 22P, an optical layer 30, a semiconductor part 15, a first metal layer 21L, a second metal layer 22L, an inorganic insulation layer 71 and an insulation part 18. The optical layer separates the first metal pillar and the second metal pillar in a second direction D2 crossing a first direction D1 from the second metal pillar toward the first metal pillar. The semiconductor part includes a first semiconductor layer 11, a second semiconductor layer 12 and a third semiconductor layer 13. The inorganic insulation layer is provided around at least part of a first lateral face 21Ps of the first metal pillar and part of a second lateral face 22Ps of the second metal pillar. A part of the insulation part is provided between the second semiconductor layer and the first metal layer and between the third semiconductor layer and the first metal layer. The other part of the insulation part is provided between an outer edge 30r of the optical layer and the inorganic insulation layer.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  A semiconductor light emitting device having a chip size package structure has been proposed. In a semiconductor light emitting device, improvement in reliability is desired.

JP 2012-70017 A

  Embodiments of the present invention provide a semiconductor light emitting device capable of improving reliability.

  According to the embodiment, the semiconductor light emitting device includes a first metal pillar, a second metal pillar, an optical layer, a semiconductor part, a first metal layer, a second metal layer, an inorganic insulating layer, and an insulating part. And comprising. The optical layer is separated from the first metal pillar and the second metal pillar in a second direction that intersects a first direction from the second metal pillar toward the first metal pillar. The semiconductor part includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is provided between the optical layer and the first metal pillar and between the optical layer and the second metal pillar. The first semiconductor layer is of a first conductivity type. At least a part of the second semiconductor layer is provided between a part of the first semiconductor layer and the second metal pillar. The second semiconductor layer is of a second conductivity type. The third semiconductor layer is provided between the part of the first semiconductor layer and the at least part of the second semiconductor layer. The first metal layer includes a portion provided between the semiconductor portion and the first metal pillar, and is electrically connected to the first semiconductor layer and the first metal pillar. The second metal layer includes a portion provided between the semiconductor portion and the second metal pillar, and is electrically connected to the second semiconductor layer and the second metal pillar. The inorganic insulating layer includes at least a part of a first side surface intersecting the second direction of the first metal pillar, and at least a part of a second side surface intersecting the second direction of the second metal pillar. It is provided around. A part of the insulating part is provided between the second semiconductor layer and the first metal layer and between the third semiconductor layer and the first metal layer. Another part of the insulating part is provided between an outer edge part of the optical layer and the inorganic insulating layer.

FIG. 1A and FIG. 1B are schematic views of the semiconductor light emitting device according to the first embodiment. 2A and 2B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. FIG. 3A and FIG. 3B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. FIG. 4A and FIG. 4B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. FIG. 5A and FIG. 5B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. 6A and 6B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. FIG. 7A and FIG. 7B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. 8A and 8B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment. FIG. 9A and FIG. 9B are schematic cross-sectional views of another semiconductor light emitting device according to the first embodiment. FIG. 10A and FIG. 10B are schematic views of a semiconductor light emitting device according to the second embodiment. FIG. 11A and FIG. 11B are schematic cross-sectional views illustrating a part of the method for manufacturing the semiconductor light emitting device according to the second embodiment. It is a schematic cross section of another semiconductor light-emitting device concerning a 2nd embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1A and FIG. 1B are schematic views of the semiconductor light emitting device according to the first embodiment. FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view. FIG. 1A corresponds to the A1-A2 cross section in FIG. FIG. 1B corresponds to a plan view seen from the direction of the arrow AA in FIG.

  As shown in FIG. 1A, the semiconductor light emitting device 110 according to this embodiment includes a first metal pillar 21P, a second metal pillar 22P, an optical layer 30, a semiconductor unit 15, a first metal layer 21L, and a second metal. The layer 22L, the inorganic insulating layer 71, and the insulating part 18 are included.

  A direction from the second metal pillar 22P toward the first metal pillar 21P is defined as a first direction D1. The first direction D1 is taken as the X-axis direction. One direction perpendicular to the X-axis direction is taken as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is taken as a Y-axis direction.

  The optical layer 30 is separated from the first metal pillar 21P and the second metal pillar 22P in the second direction D2. The second direction D2 intersects the first direction D1 (for example, the X-axis direction). The second direction D2 is, for example, the Z-axis direction. The second direction D2 is, for example, a stacking direction.

  The semiconductor unit 15 is provided between the first metal pillar 21P and the optical layer 30, and between the second metal pillar 22P and the optical layer 30.

  The semiconductor unit 15 includes a first semiconductor layer 11, a second semiconductor layer 12, and a third semiconductor layer 13.

  The first semiconductor layer 11 is provided between the optical layer 30 and the first metal pillar 21P and between the optical layer 30 and the second metal pillar 22P. The first semiconductor layer 11 is the first conductivity type.

  At least a part of the second semiconductor layer 12 is provided between a part of the first semiconductor layer 11 (first semiconductor region 11p) and the second metal pillar 22P. For example, a part 12a of the second semiconductor layer 12 is provided between a part of the first semiconductor layer 11 (first semiconductor region 11p) and the second metal pillar 22P.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type. Hereinafter, the first conductivity type is n-type and the second conductivity type is p-type.

  The third semiconductor layer 13 is provided between the part of the first semiconductor layer 11 (first semiconductor region 11p) and the at least part of the second semiconductor layer 12 (part 12a). The third semiconductor layer 13 is, for example, an active layer (light emitting layer).

  The first metal layer 21L includes a portion 21a provided between the semiconductor unit 15 and the first metal pillar 21P. The first metal layer 21L is electrically connected to the first semiconductor layer 11 and the first metal pillar 21P. In this example, another part (part 21b) of the first metal layer 21L overlaps with another part (second semiconductor region 11q) of the first semiconductor layer 11 in the second direction D2.

  The second metal layer 22L includes a portion 22a provided between the semiconductor portion 15 and the second metal pillar 22P. The second metal layer 22L is electrically connected to the second semiconductor layer 12 and the second metal pillar 22P.

  The first metal pillar 21P has a first side surface 21Ps that intersects the second direction D2. The second metal pillar 22P has a second side surface 22Ps that intersects the second direction D2.

  The inorganic insulating layer 71 is provided around at least a part of the first side surface 21Ps and at least a part of the second side surface 22Ps. For example, the inorganic insulating layer 71 overlaps the first metal pillar 21P and the second metal pillar 22P in the first direction D1. For example, the inorganic insulating layer 71 does not overlap the first metal pillar 21P and the second metal pillar 22P in the second direction D2 (Z-axis direction).

  The inorganic insulating layer 71 supports, for example, the metal pillar and the semiconductor unit 15. The inorganic insulating layer 71 includes, for example, at least one of aluminum nitride, silicon nitride, aluminum oxide, and silicon oxide. The inorganic insulating layer 71 is formed by thermal spraying, for example. The inorganic insulating layer 71 is formed by, for example, cold spray.

  A part 18a of the insulating portion 18 is provided between the second semiconductor layer 12 and the first metal layer 21L and between the third semiconductor layer 13 and the first metal layer 21L. The insulating unit 18 insulates between the second semiconductor layer 12 and the first metal layer 21L and between the third semiconductor layer 13 and the first metal layer 21L.

  Another part 18 b of the insulating part 18 is provided between the outer edge part 30 r of the optical layer 30 and the inorganic insulating layer 71.

  In the embodiment, providing the inorganic insulating layer 71 as the insulating layer provided around the metal pillar improves the reliability as compared with the case of providing the organic insulating layer.

  Furthermore, due to the structure in which the part 18 b of the insulating part 18 is sandwiched between the outer edge part 30 r of the optical layer 30 and the inorganic insulating layer 71, for example, the part 18 b of the insulating part 18 is suppressed by the inorganic insulating layer 71. It is done. Deformation (for example, peeling) of the part 18b of the insulating portion 18 is suppressed. Reliability can be further improved.

  In this example, at least a part of the first metal pillar 21P overlaps a part 12b of the second semiconductor layer 12 in the second direction D2. Another portion 18 c of the insulating portion 18 extends between at least a portion of the first metal pillar 21 </ b> P and a portion 12 b of the second semiconductor layer 12. That is, the first metal pillar 21 </ b> P electrically connected to the first semiconductor layer 11 overlaps the part 12 b of the second semiconductor layer 12. By extending the insulating portion 18 between the first metal pillar 21P and the second semiconductor layer 12, the first metal pillar 21P and the second semiconductor layer 12 are insulated. Since the first metal pillar 21P overlaps the second semiconductor layer 12, the area of the second semiconductor layer 12 can be increased, and high luminous efficiency can be obtained.

  In this example, a first electrode 25 and a second electrode 26 are further provided. The first electrode 25 is provided between a part of the first metal layer 21L (part 21b) and a part of the first semiconductor layer 11 (second semiconductor region 11q). The second electrode 22 is provided between the second metal layer 22 </ b> L and the second semiconductor layer 12. The first semiconductor layer 11 is electrically connected to the first metal pillar 21P through the first electrode 25 and the first metal layer 21L. The second semiconductor layer 12 is electrically connected to the second metal pillar 22P through the second electrode 26 and the second metal layer 22L.

  The second electrode 26 includes a reflective film that reflects the emitted light of the third semiconductor layer 13. For example, the second electrode 26 includes at least one of silver, a silver alloy, aluminum, and an aluminum alloy. The second electrode 26 may include a barrier metal (eg, Ti, Ni, etc.). Thereby, sulfurization of the reflective film and oxidation of the reflective film are suppressed.

  In this example, the first electrode 25 includes a first electrode layer 25a and a second electrode layer 25b. A second electrode layer 25 b is provided between the first electrode layer 25 a and the first semiconductor layer 11. The second electrode 26 includes a third electrode layer 26a and a fourth electrode layer 26b. A fourth electrode layer 26 b is provided between the third electrode layer 26 a and the second semiconductor layer 12. The fourth electrode layer 26b includes, for example, at least one of silver, a silver alloy, aluminum, and an aluminum alloy. The third electrode layer 26a includes, for example, Ti, Ni and the like.

  A voltage is applied between the first metal pillar 21P and the second metal pillar 22P, and the first metal layer 21L, the first electrode 25, the first semiconductor layer 11, the second metal layer 22L, the second electrode 26, and the second A current is supplied to the third semiconductor layer 13 through the semiconductor layer 12. Light is emitted from the third semiconductor layer 13.

  The first semiconductor layer 11 includes, for example, an n-type GaN layer. The first semiconductor layer 11 may further include a base buffer layer. The second semiconductor layer 12 includes, for example, a p-type GaN layer. The third semiconductor layer 13 includes, for example, InGaN. The third semiconductor layer 13 emits blue, purple, blue-violet, ultraviolet light, or the like. The peak wavelength of light emission of the third semiconductor layer 13 is, for example, 430 to 470 nm.

  The emitted light enters the optical layer 30 and exits from the optical layer 30 to the outside. The first electrode 25 and the second electrode 26 reflect light and travel the light toward the optical layer 30. The optical layer 30 becomes an emission surface of the semiconductor light emitting device 110.

  The optical layer 30 includes, for example, a plurality of phosphor particles 31 and a light transmission layer 32 provided around the plurality of phosphor particles 31. The phosphor particles 31 are excited by the emitted light of the third semiconductor layer 13 and emit light having a wavelength different from the wavelength of the emitted light. For example, blue light is emitted from the third semiconductor layer 13, and light such as yellow and red is emitted from the phosphor particles 31. As the combined light of these lights, for example, white light is obtained.

  The light transmissive layer 32 is, for example, a light transmissive resin layer. The light transmission layer 32 transmits the emitted light of the third semiconductor layer 13 and the emitted light of the phosphor particles 31. In the light transmission layer 32, light attenuation may occur.

  The optical layer 30 may not include the phosphor particles 31. In this case, for example, the surface shape of the optical layer 30 is a lens, and the direction and range of light emission are controlled, for example.

  The surface on the optical layer 30 side of the semiconductor unit 15 is provided with unevenness, for example. Thereby, light can efficiently enter the optical layer 30 from the first semiconductor layer 11.

  As a material of the first metal pillar 21P and the second metal pillar 22P, for example, at least one of copper, gold, nickel, and silver can be used. When copper is used, good thermal conductivity, high migration resistance, and high adhesion to an insulating material can be obtained.

  In this example, the semiconductor light emitting device 110 further includes a third metal layer 23L and a fourth metal layer 24L.

  The first metal pillar 21P is disposed between the third metal layer 23L and the first metal layer 21L. A second metal pillar 22P is disposed between the fourth metal layer 24L and the second metal layer 22L. The third metal layer 23L is electrically connected to the first semiconductor layer 11 via the first metal pillar 21P and the first metal layer 21L. The fourth metal layer 24L is electrically connected to the second semiconductor layer 12 through the second metal pillar 22P and the second metal layer 22L. The third metal layer 23L and the fourth metal layer 24L serve as connection terminals of the semiconductor light emitting device 110. For example, the electrode of the mounting substrate and the third metal layer 23L are connected by a connection member (solder or the like), and another electrode of the mounting substrate and the fourth metal layer 24L are connected by a connection member (solder or the like).

  In this example, the third metal layer 23L is in contact with a part of the first side surface 21Ps of the first metal pillar 21P. The fourth metal layer 24L is in contact with a part of the second side surface 22Ps of the second metal pillar 22P. That is, the third metal layer 23L covers a part of the first side surface 21Ps of the first metal pillar 21P in addition to the end surface 21E of the first metal pillar 21P. The fourth metal layer 24L covers a part of the second side surface 22Ps of the second metal pillar 22P in addition to the end surface 22E of the second metal pillar 22P. Thus, by covering a part of the side surface of the metal pillar with the metal layer, the connection with the connection member is ensured. Thereby, reliability is further improved.

  In this example, a reflective film 51 is provided. The reflective film 51 is provided between the inorganic insulating layer 71 and the side surface 15 s of the semiconductor unit 15. The reflective film 51 is reflective to the emitted light from the third semiconductor layer 13 and the emitted light from the phosphor particles 31.

Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 110 according to the present embodiment will be described.
FIG. 2A to FIG. 8B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment.

  As shown in FIG. 2A, the first semiconductor layer 11, the third semiconductor layer 13, and the second semiconductor layer 12 are arranged in this order on the upper side of the substrate 10 by, for example, MOCVD (metal organic chemical vapor deposition). Grown in. The substrate 10 is, for example, a silicon substrate. The substrate 10 may be a sapphire substrate.

  The first semiconductor layer 11 includes, for example, a buffer layer provided on the substrate 10 and an n-type GaN layer provided on the buffer layer. The second semiconductor layer 12 includes, for example, a p-type AlGaN layer provided on the third semiconductor layer 13 and a p-type GaN layer provided thereon. The third semiconductor layer 13 has, for example, an MQW (Multiple Quantum well) structure.

  FIG. 2B shows a state in which a part of the second semiconductor layer 12 and a part of the third semiconductor layer 13 are removed. For example, a part of the second semiconductor layer 12 and a part of the third semiconductor layer 13 are selectively etched by RIE (Reactive Ion Etching) to expose a part of the first semiconductor layer 11.

  As shown in FIG. 3A, a part of the first semiconductor layer 11 is removed, and a groove 90 is formed. The grooves 90 are formed, for example, in a lattice pattern on the wafer-like substrate 10. The semiconductor part 15 is separated into a plurality by the grooves 90. The groove 90 may be formed after the first electrode 25 and the second electrode 26 are formed.

  As shown in FIG. 3B, the second electrode 26 is formed on the surface of the second semiconductor layer 12. On the other hand, the first electrode 25 is formed on the surface of the first semiconductor layer 11.

  As shown in FIG. 4A, the insulating part 18 is formed on the substrate 10, the semiconductor part 15, the first electrode 25 and the second electrode 26. The insulating unit 18 includes, for example, at least one of a silicon oxide film and a silicon nitride film. The insulating portion 18 is formed by, for example, a CVD (Chemical Vapor Deposition) method.

  As shown in FIG. 4B, the first opening 18ha and the second opening 18hb are formed in the insulating portion 18 by, for example, wet etching using a resist mask. The first opening 18ha reaches the second electrode 26, and the second opening 18hb reaches the first electrode 25.

  A metal film 60 is formed on the surface of the insulating portion 18, the inner wall (side wall and bottom surface) of the first opening 18ha, and the inner wall (side wall and bottom surface) of the second opening 18hb.

  As shown in FIG. 5A, the metal film 60 includes a base metal film 61, an adhesion layer 62, and a seed layer 63. The metal film 60 is formed by, for example, a sputtering method. The base metal film 61 has high reflectivity with respect to the emitted light of the third semiconductor layer 13. The base metal layer 61 is, for example, an aluminum film. The seed layer 63 is, for example, a copper film. The seed layer 63 is a seed layer for depositing copper by plating. The adhesion layer 62 is, for example, a titanium film. The adhesion layer 62 has high adhesion to, for example, both aluminum and copper.

  As shown in FIG. 5B, after a resist mask 91 is formed on a part of the metal film 60, the first metal layer 21L, the second metal layer 22L, and the reflective film 51 are formed. In this formation, for example, an electrolytic copper plating method using the seed layer 63 of the metal film 60 as a seed layer is used. The reflective film 51 may be formed of the metal film 60 without forming the plating film (copper film) on the metal film 60.

  The second metal layer 22L is also formed in the first opening 18ha and is electrically connected to the second electrode 26. The first metal layer 21L is also formed in the second opening 18hb and is electrically connected to the first electrode 25.

As shown in FIG. 6A, the resist mask 91 is removed using, for example, a solvent or oxygen plasma. Another resist mask 92 is selectively formed. The resist mask 92 may be formed without removing the resist mask 91.
After forming the resist mask 92, the first metal pillar 21P and the second metal pillar 22P are formed.

  The first metal pillar 21P is formed on the first metal layer 21L. The first metal layer 21L and the first metal pillar 21P are integrated with the same material (for example, copper). The second metal pillar 22P is formed on the second metal layer 22L. The second metal layer 22L and the second metal pillar 22P are integrated with the same material (for example, copper).

  The resist mask 92 is removed using, for example, a solvent or oxygen plasma. At this time, the first metal layer 21L and the second metal layer 22L are connected to each other through the metal film 60. The first metal layer 21 </ b> L and the reflective film 51 are connected to each other through the metal film 60. The second metal layer 22L and the reflective film 51 are connected to each other through the metal film 60.

  As shown in FIG. 6B, the metal film 60 between the first metal layer 21L and the second metal layer 22L, the metal film 60 between the second metal layer 22L and the reflective film 51, and the first The metal film 60 between the metal layer 21L and the reflective film 51 is removed by etching. Accordingly, the electrical connection between the first metal layer 21L and the second metal layer 22L via the metal film 60, the electrical connection via the metal film 60 between the first metal layer 21L and the reflective film 51, and the second The electrical connection of the metal layer 22L and the reflective film 51 via the metal film 60 is cut off.

  As shown in FIG. 7A, an inorganic insulating layer 71 is formed on the insulating portion 18, the first metal layer 21L, the first metal pillar 21P, the second metal layer 22L, the second metal pillar 22P, and the reflective film 51. Form. The inorganic insulating layer 71 is formed by, for example, thermal spraying (for example, cold spray). The inorganic insulating layer 71 surrounds a part of the first side surface 21Ps and a part of the second side surface 22Ps.

  The inorganic insulating layer 71 becomes the support body 95 together with the first metal pillar 21P and the second metal pillar 22P. The substrate 10 is removed in a state where the semiconductor portion 15 is supported by the support body 95.

  The substrate 10 (for example, a silicon substrate) is removed by dry etching such as RIE. The silicon substrate may be removed by wet etching. When the substrate 10 is a sapphire substrate, it can be removed by, for example, a laser lift-off method.

  The optical layer 30 is formed. As the optical layer 30, sintered phosphor particles obtained by sintering phosphor particles through a light transmission layer may be bonded. The optical layer 30 is also formed on a region around the side surface 15 s of the semiconductor unit 15. An inorganic insulating layer 71 is also provided in a region around the side surface 15 s of the semiconductor unit 15. The optical layer 30 is formed on the inorganic insulating layer 71 via the insulating portion 18.

  As shown in FIG. 8A, after the optical layer 30 is formed, the surface of the inorganic insulating layer 71 (the lower surface in the drawing) is ground.

  As shown in FIG. 8B, a part of the first metal pillar 21 </ b> P and a part of the second metal pillar 22 </ b> P are exposed from the inorganic insulating layer 71. The exposed surface of the first metal pillar 21P becomes the end surface 21E, and the exposed surface of the second metal pillar 22P becomes the end surface 22E.

  In the region where the groove 90 is formed, the structure shown in FIG. 8B is cut. The optical layer 30, the insulating part 18, and the inorganic insulating layer 71 are cut.

  A structure to be a plurality of semiconductor light emitting devices is formed on one wafer-like substrate 10 and divided to obtain a plurality of semiconductor light emitting devices. Thereby, the semiconductor light emitting device 110 is formed. The semiconductor light emitting device 110 may have a single chip structure including one semiconductor portion 15 or may have a multichip structure including a plurality of semiconductor portions 15.

  The formation of the wiring layer, the formation of the pillar, the packaging with the resin layer, and the formation of the optical layer are collectively performed in a plurality of apparatuses. In the semiconductor light emitting device 110, the cost can be significantly reduced.

  In the embodiment, the inorganic insulating layer 71 and the optical layer 30 are collectively cut in a wafer state. The side surface of the optical layer 30 is along the side surface of the inorganic insulating layer 71. The semiconductor light emitting device 110 has a chip size package structure and is small.

FIG. 9A and FIG. 9B are schematic cross-sectional views of another semiconductor light emitting device according to the first embodiment.
As shown in FIG. 9A, in the semiconductor light emitting device 111, the third metal layer 23L and the fourth metal layer 24L are not provided. Other than this, the semiconductor light emitting device 110. It is the same. Thus, the third metal layer 23L and the fourth metal layer 24L may be omitted.

  In this example, a part of the first side surface 21Ps of the first metal pillar 21P and a part of the second side surface 22Ps of the second metal pillar 22P are not in contact with the inorganic insulating layer 71. Part of the first metal pillar 21 </ b> P and part of the second metal pillar 22 </ b> P are exposed from the inorganic insulating layer 71.

  As shown in FIG. 9B, in the semiconductor light emitting device 112, the width of each of the first metal pillar 21P and the second metal pillar 22P changes along the second direction. The width is a length along the first direction D1.

  The first metal pillar 21P includes a first portion 21Pa (a portion including the end surface 21E) and a second portion 21Pb provided between the first portion 21Pa and the optical layer 30. The length of the first portion 21Pa along the first direction D1 is shorter than the length of the second portion 21Pb along the first direction D1. The second metal pillar 22P includes a third portion 22Pa (a portion including the end face 22E) and a fourth portion 22Pb provided between the third portion 22Pa and the optical layer 30. The length of the third portion 22Pa along the first direction D1 is shorter than the length of the fourth portion 22Pb along the first direction D1.

Thus, the width of the metal pillar may be narrowed toward the tip portion. For example, the shape of the connection member (solder or the like) is stabilized, and the mounting reliability can be improved.
High reliability is also obtained in the semiconductor light emitting devices 111 and 112.

(Second Embodiment)
FIG. 10A and FIG. 10B are schematic views of a semiconductor light emitting device according to the second embodiment.
FIG. 10A is a cross-sectional view, and FIG. 10B is a plan view. FIG. 10A corresponds to the B1-B2 cross section in FIG. FIG. 10B corresponds to a plan view seen from the direction of the arrow AA in FIG.

  As shown in FIG. 10A, the semiconductor light emitting device 120 according to the embodiment includes a first metal pillar 21P, a second metal pillar 22P, an optical layer 30, a semiconductor unit 15, a first metal layer 21L, and a second metal layer. In addition to 22L, the inorganic insulating layer 71, and the insulating portion 18, an organic insulating layer 72 is further included. The rest is the same as the semiconductor light emitting device 110.

  The organic insulating layer 72 surrounds a part of the first side surface 21Ps and a part of the second side surface 22Ps. The inorganic insulating layer 71 is disposed between the organic insulating layer 72 and the optical layer 30.

  As already described, an organic resin is used for the optical layer 30. The thermal expansion coefficient of the organic insulating layer 72 is relatively close to the thermal expansion coefficient of the optical layer 30. For example, the difference (absolute value) between the thermal expansion coefficient of the organic insulating layer 72 and the thermal expansion coefficient of the optical layer 30 is the difference between the thermal expansion coefficient of the inorganic insulating layer 71 and the thermal expansion coefficient of the optical layer 30. Smaller than (absolute value). In the semiconductor light emitting device 120, the semiconductor unit 15 is disposed between the optical layer 30 and the organic insulating layer 72 that have similar thermal expansion coefficients. For this reason, a change in shape can be reduced with respect to a change in temperature. For example, it is possible to suppress the semiconductor light emitting device 120 from being deformed by heat accompanying light emission. Thereby, higher reliability can be obtained.

  The organic insulating layer 72 includes, for example, at least one of a resin mainly containing an epoxy resin, a resin mainly containing a silicone resin, and a resin mainly containing a fluororesin. The organic insulating layer 72 may include, for example, a base resin and a filler such as silica particles. Further, the organic insulating layer 72 may include light absorbing particles (for example, carbon).

  In the semiconductor light emitting device 120, stress may be applied to due to heat during mounting. For example, the organic insulating layer 72 relieves stress.

Hereinafter, an example of a method for manufacturing the semiconductor light emitting device 120 according to the present embodiment will be described.
FIG. 11A and FIG. 11B are schematic cross-sectional views illustrating a part of the method for manufacturing the semiconductor light emitting device according to the second embodiment.

Steps similar to those described in FIGS. 2A to 6B are performed.
As shown in FIG. 10A, an inorganic insulating layer 71 is formed on the structure including the insulating portion 18, the first metal layer 21L, the first metal pillar 21P, the second metal layer 22L, and the second metal pillar 22P. Form. The inorganic insulating layer 71 is formed by, for example, thermal spraying (for example, cold spray).

  As shown in FIG. 10B, the organic insulating layer 72 is formed on the inorganic insulating layer 71. Thereby, the organic insulating layer 72 surrounds a part of the first side surface 21Ps and a part of the second side surface 22Ps.

  Thereafter, the same processes as those described with reference to FIGS. 7A and 7B are performed. Thereafter, the same process as that described with reference to FIG. At this time, after the optical layer 30 is formed, the surface of the organic insulating layer 72 is ground. In the step shown in FIG. 8B, the first metal pillar 21P and the second metal pillar 22P are exposed from the organic insulating layer 72. Thereby, the semiconductor light emitting device 120 is formed.

  In the semiconductor light emitting device 120, the configuration of the metal pillar described with respect to the semiconductor light emitting devices 111 and 112 may be applied.

FIG. 12 is a schematic cross-sectional view of another semiconductor light emitting device according to the second embodiment.
In the semiconductor light emitting device 121 shown in FIG. 12, a part 72a of the organic insulating layer 72 overlaps the semiconductor unit 15 in the second direction D2. Except this, it is the same as the semiconductor light emitting device 120.

  A part 72 a of the organic insulating layer 72 surrounds a part 71 a of the inorganic insulating layer 71. The hardness of the organic insulating layer 72 is lower than the hardness of the inorganic insulating layer 71, for example. In the semiconductor light emitting device 121, for example, the occurrence of cracks in the inorganic insulating layer 71 during dicing is suppressed. Reliability can be further improved. Further, the yield is improved.

  According to the embodiment, a semiconductor light emitting device capable of improving reliability can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element such as a semiconductor layer, a metal layer, a metal pillar, an optical layer, and an insulating layer included in the semiconductor light emitting device, those skilled in the art can appropriately select from the well-known ranges by appropriately selecting the present invention. As long as the same effect can be obtained, it is included in the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all semiconductor light-emitting devices that can be implemented by those skilled in the art based on the semiconductor light-emitting devices described above as embodiments of the present invention are also included in the scope of the present invention as long as they include the gist of the present invention Belonging to.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10 substrate, 11 first semiconductor layer, 11p first semiconductor region, 11q second semiconductor region, 12 second semiconductor layer, part of 12a, 12b, 13 third semiconductor layer, 15 semiconductor unit, 15s side surface, 18 insulating unit, 18a, 18b, 18c part, 18ha first opening, 18hb second opening, 21E end face, 21L first metal layer, 21P first metal pillar, 21Ps first side face, 21a, 21b part, 22E end face, 22L second metal Layer, 22P second metal pillar, 22Ps second side, 22a part, 23L third metal layer, 24L fourth metal layer, 25 first electrode, 25a first electrode layer, 25b second electrode layer, 26 second electrode, 26a 3rd electrode layer, 27b 4th electrode layer, 30 optical layer, 30r outer edge part, 31 fluorescent substance grain, 32 light transmission layer, 51 Reflective film, 60 metal film, 61 base metal film, 62 adhesion layer, 63 seed layer, 71 inorganic insulating layer, 71a part, 72 organic insulating layer, 72a part, 90 groove, 91 resist mask, 92 resist mask, 95 Support, 110, 111, 112, 120, 121 Semiconductor light emitting device, AA arrow, D1, D2 direction

Claims (5)

A first metal pillar;
A second metal pillar;
An optical layer spaced from the first metal pillar and the second metal pillar in a second direction intersecting a first direction from the second metal pillar toward the first metal pillar;
A semiconductor part,
A first semiconductor layer of a first conductivity type provided between the optical layer and the first metal pillar and between the optical layer and the second metal pillar;
A second semiconductor layer of a second conductivity type, wherein at least a part of the second semiconductor layer is provided between a part of the first semiconductor layer and the second metal pillar. Layers,
A third semiconductor layer provided between the part of the first semiconductor layer and the at least part of the second semiconductor layer;
A semiconductor part including:
A first metal layer including a portion provided between the semiconductor portion and the first metal pillar and electrically connected to the first semiconductor layer and the first metal pillar;
A second metal layer including a portion provided between the semiconductor portion and the second metal pillar and electrically connected to the second semiconductor layer and the second metal pillar;
Inorganic provided around at least part of the first side surface intersecting the second direction of the first metal pillar and at least part of the second side surface intersecting the second direction of the second metal pillar. An insulating layer;
An insulation part,
A part of the insulating part is provided between the second semiconductor layer and the first metal layer, and between the third semiconductor layer and the first metal layer,
Another part of the insulating part is a semiconductor light emitting device provided between an outer edge part of the optical layer and the inorganic insulating layer. An organic insulating layer surrounding a part of the first side surface and a part of the second side surface;
The semiconductor light-emitting device according to claim 1, wherein the inorganic insulating layer is disposed between the organic insulating layer and the optical layer.   The semiconductor light emitting device according to claim 1, wherein the inorganic insulating layer includes at least one of aluminum nitride, silicon nitride, aluminum oxide, and silicon oxide. At least a portion of the first metal pillar overlaps the second semiconductor layer in the second direction;
4. The semiconductor according to claim 1, wherein another part of the insulating portion extends between the at least part of the first metal pillar and the second semiconductor layer. Light emitting device. And further comprising a third metal layer and a fourth metal layer,
The first metal pillar is disposed between the third metal layer and the first metal layer;
The second metal pillar is disposed between the fourth metal layer and the second metal layer;
The third metal layer is in contact with a part of the first side surface;
The semiconductor light-emitting device according to claim 1, wherein the fourth metal layer is in contact with a part of the second side surface.

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