JP2016171170A - Signal propagation structure in integrated circuit - Google Patents

Signal propagation structure in integrated circuit Download PDF

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JP2016171170A
JP2016171170A JP2015049213A JP2015049213A JP2016171170A JP 2016171170 A JP2016171170 A JP 2016171170A JP 2015049213 A JP2015049213 A JP 2015049213A JP 2015049213 A JP2015049213 A JP 2015049213A JP 2016171170 A JP2016171170 A JP 2016171170A
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integrated circuit
interlayer via
dielectric layer
signal propagation
propagation structure
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JP6334439B2 (en
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ホジン ソン
Ho-Jin Song
ホジン ソン
信 矢板
Makoto Yaita
信 矢板
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Nippon Telegraph and Telephone Corp
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Abstract

PROBLEM TO BE SOLVED: To allow for propagation of a high frequency AC signal between a transmission line and a circuit element in an integrated circuit through an interlayer via, while compensating for the inductance of the interlayer via.SOLUTION: A plurality of dielectric layers 4 are laminated between a first metal layer 1 and a second metal layer 2. A land 5 is provided between one dielectric layer 4 and another dielectric layer. Furthermore, an interlayer via 6 penetrating the dielectric layer 4 and being connected with the land 5 is provided. In a signal propagation structure 10 within an integrated circuit, the interlayer via 6 does not exist in at least one dielectric layer 4. In the drawing, the interlayer via 6 does not exist in the lowermost dielectric layer 4 of the signal propagation structure 10 within an integrated circuit.SELECTED DRAWING: Figure 1

Description

本発明は、集積回路内の伝送線路と回路素子間に層間ビアを介して高周波の交流信号を伝播でき且つ層間ビアのインダクタンスを補償できる技術に関する。   The present invention relates to a technique capable of propagating a high-frequency AC signal through an interlayer via between a transmission line and a circuit element in an integrated circuit and compensating for the inductance of the interlayer via.

一般に高周波信号を用いる集積回路のプロセスでは、低損失で高周波信号に適している金属厚膜は集積回路の最上層に存在し、トランジスタなどの回路素子(能動素子)は集積回路の最下層に存在する。   In general, in an integrated circuit process using a high-frequency signal, a metal thick film suitable for a high-frequency signal with low loss exists in the uppermost layer of the integrated circuit, and a circuit element such as a transistor (active element) exists in the lowermost layer of the integrated circuit. To do.

図10は、集積回路の最上層と最下層を繋ぐ部分の等価回路を示す。   FIG. 10 shows an equivalent circuit of a portion connecting the uppermost layer and the lowermost layer of the integrated circuit.

図10に示す回路100の伝送線路を構成する金属厚膜は集積回路の最上層に存在し、トランジスタ200は最下層に存在する。   The thick metal film constituting the transmission line of the circuit 100 shown in FIG. 10 exists in the uppermost layer of the integrated circuit, and the transistor 200 exists in the lowermost layer.

最上層に存在する回路100の伝送線路から、最下層のトランジスタ200へ、またはその逆に高周波信号を伝送すべく、伝送線路とトランジスタ200は、複数の層間ビアで電気的に接続される(非特許文献2)。図10は、層間ビアの等価回路として、インダクタンスLを示している。   In order to transmit a high-frequency signal from the transmission line of the circuit 100 existing in the uppermost layer to the lowermost transistor 200 or vice versa, the transmission line and the transistor 200 are electrically connected by a plurality of interlayer vias (non- Patent Document 2). FIG. 10 shows an inductance L as an equivalent circuit of the interlayer via.

図11(a)は、上記のような従来の集積回路に構成される信号伝播構造の一部断面図であり、図11(b)は、図11(a)に示す信号伝播構造の上面図である。   FIG. 11A is a partial cross-sectional view of the signal propagation structure configured in the conventional integrated circuit as described above, and FIG. 11B is a top view of the signal propagation structure shown in FIG. It is.

第1金属層1は、図10に示す回路100における伝送線路を構成し、第2金属層2は、図10に示すトランジスタ200のような集積回路内の回路素子3に接続される。   The first metal layer 1 constitutes a transmission line in the circuit 100 shown in FIG. 10, and the second metal layer 2 is connected to the circuit element 3 in the integrated circuit such as the transistor 200 shown in FIG.

第1金属層1と第2金属層2の間に複数の誘電体層4が積層される。図では、誘電体層4は4層である。   A plurality of dielectric layers 4 are stacked between the first metal layer 1 and the second metal layer 2. In the figure, the dielectric layer 4 has four layers.

1つの誘電体層4と別の誘電体層の間にランド5が設けられる。また、誘電体層4を貫通してランド5に接続される層間ビア6が設けられる。   A land 5 is provided between one dielectric layer 4 and another dielectric layer. In addition, an interlayer via 6 penetrating the dielectric layer 4 and connected to the land 5 is provided.

層間ビア6は、電気長が無視できる集中定数型の素子であり、周波数応答は無限周波数までフラットであると仮定されている。   The interlayer via 6 is a lumped constant type element whose electrical length is negligible, and the frequency response is assumed to be flat up to an infinite frequency.

一般的に、マイクロ波帯では、層間ビア6の相互インダクタンスは無視される。よって、層間ビア6は、回路性能には影響を与えず、設計においては考慮されなかった。   Generally, in the microwave band, the mutual inductance of the interlayer via 6 is ignored. Therefore, the interlayer via 6 did not affect the circuit performance and was not considered in the design.

ところが、高周波数帯、例えば、ミリ波帯では、層間ビア6の相互インダクタンスが回路に影響を与え始める。   However, in the high frequency band, for example, the millimeter wave band, the mutual inductance of the interlayer via 6 starts to affect the circuit.

つまり、周波数が高くなり、ミリ波やテラヘルツ波領域となると、集積回路内での高周波信号の有効波長が、層間ビア6の物理的な長さと同程度となり、上記仮定が成り立たなくなる。   That is, when the frequency is increased and the millimeter wave or terahertz wave region is entered, the effective wavelength of the high-frequency signal in the integrated circuit becomes approximately the same as the physical length of the interlayer via 6, and the above assumption does not hold.

例えば、層間ビア6のインダクタンスにより、インピーダンスミスマッチを引き起こし、大きな反射損失が発生する。また、このような、インピーダンスミスマッチによる反射損失は、利得、周波数安定性といった総合的なパフォーマンスの低下をもたらす。   For example, the inductance of the interlayer via 6 causes an impedance mismatch and a large reflection loss occurs. Also, such reflection loss due to impedance mismatch results in a decrease in overall performance such as gain and frequency stability.

よって、層間ビア6のインダクタンスが無視できなくなり、設計上の考慮が不可欠となる(非特許文献2)。   Therefore, the inductance of the interlayer via 6 cannot be ignored, and design considerations are indispensable (Non-Patent Document 2).

C.K. Liang et al., JSSC vol 44, no. 2, 2009C.K.Liang et al., JSSC vol 44, no. 2, 2009 C. H. Doan et al., JSSC vol. 40, no. 1, 2005C. H. Doan et al., JSSC vol. 40, no. 1, 2005

本発明は、上記課題に鑑みてなされたものであり、集積回路内の伝送線路と回路素子間に層間ビアを介して高周波の交流信号を伝播でき且つ層間ビアのインダクタンスを補償できる技術を提供することを目的とする。   The present invention has been made in view of the above problems, and provides a technique capable of propagating a high-frequency AC signal via an interlayer via between a transmission line and a circuit element in an integrated circuit and compensating for the inductance of the interlayer via. For the purpose.

上記課題を解決するために、本発明の集積回路内信号伝播構造は、集積回路内の伝送線路を構成する第1金属層と前記集積回路内の回路素子に接続される第2金属層との間に積層される複数の誘電体層と、1つの前記誘電体層と別の前記誘電体層の間に設けられるランドと、前記誘電体層を貫通して前記ランドに接続される層間ビアとを備え、前記第1金属層と第2金属層の間に前記層間ビアと前記ランドを介して交流信号を伝播する集積回路内信号伝播構造において、少なくとも1つの前記誘電体層に前記層間ビアが存在しないことを特徴とする。   In order to solve the above-described problems, the signal propagation structure in an integrated circuit according to the present invention includes a first metal layer constituting a transmission line in the integrated circuit and a second metal layer connected to a circuit element in the integrated circuit. A plurality of dielectric layers stacked in between, a land provided between one dielectric layer and another dielectric layer, and an interlayer via penetrating the dielectric layer and connected to the land A signal propagation structure in an integrated circuit that propagates an AC signal between the first metal layer and the second metal layer via the interlayer via and the land, wherein the interlayer via is provided in at least one of the dielectric layers. It does not exist.

例えば、前記層間ビアが存在する1つ以上の誘電体層の一方側に積層される前記誘電体層に前記層間ビアが存在せず、当該1つ以上の誘電体層の他方側に積層される前記誘電体層に前記層間ビアが存在しない。   For example, the interlayer via does not exist in the dielectric layer stacked on one side of one or more dielectric layers where the interlayer via exists, and is stacked on the other side of the one or more dielectric layers. The interlayer via does not exist in the dielectric layer.

例えば、前記層間ビアが存在しない誘電体層の一方側に積層される誘電体層との間のランドまたは当該一方側に配置される前記第1金属層または第2金属層に接続されるビアと、当該ビアに接続され、当該層間ビアが存在しない誘電体層の他方側に積層される誘電体層との間のランドまたは当該他方側に配置される前記第1金属層または第2金属層に対して当該層間ビアが存在しない誘電体層の一部分を介して対向するランドとを備える。   For example, a land connected to one side of the dielectric layer where the interlayer via does not exist, or a via connected to the first metal layer or the second metal layer disposed on the one side The first metal layer or the second metal layer disposed on the other side or the land between the dielectric layer connected to the via and the dielectric layer laminated on the other side of the dielectric layer where the interlayer via does not exist On the other hand, a land that is opposed to a part of the dielectric layer in which the interlayer via does not exist is provided.

例えば、前記層間ビアが存在しない誘電体層の前記一部分が当該誘電体層の他の部分とは別の材料で形成される。   For example, the part of the dielectric layer where the interlayer via does not exist is formed of a material different from the other part of the dielectric layer.

本発明の集積回路内信号伝播構造によれば、少なくとも1つの誘電体層に層間ビアが存在しないので、層間ビアが存在しない箇所にキャパシタンスが形成され、集積回路内の伝送線路と回路素子間に層間ビアを介して高周波の交流信号を伝播でき且つ層間ビアのインダクタンスをキャパシタンスにより補償できる。   According to the signal propagation structure in an integrated circuit of the present invention, since there is no interlayer via in at least one dielectric layer, a capacitance is formed in a place where the interlayer via does not exist, and between the transmission line and the circuit element in the integrated circuit. A high-frequency AC signal can be propagated through the interlayer via, and the inductance of the interlayer via can be compensated by the capacitance.

図1は、本実施の形態に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。FIG. 1 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to the present embodiment. 図2(a)は、最下層の誘電体層4に層間ビア6が存在しない別の集積回路内信号伝播構造の一部断面図であり、図2(b)は、図2(a)に示す集積回路内信号伝播構造の上面図である。2A is a partial cross-sectional view of another signal propagation structure in an integrated circuit in which the interlayer via 6 is not present in the lowermost dielectric layer 4, and FIG. 2B is a cross-sectional view of FIG. It is a top view of the signal propagation | transmission structure in an integrated circuit shown. 図3(a)は、最下層の誘電体層4に層間ビア6が存在しない別の集積回路内信号伝播構造の一部断面図であり、図3(b)は、図3(a)に示す集積回路内信号伝播構造の等価回路であり、図3(c)は、図3(b)に示す回路および比較例についての周波数と反射減衰値の関係を示す図である。FIG. 3A is a partial cross-sectional view of another integrated circuit signal propagation structure in which the interlayer via 6 does not exist in the lowermost dielectric layer 4, and FIG. 3B is a cross-sectional view of FIG. FIG. 3C is a diagram showing a relationship between the frequency and the return loss value for the circuit shown in FIG. 3B and the comparative example. 図4は、第1の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。FIG. 4 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a first modification. 図5(a)は、第2の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図5(b)は、図5(a)に示す集積回路内信号伝播構造の上面図である。FIG. 5A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a second modification, and FIG. 5B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure. 図6は、第3の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。FIG. 6 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a third modification. 図7(a)は、第4の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図7(b)は、図7(a)に示す集積回路内信号伝播構造の上面図である。FIG. 7A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a fourth modification, and FIG. 7B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure. 図8は、第5の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。FIG. 8 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a fifth modification. 図9(a)は、第6の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図9(b)は、図9(a)に示す集積回路内信号伝播構造の上面図である。FIG. 9A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a sixth modification, and FIG. 9B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure. 集積回路の最上層と最下層を繋ぐ部分の等価回路を示す。The equivalent circuit of the part which connects the uppermost layer and lowermost layer of an integrated circuit is shown. 従来の集積回路に構成される信号伝播構造を示す。1 shows a signal propagation structure configured in a conventional integrated circuit.

以下、本発明の実施の形態について図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は、本実施の形態に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。   FIG. 1 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to the present embodiment.

第1金属層1は、集積回路内の伝送線路を構成し、第2金属層2は、集積回路内の回路素子3に接続される。回路素子3は例えば、ヘテロ接合バイポーラトランジスタ (HBT:Heterojunction Bipolar Transistor)である。回路素子3は例えば、基板30の上に構成され、薄膜トランジスタ31を含む。   The first metal layer 1 constitutes a transmission line in the integrated circuit, and the second metal layer 2 is connected to the circuit element 3 in the integrated circuit. The circuit element 3 is, for example, a heterojunction bipolar transistor (HBT). For example, the circuit element 3 is configured on a substrate 30 and includes a thin film transistor 31.

第1金属層1と第2金属層2の間に複数の誘電体層4が積層される。図では、誘電体層4は4層である。   A plurality of dielectric layers 4 are stacked between the first metal layer 1 and the second metal layer 2. In the figure, the dielectric layer 4 has four layers.

1つの誘電体層4と別の誘電体層の間にランド5が設けられる。また、誘電体層4を貫通してランド5に接続される層間ビア6が設けられる。   A land 5 is provided between one dielectric layer 4 and another dielectric layer. In addition, an interlayer via 6 penetrating the dielectric layer 4 and connected to the land 5 is provided.

すなわち、第1金属層1と第2金属層2の間には、層間ビア6とランド5を介して交流信号を伝播する集積回路内信号伝播構造10が設けられる。   That is, between the first metal layer 1 and the second metal layer 2, a signal propagation structure 10 in an integrated circuit that propagates an AC signal through the interlayer via 6 and the land 5 is provided.

また、集積回路内信号伝播構造10においては、少なくとも1つの誘電体層4に層間ビア6が存在しない。図では、集積回路内信号伝播構造10の最下層の誘電体層4には層間ビア6が存在しない。   In the integrated circuit signal propagation structure 10, the interlayer via 6 does not exist in at least one dielectric layer 4. In the figure, the interlayer via 6 does not exist in the lowermost dielectric layer 4 of the signal propagation structure 10 in the integrated circuit.

図2(a)は、図1の集積回路内信号伝播構造10と同様に最下層の誘電体層4に層間ビア6が存在しない別の集積回路内信号伝播構造の一部断面図であり、図2(b)は、図2(a)に示す集積回路内信号伝播構造の上面図である。   2A is a partial cross-sectional view of another signal propagation structure in an integrated circuit in which the interlayer via 6 does not exist in the lowermost dielectric layer 4 like the signal propagation structure 10 in the integrated circuit of FIG. FIG. 2B is a top view of the signal propagation structure in the integrated circuit shown in FIG.

層間ビア6が存在しない箇所8のキャパシタンスは、最も下のランド5と、第2金属層2とがオーバーラップした領域(図2(b)の斜線部)の面積に依存する。   The capacitance of the portion 8 where the interlayer via 6 does not exist depends on the area of the region where the lowest land 5 and the second metal layer 2 overlap (shaded portion in FIG. 2B).

ここで、その面積を定めるときの計算方法の簡単な例を示す。   Here, a simple example of a calculation method for determining the area will be shown.

最も下のランド5と第2金属層2の距離hを6μm、層間ビア5の径を1μmと仮定する。   Assume that the distance h between the lowest land 5 and the second metal layer 2 is 6 μm, and the diameter of the interlayer via 5 is 1 μm.

この場合、層間ビア5による全インダクタンスは、約80pHであり、300GHzにおいて、そのリアクタンスは、約150Ωである。このインダクタンスを補償するためには、面積Aは、次の式(1)により計算される。   In this case, the total inductance due to the interlayer via 5 is about 80 pH, and at 300 GHz, the reactance is about 150Ω. In order to compensate for this inductance, the area A is calculated by the following equation (1).

A=h/{(2πf)Lε} (1)
ここで、f、L、ε、hは、それぞれ、動作周波数、層間ビア5による全インダクタンス、オーバーラップした領域における誘電体層4の誘電率、最も下のランド5と第2金属層2の距離である。
A = h / {(2πf) 2 Lε} (1)
Here, f, L, ε, and h are the operating frequency, the total inductance due to the interlayer via 5, the dielectric constant of the dielectric layer 4 in the overlapping region, and the distance between the lowest land 5 and the second metal layer 2, respectively. It is.

ε=4、h=1μmを代入すると、式(1)は約100μmとなり、例えば、斜線部は、10μm×10μmの正方形とすればよい。 Substituting ε = 4 and h = 1 μm, equation (1) becomes about 100 μm 2. For example, the hatched portion may be a square of 10 μm × 10 μm.

図3(a)は、最下層の誘電体層4に層間ビア6が存在しない別の集積回路内信号伝播構造の一部断面図であり、図3(b)は、図3(a)に示す集積回路内信号伝播構造の等価回路であり、図3(c)は、図3(b)に示す回路および比較例についての周波数と反射減衰値の関係を示す図である。   FIG. 3A is a partial cross-sectional view of another integrated circuit signal propagation structure in which the interlayer via 6 does not exist in the lowermost dielectric layer 4, and FIG. 3B is a cross-sectional view of FIG. FIG. 3C is a diagram showing a relationship between the frequency and the return loss value for the circuit shown in FIG. 3B and the comparative example.

図3(a)に示す集積回路内信号伝播構造の等価回路は、図3(b)に示すように、第1金属層1と第2金属層2の間を、第1金属層1の抵抗分R、層間ビア6とランド5によるインダクタンスL、層間ビア6が存在しない箇所8のキャパシタンスC、第2金属層2の抵抗分Rを直接接続したものである。 The equivalent circuit of the signal propagation structure in the integrated circuit shown in FIG. 3A has a resistance of the first metal layer 1 between the first metal layer 1 and the second metal layer 2 as shown in FIG. The component R 1 , the inductance L due to the interlayer via 6 and the land 5, the capacitance C of the portion 8 where the interlayer via 6 does not exist, and the resistance component R 2 of the second metal layer 2 are directly connected.

図3(c)の符号Sは、層間ビア6が存在しない箇所において仮に層間ビアを設けた場合の周波数と反射減衰値の関係を示し、符号Sは、図3(b)に示す回路の周波数と反射減衰値の関係を示す。 Symbol S 0 in FIG. 3C indicates the relationship between the frequency and the return loss value when an interlayer via is provided in a location where the interlayer via 6 does not exist, and symbol S 1 indicates the circuit shown in FIG. The relationship between the frequency and the return loss value is shown.

層間ビア6とランド5によるインダクタンスLの高周波数でのリアクタンスが、層間ビア6が存在しない箇所8のキャパシタンスCで補償されるので、反射減衰値は、目的の周波数である300GHzにおいて改善されている。   Since the reactance at a high frequency of the inductance L due to the interlayer via 6 and the land 5 is compensated by the capacitance C of the portion 8 where the interlayer via 6 does not exist, the return loss value is improved at the target frequency of 300 GHz. .

図4は、第1の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。   FIG. 4 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a first modification.

図2の集積回路内信号伝播構造では、最下層の誘電体層4には層間ビア6が存在しないが、層間ビア6が存在しない誘電体層4の位置は任意であり、下から2番目の誘電体層4に層間ビア6が存在しないようにしてもよい。   In the signal propagation structure in the integrated circuit of FIG. 2, the interlayer via 6 is not present in the lowermost dielectric layer 4, but the position of the dielectric layer 4 where the interlayer via 6 is not present is arbitrary, and is the second from the bottom. There may be no interlayer via 6 in the dielectric layer 4.

図5(a)は、第2の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図5(b)は、図5(a)に示す集積回路内信号伝播構造の上面図である。   FIG. 5A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a second modification, and FIG. 5B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure.

図2の集積回路内信号伝播構造では、各誘電体層4の層間ビア6は、直線状に配置されたが、図5に示すように、階段状に配置されていてもよい。   In the signal propagation structure in the integrated circuit of FIG. 2, the interlayer vias 6 of each dielectric layer 4 are arranged in a straight line, but may be arranged in a staircase pattern as shown in FIG. 5.

図6は、第3の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。   FIG. 6 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a third modification.

上記説明では、層間ビア6が存在しない箇所のキャパシタンスCは、式(1)の面積に依存すると述べたが、面積を調整できない場合、例えば、層間ビア6が存在しない誘電体層4を2層以上設けてもよい。   In the above description, the capacitance C where the interlayer via 6 does not exist depends on the area of the expression (1). However, when the area cannot be adjusted, for example, two dielectric layers 4 without the interlayer via 6 exist. You may provide above.

例えば、層間ビア6が存在する誘電体層4の一方側に積層される誘電体層4に層間ビアが存在せず、層間ビア6が存在する誘電体層4の他方側に積層される誘電体層4に層間ビアが存在しない。なお、層間ビア6が存在しない誘電体層4で複数の誘電体層4(層間ビア6が存在する誘電体層4)を挟んだ構造としてもよい。   For example, the dielectric layer 4 laminated on one side of the dielectric layer 4 where the interlayer via 6 exists does not have an interlayer via, and the dielectric is laminated on the other side of the dielectric layer 4 where the interlayer via 6 exists. There are no interlayer vias in layer 4. A structure in which a plurality of dielectric layers 4 (dielectric layers 4 with interlayer vias 6) are sandwiched between dielectric layers 4 without interlayer vias 6 may be adopted.

これにより、キャパシタンスCが直列接続されたこととなり、キャパシタンスCの値を小さくすることができる。すなわち、層間ビア6とランド5のインダクタンスを補償する際の自由度を高めることができる。   As a result, the capacitance C is connected in series, and the value of the capacitance C can be reduced. That is, the degree of freedom in compensating for the inductance of the interlayer via 6 and the land 5 can be increased.

図7(a)は、第4の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図7(b)は、図7(a)に示す集積回路内信号伝播構造の上面図である。   FIG. 7A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a fourth modification, and FIG. 7B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure.

図2では、層間ビア6が存在しない箇所8のランド5と、第2金属層2とがオーバーラップした部分(図2(b)の斜線部)は、層間ビア6より少し大きい程度であったが、図7(b)の斜線部のように、層間ビア6が存在しない箇所8のランド5を大きくすることで、その斜線部を大きくでき、キャパシタンスの値を増加させることができる。   In FIG. 2, the land 5 where the interlayer via 6 does not exist and the portion where the second metal layer 2 overlaps (the hatched portion in FIG. 2B) is slightly larger than the interlayer via 6. However, by enlarging the land 5 of the portion 8 where the interlayer via 6 does not exist, as shown by the shaded portion in FIG. 7B, the shaded portion can be enlarged and the capacitance value can be increased.

よって、層間ビア6とランド5のインダクタンスを補償する際の自由度を高めることができる。   Therefore, the degree of freedom in compensating the inductance of the interlayer via 6 and the land 5 can be increased.

図8は、第5の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図である。   FIG. 8 is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a fifth modification.

図に示すように、層間ビア6が存在しない誘電体層4(最下層)とその一方側(上側)に積層される誘電体層4との間のランド5にビア6Aが接続される。ビア6Aは、誘電体層4を貫通するものでなく、層間ビアとは区別して呼称する。   As shown in the drawing, a via 6A is connected to a land 5 between a dielectric layer 4 (lowermost layer) where no interlayer via 6 exists and a dielectric layer 4 laminated on one side (upper side) thereof. The via 6A does not penetrate the dielectric layer 4 and is referred to as an interlayer via.

また、ビア6Aに接続され、層間ビア6が存在しない誘電体層4(最下層)の他方側に配置される第2金属層2に対して層間ビアが存在しない誘電体層4(最下層)の一部分(符号4A)を介してランド5Aが対向する。符号4Aの部分は、層間ビア6が存在しない誘電体層4(最下層)の他の部分とは別の材料で形成される。   Further, the dielectric layer 4 (lowermost layer) which is connected to the via 6A and has no interlayer vias with respect to the second metal layer 2 disposed on the other side of the dielectric layer 4 (lowermost layer) where the interlayer via 6 does not exist. Land 5A opposes through a part (reference numeral 4A). The portion 4A is formed of a material different from other portions of the dielectric layer 4 (lowermost layer) where the interlayer via 6 is not present.

キャパシタンスCの値は、この材料に依存するので、他の例の場合の値と異ならせることができる。よって、層間ビア6とランド5のインダクタンスを補償する際の自由度を高めることができる。   Since the value of the capacitance C depends on this material, it can be different from the values in the other examples. Therefore, the degree of freedom in compensating the inductance of the interlayer via 6 and the land 5 can be increased.

なお、ビア6Aを第2金属層2側に設け、符号4Aの部分を上の誘電体層4側に設けてもよい。つまり、ビア6Aと符号4Aの部分を逆の配置としてもよい。   The via 6A may be provided on the second metal layer 2 side, and the portion 4A may be provided on the upper dielectric layer 4 side. That is, the via 6A and the reference numeral 4A may be reversely arranged.

なお、このような構造を有する誘電体層4(層間ビア6が存在せず、ビア6Aと符号4Aの部分が存在する誘電体層4)は、最下層以外の別の誘電体層4でもよい。   The dielectric layer 4 having such a structure (dielectric layer 4 in which the interlayer via 6 does not exist and the via 6A and the portion 4A exist) may be another dielectric layer 4 other than the lowermost layer. .

また、符号4Aの部分は、他の誘電体層の部分と同じ材料で形成してもよい。他の部分と同じ材料で形成しても、図2のおけるh1に相当する距離が異なるので、キャパシタンスCの値を異ならせることができ、層間ビア6とランド5のインダクタンスを補償する際の自由度を高めることができる。   Further, the portion 4A may be formed of the same material as the other dielectric layer portions. Even if it is made of the same material as other parts, the distance corresponding to h1 in FIG. 2 is different, so that the value of the capacitance C can be made different, and the freedom in compensating the inductance of the interlayer via 6 and the land 5 can be made. The degree can be increased.

図9(a)は、第6の変形例に係る集積回路内信号伝播構造を有する集積回路の一例を示す一部断面図であり、図9(b)は、図9(a)に示す集積回路内信号伝播構造の上面図である。   FIG. 9A is a partial cross-sectional view showing an example of an integrated circuit having a signal propagation structure in an integrated circuit according to a sixth modification, and FIG. 9B is an integration shown in FIG. It is a top view of the in-circuit signal propagation structure.

図9において、符号5(51)で示すランドは、図の右に延びる伝送線路と一体構成であり、符号5(52)で示すランドは、図の上に延びる伝送線路と一体構成であり、このように、ランドは、いわゆる島状のものでなくてもよい。   In FIG. 9, the land denoted by reference numeral 5 (51) is integrated with the transmission line extending to the right in the figure, and the land denoted by reference numeral 5 (52) is integral with the transmission line extending above the figure. Thus, the land does not have to be a so-called island shape.

以上のように、本実施の形態の集積回路内信号伝播構造によれば、少なくとも1つの誘電体層に層間ビアが存在しないので、層間ビアによるインダクタンスを、層間ビアが存在しない箇所のキャパシタンスで補償でき、インピーダンスミスマッチによる反射損失を低減し、利得、周波数安定性といった総合的なパフォーマンスを改善できる。   As described above, according to the signal propagation structure in the integrated circuit of the present embodiment, since there is no interlayer via in at least one dielectric layer, the inductance due to the interlayer via is compensated by the capacitance at the location where the interlayer via does not exist. It is possible to reduce reflection loss due to impedance mismatch and improve overall performance such as gain and frequency stability.

1 第1金属層
2 第2金属層
3 回路素子
4 誘電体層
5 ランド
6 層間ビア
6A ビア
10 集積回路内信号伝播構造
DESCRIPTION OF SYMBOLS 1 1st metal layer 2 2nd metal layer 3 Circuit element 4 Dielectric layer 5 Land 6 Interlayer via 6A Via 10 Signal propagation structure in integrated circuit

Claims (4)

集積回路内の伝送線路を構成する第1金属層と前記集積回路内の回路素子に接続される第2金属層との間に積層される複数の誘電体層と、
1つの前記誘電体層と別の前記誘電体層の間に設けられるランドと、
前記誘電体層を貫通して前記ランドに接続される層間ビアとを備え、
前記第1金属層と第2金属層の間に前記層間ビアと前記ランドを介して交流信号を伝播する集積回路内信号伝播構造において、
少なくとも1つの前記誘電体層に前記層間ビアが存在しない
ことを特徴とする集積回路内信号伝播構造。
A plurality of dielectric layers stacked between a first metal layer constituting a transmission line in the integrated circuit and a second metal layer connected to a circuit element in the integrated circuit;
A land provided between one of the dielectric layers and another of the dielectric layers;
An interlayer via that penetrates the dielectric layer and is connected to the land,
In the signal propagation structure in an integrated circuit that propagates an AC signal between the first metal layer and the second metal layer through the interlayer via and the land,
The signal propagation structure in an integrated circuit, wherein the interlayer via does not exist in at least one of the dielectric layers.
前記層間ビアが存在する1つ以上の誘電体層の一方側に積層される前記誘電体層に前記層間ビアが存在せず、
当該1つ以上の誘電体層の他方側に積層される前記誘電体層に前記層間ビアが存在しない
ことを特徴とする請求項1記載の集積回路内信号伝播構造。
The interlayer via does not exist in the dielectric layer stacked on one side of one or more dielectric layers in which the interlayer via exists,
2. The signal propagation structure in an integrated circuit according to claim 1, wherein the interlayer via does not exist in the dielectric layer laminated on the other side of the one or more dielectric layers.
前記層間ビアが存在しない誘電体層の一方側に積層される誘電体層との間のランドまたは当該一方側に配置される前記第1金属層または第2金属層に接続されるビアと、
当該ビアに接続され、当該層間ビアが存在しない誘電体層の他方側に積層される誘電体層との間のランドまたは当該他方側に配置される前記第1金属層または第2金属層に対して当該層間ビアが存在しない誘電体層の一部分を介して対向するランドと
を備えることを特徴とする請求項1または2記載の集積回路内信号伝播構造。
A land between the dielectric layer laminated on one side of the dielectric layer where the interlayer via does not exist or a via connected to the first metal layer or the second metal layer disposed on the one side;
To the land between the dielectric layer connected to the via and the dielectric layer laminated on the other side of the dielectric layer where the interlayer via does not exist or to the first metal layer or the second metal layer disposed on the other side 3. The signal propagation structure in an integrated circuit according to claim 1, further comprising: a land facing through a part of the dielectric layer in which the interlayer via does not exist.
前記層間ビアが存在しない誘電体層の前記一部分が当該誘電体層の他の部分とは別の材料で形成される
ことを特徴とする請求項3記載の集積回路内信号伝播構造。
The signal propagation structure in an integrated circuit according to claim 3, wherein the part of the dielectric layer where the interlayer via does not exist is formed of a material different from that of the other part of the dielectric layer.
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