JP2016168106A - Game machine control chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably generate check data of data in a backup area of a RAM without unnecessarily increasing a program capacity.SOLUTION: A game machine control chip includes: a ROM storing a program for controlling a game machine; a central processing unit performing information processing according to the program; a RAM accessed by the central processing unit; a bus connecting the ROM, the central processing unit, and the RAM; and a check data generation circuit which is connected to the bus, generates check data of all data within a prescribed address range of the RAM in response to a prescribed start trigger, and stores the data to a calculation result storage part.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a gaming machine control chip, and more particularly to a gaming machine control chip that automatically generates check data for a backup area of a RAM.

  Conventionally, a gaming machine control chip is mounted on a gaming machine such as a pachinko gaming machine, and the gaming machine is controlled by executing a program in the gaming machine control chip. The gaming machine control chip stores data for backup in a backup memory, a backup area of a RAM, or the like so as not to lose data being processed when the power is turned off. When data is backed up, the CPU calculates check data according to a program in order to confirm whether there is an abnormality in the data, and stores the data and the check data together. When reading backed up data, the CPU calculates the check data of the read data according to the program, compares it with the stored check data, and if the comparison result is the same, there is an error in the backed up data. Judge that there is no.

  Normally, the calculation of check data performed at the time of data backup or reading is executed by the CPU according to a program. Such a program relating to game control, initial data relating thereto, and the like are stored in a ROM built in the gaming machine control chip.

  A storage capacity for storing programs, data, and the like in the built-in ROM of the gaming machine control chip is regulated by various laws. Therefore, in a built-in ROM having a limited storage capacity, the capacity usable for the user program is restricted. With the diversification of game content on gaming machines, the amount of capacity you want to use in the program has increased. However, if the user program is restricted, the game content will also be restricted, so the interest of the game will decline. There is a risk.

  The calculation of the check data of the data to be backed up is started by instructing the CPU by a program. However, for example, when the power is turned off, the check data calculation may not be performed normally unless the start of the check data calculation is instructed at an appropriate timing.

  Therefore, when the CPU executes the check data generation process in the data backup process according to the program, there is a problem that the capacity of the user program is limited and the interest of the game is reduced, and the check data is not normally calculated. There was a problem that there was a possibility.

  In order to solve the above problems, a gaming machine control chip according to the present invention is accessed by a ROM that stores a program for controlling a gaming machine, a central processing unit that executes information processing according to the program, and the central processing unit. RAM, the ROM, the central processing unit, the bus connecting the RAM, and the check data of all data connected to the bus and in a predetermined address range of the RAM in response to a predetermined start trigger And a check data generation circuit that stores the result in the calculation result storage unit.

  The check data generation circuit can be configured to generate check data and store the check data in the calculation result storage unit, and to transmit a signal indicating that the generation of the check data is completed to the central processing unit.

  When the check data is generated, the check data generation circuit reads data from the read start address that is one end of the predetermined address range of the RAM toward the read end address that is the other end. The read start address specifying information for specifying the read start address and the read end address specifying information storing means for storing the read end address specifying information for specifying the read end address, respectively, can be configured. .

  The program stored in the ROM includes a user program defined by the user, and the user program gives a start trigger to the check data generation circuit by the central processing unit executing the user program, and a predetermined address of the RAM. Sequential reading or sequential writing of data within the range is started, and the check data generation circuit acquires data from the data bus at the timing when the central processing unit reads or writes data within the predetermined address range of the RAM. By doing so, it can be configured to generate check data.

  The check data generation circuit can be configured to generate check data by sequentially reading data from the read start address to the read end address of the RAM at a timing when the central processing unit does not access the RAM after receiving the start trigger. The read start address specifying information can be configured to be the value of the read start address, and the read end address specifying information can be the value of the read end address. The read start address specifying information is a value of the start address, and the read end address specifying information can be configured to be information indicating a range length from the read start address to the read end address. The start trigger of the check data generation circuit can be configured to detect that the central processing unit has written data to the read end address of the RAM.

  The program stored in the ROM includes a user program defined by the user. When the central processing unit executes the user program, the read start address specifying information and the read end address specifying information are read from the check data generation circuit, respectively. The address specifying information storage means and the read end address specifying information storage means can be stored. The program stored in the ROM includes a boot program that is executed when the power is turned on. The ROM includes a program management area that stores a setting value that is referred to by the boot program. The program management area includes read start address specifying information and The read end address specifying information is stored, and when the power is turned on, the central processing unit executes the boot program, whereby the read start address specifying information and the read end address specifying information stored in the program management area are respectively checked data generation circuits The read start address specifying information storage means and the read end address specifying information storage means can be stored.

  The program stored in the ROM includes a user program defined by the user, and the central processing unit reads the generated check data from the calculation result storage unit by executing the user program, and executes a predetermined program on the RAM. The check data storage area at the position can be stored. The check data storage area can be configured to be immediately before or immediately after a predetermined address range of the RAM.

  The program stored in the ROM includes a boot program that is executed when the power is turned on, and the central processing unit executes the boot program when the power is turned on to give a start trigger to the check data generation circuit, thereby giving a predetermined address in the RAM. Generate new check data in the range and store it in the calculation result storage unit, read the previously generated check data stored in the check data storage area, and store it in the previously generated check data and calculation result storage unit The new check data can be compared, and the comparison result can be stored in a predetermined area accessible from the user program.

  The predetermined address range of the RAM can be configured to be used as a buffer area for data transmission.

  The predetermined address range of the RAM can be configured to be used as a buffer area for data reception. The received data is sequentially buffered from a buffering start address in a predetermined address range of the RAM, and when it reaches the buffering end address, a predetermined start trigger can be generated for the check data generation circuit. The received data is sequentially buffered from the buffering start address in a predetermined address range of the RAM, and when a code indicating the end of buffering is detected in the received data, a predetermined start trigger is generated for the check data generation circuit. Can be configured.

  The present invention can also be a substrate incorporating the gaming machine control chip described above. The present invention can be configured to include the gaming machine control chip described above and a power-off monitoring circuit that monitors the power supply voltage and provides a start trigger to the check data generation circuit when the power supply voltage falls below a specified value. . The present invention may be a gaming machine including the above board.

  The gaming machine control chip according to the present invention, the gaming machine control chip according to the present invention generates check data of all data within a predetermined address range of the RAM in response to a predetermined start trigger, and a calculation result storage unit Since the check data generation circuit for storing data is stored in the memory, the check data for all the data within the predetermined address range of the RAM can be generated reliably only by giving a predetermined start trigger without unnecessarily increasing the program capacity. Can do.

  Since the check data generation circuit can be configured to transmit a signal indicating that the generation of the check data is completed to the central processing unit, it is possible to cause the central processing unit to perform subsequent processing as soon as the generation of the check data is completed. it can.

  By configuring the check data generation circuit with a logic different from that of the CPU, the execution time is shorter than that executed by the program, the processing time required for backup is shortened, and the stability of the system is improved. Moreover, the response speed at the time of transmission and reception improves by using it for BCC of transmission / reception data.

  Since the check data generation circuit can be configured to have a read start address specification information storage unit and a read end address specification information storage unit, a range to be read for generating check data can be set by writing an address therein. Can be communicated to.

  The central processing unit gives a start trigger to the check data generation circuit by execution of the user program, starts reading or writing data in the check data generation area sequentially, and the check data generation circuit reads or writes data bus Since the check data can be generated by acquiring data from the check data, the check data generation circuit itself does not need to address the RAM when generating the check data, and the configuration of the check data generation circuit can be simplified. .

  Since the check data generation circuit can be configured to sequentially read data from the read start address of the RAM to the read end address at a timing when the central processing unit does not access the RAM after receiving the start trigger, and generate check data. When the generation of check data is started, the check data can be reliably generated regardless of the execution state of the program without interfering with the operation of the central processing unit. Since the start trigger of the check data generation circuit can be a detection that the central processing unit has written data to the read end address of the RAM, generation of check data is started when the update of the entire backup area is completed, It is possible to immediately generate the latest check data for the updated data.

  Since the central processing unit executes the user program, it can be configured to store appropriate values in the read start address specifying information storage unit and the read end address specifying information storage unit of the check data generation circuit. Flexible setting is possible. The central processing unit executes the boot program when the power is turned on, and the data stored in the program management area is stored in the read start address specifying information storage unit and the read end address specifying information storage unit of the check data generation circuit. Therefore, security can be ensured by preventing the user program from handling the data.

  The central processing unit can be configured to read the generated check data from the check data generation circuit and store it in the RAM by executing the user program, so that the user program can be used when the generated check data is required. It can be read and used. Since the check data storage area can be configured immediately before or after a predetermined address range of the RAM, the position of the check data storage area can be easily specified on the RAM.

  The central processing unit executes a boot program when the power is turned on to generate a new check data in a predetermined address range of the RAM by giving a start trigger to the check data generation circuit and store it in the calculation result storage unit. The previously generated check data stored in the check data storage area can be read, the previously generated check data can be compared with new check data stored in the calculation result storage, and the comparison result can be accessed from the user program. Therefore, it is possible to easily and surely check whether there is an abnormality in the data in the backup area when the power is turned on, and to transmit the confirmation result to the user program.

  By using the RAM backup area as a buffer area for data transmission, check data for transmission data can be generated easily and reliably.

  By using the backup area of the RAM as a buffer area for data reception, check data for the received data can be generated easily and reliably, and whether there is an abnormality in the received data can be confirmed. Since the check data generation can be started when the received data is buffered up to the buffering end address, the check data generation can be performed immediately when the data reception of the entire buffer area is performed. Since the check data generation can be started when the code indicating the end of buffering is detected in the received data, the check data generation can be performed immediately after the data reception is completed.

  By using the board in which the gaming machine control chip is incorporated, the various effects described above can be imparted to the board for realizing the gaming function. By installing a power-off monitoring circuit that monitors the power supply voltage and starts check data generation when the power supply voltage drops below the specified value, check data can be generated even in the event of an unexpected power failure. Can do.

It is a figure which shows the external appearance of the game machine system which concerns on the 1st and 2nd embodiment of this invention. It is the block diagram which showed the structure of the gaming machine control chip which concerns on the 1st and 2nd embodiment of this invention. It is a memory map figure of user ROM which the gaming machine control chip concerning the 1st and 2nd embodiments of the present invention has. It is a memory map figure of user RAM which the chip for game machine control concerning the 1st and 2nd embodiment of the present invention has. It is an operation | movement flowchart at the time of the power-down of the chip for gaming machine control which concerns on the 1st and 2nd embodiment of this invention. It is an operation | movement flowchart at the time of the power-on of the chip for gaming machine control which concerns on the 1st and 2nd embodiment of this invention. It is an operation | movement flowchart at the time of the check data generation by the CPU core and check data generation circuit which concern on the 1st Embodiment of this invention. It is an operation | movement flowchart at the time of the check data generation by the check data generation circuit which concerns on the 2nd Embodiment of this invention.

  The configuration of the gaming machine control chip according to the present invention will be described with reference to the drawings. The present invention relates to a first embodiment in which a CPU core and a check data generation circuit cooperate to generate check data, and a second embodiment in which check data is generated by the check data generation circuit without using the CPU core. There is. Hereinafter, unless otherwise specified, the configuration and operation common to the first and second embodiments will be described. First, the configuration of the gaming system related to the chip and the configuration of each chip in the gaming system will be described.

Configuration Figure 1 of the gaming machine system, showing an appearance of a pachinko system 100 according to an embodiment of the present invention. In this embodiment, a pachinko machine will be described as an example of a gaming machine, but it may be replaced with another gaming machine such as a pachislot machine. In FIG. 1, the pachinko system 100 includes two pachinko machines 105 and 110 and a lottery medium supply device (also called a ball lending device or a sand) 115.

  The pachinko machine 105 includes a game board unit 120 that executes a lottery and displays a lottery result, a payout unit 125 that makes a payout according to the lottery result, and a handle unit 130. The pachinko machine 110 has the same configuration as the pachinko machine 105. The pachinko machines 105 and 110 discharge the actual balls from the payout unit 125.

  The lottery medium supply device 115 is a device that supplies a pachinko ball purchased by a player to the pachinko machine 105. The lottery medium supply device 115 includes a coin insertion unit 135 and supplies a pachinko ball, which is a lottery medium, to the pachinko machine 105 in accordance with the coin insertion by the player. The coin insertion unit 135 may be an insertion unit such as a bill or a prepaid card. In this case, the lottery medium is supplied in response to the insertion of a bill or a prepaid card. When the player inserts coins or the like into the lottery medium supply device 115, the lottery medium supply device 115 supplies the number of lottery media corresponding to the amount of coins inserted into the pachinko machine 105. The pachinko machine 105 causes a player to play a pachinko game by using a lottery medium. The handle portion 130 is used by a player to launch a pachinko ball into the pachinko machine 105.

  In the gaming machine system, the gaming board unit 120 and the payout unit 125 are controlled by a gaming machine control chip and a payout control chip mounted on independent boards, respectively. The gaming machine control chip performs ball detection, lottery, payout notification at the time of winning a prize, production control of images and sounds, and the like. Specifically, for example, when a ball payout is required, such as when winning a prize, a payout command is sent to the payout control chip, or when the liquid crystal screen mounted on the gaming machine is controlled, the image control chip The game is controlled by sending an image control command. The payout control chip performs control such as payout other than the processing controlled by the gaming machine control chip. Specifically, for example, a pachinko ball is paid out in response to a payout command from the gaming machine control chip. The present invention is applicable to any of those chips, and is also applicable to other types of chips that require data backup. In the following, a gaming machine control chip will be described as an example.

Configuration of Game Machine Control Chip FIG. 2 is a block diagram of a game machine control chip 200. In the first embodiment of the present invention, the gaming machine control chip 200 includes a CPU core 211, a clock circuit 212, a reset mode control circuit 213, and memory (a boot ROM 214, a user ROM 215, a boot RAM 216, and a user RAM 217). A check data generation circuit 221, a security check circuit 251, an out-of-designated area prohibition (IAT) circuit 252, a watchdog timer (WDT) circuit 253, a unique data storage circuit 254, and a random number circuit 255. , A verification circuit 256 and a bus 261 connecting them. The check data generation circuit 221 according to the first embodiment of the present invention has a configuration in a case where the CPU core 211 reads data to be generated from the RAM from the RAM. The function instruction register 222, the RAM check data calculation circuit 223, a RAM check start address register 224, a RAM check end address register 225, a status register 226, and a calculation result storage register 227. The function instruction register 222 is a register that receives a function instruction command from the CPU core 211, and the RAM check data calculation circuit 223 is a circuit that calculates and generates check data such as a checksum and CRC, and a RAM check start address register. 224 is a register for storing the backup start address of the backup area 402, RAM check end address register 225 is a register for storing the backup end address of the backup area 402, and the status register 226 is an execution state of the check data generation circuit 221 ( The calculation result storage register 227 is a register for storing calculated check data.

  The second embodiment of the present invention has a check data generation circuit 231 in place of the check data generation circuit 221 in FIG. In the second embodiment, the check data generation circuit 231 reads the data for which the check data is to be generated from the RAM without using the CPU core. The check data generation circuit 231 includes a function instruction register 232, a RAM check data calculation circuit 233, a RAM check start address register 234, a status register 236, a calculation result storage register 237, a data pointer 241, and a RAM check byte number counter 242. . The function instruction register 232 is a register that receives a function instruction command from the CPU core 211, and the RAM check data calculation circuit 233 is a circuit that calculates and generates check data such as a checksum and CRC, and a RAM check start address register. 234 is a register for storing the head address of the backup area 402, and the status register 236 is a register for storing a value indicating an execution state (initialization completed, calculation in progress, calculation completed, etc.) of the check data generation circuit 221. The calculation result storage register 237 is a register for storing calculated check data, and the data pointer 241 is a pointer for holding an address when the check data generation circuit 221 accesses the user RAM 217, and the RAM check byte count is counted. The register 242 is a register for storing a value indicating the range length of the backup area 402, and is preferably subtracted according to the number of accesses to the user RAM 217 at the time of check data calculation, and the range of the remaining area to be accessed Indicates length.

  The description returns to the configuration common to the first and second embodiments of the present invention. The CPU core 211 functions as a central processing unit that executes a program stored in the memory, and performs information processing according to the purpose of the program by fetching, decoding, and executing the program stored in the memory. It is the structure to perform.

  The clock circuit 212 is a circuit that generates a system clock signal for operating each element in the gaming machine control chip 200 in synchronization. The clock circuit 212 divides a predetermined reference clock and supplies it as a system clock to the CPU core 211 and internal circuits.

  The reset mode control circuit 213 is a circuit that controls an external system reset, an internal system reset, and an internal user reset input from the system reset terminal. The internal system reset and the internal user reset are generated in response to a watchdog timer time-out signal or an out-of-designated area running prohibition (IAT) generation signal. When a system reset request is made, all internal circuits including the CPU core 211 are initialized. When a user reset request is made, the CPU core 211 and some internal circuits are initialized. Internal system reset and internal user reset operations are selected and set by data in the program management area.

The reset mode control circuit 213 also executes mode control. The reset mode control circuit 213 is a circuit for switching the mode of the gaming machine control chip between the PROM mode, the security mode, and the user mode based on the input of a system reset, the input of a signal requesting the PROM mode, and the result of the security check. Here, each mode will be described.
When the system reset signal is input after the power is turned on and the PROM mode signal is input, the gaming machine control chip shifts to the PROM mode. If the PROM mode signal is not input, the gaming machine control chip shifts to the security mode.
The PROM mode is a mode for the user to write a program to the user ROM 215. Although it can be rewritten by a development gaming machine control chip used at the time of development, it is a mass production gaming machine system mounted on a commercially available gaming machine. In the control chip, writing is possible only once.
The security mode is a mode executed by the boot ROM 214, and is a mode for performing a security check to determine whether or not the program in the user ROM 215 of the gaming machine control chip has been tampered with after the chip is initialized. The security check calculation is performed by a security check circuit 251 described later.
The user mode is a mode for operating the gaming machine according to the user program in the user ROM 215.

  The boot ROM 214 is a ROM that stores a boot program for executing a security check and a chip initialization operation at the time of system reset or power-on. For security, the boot ROM 214 is restricted so that it cannot be accessed except in the security mode.

  The user ROM 215 is a ROM for storing a user program including a game control program and game machine control data for the gaming machine manufacturer to control the operation of the gaming machine.

  The boot RAM 216 is a RAM used when the boot program executes an initialization operation. For security reasons, the boot RAM 216 is restricted so that it cannot be accessed except in the security mode.

  The user RAM 217 is a RAM for use when executing a user program. A check data storage area 217a is provided in one area of the user RAM 217 for storing the backup area 402 and check data 217b for checking whether the data in the backup area is normally stored.

  The security check circuit 251 is a circuit for checking whether or not the information such as the program in the user ROM 215 is authentic in the security mode, and performs a predetermined operation such as a hash operation on the program code in the user ROM 215. This circuit compares the obtained code with the security code in the program management area 302 to confirm whether the adapted program has been altered. At this time, the act of confirming whether the above program has been tampered with is called a security check. Here, the security code is a code in which a result obtained by performing a predetermined operation similar to that at the time of the security check on a code of a program stored in the user ROM 215 is written in advance. As a result of the security check, if the code of the operation result matches the security code, it is determined that the program is a legitimate program, and the user mode is entered. If they do not match, it is determined that the program is not a legitimate program, the gaming machine control chip 200 is stopped, and the gaming machine is not operated.

  The out-of-designated-area travel prohibition (IAT) circuit 252 is a circuit that monitors whether the user program is correctly executed in the designated area set in the program management area. When the user program is executed outside the designated area, an IAT generation signal is output and the CPU core 211 is reset.

  The watchdog timer (WDT) circuit 253 is a timer for monitoring the runaway of the chip. The watchdog timer (WDT) circuit 253 monitors the presence or absence of regular access from the chip, and determines that the chip has runaway if there is no access within a certain time. This is a circuit for causing the CPU core 211 to generate a reset request in response to a timeout signal. The above-described program management area 302 is an area for storing information necessary for executing the user program in the user ROM 215. A system for setting a timeout time in the program management area 302 and resetting the IAT and WDT is provided. It is possible to set whether to perform a reset or a user reset.

  The unique data storage circuit 254 stores a plurality of unique data (ID), and specific information therein can be read from the user program and an external collator.

  The random number circuit 255 is a circuit that generates a random number. For example, the random number circuit 255 can generate a random number using 6 channels of 8-bit random numbers and 4 channels of 16-bit random numbers. The generated random number is used for game lottery and the like.

  The verification circuit 256 is a circuit for connecting to an external verification machine and checking the chip for true cancer by verifying the chip in a predetermined procedure. The collation circuit 256 can output the unique data stored in the unique data storage circuit 254 to the outside under specific conditions.

  The bus 261 connects the CPU core 211 and other elements in the gaming machine control chip 200, and includes a data bus, an address bus, a control signal line, and the like.

Memory Map FIG. 3 shows a memory map of the user ROM 215. The program code area / program data area 301 can be freely set within the indicated address range (0000h to 2FBFh). A user such as a gaming machine manufacturer writes a program for controlling his / her gaming machine in the program code area and the program data area when developing software for the gaming machine. The lower 64 bytes of the user ROM 215 are a program management area 302 for storing information necessary for the gaming machine control chip 200 to execute the user program. Various codes, data for setting internal functions in the chip, illegal modification The information etc. for preventing are stored. Note that the above-mentioned rule restrictions relating to gaming machines are specifically restrictions on the storage capacity of the user ROM 215, the capacity of the control area, the capacity of the data area, and the like. The program management area 302 has a structure that cannot be read from the user program.

  FIG. 4 shows a memory map of the user RAM 217. The user RAM 217 includes a work area 401 used when the CPU core 211 mainly executes a user program and the like, a backup area 402 that is an area of a predetermined address range for storing data to be backed up for use even after the power is turned off, A check data storage area 217 a for storing check data of data stored in the backup area 402 is included. The data to be backed up can be information stored in a register of the CPU core 211, information necessary for game machine control, information indicating a game result, or the like. If these data are backed up when the power is turned off, the game machine can be started by returning to the state before the power is turned off at the time of restart, and the game can be continued from the state before the power is turned off. The check data is used to check whether the data to be backed up has an abnormality such as data corruption during the backup. The user RAM 217 is preferably backed up by a battery, a super capacitor, or the like, and retains data in the RAM even after the power is turned off.

Check Data Generation Start Trigger Next, the check data generation operation of the gaming machine control chip 200 according to the present invention will be described. The check data generation processing for the data in the backup area 402 is started by a predetermined start trigger. As the predetermined start trigger, first, a case where a power supply monitoring circuit (not shown) detects a power-off is considered. The power source for the gaming machine control chip 200 or the like is usually supplied by converting a DC input obtained by rectifying an AC power source to 5 V or the like by a regulator. The power supply monitoring circuit monitors the DC input voltage that enters the regulator. If the voltage drops below a specified value that is considered to be, for example, a power failure, the power monitoring circuit determines that a power failure has occurred and starts the check data generation circuit 221. Apply a trigger. When the power is actually turned off, the input voltage to the regulator drops quickly, but the regulator keeps the voltage of 5V until it drops below the specified value that is considered to be a power cut to the lowest voltage that the regulator can output. Since the gaming machine control chip 200 can be supplied to the gaming machine control chip 200, there is a time margin from the power-off until the gaming machine control chip 200 becomes inoperable. It is preferable to generate check data during this time margin. The start trigger can be performed by a user program by transmitting a non-maskable interrupt (NMI) signal or the like to the CPU core 211, for example. The CPU core 211 starts generation of check data by sending a function instruction command for instructing start of check data generation to the function instruction register 222 of the check data generation circuit 221 by executing a program. It is also possible to start generating check data by sending a predetermined signal directly to the check data generating circuit 221 without passing through the CPU 211.
The above-mentioned NMI signal is a signal mounted on a general CPU core that activates the highest-priority interrupt processing that cannot be interrupt prohibited, but a power-off detection signal is sent to an I / O port or the like from the CPU core periphery. Monitoring with a program that is always executed such as timer interrupt assigned to an input signal, and when a power-off signal is detected, backup processing during power-down can be performed as the highest priority processing for interrupt inhibition.

  As another start trigger, for example, the CPU core 211 sends a function instruction command for instructing start of check data generation to the function instruction register 222 of the check data generation circuit 221 when necessary according to an instruction of the user program. It is also possible to configure to start generating check data. In this case, the check data can be dynamically used in the user program for purposes other than confirmation of data retention accuracy when the power is turned off, such as generation of check data for transmission / reception of communication data.

  As another start trigger, for example, the check data generation circuit 221 monitors memory access such as writing to the user RAM 217 of the CPU core 211, and the check data calculation end address 402b, which is the read end address of the backup area 402, is displayed. When writing is performed, it can be determined that the update of the data in the entire backup area 402 has been completed, and the check data generation circuit 221 can start generating check data. By doing so, it is possible to immediately generate the latest check data for the updated data.

Operation Figure 5 during power-down is an operation flowchart of the power-down the gaming machine control chip 200. When the power monitoring circuit detects a power-off (power-down), it transmits an NMI signal or the like to the CPU core 211 and / or the check data generation circuit 221. In response to this, the check data generation circuit 221 calculates check data of the backup area data (step S501). The detailed operation flow for calculating check data will be described later. When the check data calculation is completed, the check data calculated by the check data generation circuit 221 is written in the check data storage area 217a (step S502). The check data storage area 217a may be a register in the check data generation circuit 221 instead of one area of the user RAM 217.

Operation at power-on FIG. 6 is an operation flow diagram at power-on of the gaming machine control chip. When the gaming machine control chip 200 is powered on, the check data 217b previously calculated and stored is read (step S601). Reading may be performed by the CPU core 211 or the check data generation circuit 221. Next, the check data generation circuit 221 calculates the check data of the backup area data by the same operation as step S501 (step S602). Note that step S601 may be executed after step S602. Next, the CPU core 211 compares the previous check data 217b read in step S601 with the check data calculated in step S602 immediately after power-on (step S603). If the two check data are the same, it is confirmed that there is no abnormality in the data stored in the backup area. In that case, the process moves to step S604, and a process of returning to the state executed when the power is turned off is performed based on the data and work stored in the backup area. On the other hand, if the two check data are different from each other, it means that the data stored in the backup area is abnormal and garbled. Accordingly, the RAM work area 401 and the like are returned to the initial state (step S605).

Detailed operation flow of check data generation (first embodiment: CPU read)
Next, a detailed operation flow of check data generation executed in step S501 and step S602 will be described. FIG. 7 is an operation flowchart when the CPU core 211 and the check data generation circuit 221 cooperate to generate check data according to the first embodiment of the present invention. In the first embodiment, the CPU core 211 sequentially reads the data in the backup area 402 that is the check data generation target according to the program, and the check data generation circuit 221 acquires the data that appears on the data bus at that time to generate the check data. Is. In the first embodiment, when the check data is generated, the check data generation circuit 221 itself does not need to specify the address of the RAM backup area 402, and the RAM data sequentially appearing on the data bus is monitored while monitoring the address bus. Therefore, the circuit configuration of the check data generation circuit 221 can be simplified, and the calculation processing by the CPU is not performed, so that the check data is generated at high speed.

  First, preparation is performed so that check data can be generated. At power-on, initialization of the check data generation circuit 221 is executed (step S701). The initialization is preferably performed by the CPU 211 in accordance with a boot program stored in the boot ROM 214, but the CPU 211 may be performed in accordance with a user program stored in the user ROM 215. The check data generation circuit 221 may execute part or all of the initialization instead of the CPU 211. In the initialization of the check data generation circuit 221, the RAM check start address register 224 stores the check data calculation start address 402a that is the read start address of the backup area 402, and the RAM check end address register 225 stores the read end address of the backup area 402. The check data calculation end address 402b is stored. Here, normally, the value of the check data calculation end address 402b is larger than the value of the check data calculation start address 402a, and the address from the check data calculation start address 402a to the check data calculation end address 402b is generated when the check data is generated. The check data is generated by reading the data of the CPU core 211 while incrementing. However, the value of the check data calculation end address 402b is smaller than the value of the check data calculation start address 402a, and the address is decremented from the check data calculation start address 402a to the check data calculation end address 402b when generating check data. It is also possible to generate check data by reading data from the CPU core 211. The data stored in the RAM check start address register 224 and the RAM check end address register 225 may be information that can specify the range of the backup area 402. For example, the check data calculation start address 402a (address value) Read start address specifying information) and a range length from the check data calculation start address 402a to the check data calculation end address 402b (read end address specifying information as information that can specify an address). Can also be used. It is preferable to configure the check data generation circuit 221 to store a value indicating the completion of initialization in the status register 226 after the initialization is completed.

  When the CPU 211 executes initialization of the check data generation circuit 221 according to the user program, appropriate values are set in the RAM check start address register 224 and the RAM check end address register 225 according to data in the user program. In this case, the user program can flexibly set these addresses.

  When the CPU 211 executes initialization of the check data generation circuit 221 in accordance with the boot program, appropriate values are stored in the RAM check start address register 224 and the RAM check end address register 225 using the data stored in the user ROM 215 or the boot ROM 214. Is set. In this case, those data can be stored in the program management area 302 of the user ROM 215. In this case, since the program management area 302 cannot be accessed from the user program, it is possible to easily manage the data while maintaining security.

  When the check data generation circuit 221 executes part or all of the initialization, it is preferable to write an initialization start command from the CPU core 211 to the function register 222 to instruct the start of initialization.

  Next, an operation for generating check data at the time of power-down will be described. The power supply monitoring circuit that has detected the power down inputs an NMI signal or the like to the CPU core 211, and uses it as a start trigger to start generating check data. As the start trigger, as described above, an instruction from the user program, access to a predetermined address of the CPU core 211, or the like can also be used.

  The CPU core 211 starts execution of a check data creation routine such as a user program by an NMI signal or the like, and performs processing described below. The CPU core 211 creates or updates data to be backed up and stores it in the backup area 402 (step S751). The data to be backed up includes game information that should be taken over by the gaming machine regardless of the power interruption, such as game progress status, lottery and winning data. Note that the CPU core 211 can periodically create, save, and update data to be backed up as appropriate during normal operation by the user program. In such a case, step S751 can be omitted. Next, the CPU core 211 writes a command for instructing generation of check data in the function instruction register 222 (step S752). The check data generation circuit 221 that has detected this command initializes the calculation result stored in the calculation result storage register 227, and starts monitoring the data bus in order to acquire data to be read by the CPU. The check data generation circuit 221 stores a value indicating that calculation is in progress in the status register 226. The CPU core 211 acquires the values of the data calculation start address 402a and the check data calculation end address 402b of the backup area 402 and sets them to function as the start address and end address of the loop (step S753). These values may be obtained from the RAM check start address register 224 and the RAM check end address register 225.

  Next, when the CPU core 211 sequentially reads data in the backup area 402 from the check data calculation start address 402a to the check data calculation end address 402b (step S754), the check data generation circuit 221 appears on the data bus at the same time as reading. Based on this data, the RAM check data calculation circuit 223 accumulates check data using an arithmetic circuit for generating check data. Preferably, the check data generation circuit 221 monitors the address bus, and acquires data appearing on the data bus at the timing when the CPU core 211 is accessing an address in the backup area 402. The check data can be a checksum, a CRC using a generator polynomial, or the like, and can be switched to any one by inputting a command to the function instruction register 222.

  When the CPU core 211 completes the data reading up to the check data calculation end address 402b and the check data generation circuit 221 completes the generation of the check data, the check data generation circuit 221 stores the generated check data in the calculation result storage register 227. At the same time, a value indicating completion of calculation is stored in the status register 226. When the CPU core 211 refers to the value of the status register 226 and confirms that the calculation of the check data is completed, the CPU core 211 reads the check data as the calculation result from the calculation result storage register 227 and stores it in the check data storage area 217a. (Step S755).

The check data storage area 217a is backed up by the battery together with the backup area 402, and keeps the stored value even after the power is turned off. In addition, instead of executing reading from the check data calculation start address 402a, which is the smaller address, toward the check data calculation end address 402b, which is the larger address, reading may be performed in the reverse order. Good.
In the above example, the check data is written by the CPU core 211 reading the result calculated by the check data generation circuit 221 from the calculation result storage register 227 and writing it in the check data storage area 217a. When the check data generation end address 402b is placed at an address (or an address having an arbitrary address relationship), the check data generation circuit 221 may write the calculation result in the check data storage area 217a by cycle steal. Good.

In the above example, the check data generation circuit 221 acquires the data on the data bus read by the CPU core 211 and generates the check data. However, in order for the check data generation circuit 221 to acquire the calculation target data, the data Since the data in the backup area 402 only needs to appear sequentially on the bus, when the backup data once edited by the CPU core 211 is sequentially written in the backup area 402 successively, the check data generation circuit 221 determines the value. May be obtained.
The execution state (initialized, being calculated, calculation completed, etc.) of the check data generation circuit 221 can be read from the status register 226 by the CPU core 211, and the program monitors the status register 226 to check the check data generation circuit 221. Can be read. As a method for the check data generation circuit 221 to notify the CPU 211 of the completion of check data generation, there is a method in which the CPU 211 is interrupted and an interrupt program is started. Thereby, when the check data generation is completed, the CPU 211 can immediately execute the subsequent processing by the interrupt program.

Detailed operation flow of check data generation (second embodiment: circuit reading)
Next, a case where the check data generation circuit 231 generates check data without using the CPU core 211 according to the second embodiment of the present invention will be described. Reference is made to the operational flow diagram of FIG. In the second embodiment, the check data generation circuit 231 acquires the data of the backup area 402 that is the check data generation target, and generates check data. Since the check data generation circuit 231 also accesses the memory, it is preferable to use cycle stealing in which the check data generation circuit 221 accesses the memory when the CPU core 211 is not accessing the memory. In the second embodiment, when the check data is generated, the check data generation circuit 231 itself needs to specify the address of the RAM backup area 402. Therefore, the circuit configuration of the check data generation circuit 231 is slightly complicated. Once the generation of the check data is started, the check data can be generated reliably at high speed regardless of the execution state of the program of the CPU core 211 without interfering with the operation of the CPU core 211. In the operation of cycle steal, the generation of check data is processed at higher speed because it does not involve internal processing such as CPU program read.

  First, preparation is performed so that check data can be generated. At power-on, initialization of the check data generation circuit 231 is executed (step S801). The initialization is preferably performed by the CPU 211 in accordance with a boot program stored in the boot ROM 214, but the CPU 211 may be performed in accordance with a user program stored in the user ROM 215. In addition, the check data generation circuit 231 may execute part or all of the initialization instead of the CPU 211. In the initialization of the check data generation circuit 231, the check data calculation start address 402a that is the read start address of the backup area 402 is stored in the RAM check start address register 234, and the read start of the backup area 402 is started in the RAM check byte number counter 242. A value indicating the range length from the address to the read end address is stored. Here, data is normally read while incrementing the address from the value of the check data calculation start address 402a. However, it is also possible to read data while decrementing the address from the value of the check data calculation start address 402a. It is preferable that a value indicating completion of initialization is stored in the status register 236 after completion of initialization.

  When the CPU 211 executes initialization of the check data generation circuit 231 according to the user program, appropriate values are set in the RAM check start address register 234 and the RAM check byte number counter 242 according to the data in the user program. In this case, the user program can set those values flexibly.

  When the CPU 211 executes initialization of the check data generation circuit 231 in accordance with the boot program, appropriate values are stored in the RAM check start address register 234 and the RAM check byte number counter 242 using the data stored in the user ROM 215 or the boot ROM 214. Is set. In this case, those data can be stored in the program management area 302 of the user ROM 215. In this case, since the program management area 302 cannot be accessed from the user program, it is possible to easily manage the data while maintaining security.

  Next, an operation for generating check data at the time of power-down will be described. As a start trigger, in addition to power down, as described above, an instruction from a user program, an access to a predetermined address of the CPU core 211, or the like can be used. Preferably, the power supply monitoring circuit inputs an NMI signal or the like to the CPU core 211 to prepare backup data.

  The CPU core 211 starts execution of a backup data creation routine such as a user program by an NMI signal or the like, and performs processing described below. The CPU core 211 creates or updates data to be backed up and stores it in the backup area 402 (step S851). The data to be backed up includes game information that should be taken over by the gaming machine regardless of the power interruption, such as game progress status, lottery and winning data. Note that the CPU core 211 can periodically create, save, and update data to be backed up as appropriate during normal operation by the user program. In such a case, step S851 can be omitted. Next, the CPU core 211 writes a command for instructing generation of check data in the function instruction register 232 (step S852). The check data generation circuit 231 that has detected this command initializes the calculation result stored in the calculation result storage register 227, and then at the timing when the CPU core 211 does not output the memory read signal or memory write signal. The RAM check data calculation circuit 234 generates check data based on the data sequentially read out. The check data generation circuit 231 stores a value indicating that calculation is in progress in the status register 236.

  As a specific operation, first, the check data generation circuit 231 holds the value of the data calculation start address 402a stored in the RAM check start address register 234 and the address when the check data generation circuit 231 accesses the memory. Set to data pointer 241. The check data generation circuit 231 reads data at the address in the backup area 402 set in the data pointer 241, and the RAM check data calculation circuit 234 is an arithmetic circuit for generating check data. Generate check data. Next, the value of the RAM check byte number counter 242 is decremented by 1. If it is not zero, the value of the data pointer 241 is incremented. Based on the value of the new data pointer 241, the process returns to the above-described data reading and check data generation, and the processing is continued. On the other hand, if the value of the RAM check byte counter 242 is decremented by one and the value becomes zero, it is determined that the generation of check data for all data in the backup area 402 is completed, and this step is ended. .

  This example is processing when reading from a small address toward a large address, but when reading from a large address toward a small address, the check data is calculated by incrementing the data pointer 241 (reading address). Instead, the data pointer 241 (read address) is decremented to calculate check data. The check data can be a checksum or a CRC using a generator polynomial, and can be switched to any one by inputting a command to the function instruction register 232. When the generation of check data by the check data generation circuit 231 is completed, the check data generation circuit 231 stores the generated check data in the calculation result storage register 237 and also stores a value indicating the completion of calculation in the status register 236. When the CPU core 211 refers to the value of the status register 236 and confirms that the calculation of the check data is completed, the CPU core 211 reads the check data as the calculation result from the calculation result storage register 227 and stores it in the check data storage area 217a. (Step S854). The check data storage area 217a is backed up by the battery together with the backup area 402, and keeps the stored value even after the power is turned off. The check data may be directly stored in the check data storage area 217a by the check data generation circuit 231 without using the CPU core 211.

  In the above-described embodiment, the data pointer is incremented or decremented from the start address stored in the RAM check start address register 234 to the number of counters stored in the RAM check byte number counter 242, and the counter is subtracted each time. The processing is performed until it becomes zero, but instead of the RAM check byte number counter 242, the RAM check start address and the data pointer may be compared each time increment or decrement, and the process may be terminated if they match.

In the above embodiment, the check data generation circuit 231 is activated by a trigger by the program execution of the CPU core 221 after the backup data is generated. However, when the backup area is always generated (backup is required by the gaming machine control program). When necessary data is written to the backup area whenever necessary data is generated, or when data that must be backed up constantly is written to the backup area by timer interrupt processing, etc.) The check data generation circuit 231 may be activated, the control process may be interrupted by an NMI interrupt process or the like, and the check data generation completion may be waited.
In the power-on process, the check data generation circuit 231 is initialized in the security mode, and the gaming machine control program (user program) is executed in the user mode. The check data generation circuit 231 is triggered by the user mode activation. If the activation is performed, the user program may wait for completion of the check data generation, and compare the calculated check data with the check data stored at the time of backup to determine whether there is an abnormality in the backup data.

In the above description, the backup area 402 stores data to be backed up and generates check data for the data to be transmitted / received. However, data to be backed up can be stored in the backup area 402 and the present invention can be used to generate check data for the data. For example, the backup area 402 can be used as a buffer area for data transmission / reception in communication, and check data for buffered transmission data or reception data can be generated. At the time of transmission, the check data can be added to the transmission data as a BCC (block check code), and at the time of reception, the presence or absence of data abnormality can be confirmed by comparing the check data with the transmitted BCC.

  A case where the backup area 402 is used as a transmission buffer will be described. When the transmission data is buffered in the backup area 402, the check data generation circuits 221 and 231 start generating the check data from the buffering start address, and when the check data generation is completed up to the buffering end address, In order to start transmission, a signal indicating that is transmitted to the CPU core 211 via the status register 226 or 236. The check data generation is started after the transmission data is buffered up to the buffering end address. The generated check data is transferred from the check data generation circuits 221 and 231 to the CPU core 211 and added as a BCC after the end area of the transmission data and transmitted.

  A case where the backup area 402 is used as a reception buffer will be described. The check data generation circuits 221 and 231 start generating check data when buffering of received data is started in the backup area 402 and buffered to the buffering end address. It is also possible to detect the moment when the buffering end code (ETX) is buffered, and the check data generation circuits 221 and 231 start generating check data accordingly. . When the generation of the check data is completed, a signal indicating that is transmitted to the CPU core 211 in order to acquire the received data. The generated check data is passed from the check data generation circuits 221 and 231 to the CPU core 211 and used to verify the presence or absence of an abnormality by comparing with the BCC of the received data.

  The present invention can also be realized as a chip that uses backup data or communication data of other types such as a payout control chip and an image control chip having a check data generation mechanism having the same configuration as the gaming machine control chip 200 described above. . In addition, the present invention is established as a board in which those chips are incorporated, and is also established as a gaming machine including the board.

  In the process or operation described above, a process or operation can be freely performed at a certain step as long as there is no inconsistency in the process or operation such as using data that should not be used at that step. Can be changed. Also, steps that do not affect subsequent processing can be omitted. In addition, any step from each embodiment can be combined as long as there is no operational contradiction.

  Each Example described above is an illustration for explaining the present invention, and the present invention is not limited to these Examples. For example, these embodiments can be combined, and two or more embodiments can be combined into one embodiment. The present invention can be implemented in various forms without departing from the gist thereof.

DESCRIPTION OF SYMBOLS 100 Pachinko system 105, 110 Pachinko machine 115 Lottery medium supply apparatus 120 Game board part 125 Payout part 130 Handle part 200 Game machine control chip 211 CPU core 212 Clock circuit 213 Reset mode control circuit 214 Boot ROM
215 User ROM
216 Boot RAM
217 User RAM 217
217a Check data storage area 217b Check data 221 Check data generation circuit (first embodiment)
222 Function instruction register (first embodiment)
223 RAM check data calculation circuit (first embodiment)
224 RAM check start address register (first embodiment)
225 RAM check end address register (first embodiment)
226 Status register (first embodiment)
227 Calculation result storage register (first embodiment)
231 Check data generation circuit (second embodiment)
232 Function instruction register (second embodiment)
233 RAM check data calculation circuit (second embodiment)
234 RAM check start address register (second embodiment)
236 Status register (second embodiment)
237 Calculation result storage register (second embodiment)
241 Data pointer (second embodiment)
242 RAM check byte number counter (second embodiment)
251 Security check circuit 252 Non-designated area travel prohibition (IAT) circuit 253 Watchdog timer (WDT) circuit 254 Specific data storage circuit 255 Random number circuit 256 Verification circuit 261 Bus 301 Program code area / program data area 302 Program management area 401 Work area 402 Backup area

Claims (20)

A ROM for storing a program for controlling the gaming machine;
A central processing unit that executes information processing according to the program;
RAM accessed by the central processing unit;
A bus connecting the ROM, the central processing unit, and the RAM;
A check data generation circuit connected to the bus and generating check data of all data within a predetermined address range of the RAM in response to a predetermined start trigger and storing the check data in a calculation result storage unit A gaming machine control chip characterized by   The check data generation circuit generates the check data, stores the check data in the calculation result storage unit, and transmits a signal indicating that the generation of the check data is completed to the central processing unit. Game machine control chip.   When the check data is generated, the check data generation circuit reads data from a read start address that is one end of the predetermined address range of the RAM toward a read end address that is the other end. A read start address specifying information storage unit for storing the read start address specifying information for specifying the read start address and a read end address specifying information for specifying the read end address, respectively, and a read end address specifying information storing unit for storing the read end address specifying information. Item 3. A gaming machine control chip according to Item 1 or 2. The program stored in the ROM includes a user program defined by a user,
The user program, when the central processing unit executes the user program, gives the start trigger to the check data generation circuit and sequentially reads or writes data within the predetermined address range of the RAM. Is to start,
The check data generation circuit generates the check data by acquiring the data from a data bus at a timing when the central processing unit reads or writes data in the predetermined address range of the RAM. The gaming machine control chip according to any one of 1 to 3.   The check data generation circuit sequentially reads data from the read start address to the read end address of the RAM at a timing when the central processing unit does not access the RAM after receiving the start trigger. The gaming machine control chip according to claim 3, wherein:   6. The gaming machine control chip according to claim 3, wherein the read start address specifying information is a value of the read start address, and the read end address specifying information is a value of the read end address.   6. The game according to claim 3, wherein the read start address specifying information is a value of the start address, and the read end address specifying information is information indicating a range length from the read start address to the read end address. Chip for machine control.   The gaming machine control chip according to claim 3 or 5, wherein the start trigger of the check data generation circuit is detection that the central processing unit has written data to the read end address of the RAM. The program stored in the ROM includes a user program defined by a user,
When the central processing unit executes the user program, the read start address specifying information and the read end address specifying information are respectively stored in the read start address specifying information storage unit and the read end address specifying information of the check data generation circuit. 6. The gaming machine control chip according to claim 3 or 5, which is stored in a storage means. The program stored in the ROM includes a boot program that is executed when the power is turned on,
The ROM includes a program management area for storing setting values referred to by the boot program,
The program management area stores the read start address specifying information and the read end address specifying information,
When the central processing unit executes the boot program when the power is turned on, the read start address specifying information and the read end address specifying information stored in the program management area are respectively set to the read start address of the check data generating circuit. 6. The gaming machine control chip according to claim 3 or 5, which is stored in the specific information storage means and the read end address specific information storage means. The program stored in the ROM includes a user program defined by a user,
The central processing unit reads the generated check data from the calculation result storage unit by executing the user program, and stores the check data in a check data storage area at a predetermined position on the RAM. 3. A gaming machine control chip according to 1 or 2.   12. The gaming machine control chip according to claim 11, wherein the check data storage area is immediately before or after the predetermined address range of the RAM. The program stored in the ROM includes a boot program that is executed when the power is turned on,
The central processing unit executes the boot program when the power is turned on to generate the new check data in the predetermined address range of the RAM by giving the start trigger to the check data generation circuit, and the calculation result While storing in the storage unit, reading the check data generated last time stored in the check data storage area, and comparing the check data generated last time and the new check data stored in the calculation result storage unit The gaming machine control chip according to claim 11, wherein the comparison result is stored in a predetermined area accessible from the user program.   The gaming machine control chip according to claim 1 or 2, wherein the predetermined address range of the RAM is used as a buffer area for data transmission.   The gaming machine control chip according to claim 1 or 2, wherein the predetermined address range of the RAM is used as a buffer area for data reception.   The received data is sequentially buffered from the buffering start address of the predetermined address range of the RAM, and when it reaches the buffering end address, the predetermined start trigger is generated for the check data generation circuit. The gaming machine control chip according to claim 15.   When the received data is sequentially buffered from the buffering start address in the predetermined address range of the RAM and a code indicating the end of buffering is detected in the received data, the predetermined data is detected by the check data generation circuit. The gaming machine control chip according to claim 15, wherein a start trigger is generated.   A board incorporating the gaming machine control chip according to any one of claims 1 to 17. A gaming machine control chip according to any one of claims 1 to 17,
And a power-off monitoring circuit that monitors a power supply voltage and provides the start trigger to the check data generation circuit when the power supply voltage falls below a specified value.   A game machine comprising the substrate according to claim 18.

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