JP2016123803A - Chip for game machine control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip for game machine control which achieves a portion of processing executed by software by hardware included in the chip for game machine control.SOLUTION: The chip for game machine control includes: a central processing part; a memory for having game information about a game written; a game information output circuit including a register and an output signal generation circuit; a bus for connecting the central processing part, the memory, and the game information output circuit; and an output terminal for outputting an output signal. When monitoring the bus to detect that the central processing part writes the game information at a prescribed address of the memory, the game information output circuit acquires the game information to be written to write the game information in the register. The output signal generation circuit generates an output signal on the basis of information of a bit at a prescribed bit position of the game information written in the register, and outputs the output signal from an output terminal.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a gaming machine control chip.

  Conventionally, a gaming machine control chip is mounted on a gaming machine such as a pachinko gaming machine, and the gaming machine is controlled by executing a program of the gaming machine control chip. The gaming machine must be certified by a third party in accordance with the rules of the National Public Safety Commission (rules for gaming machines), and the rules based on the rules are also set for the gaming machine control chip. For example, a program related to game control, data related thereto, and the like are stored in a built-in ROM built in the gaming machine control chip, but the storage capacity for storing the program, the data, etc. is stored in the built-in ROM according to the rules. It is prescribed.

  Due to the above circumstances, the capacity that can be used for the user program is limited in the built-in ROM having a limited storage capacity. Along with the diversification of the game characteristics of gaming machines, the capacity to be used in the program is increasing, but if the user program is restricted, the contents of the game are also restricted, so the interest of the game is reduced. There is a risk that.

  In general, a gaming machine outputs a signal for connection with a number lamp (calling lamp) or a hall computer to an external terminal board (board external terminal board, frame external terminal board, external concentrated terminal board, etc.). The output of the signal is provided as an external I / O of the microcomputer, and is output by software such as a program stored in the built-in ROM. In addition, a similar signal output is provided as an external I / O for a test engine test test. If a part of the processing executed by these software can be realized by processing by hardware built in the gaming machine control chip, it becomes possible to more efficiently use the capacity of a limited program. Furthermore, an IC such as a decoder / buffer has been conventionally required for external I / O, but if it can be realized by hardware processing built in the gaming machine control chip as described above, a decoder / buffer, etc. It is possible to remove the IC from the substrate.

  The present invention realizes a part of processing executed by software in the gaming machine control chip by processing by hardware built in the gaming machine control chip. This makes it possible to provide a gaming machine control chip capable of realizing an amusement-rich game. Furthermore, it is possible to remove ICs such as decoders and buffers for external I / O from the substrate.

  In order to solve the above problems, a gaming machine control chip according to the present invention includes a central processing unit, a memory in which game information relating to a game is written, a game information output circuit including a register and an output signal generation circuit, and a central processing unit. A bus connecting the memory and the game information output circuit, and an output terminal for outputting an output signal. The game information output circuit monitors the bus, and when the central processing unit detects that the game information is written to a predetermined address in the memory, the game information output circuit acquires the written game information and writes it to the register. Can generate an output signal based on the bit information at a predetermined bit position of the game information written in the register and output it from the output terminal. According to the gaming machine control chip, output to the outside can be processed by hardware.

  In the gaming machine control chip according to the present invention, the memory may be a RAM used by the central processing unit when executing a program.

  In the gaming machine control chip according to the present invention, the game information output circuit may include registers corresponding to a plurality of predetermined addresses.

  In the gaming machine control chip according to the present invention, the game information output circuit further includes a cue-structure storage circuit disposed between the register and the output signal generation circuit, and the output signal generation circuit is stored in the cue-structure storage circuit. Then, an output signal can be generated based on the bit information at a predetermined bit position of the game information that is sequentially output and output from the output terminal. According to the gaming machine control chip, loss of information written to the register can be prevented when the register is successively written before the output signal generation circuit generates and outputs the output signal. The storage circuit having a queue structure can be constituted by a first-in first-out (FIFO) counter or a FIFO type memory.

  In the gaming machine control chip according to the present invention, the output signal generation circuit can also generate a predetermined number of pulse signals based on bit information at predetermined bit positions of the game information written in the register.

  In the gaming machine control chip according to the present invention, the output signal generation circuit can also generate a serial output signal based on the game information written in the register.

  In one embodiment of the present invention, the gaming machine control chip can be incorporated into a board, and the board can be included in a gaming machine.

It is a figure which shows the external appearance of the game machine system by the Example of this invention. It is a schematic diagram of each chip in the gaming machine according to the embodiment of the present invention. It is the block diagram which showed the outline of the chip | tip for game machine control by the Example of this invention. It is a figure which shows the memory map of the user ROM which the game machine control chip | tip by the Example of this invention has. It is a figure which shows the flow by which the jackpot signal is output-processed by execution of the conventional program. It is a block diagram explaining the outline | summary of the game machine control chip | tip containing the game information output circuit by the Example of this invention. It is a figure which shows the flow of the data acquisition operation | movement of the game information output circuit by the Example of this invention. It is a figure which shows operation | movement of the game information output circuit when a CPU core writes the static signal which shows a jackpot signal in the predetermined address of RAM. It is a figure which shows operation | movement of the game information output circuit when a CPU core writes the pulse signal which shows a symbol stop signal in the predetermined address of RAM. It is a figure which shows operation | movement of the game information output circuit in case a CPU core writes the continuous pulse signal which shows a prize ball signal to the predetermined address of RAM. It is a figure which shows the functional flow of the pulse generation circuit corresponding to one input position of an output signal generation circuit. It is a figure which shows the functional block of the pulse generation circuit corresponding to one input position of an output signal generation circuit. It is a block diagram explaining the outline | summary of the game information output of the chip for gaming machine control by the Example of this invention.

  A gaming machine control chip according to the present invention will now be described with reference to the drawings. Before that, the configuration of the gaming system related to the chip and the configuration of each chip in the gaming system will be described.

Diagram 1 of the gaming machine system indicates a pachinko system 100 according to an embodiment of the present invention. In this embodiment, a pachinko machine will be described as an example of a gaming machine, but it may be replaced with another gaming machine such as a pachislot machine. In FIG. 1, the system 100 includes two pachinko machines 105 and 110 and a lottery medium supply device (also called a ball lending device or a sand) 115.

  The pachinko machine 105 includes a game board unit 120 that executes a lottery and displays a lottery result, a payout unit 125 that makes a payout according to the lottery result, and a handle unit 130. The pachinko machine 110 has the same configuration as the pachinko machine 105. The pachinko machines 105 and 110 can discharge the actual balls from the payout unit 125.

  The lottery medium supply device 115 supplies the purchased pachinko balls to the pachinko machine 105. The lottery medium supply device 115 has a coin insertion unit 135 and supplies a pachinko ball or medal as a lottery medium to the pachinko machine 105 in accordance with the insertion of a coin by a player. When the lottery medium is supplied in response to insertion of a bill or a prepaid card, the coin insertion unit 135 can be an insertion unit such as a bill or a prepaid card. When the player inserts coins or the like into the lottery medium supply device 115, the lottery medium supply device 115 supplies the lottery medium corresponding to the inserted coins or the like to the pachinko machine 105. The pachinko machine 105 causes the player to play a game in accordance with the lottery medium. The handle portion 130 is used by a player to launch a pachinko ball into the pachinko machine 105.

Configuration of Each Chip in the Gaming Machine System FIG. 2 is a diagram showing an outline of each chip 200 in the gaming machine according to the embodiment of the present invention. In the gaming machine system, the game board unit 120 and the payout unit 125 are each composed of an independent substrate, and each have an independent chip (microprocessor).

  The gaming board 120 is controlled by a gaming machine control chip 215 mounted on the gaming machine control board 210. The payout unit 125 is controlled by a payout control chip 225 mounted on the payout control board 220. The gaming machine control chip 215 is connected to the payout control chip 225.

  The gaming machine control chip 215 performs ball detection, lottery, notification of payout at the time of winning a prize, control of effects such as images and sounds. Specifically, for example, when a payout command is sent to the payout control chip 225 or when a liquid crystal screen (not shown) mounted on the gaming machine is controlled when it is necessary to pay out a ball such as when winning a prize. The game is controlled by transmitting an image control command to an image control chip (not shown). In the embodiment according to the present invention, a desired signal can be output by connecting an external terminal board or a test fire test relay board to the gaming machine control chip 215.

  The payout control chip 225 performs control such as payout other than the processing controlled by the gaming machine control chip 215. Specifically, for example, a pachinko ball is paid out in response to a payout command from the gaming machine control chip 215. In another embodiment according to the present invention, a desired signal can be output to the outside of the gaming machine by connecting an external terminal board or a test firing relay board to the payout control chip 225.

  As one example, the gaming machine control chip and the payout control chip may be configured as a chip set.

Configuration of Game Machine Control Chip FIG. 3 is a block diagram of a game machine control chip 300 according to an embodiment of the present invention. The gaming machine control chip 300 includes a CPU core 310, a memory 320, an external bus interface 330, a clock circuit 332, a verification circuit 334, specific information 336, an arithmetic circuit 338, an address decoder circuit 340, and a reset. Controller 342, mode control circuit 348, security circuit 350, random number circuit 352, free-run counter circuit 354, timer circuit 356, interrupt controller 358, parallel output port 360, parallel input port 362, communication A circuit 364, a game information output circuit 370, and a CPU bus 312 for connecting them are provided.

  The CPU core 310 controls the overall operation of the gaming machine as a central processing unit and incorporates one or more registers. As the register, another dedicated register including an accumulator or a general-purpose register can be used.

  The CPU bus 312 is a bus connected to the CPU core 310 and includes a data bus, an address bus, a control signal, and the like.

  The memory 320 includes a boot ROM 322, a boot RAM 324, a user ROM 326, and a user RAM 328. The boot ROM 322 stores a boot program. The boot program performs security checks and chip initialization. The boot RAM 324 is a RAM when executing the boot program. Since the boot RAM 324 is arranged as a RAM different from the user RAM 328, the boot RAM 324 has a structure that does not affect the information in the user RAM 328, and the user RAM 328 has a structure that does not affect the information in the boot RAM 324. ing.

  The user ROM 326 stores game control programs such as user programs and game machine control data.

  FIG. 4 shows a memory map of the user ROM 326 as one embodiment. The program code area and the program data area can be freely set within the range shown. For example, a user such as a gaming machine manufacturer writes a program for controlling his / her gaming machine in the program code area and the program data area when developing software for the gaming machine. The lower 64 bytes are a program management area for storing information necessary for the CPU core 310 to execute the user program. Various codes, data for setting internal functions in the chip, and information for preventing unauthorized modification. Etc. are stored. Note that the above-mentioned rule restrictions regarding gaming machines mean limitations on the storage capacity of the user ROM 326, the capacity of the control area, the capacity of the data area, and the like shown in this embodiment. The address and size of the illustrated memory map are examples at the time of implementation, and are not limited to this.

  The user RAM 328 is a work RAM used when the CPU core 310 mainly executes a user program or the like. The user RAM 328 can also store information stored in a register of the CPU core 310, information necessary for game machine control, information indicating a game result, and the like. Further, the RAM has a backup function after the power is turned off, and data in the RAM can be stored even after the power is turned off.

  The external bus interface 330 is a bus interface that enhances the direction control and drive capability of the address bus, data bus, and control signals.

  The clock circuit 332 divides a clock input from an EX terminal (not shown) that can be included in the clock circuit, and supplies the divided clock as a system clock to the CPU core 310 and internal circuits. The generated system clock can be output to the outside from a CLKO terminal (not shown) that the clock circuit 332 can have. Further, a clock obtained by dividing the system clock can be output.

  The verification circuit 334 is a circuit that is connected to an external verification machine and performs chip verification (check for true cancer of the chip).

  The unique information 336 includes a plurality of unique information (ID), and the specific information therein can be read from the user program. Further, it is possible to read from the outside via the verification circuit 334.

  The arithmetic circuit 338 is a circuit that performs operations including multiplication and division.

  The address decoder circuit 340 is a decode circuit for an external device of the user program, and outputs a chip select signal.

  The reset controller 342 is a circuit that controls an external system reset, an internal system reset, and an internal user reset input from the system reset terminal. The internal system reset and the internal user reset are generated in response to a watchdog timer time-out signal or an out-of-designated area running prohibition (IAT) generation signal. When a system reset is received, all internal circuits including the CPU core 310 are initialized. When a user reset is accepted, the CPU core 310 and some internal circuits are initialized. Internal system reset and internal user reset are selected and set in the program management area. The watchdog timer 344 is a circuit that monitors a chip runaway and is a circuit that generates a reset as a time-out signal when there is no access within a predetermined time. The above-described program management area is an area for storing information necessary for executing the user program in the user ROM 326, but the timeout time can be selected by setting the program management area. The non-designated area travel prohibition (IAT) 346 is a circuit that monitors whether the user program is correctly executed in the designated area set in the program management area. When the user program is executed outside the designated area, an IAT generation signal is output.

  The mode control circuit 348 is a circuit that switches the mode of the gaming machine control chip between the PROM mode, the security mode, and the user mode based on the input of a system reset, the input of a signal requesting the PROM mode, and the result of the security check. Here, each mode will be described. The PROM mode is a mode in which a program is written in the user ROM 326. In a mass production gaming machine control chip mounted on a commercially available gaming machine, writing can be performed only once. The security mode is a mode for performing a security check to determine whether the program in the user ROM 326 of the gaming machine control chip has been tampered with after the chip is executed by the boot ROM 322 and the chip is initialized. The security check is performed by a security circuit described later. The user mode is a mode in which a gaming machine is operated according to a user program, and is a mode in which a user plays a game at a so-called game hall. When the system reset signal is input after the power is turned on and the PROM mode signal is input, the gaming machine control chip shifts to the PROM mode. If the PROM mode signal is not input, the gaming machine control chip shifts to the security mode.

  The security circuit 350 is a circuit for inspecting whether information such as a program in the user ROM 326 is legitimate in the security mode. The security circuit 350 includes a code obtained by performing a predetermined operation on the program in the user ROM 326, and program management. This is a circuit that checks whether the conforming program has been altered by comparing the security codes in the area. Here, the security code is a code obtained by calculating information such as a program stored in the user ROM 326 by a predetermined calculation formula such as hash calculation. If they match as a result of the comparison, it is determined that the program is a legitimate program, and the mode is shifted to the user mode. If they do not match, it is determined that the program is not a legitimate program, the CPU core 310 is stopped, and the gaming machine does not operate. In addition, by setting the time of this security mode, it can be extended by a fixed time or can be delayed at random within a certain range.

  The random number circuit 352 is a circuit for generating random numbers, and can generate, for example, 6 channels of 8-bit random numbers and 4 channels of 16-bit random numbers.

  The free-run counter 354 performs a counting operation and can be, for example, an 8-bit counter 4 channel.

  The timer circuit 356 is an 8-bit programmable timer and incorporates three channels of 8-bit counters. Real-time interrupt requests and time measurement can be performed by setting the user program.

  The interrupt controller 358 is a circuit that controls external interrupt requests and interrupt requests from built-in peripheral circuits (timer circuit, free-run counter circuit, communication circuit, random number circuit). Interrupt requests can also be masked.

  The parallel output port 360 can be an output port having an 8-bit width, for example, and can be a terminal shared with other functions. The parallel output port 360 can also be configured outside the gaming machine control chip.

  The parallel input port 362 can be, for example, a 6-bit width input port, and some of the input terminals can also be used as other functions. For example, information such as a ball passing sensor can be received by the parallel input port 362. Note that the parallel input port 362 can also be configured outside the gaming machine control chip.

  The communication circuit 364 includes a circuit that performs serial communication asynchronously or synchronously with the external I / O of the gaming machine control chip 300 and external devices.

  The game information output circuit 370 is a hardware circuit for performing the objective function of the present invention, and includes one or more game information output data registers (hereinafter referred to as “data registers”) and an output signal generation circuit 372. When the CPU core 310 writes the game information to a predetermined address in the user RAM 328, the game information data and address are output to the CPU bus 312. As one example, the game information output circuit 370 includes a CPU When writing to a predetermined address is detected on the bus 312, game information data is acquired from the CPU bus 312 and the acquired data is written to the data register. Subsequently, the game information output circuit 370 inputs the data to the output signal generation circuit 372 based on the data stored in the data register. The data register is a register that stores written data, and includes, for example, one or more (for example, eight) flip-flops (for example, D-flip-flops) that store 1-bit data. Further, the game information output circuit is configured such that the input to the output signal generation circuit 372 in the game information output circuit is input in correspondence with the input position of the output signal generation circuit 372 corresponding to a predetermined address of the user RAM. Can. This can be realized, for example, by providing the game information output circuit with data registers corresponding to the respective predetermined addresses and associating each data register with the input position of the output signal generation circuit 372. According to the above embodiment, the game information output circuit can acquire the game information without using the CPU core. Note that the game information output circuit is configured to operate in synchronization with a clock (or a divided clock). In addition, the data register may be configured by a memory circuit, and the data register may be configured to be readable / writable by the CPU.

  The game information output circuit 370 may further include a comparison circuit and a comparison register. The comparison circuit compares the data content written in the data register with the data content in the comparison register. The game information output circuit 370 can set the data in the comparison register to a predetermined value, or if the data in the comparison register is different from the data in the data register, the data in the data register is converted into the comparison register. It can also be written as the previous value. When the game information output circuit 370 includes a comparison circuit, the game information output circuit 370 can be input to the output signal generation circuit 372 based on the comparison result of the comparison circuit, instead of the data stored in the data register. This is suitable for the case where the game information is input to the output signal generation circuit 372 only when the game information has changed a predetermined amount.

  The output signal generation circuit 372 is electrically connected to the data register, and generates an output signal based on bit information at a predetermined bit position of the game information written in the data register. The output signal generation circuit 372 can have a plurality of input positions corresponding to each bit of the data register, and can be configured such that each input position and each bit of the data register are electrically connected. Further, when there are a plurality of data registers, it may be configured to have a plurality of input positions corresponding to each bit of each data register and to electrically connect each input position and each bit of each data register. it can. In addition, the gaming machine control chip can include an output terminal for outputting an output signal. As one embodiment of the output signal output method, the output signal generation circuit 372 generates each waveform based on the bit information at a predetermined bit position of the game information stored in the data register, and outputs it as a parallel signal. It is possible to output from the terminal, or to extract the bit information in order and generate a waveform as one serial signal and output it from the output terminal. As another embodiment, the output signal generation circuit 372 generates a pulse waveform having a predetermined time width and voltage based on an input signal from the data register. It is also possible to generate a quantity of pulses based on the input position of the input signal (trigger signal) and to output from the output terminal based on the input position of the input signal. This can generate a waveform as a parallel signal for each predetermined address (bit) and output it from the output terminal, or combine these signals into one to generate a waveform as a serial signal and output it from the output terminal. it can. The time width and voltage of the pulse waveform, the output terminal position to be output, and the number of pulses to be generated can be set by hardware in the game information output circuit, or can be set in the program management area by the user program or the boot program. It is also possible to set the data placed in the software. As a further embodiment, the output signal generation circuit 372 generates a serial output signal having a predetermined output waveform based on bit information at a predetermined bit position of game information written in the data register, and outputs it from an output terminal. Can be output. The gaming machine control chip and the dedicated IC can further communicate with each other by encrypting the serial output signal by further including an encryption circuit and a decryption circuit.

  As mentioned above, it is output from the gaming machine dedicated chip as a parallel signal, pulse signal or serial signal, but this signal is received by the external device of the gaming machine, and the state of the gaming machine can be grasped externally, and the signal of the test firing test device It can also be used for input information.

  In addition, when the gaming information output of the gaming machine is serial data, the serial output signal is received by communication via the output terminal of the gaming machine control chip by a dedicated circuit (dedicated IC) on the inside or outside board of the gaming machine, After converting to parallel data, the state of the gaming machine can be grasped from the information of each bit.

  Here, there is a possibility that the game information output circuit 370 may successively input signals to the output signal generation circuit 372 before the output signal generation circuit 372 generates an output signal and outputs the output signal from the output terminal. In order to prevent the loss of information due to this, the game information output circuit may further include a queue-structured storage circuit, or the data register may be a FIFO type register. Thus, data to be written to the data register can be accumulated in the queue-structured storage circuit and sequentially input to the output signal generation circuit 372.

Game Information Output of Game Machine Control Chip Hereinafter, game information output in the game machine control chip according to an embodiment of the present invention will be described. First, game information will be described. The game information is game information relating to a game having a predetermined number of bits (generally composed of a plurality of bits), for controlling the gaming machine based on information such as a ball passing sensor received from the parallel input port. Created by the chip. In one embodiment, the game information includes a static signal indicating a jackpot signal, a pulse signal indicating a symbol stop signal, and a continuous pulse signal indicating a prize ball signal.

  Next, the operation of the CPU core will be described. The CPU core stores the game information generated as a result of the game in the game information area, and then writes it in a predetermined address of the user RAM. The user of the gaming machine control chip can set the bit size of the game information, the address of the user RAM that stores the game information, and the like.

  Conventionally, game information stored at a predetermined address of the user RAM has been subjected to a liquid crystal / function output, an external terminal board output, and a test firing test output by executing a program in the CPU core. As an example, FIG. 5 shows a flow in which a jackpot signal is output by a program. The detailed flow of register operations in the CPU core is omitted. The gaming machine control chip is configured to perform a jackpot or a jackpot operation based on information such as a ball passing sensor and output the game information. When operation of the gaming machine is started, when game information according to the status of winning such as big win or small win is output (S501), the game information is stored in the game information area, and then a predetermined address of the user RAM (S502). Subsequently, the stored game information is written in the I / O area set for external output (S503), and is output to the external I / O, and various state output processing is performed (S504). When the game ends, this flow ends (S505). At this time, the signal output to the external I / O is output as a static state output according to the signal attribute by the program, or as a pulse signal or a continuous pulse signal based on a signal whose waveform is formed by timer interrupt processing or the like. It was.

  Next, the operation of the game information output circuit will be described. In the present invention, the game information output circuit performs the external terminal board output and the test firing test output other than the liquid crystal / function output output in a program linked with other operations without using the CPU core. That is, the above-described S503 and S504 are not performed by executing the program, but by the game information output circuit. FIG. 6 shows a schematic diagram of a gaming machine control chip including the game information output circuit, and FIG. 7 shows a data fetch operation flow in the game information output circuit. As shown in FIG. 6, the CPU bus 312 includes a data bus (D0-D7), an address bus (A0-A15), and control signals (RD, WR). Other control signals (chip select signal and address decoder circuit related to the signal) are omitted. When the CPU core 310 writes game information to a predetermined address of the user RAM 328, game information data (D0-D7), predetermined address data (A0-A15) of the user RAM, and a write signal on the CPU bus 312 (WR) is output. Here, the game information output circuit 370 monitors the CPU bus 312 and receives (detects) writing to a predetermined address data in the user RAM 328 (S701), and outputs the game information data written to the predetermined address. Obtain (S702) and write to the data register (S703). Writing to the data register may be configured to write data (8 bits) at a predetermined address as it is, or may be configured to selectively write some bits of data at a predetermined address. The data register has a size capable of storing game information acquired as data.

  The gaming machine control chip performs operations other than those performed by the game information output circuit by executing a program via the CPU core. The program execution mainly consists of instruction fetch (instruction code reading), decoding (instruction code analysis), and instruction execution (operation corresponding to the instruction code). The CPU bus is used for instruction fetch and instruction execution. It will be. The above-described data acquisition in the game information output circuit is an operation at the time of data storage in the RAM when the CPU core executes an instruction. Also, by setting a user program, game information may be written to a data register of the game information output circuit via the CPU core.

  Further, the operation of the game information output circuit will be described. In the first embodiment, when the game information output circuit detects writing to a predetermined address data in the user RAM, the game information output circuit acquires the game information data written to the address, and acquires it in the data register (holding register). The written data is written and input to the output signal generation circuit based on the data stored in the data register. The data register is configured to hold the written bit information until it is newly written. The output signal generation circuit outputs a signal corresponding to each bit information of the data register as a parallel signal based on the bit information stored in the data register, or takes out and arranges each bit information of the data register in order. Output as a serial signal. In any case, the gaming machine control chip has a number of terminals necessary for output. In the case of outputting as a serial signal, the output signal generation circuit can further have an encryption communication function.

  As one of the first embodiments, FIG. 8 is a diagram showing the operation of the game information output circuit 370 when the CPU core 310 writes a static signal indicating a jackpot signal to a predetermined address (eg, “7XX1h”) of the RAM 328. It is. The address “7XX1h” includes 8 bits from bit 0 to bit 7, and each bit corresponds to static output 0 to static output 7, respectively. Only a part of the 8 bits may correspond to the static output. The CPU core 310 writes “1” in the corresponding bit when the jackpot starts and writes “0” in the corresponding bit when the jackpot ends. In this case, the game information output circuit 370 monitors the CPU bus 312 and, when detecting the writing of the address “7XX1h”, the CPU bus outputs “0” or “1” written from bit 0 to bit 7 of the address “7XX1h”. The bit information is acquired from 312 and the bit information is written into bit 0 to bit 7 of the corresponding data register. The output signal generation circuit 372 may have a plurality of input positions corresponding to each bit of the data register, and each input position and each bit of the data register may be electrically connected. The output signal generation circuit 372 generates a static signal waveform based on bit information (bits 0 to 7) stored in the data register and outputs a parallel signal, or outputs a parallel signal. Are sequentially extracted and arranged and output as one serial signal. Thus, in this embodiment, the write data to the RAM can be output to the output terminal without going through the CPU core.

  In the second embodiment, when the game information output circuit detects writing to predetermined address data in the user RAM, the game information output circuit acquires game information data written to the address, and writes the acquired data to the data register. The data register is configured to input the written bit information to the output signal generation circuit as an input signal (trigger signal). The output signal generation circuit generates a pulse waveform having a predetermined time width and voltage based on the input signal, and outputs the pulse waveform from the output terminal based on the input position of the input signal. It can also be configured to generate the number of pulses based on the input position of the input signal. The gaming machine control chip includes an output terminal corresponding to a predetermined address or bit of the user RAM, and can output one pulse waveform or a plurality of pulse waveforms corresponding to each bit of the user RAM.

  As one of the second embodiments, FIG. 9 shows the operation of the game information output circuit 370 when the CPU core 310 writes a pulse signal indicating a symbol stop signal to a predetermined address (eg, “7XX2h”) of the RAM 328. FIG. The address “7XX2h” is composed of 8 bits from bit 0 to bit 7, and each bit corresponds to pulse output 0 to pulse output 7, respectively. Only a part of the 8 bits may correspond to the pulse output. The CPU core 310 writes “1” in the corresponding bit every time the symbol is stopped (“0” is not written). In this case, when the game information output circuit 370 detects the writing of the address “7XX2h” by monitoring the CPU bus 312, the bit information (“1”) written from the bit 0 to the bit 7 of the address “7XX2h” is stored in the CPU. Of the data register corresponding to the predetermined address “7XX2h” acquired from the bus 312, “1” is written into the bit corresponding to the bit in which “1” is written at the address “7XX2h”. Subsequently, the game information output circuit 370 inputs the bit information written in the data register to the input position of the output signal generation circuit 372 corresponding to bit 0 to bit 7 of the address “7XX2h”. That is, here, “1” is input only at the input position of the output signal generation circuit 372 corresponding to the bit in which “1” is written in the data register. The output signal generation circuit 372 generates one 1-pulse waveform having a predetermined time width and voltage every time “1” is input. It can also be output to a predetermined output terminal corresponding to the input position. In this way, in this embodiment, one pulse can be output to the output terminal without going through the CPU core.

  Further, as one of the second embodiments, FIG. 10 shows a game information output circuit 370 when the CPU core 310 writes a pulse continuous signal indicating a prize ball signal to a predetermined address (for example, “7XX3h”) of the RAM 328. FIG. The address “7XX3h” is composed of 8 bits from bit 0 to bit 7, and each bit corresponds to pulse output 0 to pulse output 7, respectively. Only a part of the 8 bits may correspond to the pulse output. The CPU core 310 writes “1” in the bit according to the number of winning balls (“0” is not written). Here, the CPU core 310 executes a write command to the RAM 328 such that one pulse is output for every ten winning balls, and for example, when “1” is written in a certain bit of the RAM 328, two pulses are output and another one bit is output. When “1” is written, 3 pulses are output. In this case, when the game information output circuit 370 detects the writing of the address “7XX3h” by monitoring the CPU bus 312, the bit information (“1”) written from the bit 0 to the bit 7 of the address “7XX3h” is stored in the CPU. Of the data register corresponding to the predetermined address “7XX3h” acquired from the bus 312, “1” is written to the bit corresponding to the bit in which “1” is written at the address “7XX3h”. Subsequently, the game information output circuit 370 inputs the bit information written in the data register to the input position of the output signal generation circuit 372 corresponding to bit 0 to bit 7 of the address “7XX3h”. That is, here, “1” is input only at the input position of the output signal generation circuit 372 corresponding to the bit in which “1” is written in the data register. Each time “1” is input, the output signal generation circuit 372 generates a pulse waveform having a predetermined number corresponding to the input position, a predetermined time width and voltage. It is also possible to output to a predetermined output terminal corresponding to the input position. In this way, in this embodiment, when the CPU core commands the continuous pulse output, it is possible to output the continuous pulse to the output terminal without going through the CPU core. The game information output circuit can further include a data register corresponding to a predetermined address (for example, “7XX4h”, etc.), and bit information is input to the input position of the output signal generation circuit corresponding to each bit of each data register. Can be configured to input. With such a configuration, various types and numbers of pulses corresponding to the input position can be generated.

  FIG. 11 shows a functional flow of the pulse generation circuit 374 corresponding to one input position of the output signal generation circuit 372 according to one embodiment in the second example. The output signal generation circuit can comprise one or more pulse generation circuits. Note that the initial value of the output signal generation circuit (pulse generation circuit) is set, for example, the initial value of the pulse count number, the initial value of the pulse output value (voltage), the setting of the pulse width time (T1), or the pulse The setting of the interval width time (T2) may be fixed by a hardware circuit, but can also be performed by a program (user program or boot program) through the CPU bus. When holding data (“1”) from the data register is received (S1101), the counter is activated and an initial value of the pulse count number is set (S1102). Subsequently, an initial value is set to the output value, and output of the initial value is started. (S1103). Here, it is assumed that the signal before the start of output is “0 (0 V)” and the signal after the start of output is “1 (5 V)”, but the signal may be reversed. When output is started, time (T1) counting with a predetermined pulse width is started (S1104), and the output signal is inverted when T1 elapses (S1105). The inversion of the output signal means that when the original output is “0”, the output is “1”, and when the original output is “1”, the output is “0”. Subsequently, a time (T2) count of a predetermined pulse interval width is started (S1106), and the pulse count number is updated (S1107). In this flow, since the counter is a down counter, the number of times is "-1" when updated. When the pulse count reaches “0” (S1108), the pulse output is terminated (S1109). If the pulse count is not “0” (S1108), pulse generation is continued. The above operation is continued until the pulse count number becomes “0”.

  FIG. 12 is a functional block diagram of the pulse generation circuit 374 corresponding to one input position of the output signal generation circuit 372 according to one embodiment in the second example. When “1” is written to the register, the pulse generation circuit 374 activates the counter and sets the pulse count number in the initial value of the number of pulses. Subsequently, the output of the initial value is started by setting the initial value to the output value by the initial value setting, the pulse width T1 is set by the initial value of the pulse width T1, and the pulse width time T1 is measured by the pulse width T1 counter. Start. The game information output circuit 372 is preferably configured to operate in synchronization with a clock (or a divided clock), and in this case, the pulse width T1 (T2) counter performs measurement using the divided clock. . When the pulse width time T1 elapses, the output data is inverted by data inversion, the pulse width T2 is set by the initial value of the pulse width T2, and measurement of the pulse width time T2 is started in the pulse width T2 counter. When the pulse width time T2 elapses, the pulse count number is updated by the pulse number counter and the initial value of the data is used as the output value. When the pulse count number reaches “0”, the pulse output is terminated. When the pulse count number is “1” or more, the pulse generation is continued until the pulse count number becomes “0”. Each pulse generation circuit 374 of the output signal generation circuit 372 can further include a status register indicating whether or not a pulse is being output.

  In these first and second embodiments, the game information output circuit can further include a storage circuit having a queue structure. The game information output circuit stores the game information data written in the data register in a storage circuit having a queue structure. The queue-structure storage circuit sequentially inputs the accumulated bit information to the output signal generation circuit. When each bit of the data register and each input position of the output signal generation circuit are electrically connected to each other, the storage circuit having the queue structure can be arranged for each bit or for each byte. It can also be arranged. For example, when a queue-structure storage circuit is arranged between bit 0 of the data register for the address “7XX3h” in FIG. 10 and the corresponding input position of the output signal generation circuit, the queue-structure storage circuit is the same as that shown in FIG. By detecting the end of pulse output, it is possible to sequentially input “1” input signals to corresponding input positions of the output signal generation circuit. In this case, the queue-structure storage circuit may be configured to sequentially input “1” input signals to the output signal generation circuit based on the status register. The storage circuit having a queue structure may be configured by a FIFO counter or a memory (register) having a queue structure in which “1” is added when “1” is input and “1” is subtracted when “1” is transferred. it can. The FIFO counter is used when a queue structure storage circuit is arranged for each bit, and the FIFO memory can be used when a queue structure storage circuit is arranged for each byte. A configuration may be used in which only a portion of bits is used. As a further modification, the game information output circuit may further include a queue-structured storage circuit, and the data register may be a FIFO register. In the embodiment including the storage circuit of these queue structures, the game information output circuit is prevented from inputting the output signal generation circuit one after another before generating the output signal in the output signal generation circuit and outputting it from the output terminal. This is effective in that information can be stored in a storage circuit having a queue structure.

  The embodiment centering on the operation of the game information output circuit has been described above. FIG. 13 is a block diagram for explaining the outline of the game information output of the gaming machine control chip according to one embodiment. The game information output circuit 370 includes a data register A, a data register B, and a data register C corresponding to a predetermined address of the user RAM. The output signal generation circuit 372 includes an output signal generation circuit A that generates a waveform of static output, An output signal generation circuit B that generates a waveform of a pulse output (including a continuous pulse) and an output signal generation circuit C that generates a waveform of a serial data output are included. The output signal generation circuit C can include an encryption circuit. When the game information output circuit 370 detects writing to a plurality of predetermined addresses of the user RAM 328 of the CPU core 310 by the CPU bus 312, the game information output circuit 370 acquires game information data from the CPU bus 312, and acquires the acquired data for each predetermined data. Write to data register A, data register B, or data register C corresponding to the address. As one embodiment, data written to all bits of the data register A is data for static output, data written to all bits of the data register B is data for pulse output, When the data written in all the bits is the serial signal output target data, the input positions of the output signal generation circuits A, B, and C are electrically connected to the bit positions of the data registers A, B, and C, respectively. With this configuration, the output signal generation circuits A, B, and C can perform static output, pulse output, and serial signal output based on each bit information written in the data registers A, B, and C, respectively. it can. As another embodiment, when the data written to some bits of the data register A is data for static output, and the data written to the remaining some bits is data for pulse output, an output signal is generated. The input position of the circuit A is electrically connected to each bit position of the data register A to which the data to be static output is written, and the input position of the output signal generation circuit B is the data register A to which the data to be pulse output is written. By being configured to be electrically connected to each bit position, the output signal generation circuits A and B can perform static output and pulse output based on each bit information written in the data register A, respectively. it can. As another example, when data written to all bits of the data register A is data for static output, and data written to all bits of the data register B is data for pulse output, The input positions of the output signal generation circuits A and B are configured to be electrically connected to the bit positions of the data registers A and B, respectively, and the input positions of the output signal generation circuit C are the data registers A and B. The output signal generation circuits A, B, and C are configured to be statically output based on the bit information written in the data registers A and B, respectively. Pulse output and serial signal output can be performed. In this case, the predetermined bit position of the data register A or the data register B is electrically connected to each input position of the output signal generation circuit A or the output signal generation circuit B, and the input position of the output signal generation circuit C. Can be configured to be electrically connected to each other. Thus, the data written in the data registers A and B generates a static or pulse waveform via the output signal generation circuit A or the output signal generation circuit B, and at the same time configures a serial output via the output signal generation circuit C. However, the data written in all the data registers A, B, and C may be output by serial communication without going through the output signal generation circuit A or the output signal generation circuit B. In this case, there is an effect that an output terminal for static output or pulse output can be omitted.

  The output signals output from each of the output signal generation circuits described above can be received by a gaming machine external device such as an external terminal board or a relay board through communication via the output terminal. The gaming machine external device can restore the data written in the data register of the gaming information output circuit 370 from the received signal. As a result, the state of the gaming machine can be ascertained externally, and the signal can be used as input information for a hall computer, a number lamp (calling lamp), and a test firing test apparatus. When the output signal is serial data, the state of the gaming machine can be grasped by the information of each bit by converting it into parallel data by a dedicated circuit (dedicated IC) of the relay board or the gaming machine external device. If the output signal generation circuit C is encrypted, the above process is performed after decryption by a dedicated circuit (dedicated IC).

  In the above embodiments, the address at which the game information output circuit detects writing is on the RAM (user RAM), but the address to be detected may be an address other than the RAM or may be allocated on an arbitrary memory. In the case of allocation on the RAM, the data written in the data register can be read as data on the RAM by assigning a detection address to a data storage area on the work RAM in executing the program.

  As described above, by outputting the game information from the gaming machine control chip, the capacity of the user ROM program can be reduced. In addition, as described above, conventionally, since an I / O area set for external output is passed through a decoder / buffer for external I / O output, an IC for that purpose is required on the substrate. According to the gaming machine control chip, since the output signal generation circuit outputs a signal from the output terminal, the IC can be removed from the substrate. Conventionally, game information is directly output to the connector as a parallel signal from an IC such as a buffer on the board. However, according to the gaming machine control chip according to the present invention, a serial signal is output by the output signal generation circuit. With the configuration, it is possible to reduce the wiring between the board and the external terminal board connection connector and the wiring between the board and the relay board connection connector for the trial test. Furthermore, in the past, a circuit corresponding to the parallel signal from the connection connector had to be prepared on the external terminal board or the relay board for the trial test, but a configuration in which a serial signal is output by the output signal generation circuit as described above. By doing so, the external terminal board and the like can be made simple. At this time, the output serial signal can be further encrypted by the output signal generation circuit. If a decryption circuit etc. is provided on the external terminal board or relay board for trial test, the signal can be concealed and illegal modification or signal It becomes difficult to tamper.

  In the process or operation described above, a process or operation can be freely performed at a certain step as long as there is no inconsistency in the process or operation such as using data that should not be used at that step. Can be changed.

  Each Example described above is an illustration for explaining the present invention, and the present invention is not limited to these Examples. For example, these embodiments can be combined, and two or more embodiments can be combined into one embodiment. The present invention can be implemented in various forms without departing from the gist thereof.

DESCRIPTION OF SYMBOLS 100 Pachinko system 105, 110 Pachinko machine 115 Lottery medium supply apparatus 120 Game board part 125 Delivery part 130 Handle part 200 Each chip 210 Game machine control board 215 Game machine control chip 220 Delivery control board 225 Delivery control chip 300 For game machine control Chip 310 CPU core 312 CPU bus 320 Memory 322 Boot ROM
324 Boot RAM
326 User ROM
328 User RAM
330 External bus interface 332 Clock circuit 334 Verification circuit 336 Specific information 338 Operation circuit 340 Address decoder circuit 342 Reset controller 344 Watchdog timer 346 Out-of-area travel prohibition (IAT) circuit 348 Mode control circuit 350 Security circuit 352 Random number circuit 354 Free Run counter circuit 356 Timer circuit 358 Interrupt controller 360 Parallel output port 362 Parallel input port 364 Communication circuit 370 Game information output circuit 372 Output signal generation circuit 374 Pulse generation circuit

Claims (9)

A central processing unit;
A memory in which game information about the game is written;
A game information output circuit including a register and an output signal generation circuit;
A bus connecting the central processing unit, the memory, and the game information output circuit;
A gaming machine control chip comprising an output terminal for outputting an output signal,
The game information output circuit monitors the bus, and when the central processing unit detects that the game information is written to a predetermined address of the memory, acquires the game information to be written and writes it to the register And
The output signal generation circuit generates an output signal based on bit information at a predetermined bit position of the game information written in the register and outputs the output signal from the output terminal. Tip for your use.   The gaming machine control chip according to claim 1, wherein the memory is a RAM used by the central processing unit when executing a program.   The gaming machine control chip according to claim 1, wherein the gaming information output circuit includes each of the registers corresponding to a plurality of the predetermined addresses. The game information output circuit further includes a storage circuit having a queue structure disposed between the register and the output signal generation circuit,
The output signal generation circuit is configured to generate an output signal based on bit information at a predetermined bit position of the game information that is accumulated and sequentially output in the storage circuit having the queue structure, and outputs the output signal from the output terminal. The gaming machine control chip according to any one of claims 1 to 3.   5. The gaming machine control chip according to claim 1, wherein the storage circuit having the queue structure includes a FIFO counter or a FIFO type memory.   6. The output signal generation circuit according to claim 1, wherein the output signal generation circuit generates a predetermined number of pulse signals based on bit information of a predetermined bit position of the game information written in the register. Game machine control chip.   6. The gaming machine control chip according to claim 1, wherein the output signal generation circuit generates a serial output signal based on the game information written in the register.   A board incorporating the gaming machine control chip according to any one of claims 1 to 7.   A gaming machine including the board according to claim 8.

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