JP5985196B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, and more particularly to a gaming machine capable of performing a predetermined game and giving a predetermined game value based on a game result.

  As a gaming machine, when a game medium such as a game ball is launched into a game area by a launching device, and the game medium wins a prize area such as a prize opening provided in the game area and a start condition is satisfied, a plurality of types of identification are made. There is a pachinko gaming machine in which information (hereinafter referred to as a display symbol) is variably displayed on a variable display device, and the game interest is enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on the display result. . In such a pachinko gaming machine, a specific game state (big hit game state) advantageous to the player is obtained when the stop symbol mode when the variable display of the display symbol in the variable display game is completely stopped becomes the specific display mode. . For example, a pachinko gaming machine that has become a big hit game state has a special electric accessory called a big prize opening or an attacker opened, and a state where a player can easily win a game ball for a certain period of time continuously. provide.

  In addition, after setting a predetermined number of bets for one game using a game medium such as a medal, a coin, or a game ball similar to a pachinko gaming machine, the player operates the start lever to display on the variable display device. The variable display of the display symbol is started within the range of the maximum delay time determined in advance from the operation timing by starting the variable display of the symbol and the player operating the stop button provided corresponding to each variable display device. And a winning is generated according to the display result derived when the variable display of all the variable display devices is stopped, and a predetermined game medium predetermined according to the winning is paid out, and a specific winning is generated. In some cases, there is a slot machine configured to change the gaming state to a state in which a predetermined gaming value is given to the player.

  As such a gaming machine, when power supply stops (instantaneous power failure) in a short period of time, a timer (watchdog timer) for measuring a predetermined monitoring time is timed out to reset the gaming control microcomputer. Has been proposed (for example, Patent Document 1).

Japanese Patent Laid-Open No. 2007-190095

  In the technique described in Patent Document 1, resetting is performed by executing processing (initialization processing) that periodically clears and restarts the count value of the timer even during execution of the game control processing that controls the progress of the game. It is prevented from being done. Therefore, there is a problem that the control burden for controlling the progress of the game becomes large.

This invention has been made in consideration of the above, an object while reducing the control load for the control progress of the game, to provide a gaming machine which can be recovered appropriately from stop instantaneous power supply And

(1) In order to achieve the above object, the gaming machine according to the present invention can play a game and give a game value (for example, paying out a game ball or medal, a score corresponding to these, a jackpot gaming state, a probability variation state, etc.) a become game machine (e.g., a pachinko game machine 1 and the slot machine, etc.), after executing initialization processing based on the stored contents of the nonvolatile memory (e.g., etc. security check processing), the progress of the game in accordance with a control program A game control microcomputer (for example, a game control microcomputer 100 including a CPU 505) that executes a game control process (for example, a game control main process, a process of steps S91 to S98 that is a game control timer interrupt process), and the like ) And monitoring the state of the predetermined power source used in the gaming machine, Power supply monitoring means (for example, the power supply monitoring circuit 303) that outputs a detection signal (for example, a power-off signal) based on the fact that the detection condition is satisfied (for example, the voltage value of the + 30V power supply has decreased to + 22V), Reset means (for example, reset controller 504A or watchdog timer) that measures a predetermined monitoring time (for example, timeout time) and resets the gaming control microcomputer when it is measured that the monitoring time has elapsed. 520), reset setting means (for example, reset setting KRES and WDT control circuit 533 in the program management area of the ROM 506) for setting to enable or disable the operation of the reset means in accordance with the control program, and power to the gaming machine When the supply is started, The source includes a start determination means for determining whether the detection signal is output from the monitoring means, when the power supply to the gaming machine is started, a start time setting means for setting said reset means, The monitoring time measured by the reset means is initialized by writing a predetermined value in accordance with a control program, and the gaming control microcomputer performs processing when power supply is stopped according to a detection signal from the power supply monitoring means. When shifting to a standby state (for example, a state in which an infinite loop process is performed after executing the process of step S53) after executing (for example, the main-side power-off process in step S52), the reset setting means After the operation of the reset means is validated, the power interruption time control means (for example, the processing of step S53) for shifting to the standby state. The CPU 505 of the game control microcomputer 100 for executing the processing), security check means for executing a security check for checking whether or not the storage content of the nonvolatile memory has been changed in the initial setting process, and the initial setting Including a period setting unit that can variably set the processing period, and the predetermined value is not written in the standby state, and when the detection signal from the power supply monitoring unit is not input after the transition to the standby state, The monitoring time measured by the reset means is not initialized.
According to such a configuration, it is possible to appropriately recover from the instantaneous power supply interruption while reducing the control burden for controlling the progress of the game .

(2) In the gaming machine of (1), the monitoring time measured by the reset means can be set from a plurality of predetermined types (for example, bit number [5-4] of reset setting KRES) And a part for setting a timeout time as shown in FIG. 8B by the value of the bit number [3-0]), the reset setting unit operates as the reset unit operates in accordance with the execution of the power supply stop process. when enabled, the when the process may be set the maximum time that can be set as the monitoring time (e.g., step S53 is executed, WDT control circuit 533 2 timeout period ²⁵ based on the reset setting KRES × T _SCLK × 15 etc.)
In such a configuration, the longest time that can be set as the monitoring time measured by the reset means is set, so that when the power supply is completely stopped for a predetermined period due to a power switch disconnection or the like, it is erroneously reset. Can be prevented.

(3) In the gaming machine according to (1) or (2), the gaming control microcomputer is reset by the resetting unit after the monitoring time has elapsed after executing the power supply stop process. Reset information storage means (for example, bit number [1] of a built-in register that stores internal information data CIF) and the like, and when the predetermined initial setting process is executed, When it is determined that the reset information is stored by a reset information determination unit (for example, the CPU 505 that executes the process of step S72) that determines whether the reset information is stored, the reset information Post-reset activation control means (e.g., step) for invalidating the operation of the reset means by setting means The process of 74, such as CPU505 to perform) and may contain.
In such a configuration, if the reset information is stored when the initial setting process is performed, the operation of the reset unit is invalidated to prevent inadvertent resetting.

(4) In the gaming machine of any one of (1) to (3), the gaming control microcomputer writes a plurality of data having different values in a predetermined storage area in a predetermined order, so that the reset means A measurement initialization unit that initializes the measured time may be included (for example, a portion that sequentially writes “55H” and “AAH” in the WDT clear register WCL in the process of step S25C).
In such a configuration, the time measured by the reset means is not initialized unless a plurality of data having different values are written in a predetermined order. Therefore, the measurement time is erroneously initialized due to noise or the like when the power supply instantaneously stops. Can be prevented.

It is a front view of the pachinko gaming machine in this embodiment. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko game machine. It is a block diagram which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which illustrates the main part of a program management area and a built-in register area. It is a figure which shows an example of the setting content in a header and reset setting. It is a figure which shows an example of the setting content in the interruption initial setting, the 16-bit random number initial setting 1st, and the 16-bit random number initial setting 3rd. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the structural example of a watchdog timer. It is a figure which shows the structural example etc. of a WDT start register. It is a figure which shows the structural example etc. of a WDT clear register. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is a figure which shows the operation example which changes a random number sequence update rule with software. It is a figure which shows the operation example which changes a random number sequence update rule automatically. It is a figure which shows the structural example of a random number maximum value setting register. It is a figure which shows the structural example etc. of a hard latch selection register. It is a figure which shows the structural example etc. of a random number hard latch flag register. It is a figure which shows the structural example etc. of a hard latch interrupt control register. It is a figure which shows the structural example etc. of a random number soft latch register. It is a figure which shows the structural example etc. of a random number soft latch flag register. It is a flowchart which shows an example of a security check process. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of the process which sets a watchdog timer. It is a flowchart which shows an example of the main side power-off process. It is a flowchart which shows an example of the timer interruption process for game control. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of a start winning determination process. It is a flowchart which shows an example of a process at the time of starting port passage. It is a flowchart which shows an example of a special symbol normal process. It is a figure which shows the example of determination of a special figure display result and jackpot classification. It is the flowchart etc. which show an example of a fluctuation pattern setting process. It is a flowchart which shows an example of a special symbol stop process. It is a flowchart which shows an example of production control main processing. It is a flowchart which shows an example of production control process processing. It is a timing chart which shows the operation example in a random number circuit. 6 is a timing chart illustrating an example of a read operation of a hard latch random number register. It is a timing chart which shows the operation example when a power supply voltage falls during execution of game control. It is a timing chart which shows the operation example when the stability of a power supply voltage cannot be confirmed at the time of power activation.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails. In this game area, a game ball as a game medium is shot and shot by a ball hitting device including a shooting motor 61 shown in FIG.

  A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions of the game board 2 (in the example shown in FIG. 1, on the right side of the game area). Each of the first special symbol display device 4A and the second special symbol display device 4B is composed of, for example, 7-segment or dot matrix LEDs (light emitting diodes). Special symbols (also referred to as “special graphics”), which are a plurality of types of identification information (special identification information) that can be displayed, are variably displayed (variable display). For example, each of the first special symbol display device 4A and the second special symbol display device 4B variably displays a plurality of types of special symbols composed of numbers indicating "0" to "9", symbols indicating "-", and the like. To do. The special symbols displayed on the first special symbol display device 4A and the second special symbol display device 4B are composed of numbers indicating "0" to "9", symbols indicating "-", and the like. There is no limitation, and for example, a plurality of types of lighting patterns in which the combination of the LED to be turned on and the LED to be turned off in the 7-segment LED may be set in advance as a plurality of types of special symbols. A plurality of special symbols are assigned symbol numbers corresponding thereto. As an example, symbol numbers “0” to “9” are assigned to numbers indicating “0” to “9”, and symbol numbers “10” are assigned to symbols indicating “−”. Just do it. Hereinafter, the special symbol variably displayed by the first special symbol display device 4A is also referred to as "first special symbol", and the special symbol variably displayed by the second special symbol display device 4B is also referred to as "second special symbol". .

  A first hold indicator 25A and a second hold indicator 25B are provided above the first special symbol display device 4A and the second special symbol display device 4B. Each of the first hold indicator 25A and the second hold indicator 25B displays the variable display hold memory number (special figure hold memory number) in the special figure game so that it can be specified (special figure hold memory display). As an example, the first hold indicator 25A displays the variable display hold memory number (first special figure hold memory number) in the special figure game using the first special figure by the first special symbol display device 4A so as to be specified. To do. The second hold indicator 25B displays the variable display hold memory number (second special figure hold memory number) in the special figure game using the second special figure by the second special symbol display device 4B so that it can be specified. The variable display hold memory in the special game is started when the game ball passes (enters) the first start winning opening formed by the normal winning ball apparatus 6A and the second starting winning opening formed by the normal variable winning ball apparatus 6B. Occurs when winning a prize. That is, the start condition (also referred to as “execution condition”) for executing a variable display game such as a special figure game or a variable display of decorative symbols has been established, but a variable display game based on the previously established start condition is being executed. The start that is established when the start condition for starting the variable display game is not satisfied because the game state in the pachinko gaming machine 1 is controlled to the big hit game state or the small hit game state. The variable display holding storage corresponding to the condition is performed. Each of the first hold indicator 25A and the second hold indicator 25B has a number (for example, 4) corresponding to an upper limit value (for example, “4”) in each of the first special figure hold memory number and the second special figure hold memory number, for example. As long as it is configured to include a plurality of LEDs.

  A normal symbol display 20 is provided at a predetermined position of the game board 2 (on the left side of the game area in the example shown in FIG. 1). As an example, the normal symbol display 20 is composed of 7 segments, dot matrix LEDs, and the like, like the first special symbol display device 4A and the second special symbol display device 4B, and a plurality of types of identification information different from the special symbols. Is displayed (variably displayed) in a variable manner. Such variable display of normal symbols is called a general game (also referred to as “normal game”). The normal symbol display 20 variably displays, for example, a plurality of types of normal symbols composed of numbers indicating “0” to “9”, symbols indicating “−”, and the like. A plurality of types of normal symbols are assigned symbol numbers corresponding thereto. As an example, symbol numbers “0” to “9” are assigned to numbers indicating “0” to “9”, and symbol numbers “10” are assigned to symbols indicating “−”. Just do it. The normal symbol display 20 is not limited to the one that variably displays the numbers indicating “0” to “9” or the symbols indicating “−” as normal symbols. For example, “O” and “X” are displayed. Ordinary symbols are variably displayed by alternately illuminating the decorative lamps (or LEDs) to be displayed and lighting a plurality of decorative lamps (or LEDs) such as “left”, “middle”, and “right” in a predetermined order. It may be a thing.

  Above the normal symbol display 20, a universal figure holding display 25 </ b> C is provided. The general figure hold display unit 25C displays the variable display hold memory number (the general figure hold memory number) in the general game so that it can be specified (the general figure hold memory display). Here, the variable display hold storage in the usual game occurs when the game ball passes through the passing gate 41 provided in the game area. That is, when the condition for executing the variable display of the usual game is established, but the condition for starting the usual game is not established, the pending game is stored. The general-purpose hold display unit 25C may be configured to include, for example, a number (for example, four) of LEDs corresponding to the upper limit value (for example, “4”) of the general-purpose reserved storage number.

  An image display device 5 is provided near the center of the game area on the game board 2. The image display device 5 is composed of, for example, a liquid crystal display (LCD) or the like, and forms a display area for displaying various effect images. In the display area of the image display device 5, the first special symbol variable display by the first special symbol display device 4A and the second special symbol variable display by the second special symbol display device 4B in the special symbol game respectively correspond to the variable display. For example, in a decorative symbol display unit serving as a variable display unit divided into a plurality of parts such as three, decorative symbols that are a plurality of types of identification information (decorative identification information) that can be identified are variably displayed.

  As an example, “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R are arranged in the display area of the image display device 5. Then, in the special symbol game, any one of the variable display of the first special symbol by the first special symbol display device 4A and the variable display of the second special symbol by the second special symbol display device 4B is started. In response to this, variable display of decorative symbols (for example, vertical or horizontal scroll display) is performed in all of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. Be started. Thereafter, when the fixed special symbol is stopped and displayed as a variable display result in the special symbol game (completely stopped display), the “left”, “middle”, and “right” decorative symbol display portions 5L in the image display device 5 are displayed. At 5C and 5R, the fixed decorative symbol (final stop symbol) that is the variable display result of the decorative symbol is stopped (completely stopped). The “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R are movable within the display area of the image display device 5, and display the decorative symbols in a reduced or enlarged manner. You may be able to do that. When the special symbol or the decorative symbol is completely stopped and displayed, the display result in the variable display of each symbol is definitely displayed, and thereafter, the display state is such that the player can recognize that the current variable display does not proceed. On the other hand, during the variable display from the start of the variable display of the decorative pattern until the fixed decorative pattern that is the variable display result is displayed completely stopped, the variation speed of the decorative pattern becomes “0”. Ornamental symbols may be displayed in a stationary state, for example, in a display state that causes slight shaking or expansion / contraction. Such a display state is also called a temporary stop display, and although the display result in the variable display is not displayed deterministically, the player can recognize that the variation of the decorative pattern due to the scroll display or the update display is not progressing. It becomes. The temporary stop display may include displaying the decorative symbols completely stopped for a time shorter than a predetermined time (for example, 1 second) without causing slight shaking or expansion / contraction. Stopping and displaying the display symbol to the extent that the player can recognize that the variation of the special symbol or the decorative symbol is not progressing like the complete stop display or the temporary stop display is also referred to as a derivation display.

  The decorative symbols variably displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R include, for example, eight types of symbols (alphanumeric characters “1” to “8” or Chinese characters). Numbers “1” to “8”, English letters “A” to “H”, effect images showing eight characters related to a predetermined motif, effect images combining numbers, characters or symbols and characters, and the like. The effect image indicating the character may include, for example, a person or an animal, an object other than these, a symbol such as a character, or an image indicating any other figure. In addition to these eight types of decorative symbols, a blank symbol (a symbol that does not constitute a jackpot combination) may be included. A corresponding symbol number is assigned to each of the decorative symbols. For example, symbol numbers “1” to “8” are assigned to alphanumeric characters indicating “1” to “8”, respectively. Note that the number of types of decorative symbols that are variably displayed is not limited to eight, but may be any number of decorative symbols.

  While the decorative symbols are changing, in the decorative symbol display portions 5L, 5C, and 5R of “left”, “middle”, and “right”, for example, from the smallest to the largest symbol numbers, for example, from top to bottom. Alternatively, a scrolling display that flows from the right side to the left side is performed. Then, when the decorative symbol having the largest symbol number (for example, “8”) is displayed, the decorative symbol having the smallest symbol number (for example, “1”) is displayed. Alternatively, in at least one of the decorative symbol display portions 5L, 5C, and 5R (for example, the “left” decorative symbol display portion 5L), the symbol number is scrolled from the largest to the smallest, and the symbols are displayed. When the decorative design having the smallest number is displayed, the decorative design having the largest design number may be displayed.

  In the display area of the image display device 5, a start winning storage display 5H is also arranged. The start winning memory display unit 5H displays the variable display holding memory number (special drawing holding memory number) in the special figure game so as to be specified. As an example, the start winning memory display section 5H is provided with a plurality of display parts whose display colors are changed from left to right in order from the variable display game in which the start condition is established based on the occurrence of the start winning. Yes. When the start condition (first start condition) of the special figure game using the first special figure in the first special symbol display device 4A is established based on the game ball entering the first start winning opening, the One of the display parts that are displayed (transparent color) (for example, the leftmost display part among the non-displayed display parts) is changed to blue display. Further, when a special ball game start condition (second start condition) using the second special figure in the second special symbol display device 4B is established based on the game ball entering the second start winning opening, it is normally not One of the displayed display parts is changed to a red display. Thereafter, when one of the start condition (first start condition) of the special figure game using the first special figure and the start condition (second start condition) of the special figure game using the second special figure is established, for example, The display at the leftmost display part is removed and the display at each display part is moved leftward one by one. At this time, one of the display parts that have changed to blue display or red display (for example, the display part at the right end of the display part whose display color has changed) returns to non-display. Here, when the hold memory display is performed, the special figure hold memory number based on the establishment of the variable display game start condition can be specified, but the start condition is the first start condition or the second start condition. If it cannot be specified, the display mode of the special figure reserved memory number may be changed to a predetermined display mode, for example, by changing the number of display parts corresponding to the special figure reserved memory number to gray display. .

  In the start winning memory display section 5H, a number indicating the special figure reserved memory number may be displayed so that the player or the like can recognize the special figure reserved memory number. In the example shown in FIG. 1, a first hold indicator 25 </ b> A and a second hold indicator 25 </ b> B are provided above the first special symbol display device 4 </ b> A and the second special symbol display device 4 </ b> B together with the start winning memory display unit 5 </ b> H. It has been. On the other hand, you may make it provide only any one among the start winning memory | storage display part 5H and the 1st holding | maintenance display device 25A and the 2nd holding | maintenance display device 25B.

  The display area of the image display device 5 may be provided with a color symbol display unit that variably displays a color symbol as identification information different from the decorative symbol. As an example, when the special symbol game using the first special symbol by the first special symbol display device 4A is started in the color symbol display unit, the variation of the color symbol (for example, display color update display) is started. When the special symbol game using the second special symbol is started by the “left” color symbol display unit and the second special symbol display device 4B, the variation of the color symbol is started. The display part should just be included. Then, when the fixed special symbol that is the variable display result in the special graphic game is completely stopped and displayed, the variation of the color symbol is finished, and the fixed color symbol that is the variable display result of the color symbol is completely stopped and displayed. There are, for example, five types of symbols (“yellow”, “green”, “red”, “blue”, “purple”, etc.) for the color symbols variably displayed on the “left” and “right” color symbol display sections. It is sufficient that a plurality of types of color designs are included. Each of the color symbols is assigned a corresponding symbol number. As an example, the symbol numbers “1” to “5” may be assigned to the color symbols “yellow”, “green”, “red”, “blue”, and “purple”. For example, when the variable symbol display result (special symbol display result) is “losing”, the color symbol variable symbol display result is “yellow”, and the special symbol display result is “big hit”. When the big hit type is “non-probable change”, the fixed color design of “green” is stopped and displayed as the variable display result of the color design, the special figure display result is “big hit” and the big hit type is “probable change” In this case, the fixed color design of “red” is stopped and displayed as the variable symbol display result, and when the special symbol display result is “big hit” and the big hit type is “surprise”, the variable symbol display result is “ When the “blue” fixed color symbol is stopped and the special symbol display result is “small hit”, the “purple” fixed color symbol may be stopped and displayed as the variable symbol display result.

  Below the image display device 5, an ordinary winning ball device 6A and an ordinary variable winning ball device 6B are provided. The normal winning ball device 6A forms a first start winning opening that is always kept in a certain open state by a predetermined ball receiving member, for example. The normal variable winning ball apparatus 6B is an electric tulip type having a pair of movable wing pieces that are changed into a normal open state that is a vertical position and an expanded open state that is a tilt position by a solenoid 81 for a normal electric accessory shown in FIG. An accessory (ordinary electric accessory) is provided to form a second start winning opening. As an example, in the normally variable winning ball apparatus 6B, the movable wing piece is in the vertical position when the solenoid 81 for the ordinary electric accessory is in the off state, so that the game ball is unlikely to enter the second start winning opening. It becomes an open state. On the other hand, in the normal variable winning ball apparatus 6B, the movable wing piece is in the tilting position when the solenoid 81 for the normal electric accessory is in the on state, so that the game ball can easily enter the second start winning opening. Expanded open state. In the normal variable winning ball apparatus 6B, although the game ball can enter the second start winning opening even in the normal open state, there is a possibility that the game ball may enter more than in the expanded open state. You may comprise so that it may become low. Alternatively, the normally variable winning ball apparatus 6B may be configured so that the game ball does not enter the second starting winning opening in the normally open state, for example, by closing the second starting winning opening.

  A game ball that has entered the first start winning opening formed in the normal winning ball apparatus 6A is detected by, for example, a first start opening switch 22A shown in FIG. A game ball that has entered the second start winning opening formed in the normal variable winning ball apparatus 6B is detected by, for example, a second start opening switch 22B shown in FIG. Based on the detection of the game ball by the first start port switch 22A, a predetermined number (for example, three) of game balls are paid out as prize balls, and the first reserved memory number is set to a predetermined upper limit value (for example, “4”). ) If the following, the first start condition is satisfied. Based on the detection of the game ball by the second start port switch 22B, a predetermined number (for example, three) of game balls are paid out as prize balls, and if the second reserved memory number is equal to or less than a predetermined upper limit value, The second start condition is satisfied. The number of prize balls to be paid out based on the detection of the game ball by the first start port switch 22A and the number of prize balls to be paid out based on the detection of the game ball by the second start port switch 22B. May be the same number or different numbers.

  A special variable winning ball device 7 is provided below the normal winning ball device 6A and the normal variable winning ball device 6B. The special variable winning ball apparatus 7 includes a large winning opening door that is opened and closed by a solenoid 82 for the large winning opening door shown in FIG. 2, and is opened (first state) and closed (first state) by the large winning opening door. 2) to form a big prize opening. As an example, in the special variable winning ball apparatus 7, when the solenoid 82 for the special prize opening door is in the off state, the special prize opening door closes the special prize opening. On the other hand, in the special variable winning ball apparatus 7, when the solenoid 82 for the big prize opening door is in the ON state, the big prize opening door opens the big winning opening. A game ball that has entered a special winning opening formed in the special variable winning ball apparatus 7 is detected by, for example, a count switch 23 shown in FIG. Based on the detection of the game ball by the count switch 23, a predetermined number (for example, 13) of game balls are paid out as prize balls.

  In addition to the above configuration, the surface of the game board 2 is provided with a windmill for changing the flow direction and speed of the game ball and a number of obstacle nails. In addition, as a winning opening different from the first starting winning opening, the second starting winning opening and the large winning opening, for example, one or more general winning openings which are always kept in a certain open state by a predetermined ball receiving member are provided. May be. In this case, a predetermined number (for example, 10) of game balls may be paid out as a prize ball based on the fact that a game ball that has entered one of the general prize openings is detected by a predetermined general prize ball switch. In the lowermost part of the game area, there is provided an out port through which game balls that have not entered any winning port are taken. Speakers 8L and 8R for reproducing and outputting sound effects and the like are provided at the left and right upper positions of the gaming machine frame 3, and a game effect lamp 9 is provided at the periphery of the game area. A decorative LED may be arranged around each structure (for example, the normal winning ball device 6A, the normal variable winning ball device 6B, the special variable winning ball device 7, etc.) in the game area of the pachinko gaming machine 1.

  At the lower right position of the gaming machine frame 3, there is provided an operation knob 30 serving as a hitting operation handle operated by a player or the like to launch a game ball as a game medium toward the game area. For example, the resilience of the game ball is adjusted according to the operation amount (rotation amount) by the player or the like. The hitting operation handle only needs to be provided with a single shot switch or a touch ring (touch sensor) for stopping the driving of a shooting motor included in the hitting ball shooting device. At a predetermined position of the gaming machine frame 3 below the gaming area, a game ball paid out as a prize ball or a game ball lent out by a predetermined ball lending machine is held (stored) so as to be supplied to a ball hitting device. ) Is provided. For example, an operation button that can be operated by the player by a pressing operation or the like may be provided at a predetermined position in the gaming machine frame 3 of the pachinko gaming machine 1 such as a central position on the front side of the upper surface of the hitting ball supply tray. Further, below the hitting ball supply tray, there is provided an extra ball receiving tray (lower plate) that holds (stores) game balls that cannot be stored in the hitting ball supply tray.

  Furthermore, a prepaid card unit (card unit) for executing processing for enabling ball lending using a prepaid card or the like may be installed at a predetermined position adjacent to the pachinko gaming machine 1. The card unit may not only execute a lending process by taking a prepaid card, but may also execute a lending process by taking a membership card or cash.

  In the normal game with the normal symbol display 20, the normal symbol display 20 shows that the game ball that has passed through the passing gate 41 provided in the game area is detected by the gate switch 21 shown in FIG. After the general chart start condition for executing variable display is established, based on the fact that the general chart start condition for starting variable display of normal symbols, such as the end of the previous general chart game, is established, Be started. In this normal game, after a normal symbol change is started, when a predetermined variable display time (normal symbol change time) elapses, a fixed normal symbol that is a variable symbol display result is displayed in a completely stopped manner. The variable symbol display time may be determined as one of a plurality of variable display times by, for example, extracting numerical data indicating a predetermined random value at the start of each normal game. . If a specific normal symbol (a symbol per symbol) such as a number indicating “7” or a symbol indicating “O” is stopped and displayed as a fixed normal symbol that is a variable display result of the normal symbol in the normal game, The variable display result of the normal symbol is “per standard”. On the other hand, if a normal symbol other than the symbol per symbol such as a number other than the number indicating “7” or a symbol indicating “x” is stopped and displayed as the fixed normal symbol, for example, the variable display result of the normal symbol is “ It will be “usually lost”. Corresponding to the fact that the variable symbol display result of the normal symbol is “per normal symbol”, the expansion / release control is performed in which the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6B is tilted, for a predetermined time. When elapses, normal opening control is performed to return to the vertical position.

  The special symbol game by the first special symbol display device 4A is caused by the fact that the game ball that has entered the first starting winning port formed in the normal winning ball device 6A is detected by the first starting port switch 22A shown in FIG. The process starts when the first start condition is satisfied after the first start condition is satisfied. The first start condition is satisfied when the current special figure game using the first special figure can be started, for example, when the previous special figure game, the big hit game state, or the small hit game state is finished. In the special game by the second special symbol display device 4B, a game ball that has entered the second start winning port formed in the normal variable winning ball device 6B is detected by the second start port switch 22B shown in FIG. Is started based on the fact that the second start condition is satisfied after the second start condition is satisfied. The second start condition is satisfied when the current special figure game using the second special figure can be started, for example, when the previous special figure game, the big hit gaming state, or the small hit gaming state is finished.

  In the special symbol game by the first special symbol display device 4A or the second special symbol display device 4B, after a predetermined variable display time (special symbol variation time) elapses after the variable symbol special display is started, the special symbol is displayed. The fixed special symbol that will be the variable display result is displayed as a complete stop. The special symbol variable display time is, for example, numerical data indicating a random value MR4 for determining a variation pattern type as shown in FIG. 14 or numerical data indicating a random value MR5 for determining a variation pattern at the start of each special graphic game. Corresponding to the variation pattern determined based on the above, it is determined as one of a plurality of types of variable display times. The variable display result of the special symbol in the special figure game is also referred to as a special figure display result. If a specific special symbol (big hit symbol) is stopped and displayed as a fixed special symbol that will be the variable display result of the special symbol in the special symbol game, it will be a “big hit” as the specific display result, and a specific special that is different from the big bonus symbol If the symbol (small hit symbol) is stopped and displayed, it will be the “small hit” as the predetermined display result. If the special symbol (losing symbol) other than the big hit symbol or small hit symbol is stopped, the non-specific display result will be displayed. It becomes "losing". After the variable display result in the special figure game becomes “big hit”, the game is controlled to the big hit gaming state as the specific gaming state. Further, after the variable display result in the special figure game becomes “small hit”, the game is controlled to the small hit game state different from the big hit game state. In the pachinko gaming machine 1 in this embodiment, as an example, numbers indicating “1”, “3”, and “7” are jackpot symbols, numbers indicating “5” are jackpot symbols, and “−” is indicated. The symbol is a lost pattern. It should be noted that each symbol such as a big win symbol, a small bonus symbol, or a lose symbol in the special symbol game by the first special symbol display device 4A is different from each symbol in the special symbol game by the second special symbol display device 4B. Alternatively, a special symbol common to both special symbol games may be a big hit symbol, a small bonus symbol, or a lost symbol.

  In this embodiment, among the special symbols indicating the numbers “1”, “3”, and “7” that are jackpot symbols, the special symbols indicating the numbers “3” and “7” are 15 round jackpot symbols, A special symbol indicating the number “1” is a two-round jackpot symbol. In the big hit gaming state (15 round big hit state) as the first specific gaming state controlled after the 15 round big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, the open / close plate of the special variable winning ball apparatus 7 is The special variable winning ball apparatus 7 is played by opening the large winning opening in a predetermined period (for example, 29 seconds) which is the first period or until a predetermined number (for example, 9) of winning balls are generated. A round is performed that changes to a first state that is advantageous to the user. In this way, the open / close plate that opened the grand prize opening during the round receives the game ball falling on the surface of the game board 2, and then closed the grand prize opening to play the special variable prize ball device 7 as a game. Change to the second state, which is disadvantageous to the person, and finish one round. In the 15 round big hit state, the number of executions of the round, which is the open cycle of the big prize opening, is the first number (for example, “15”). A game in the 15 round big hit state in which the number of round executions is “15” is also referred to as a 15-time open game.

  In the big hit gaming state (two round big hit state) as the second specific gaming state controlled after the two round big hit symbol is stopped and displayed as the confirmed special symbol in the special figure game, the special variable winning ball apparatus 7 is played in each round. The period for changing to the first state that is advantageous to the player (the period in which the big prize opening is opened by the opening / closing plate) is a second period (for example, 0.5 seconds) shorter than the first period in the 15 round big hit state. . In the 2 round big hit state, the number of executions of the round is a second number (for example, “2”) smaller than the first number in the 15 round big hit state. In addition, in the two round big hit state, at least one of the period in which the big winning opening is opened in each round is the second period and the number of executions of the round is the second number is performed. The other control may be performed in the same manner as in the 15 round big hit state. A game in the round two big hit state in which the number of round executions is “2” is also referred to as a two-time open game. In the two-round big hit state, the predetermined winning ball device provided separately from the special variable winning ball device 7 in each round is changed from the second state which is disadvantageous to the player to the first state which is advantageous to the player. It is also possible to return to the second state after a predetermined period (first period or second period) has elapsed.

  Further, among the special symbols indicating the numbers “3” and “7” which are the 15-round jackpot symbol, the special symbol indicating the number “3” is stopped and displayed as the confirmed special symbol in the special game 15 After the round big hit state is over, as one of the special game states, the special symbol variation time (special diagram variation time) in the special figure game is controlled to be a short time state as compared with the normal state. Here, the normal state is a game state other than a special game state such as a big hit game state or a special game state such as a short-time state, and an initial setting state of the pachinko gaming machine 1 (for example, when a system reset is performed) Thus, the same control as in the state in which the initialization process is executed after power-on is performed. If the time-short state is terminated when any of the conditions of the special game is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit” is satisfied first, Good. In addition, after the 15 round big hit state based on the fact that the special symbol indicating the number “3” out of the 15 round big hit symbols is stopped and displayed as a confirmed special symbol in the special figure game, it does not become the short-time state. You may make it be in a normal state. Like the special symbol indicating the number “3”, the 15 round jackpot symbol controlled to the short-time state or the normal state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is This is called a non-probable big hit symbol (also referred to as “normal big hit symbol”). The variable display mode of special symbols and decorative symbols when the confirmed special symbol in the special figure game is a non-probable big hit symbol is "non-probable change" (also called "normal") when the variable display result is "big hit" This is referred to as a variable display mode (also referred to as “big hit type”).

  Out of the special symbols showing the numbers “3” and “7” that will be the 15-round jackpot symbol, the 15-round jackpot is based on the special symbol showing the number “7” being stopped and displayed as a confirmed special symbol in the special game. After the state is over, or after the two round jackpot state is over based on the fact that the special symbol indicating the number “1” that becomes the two-round jackpot symbol is stopped and displayed as the confirmed special symbol in the special figure game, As one of the special game states different from the normal game state, for example, the special figure change time is shortened compared to the normal state, and the probability change state (high probability game state) in which probability change control (probability change control) is continuously performed is controlled. Is done. In this probability change state, the variable display result of each special figure game and the decorative symbol variable display is improved so that the probability that the variable display result becomes “big hit” and is further controlled to the big hit gaming state is higher than in the normal state. Such a probability change state may be continued until the next variable display result becomes “big hit” regardless of the number of executions of the special game. On the other hand, after the certainty change state is reached, any one of the conditions that the special game is executed a predetermined number of times (for example, 100 times) or the variable display result is “big hit” is first. You may make it complete | finish when it is materialized. In addition, even if the special figure game is executed a predetermined number of times in the probability change state or before the variable display result is “big hit”, the probability change state ends at a predetermined rate when the special figure game is started. There may be.

  Like the special symbol indicating the number “7”, the 15-round jackpot symbol controlled to the probable change state after the jackpot gaming state based on being stopped and displayed as the confirmed special symbol in the special symbol game is a probabilistic big hit symbol. It is called. The variable display mode of special symbols and decorative symbols when the confirmed special symbol in the special figure game becomes a probable big hit symbol is variable "probable change" (also called "probable big hit") when the variable display result is "big hit". It is referred to as a display mode (also referred to as “big hit type”). Like the special symbol indicating the number “1”, the two-round big hit symbol controlled to the probable change state after the big hit gaming state based on being stopped and displayed as the confirmed special symbol in the special figure game is a sudden big hit symbol. It is called. The variable display mode of special symbols and decorative symbols when the confirmed special symbol in the special figure game is a sudden big hit symbol is “surprise” (“surprise big hit” or “sudden probability big hit” when the variable display result is “big hit”. ")" As a variable display mode (also referred to as "big hit type").

  In the probabilistic state and the short time state, the normal symbol display unit 20 controls the normal symbol variable display time in the normal symbol game to be shorter than that in the normal state, and the normal symbol variable display result of each time the normal symbol game is “normal”. Control for improving the probability of “per figure” than in the normal state, when the tilt time of the movable blade piece in the normal variable winning ball apparatus 6B based on the fact that the variable display result is “per normal figure” is in the normal state The player can be more likely to satisfy the second start condition by increasing the possibility that the game ball will enter the second start winning opening, such as a control for making it longer and a control for increasing the number of tilts than in the normal state. Control which is advantageous to the user is performed. It should be noted that any one of these controls may be performed in the probability variation state or the short time state, or a plurality of controls may be performed in combination. The control to be performed may be different between the probability variation state and the time-short state, or the combination of the controls to be performed (which may or may not include the same control) may be different.

  After the small hit symbol is stopped and displayed as the confirmed special symbol in the special symbol game, the small hit game state different from the big hit game state is controlled. In this small hit gaming state, a variable winning operation for changing the special variable winning device 7 to the first state advantageous to the player is performed as in the two round big hit state. That is, in the small hit game state, for example, the operation of opening the large winning opening over the second period by the opening / closing plate provided in the special variable winning ball apparatus 7 is repeatedly executed until the second number of times is reached. In the small hit gaming state, similarly to the two round big hit state, the period in which the big prize opening is in the open state is the second period, and the number of executions of the operation in which the big prize opening is in the open state is the second number. It may be controlled so that at least one of them is performed. After the small hit gaming state ends, the gaming state is not changed, and the game state before the variable display result becomes “small hit” is continuously controlled. However, if it is determined to end the short-time state corresponding to the variable display game in which the variable display result is “small hit”, the normal state is controlled after the end of the small hit gaming state. It will be. A game in the small hit gaming state in which the number of times that the big winning opening is opened by the variable winning operation is “2” is also referred to as a two-time open game, similar to the game in the two round big hit state. When the winning ball device provided separately from the special variable winning ball device 7 in each round in the two round big hit state is changed to the first state, the same as the two round big hit state in the small hit gaming state. In the aspect, the winning ball apparatus may be changed to the first state.

  In the display area of the image display device 5, variable display of decorative symbols is performed in response to variable display of special symbols by the first special symbol display device 4A and the second special symbol display device 4B. That is, in the display area of the image display device 5, for example, the “left”, “middle”, or “right” decorative symbol display portion 5 </ b> L based on the fact that either the first start condition or the second start condition is satisfied. In all of 5C and 5R, decorative symbols are displayed in an accelerated manner (all symbols accelerated display). When a predetermined speed is reached, the decorative symbols are displayed at a constant speed (all symbols are displayed at a constant speed). Such all symbols acceleration display and all symbols constant speed display are included in all symbol variations that variably display the ornament symbols in all of the “left”, “middle”, and “right” ornament symbol display portions 5L, 5C, and 5R. . After all the symbols change, for example, display the symbols in a decelerating display (each symbol deceleration display) in a predetermined order such as “Left” → “Right” → “Medium”. While stopping and displaying, for example, temporary stop display that causes slight shaking or expansion / contraction is performed. Then, when the elapsed time from the start of the variable display of the decorative pattern reaches the variable display time determined based on the variation pattern or the like, the fixed decorative pattern that is the variable display result is displayed in a completely stopped state. Note that the procedure for stopping and displaying the confirmed decorative symbols is not limited to displaying the decorative symbols in a predetermined order in the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. In each of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R, a decorative symbol that is a confirmed decorative symbol at the same time may be displayed in a decelerating display (all symbol decelerating display).

  After all symbols change is started, the decorative symbols are reach-displayed on some or all of the decorative symbol display portions 5L, 5C, 5R of “left”, “middle”, and “right”. It may be derived and displayed in the state. Here, the reach display state refers to a decorative symbol that has not yet been derived and displayed when the decorative symbol derived and displayed in the display area of the image display device 5 forms a part of the jackpot combination (“reach variation symbol”). ")" Is a display state in which the variation continues, or a display state in which some or all of the decorative symbols change synchronously while constituting a part or all of the jackpot combination. Specifically, in some of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R (for example, “left” and “right” decorative symbol display portions 5L and 5R, etc.) The remaining decorative symbol display part (for example, “medium”) that has not yet been derived and displayed when the decorative symbol (for example, the decorative symbol indicating the alphanumeric character “7”) that constitutes the determined jackpot combination is derived and displayed. In the symbol display portion 5C, etc., the display state in which the decorative symbol is fluctuating, or the decorative symbols in part or all of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R are big hits. This is a display state that changes synchronously while constituting a part or all of the combination. Further, in response to the reach display state, an effect image such as an animation image or a live-action image different from the decorative design is displayed in the display area of the image display device 5, the display mode of the background image is changed, There are times when the variation pattern of the decorative design is changed. Such an effect image display, background image display mode change, and decorative pattern change mode change are referred to as reach effect display (or simply reach effect). Some reach productions are set such that when they appear, a big hit is likely to occur (a high probability is a big win) compared to a normal reach production (normal reach). Such a special reach production is also called a super reach production (or simply “super reach”). As an example, for reach production that becomes super reach, after performing a reach production similar to normal reach until a predetermined time elapses, for example, a decorative pattern such as a background image display mode, a displayed character, a decorative pattern variation direction, etc. The change of the production mode (so-called “development”) by changing at least one of the fluctuation modes before the reach display state or at the time of the normal reach, and the reach production peculiar to the super reach It is sufficient if the introduction part in is started. In addition, in the reach production that becomes super reach, when the decorative design is derived and displayed in the reach display state, the introduction part in the reach production peculiar to super reach is started without performing the reach production similar to the normal reach. Things may be included.

  In addition, during the variable display of decorative symbols, unlike reach production, there is a possibility that the decorative symbols may be derived and displayed in the reach state, and that the variable display result may be a “hit”, There may be a case where a specific effect for informing the player is given in accordance with a variable display mode of the decorative design. In this embodiment, specific effects such as “slip” and “pseudo-run” are set to be executable. In addition, the specific effect in this embodiment should just change a special figure fluctuation time according to whether a corresponding effect operation is performed. For example, when a specific effect is executed, it is only necessary that the special figure change time becomes longer than when the specific effect is not executed.

  In the specific effect of “sliding”, after performing all symbol variations that change the ornament symbols in all of the “left”, “middle”, and “right” ornament symbol display portions 5L, 5C, and 5R, two or more After temporarily displaying a decorative symbol on a decorative symbol display unit (for example, “left” and “right” decorative symbol display units 5L, 5R, etc.), a predetermined number (for example, of the decorative symbol display units temporarily displayed) “1” or “2”), the decorative symbols are changed again in the decorative symbol display section (for example, one or both of the “left” decorative symbol display section 5L and the “right” decorative symbol display section 5R). The effect display which changes the decorative design to be stopped and displayed by performing the stop display later is performed. In addition, in the temporary stop display of the decorative design in the specific effect, while the decorative design is stopped and displayed, for example, by performing a fluctuation change display or immediately changing the decorative design only by a short stop, etc. What is necessary is just to alert | report that the decoration symbol stopped and displayed to the player is not decided. Alternatively, in the temporary stop display, the decorative design may be re-fluctuated after the decorative design is stopped to the extent that the player recognizes that the decorative design that has been stopped is confirmed.

  In the “pseudo-ream” specific production, all symbol fluctuations are started in response to the first start condition or the second start condition for starting the variable display of special symbols and decorative symbols being established once. , “Left”, “Middle”, “Right” decorative symbols are displayed in a temporary stop or sequential manner on all of the decorative symbol display portions 5L, 5C, 5R, and then “Left”, “Middle”, “Right” This is an effect operation in which the re-variable display operation (re-variation) for changing the decorative symbols again in all of the decorative symbol display portions 5L, 5C, and 5R is executed a predetermined number of times (for example, up to three times). As an example, in the specific effect of “pseudo train”, the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R have a plurality of types of decorative symbols that are predetermined as pseudo-success chances. One of the combinations is displayed as a temporary stop. Then, it is only necessary to set so that the rate at which the variable display result becomes “big hit” increases as the number of re-variations increases. As a result, the player can recognize that one of the pseudo-continuous chances is temporarily stopped and displayed, so that the specific effect of the “pseudo-continuous” is performed, and the variable display result becomes “ The expectation of becoming a “big hit” is enhanced. In this embodiment, in the specific effect of “pseudo-continuous”, the re-variation is performed once to three times, so that the decorative design can be changed based on the fact that the first start condition or the second start condition is satisfied once. The display can appear as if it has been started 2-4 times in a row.

  During the variable display of the decorative pattern in which the specific effect of “pseudo-continuation” is executed, an effect image showing a character prepared in advance at a predetermined position in the display area of the image display device 5 as the pseudo continuous variation progresses , Displaying a predetermined sound (special sound) from the speakers 8L and 8R, lighting the game effect lamp 9 with a predetermined lighting pattern, for effects provided inside or outside the game area A predetermined effect operation such as operating a plurality of movable members included in the accessory may be executed. As an example, when the decorative symbols are temporarily stopped and displayed on all the decorative symbol display portions 5L, 5C, and 5R, and then the decorative symbols are displayed again on all the decorative symbol display portions 5L, 5C, and 5R, Pseudo continuous variation is performed by performing any one or a combination of a plurality of operations among the display of the displayed effect image, the output of the special sound, the lighting of the lamp, and the operation of the movable member. May be notified in a recognizable manner.

  In addition to “pseudo-ream” and “slip”, specific effects using such decorative display variable display operations include, for example, “Development chance eyes”, “Development chance eyes end”, “Slip after chance eyes stop” Various production operations may be executed. Here, in the specific effect of “Development Opportunity”, “Left”, “Middle”, “Right” from the start of the variable display of the decorative pattern to the display of the fixed decorative pattern resulting in the variable display result. In all of the decorative symbol display portions 5L, 5C, and 5R, the decorative symbols constituting the development chances included in the predetermined special combination are temporarily stopped and displayed, and then the decorative symbol variable display state is set to the reach state. A predetermined reach production is started. As a result, when the decorative symbol constituting the development opportunity is temporarily stopped, the variable display state of the decorative symbol becomes the reach state, and the variable display result becomes “big hit” after the reach state is reached. , The player's expectation is enhanced. Further, in the specific effect of “end of development opportunity”, after the decorative symbol variable display is started, the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, 5R An effect display is performed for deriving and displaying a decorative pattern of a predetermined combination as a development opportunity. In the specific effect of “slip after the chance stop”, as with the variable display effect of “pseudo ream”, after the variable display of the decorative pattern is started, until the fixed decorative pattern that becomes the variable display result is derived and displayed, Temporarily stop display of decorative combinations (special combinations) that are one of a plurality of types of pseudo consecutive chances in the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. Then, unlike the specific effect of the “pseudo-ream”, an effect display for changing the decorative symbol to be stopped is performed by changing the decorative symbol again in a part of the decorative symbol display portions 5L, 5C, and 5R. Is called.

  Furthermore, during the variable display of the decorative pattern, unlike the reach effect or the specific effect, for example, by displaying the decorative pattern in a display mode other than the variable display mode of the decorative pattern, such as displaying a predetermined character image or message image. A notice effect may be executed to notify the player that the variable display state may become a reach state and that the variable display result may be a “hit”. For example, the notice effect such as “character display”, “step-up image”, and “background change” may be set to be executable. Note that the notice effect may be any one that does not change in the special figure fluctuation time depending on whether or not the corresponding effect operation is executed. In the notice effect of “character display”, two or more decorative symbols are displayed after the decorative symbols are changed in all of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. Before a decorative symbol is derived and displayed by a part (for example, “left” and “right” decorative symbol display units 5L, 5R, etc.), a character image prepared in advance in a predetermined position in the display area of the image display device 5 is displayed. An effect display is performed. In the notice effect of “step-up image”, two or more decorative symbols are displayed after changing the decorative symbols in all of the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R. Before the decorative part is derived and displayed on the display unit, there may be an effect display in which a plurality of types of effect images prepared in advance are switched and displayed in a predetermined order in the display area of the image display device 5. In the notice effect of “step-up image”, after any one of a plurality of kinds of effect images prepared in advance (for example, an effect image that is displayed first in a predetermined order) is displayed, the effect image The effect display in the notice effect may be terminated without being switched. In the “background change” notice effect, an effect display that changes the display of the background image in the display area of the image display device 5 to one of a plurality of types is performed.

  Such a notice effect may include a pre-read notice effect (also simply referred to as “pre-fetch notice”). The pre-reading notice effect indicates that the variable display result is “big hit” according to the production mode before the variable display that is subject to notice (the notice target) is the possibility that the variable display result will be “big hit”. It is a notice effect that warns of the possibility of becoming. In particular, a pre-reading notice effect that continuously gives notice over a variable display of decorative symbols that is executed a plurality of times in response to a plurality of special drawing games is also referred to as a continuous notice effect. In the pre-reading notice effect, before the variable display subject to the notice is started, there is an effect action for notifying the possibility that the variable display result will be a “hit” based on the hold memory information of the special figure game. Be started. In contrast to the pre-reading notice effect, the notice effect that is executed after the variable display to be noticed is started is referred to as a single notice effect (also called a single notice, or a notice effect during variable display). The In order to execute the pre-reading notice effect, when a game ball as a game medium passes (enters) a starting area such as the first starting winning opening and the second starting winning opening, a predetermined extracted based on the occurrence of the starting winning is performed. Using numerical data indicating a random value (such as a random number MR1 for determining a special figure display result described later), whether or not a specific gaming state such as a big hit gaming state is reached, or a specific effect such as a reach effect that becomes a super reach Whether or not the mode is to be set may be determined before the variable display start condition to be notified is satisfied. Whether or not to execute the pre-reading notice effect at a different rate depending on part or all of the determination result, and the effect mode of the pre-reading notice effect in the case of execution may be determined.

  After execution of the pre-reading notice effect is started, for example, every time variable display of decorative symbols is executed, an effect mode is provided by an effect display that selectively displays a plurality of types of effect images prepared in advance in a predetermined order. An effect operation that changes (steps up) in a plurality of stages may be performed. At this time, as the number of times of change (the number of steps) increases, the possibility (reliability) of the variable display result to be “big hit” or “small hit” may increase. Further, the object to be notified may change depending on the number of times of change (number of steps). For example, “reach determination” may be performed when going to the second step, “super reach confirmation” when going to the third step, and “big hit confirmation” going to the fourth step. As the change of the notice mode (step-up), different character images may be displayed in order, or the step-up may be performed by changing the shape or color of one character. May be. That is, it is only necessary to be able to recognize that the state of the notice means (display, sound, lamp, movable object, etc.) as viewed from the player changes stepwise.

  If a special symbol that will be a lost symbol is stopped and displayed as a special symbol to be confirmed in the special symbol game, the decorative symbol variable display state will not reach the reach state after the variable symbol variable display starts. There are cases where a fixed decorative symbol that is a non-reach combination or a fixed decorative symbol that is one of a plurality of types of development chances is stopped and displayed. Such a decorative display variable display mode is referred to as a “non-reach” (also referred to as “normal loss”) variable display mode when the variable display result is “losing”.

  When a special symbol that becomes a losing symbol is stopped and displayed as a confirmed special symbol in the special symbol game, it corresponds to the fact that the decorative symbol variable display state has reached the reach state after the decorative symbol variable display has started. Then, after the reach effect is executed, a fixed decorative pattern that becomes a predetermined reach-losing combination (also simply referred to as “reach combination”) may be stopped and displayed. Such a variable display result of the decorative design is referred to as a variable display mode of “reach” (also referred to as “reach lose”) when the variable display result is “losing”.

  When the special symbol indicating the number “3”, which is a non-probable variable jackpot symbol, is stopped and displayed as a special symbol to be confirmed in the special symbol game as a 15-round jackpot symbol, the variable display state of the decorative symbol is changed. Corresponding to the reach state, after a predetermined reach effect is executed, a definite decorative symbol that is a predetermined non-probable variation big hit combination (also referred to as “normal big hit combination”) is stopped and displayed. Here, the confirmed decorative symbols that are non-probable big hit combinations are, for example, symbol numbers that are variably displayed in the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R in the image display device 5. Among the decorative symbols with "1" to "8", any one of the decorative symbols with even numbers "2", "4", "6", "8" is "left", "middle" The “right” decorative symbol display portions 5L, 5C, and 5R may be stopped and displayed on a predetermined effective line. In this way, the decorative symbols having the even number “2”, “4”, “6”, and “8” constituting the non-probable variation big hit combination are referred to as non-probable variation symbols (also referred to as “normal symbols”). . Then, in response to the confirmed special symbol in the special symbol game becoming the non-probable variable big hit symbol, the fixed decorative symbol of the non-probable variable big hit combination is stopped and displayed after the predetermined reach effect is executed. The mode is referred to as a variable display mode (also referred to as a jackpot type) of “non-probable change” (also referred to as “normal”) when the variable display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “non-probability change”, the game is controlled to the 15 round big hit gaming state, and when the 15 round big hit state is finished, it is controlled to the short time state or the normal state. It will be.

  When the special symbol indicating the number “7”, which is the probability variable big hit symbol, is stopped and displayed as a special symbol to be confirmed in the special figure game as a 15-round big hit symbol, the variable display state of the decorative symbol is reached. Corresponding to the situation, after reaching the same reach effect as when the jackpot type is "non-probable change", or the reach effect different from when the jackpot type is "non-probable change" For example, after the process is executed, a fixed decorative symbol that becomes a predetermined probability variation jackpot combination may be stopped and displayed. Here, the confirmed decorative symbols that are the probable big hit combinations are, for example, symbol numbers that are variably displayed on the decorative symbol display portions 5L, 5C, and 5R of “left”, “middle”, and “right” in the image display device 5. Among the decorative symbols “1” to “8”, any one of the decorative symbols whose symbol numbers are odd numbers “1”, “3”, “5”, “7” are “left”, “middle”, What is necessary is just to be stopped and displayed on the predetermined effective line in each of the “right” decorative symbol display portions 5L, 5C, and 5R. In this way, the decorative symbols having odd numbers “1”, “3”, “5”, and “7” constituting the probability variation big hit combination are referred to as probability variation symbols. Then, in response to the confirmed special symbol in the special figure game becoming a probable big hit symbol, after the reach effect is executed, the decorative display variable display mode in which the definite decorative combination of the probable big hit combination is stopped is displayed. This is referred to as “probability change” variable display mode (also referred to as a big hit type) when the variable display result is “big hit”.

  When the probability variable big hit symbol is stopped and displayed as a fixed special symbol in the special figure game, the fixed decorative symbol that is a non-probable variable big hit combination may be stopped and displayed as a variable display result of the decorative symbol. In this way, even when the fixed decorative symbol that is a non-probable big hit combination is stopped and displayed, if the probable big hit symbol is stopped and displayed as a fixed special symbol in the special figure game, it is included in the variable display mode of “probable change”. . Thus, after the variable display result becomes “big hit” by the variable display mode of “probability change”, it is controlled to the 15 round big hit state, and when the 15 round big hit state ends, it is controlled to the positive change state. The confirmed decorative symbol that is a non-probable big hit combination and the definite decorative symbol that is a probable big hit combination are also collectively referred to as a definitive decorative symbol of a big winning combination (specific combination).

  A re-lottery effect may be executed during the variable display of the decorative symbols in which the confirmed decorative symbol is a non-probable variable big hit combination or a probable variable big hit combination. In the re-lottery effect, after the decorative symbols that are the non-probable big hit combinations are temporarily stopped and displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R in the image display device 5, for example, “ The left, middle, and right decorative symbol display portions 5L, 5C, and 5R are varied again with the same decorative symbol in a uniform state, and the decorative symbol (probable variable symbol) that is a probabilistic big hit combination is displayed. One of the decorative symbols (non-probable variable symbols) that is a probable big hit combination is stopped and displayed as a final decorative symbol (final stop display). Here, when the re-lottery effect is executed when the big hit type is “non-probable change”, as the re-lottery effect, the confirmed decoration that becomes the non-probable big hit combination after re-changing the temporarily stopped display decorative pattern A change promotion promotion effect that derives and displays a symbol is performed. On the other hand, when the re-lottery effect is executed when the big hit type is “probable change”, as the re-lottery effect, the definite decoration that becomes the probable big hit combination after re-variation of the temporarily stopped decorative pattern The changing promotion success effect during the stop display of the symbol may be executed, or the changing promotion failure effect during the change may be executed.

  After the definitive decorative symbol that is a non-probable jackpot combination is derived and displayed, at the start of the jackpot gaming state or during execution of the round in the jackpot gaming state, the next round will start after any round ends in the jackpot gaming state During the big hit, which is a notification effect on whether or not to control to the probable change state in the period until the start, the period from the end of the last round in the big hit gaming state to the start of the next variable display game, etc. A promotion effect may be executed. Note that a notification effect similar to the jackpot promotion effect may be executed during the first variable display game after the end of the jackpot gaming state. The jackpot promotion effect that is executed after the last round in the jackpot game state is particularly called “ending promotion effect”.

  In the jackpot promotion effect, there is no jackpot promotion success effect that notifies that there is a promotion that the game state becomes a probabilistic state even though the confirmed decorative pattern is a non-probable big hit combination, and there is no promotion that becomes a promiscuous state There is a promotion promotion failure during jackpot. For example, in the jackpot promotion effect, the decorative symbol is variably displayed in the display area of the image display device 5 and either the non-probable variable symbol or the probable variable symbol is stopped and displayed as the effect display result, or the decorative symbol variable display What is necessary is just to alert | report so that a player can recognize the presence or absence of the promotion which will be in a probability change state by displaying the effect image different from.

  As a confirmed special symbol in the special symbol game, a special symbol indicating the number “1” which is a two-round big hit symbol is stopped or displayed, or a special symbol indicating the number “2” which is a small hit symbol is stopped and displayed. In such a case, the variable display state of the decorative symbols may not reach the reach state, and any one of a combination of a plurality of types of fixed decorative symbols that are determined in advance as the second opening chance may be displayed. In addition, when the special symbol indicating the number “1”, which is a two-round jackpot symbol, is stopped and displayed as a confirmed special symbol in the special symbol game, the variable symbol display state of the decorative symbol is changed to the reach state. Then, after a predetermined reach effect is executed, a fixed decorative symbol that becomes a predetermined reach combination may be stopped and displayed. Corresponding to the fact that the confirmed special symbol in the special figure game becomes a special symbol indicating the number of “1” which is a two-round jackpot symbol, the variable display mode of the decorative symbols in which various fixed ornament symbols are stopped and displayed is variable. This is referred to as a variable display mode (also referred to as a jackpot type) of “surprise accuracy” (also referred to as “surprising accuracy hit” or “sudden probability change big hit”) when the display result is “big hit”. Thus, after the variable display result is “big hit” by the variable display mode of “surprise accuracy”, it is controlled to the two round big hit state, and when the two round big hit state is finished, it is controlled to the probability changing state.

  When the variable display result is “big hit” and the big hit type is “accuracy”, the accuracy mode start effect may be executed during variable display of the decorative symbols. In the surprise mode start effect, a predetermined effect operation is performed in response to the big hit type being “Accuracy”. After the surprise mode start effect is performed, an effect mode different from the normal effect mode called the accuracy mode may be started. In addition, the random mode start effect is not limited to the effect operation that is executed during the variable display of special symbols and decorative symbols, and continues from the variable display even during part or all of the period of the two round big hit state. An effect operation may be performed. When the suddenness mode start effect is started, the decorative symbol that is variably displayed may be erased, and after the suddenness mode start effect is executed, the confirmed decorative symbol may not be derived and displayed. In the sudden accuracy mode, for example, until the variable display result is “big hit” and the probability variation state ends, the effect in the sudden accuracy mode is performed. In the effect in the sudden accuracy mode, the display mode of the background image in the display area of the image display device 5 is different from the display mode in the normal rendering mode, and is output from the speakers 8L and 8R in accordance with the variable display of the decorative pattern. The sound to be different from the sound in the normal effect mode, the lighting pattern of the game effect lamp 9 and the decoration LED to be different from the lighting pattern in the normal effect mode, or a part of these Alternatively, by combining all of them, it may be informed so that the player can recognize that the mode is the suddenness mode.

  In the probability variation state, for example, an effect image for notifying that the probability variation state is “being probability variation” is displayed in the display area of the image display device 5, or a background image or a decorative pattern display mode in the display region of the image display device 5 is displayed. The display mode in the normal effect mode may be different from the display mode in the normal effect mode, so that the effect mode during probability change in which the player can recognize the probability change state may be set.

  The pachinko gaming machine 1 includes various power supply boards 10, a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a payout control board 15, a launch control board 17 as shown in FIG. A control board is mounted. The pachinko gaming machine 1 is also equipped with a relay board 18 for relaying various control signals transmitted between the main board 11 and the effect control board 12. Note that the audio control board 13 and the lamp control board 14 may be configured as independent boards that are separate from the effect control board 12, or may be integrated into the effect control board 12 and configured as one board. In addition, various control boards such as an information terminal board and an interface board are disposed on the back surface of the pachinko gaming machine 1. The interface board is a control board interposed between the payout control board 15 and the card unit when the card unit is installed adjacent to the pachinko gaming machine 1.

  The power supply board 10 is installed independently of the control boards such as the main board 11, the effect control board 12, and the payout control board 15, and generates voltages used by the control boards and the mechanical components in the pachinko gaming machine 1. . For example, in the power supply board 10, as shown in FIG. 3, AC24V, VLP (DC + 24V), VSL (DC + 30V), VDD (DC + 12V), VCC (DC + 5V) and VBB (DC + 5V) are generated. For example, as shown in FIG. 3, the power supply board 10 includes a transformer circuit 301, a DC voltage generation circuit 302, a power supply monitoring circuit 303, and a clear switch 304. Further, the power supply substrate 10 may be provided with a capacitor serving as a backup power supply. For example, this capacitor may be charged from a power supply line of VBB (DC + 5V). In addition, the power supply board 10 may be provided with a power switch for executing or cutting off the power supply to each control board and the mechanical components in the pachinko gaming machine 1. Alternatively, the power switch may be provided outside the power supply board 10 in the pachinko gaming machine 1.

  For example, the transformer circuit 301 may be configured to include a transformer to which commercial power is applied to the input side (primary side), a varistor as an overvoltage protection circuit provided on the input side of the transformer, and the like. Here, the transformer included in the transformer circuit 301 may be any one that electrically insulates the commercial power supply from the power supply substrate 10. The transformer circuit 301 generates AC 24V as its output voltage. The DC voltage generation circuit 302 includes, for example, a rectifying / smoothing circuit that generates VSL by rectifying and boosting AC 24V with a rectifying element. VSL is used as a power supply voltage for driving the solenoid. Further, the DC voltage generation circuit 302 includes a rectifier circuit that generates VLP by rectifying AC24V with a rectifier, for example. The VLP is used as a power supply voltage for lighting a light emitter such as the game effect lamp 9. In addition, the DC voltage generation circuit 302 includes a DC-DC converter that generates VDD and VCC based on, for example, VSL. This DC-DC converter includes, for example, one or more switching regulators and a relatively large capacity capacitor connected to the input side of the switching regulator, and power supply to the pachinko gaming machine 1 from the outside is stopped. Sometimes, it may be configured so that the direct current voltage such as VSL, VDD, VBB, etc. decreases relatively slowly. The VDD is supplied to various switches for detecting game media such as the gate switch 21, the first and second start port switches 22A and 22B, and the count switch 23 shown in FIG. 2, and is used to operate these switches. .

  As shown in FIG. 3, AC24V output from the transformer circuit 301 is transmitted to the payout control board 15 via a predetermined connector or a power supply line, for example. The VLP is transmitted to the lamp control board 14 via, for example, a predetermined connector or a power supply line. VSL, VDD, and VCC are transmitted to the main board 11, the lamp control board 14, and the payout control board 15 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 11 and the payout control board 15 through, for example, a predetermined connector and a power supply line. Note that each voltage may be supplied to the effect control board 12 and the sound control board 13 via the lamp control board 14. Alternatively, each voltage may be directly supplied to the effect control board 12 and the sound control board 13 from the power supply board 10 without going through the lamp control board 14.

  The power monitoring circuit 303 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes a power monitoring unit that outputs a power interruption signal. For example, when a predetermined power supply voltage (VSL as an example) used in the pachinko gaming machine 1 exceeds a predetermined value (+22 V as an example), the power supply monitoring circuit 303 outputs a power-off signal in an off state (high level). On the other hand, when the period during which the predetermined power supply voltage is equal to or lower than the predetermined value continues for a predetermined time (for example, 56 milliseconds), an on-state (low level) power-off signal is output. Alternatively, the power supply monitoring circuit 303 may output an on-state power-off signal immediately when a predetermined power supply voltage used in the pachinko gaming machine 1 becomes a predetermined value or less. For example, the power-off signal may be a negative logic electric signal that is turned on when it is low and turned off when it is high. The power-off signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then transmitted to the main board 11 or the payout control board 15 via a predetermined connector or signal line. Is done. The power-off signal may be transmitted to the main board 11 via the payout control board 15.

  The predetermined power supply voltage to be monitored for outputting the power-off signal is preferably a voltage higher than a specified value (for example, +12 V) in the power supply voltage VDD for operating the switch, such as the power supply voltage VSL. Thereby, before the power supply voltage VDD for operating the switch decreases and the operation state of various switches (for example, the gate switch 21, the first and second start port switches 22A and 22B, the count switch 23, etc.) becomes unstable, By outputting the power-off signal (turning on), it is possible to prevent the progress of game control based on erroneous detection by various switches. That is, when the power supply voltage VDD for operating the switch is lowered, the switch output of the negative logic (turned on at a low level) is turned on, but the power supply voltage VSL that drops earlier than the power supply voltage VDD is monitored to supply power By recognizing the stop, it becomes possible to enter a state of waiting for power supply recovery and not detecting the switch output before the switch output is turned on.

  A large capacity capacitor may be connected to the power supply line for transmitting the power supply voltage VSL and the like to the main board 11, the lamp control board 14, and the payout control board 15. On the other hand, such a capacitor may not be connected to the input line that transmits to the power supply monitoring circuit 303 in order to monitor the power supply voltage VSL. In this case, the power supply voltage VSL in the input line to the power supply monitoring circuit 303 to be monitored drops earlier than the power supply voltage VSL in the power supply line to which the capacitor is connected. That is, even after the monitored power supply voltage VSL starts to decrease, the supply state of the power supply voltage VSL in the power supply line supplied to the solenoid, the motor, or the like is maintained for a predetermined period. Therefore, even when the power supply voltage VSL to be monitored starts to decrease, the solenoid, the motor, and the like can be driven for a predetermined period. Further, it is possible to recognize the stop of the power supply before the power supply voltage VSL in the power supply line starts to decrease.

  In place of the solenoid drive power supply voltage VSL, for example, a power cut-off signal is generated by monitoring an arbitrary power supply voltage higher than a specified value in the switch operation power supply voltage VDD, for example, the power supply voltage VLP for lighting the light emitter. You may make it output. In addition, the condition for detecting the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is not limited to the fact that the predetermined power supply voltage used in the pachinko gaming machine 1 has become a predetermined value or less. Any condition can be used as long as it is possible to detect that the power has been cut off. For example, the AC wave such as AC 24V may be monitored to detect that the AC wave has stopped, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be generated when the digital signal becomes flat. It may be a detection condition for the interruption.

  For example, the power supply monitoring circuit 303 may output a reset signal when a predetermined power supply voltage (VCC as an example) becomes equal to or lower than a predetermined value (+4.5 V as an example). The reset signal may be an electric signal that is turned on when the reset signal becomes low level, for example. The reset signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10, and then the main board 11, the lamp control board 14, and the payout control board via predetermined connectors and signal lines. 15 is transmitted. A reset signal may be transmitted to the effect control board 12 via the lamp control board 14. Alternatively, the reset signal may be transmitted directly to the effect control board 12 without going through the lamp control board 14. Furthermore, the circuit that outputs the reset signal may be configured by using a watchdog timer built-in IC provided separately from the power supply monitoring circuit 303, a system reset IC, or the like.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 303 outputs a reset signal (sets to a low level) when a predetermined period elapses after the power-off circuit 303 outputs a power-off signal (sets to a low level). ) In the predetermined period, for example, the game control microcomputer 100 mounted on the main board 11 and the payout control microcomputer 150 mounted on the payout control board 15 shown in FIG. It is sufficient if the time is sufficient for execution. In other words, the power monitoring circuit 303 outputs a power-off signal as a power feeding signal, and after the game control microcomputer 100 and the payout control microcomputer 150 complete execution of predetermined power-off processing, the operation stop signal The reset signal is output (set to low level). The game control microcomputer 100 and the payout control microcomputer 150 that have received the reset signal output from the power supply monitoring circuit 303 are in an operation stop state, and execution of various control processes is stopped. In addition, when the power supply to the pachinko gaming machine 1 is started, for example, when a predetermined power supply voltage (VCC as an example) exceeds a predetermined value (+4.5 V as an example), the power monitoring circuit 303 stops outputting the reset signal (Set to high level).

  FIG. 4 is a timing diagram schematically showing the states of AC 24 V, VSL, VCC, reset signal and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 4, when power supply to the pachinko gaming machine 1 is started, VSL and VCC gradually reach the specified values (DC + 30V and DC + 5V). At this time, when VCC exceeds a first predetermined value (for example, +4.5 V), the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. When VSL exceeds a second predetermined value (for example, +22 V), the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VSL and VCC gradually decrease. At this time, when VSL decreases to the second predetermined value (+22 V), the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). Further, when VCC decreases to the first predetermined value (+4.5 V), the power monitoring circuit 303 outputs the reset signal as an ON state (sets it to a low level).

  The clear switch 304 included in the power supply substrate 10 illustrated in FIG. 3 has a push button structure, for example, and outputs a clear signal in response to an operation such as pressing. The clear signal may be an electrical signal that is turned on when it becomes low level in response to an operation such as pressing. Alternatively, the clear signal may be an electrical signal that is turned on when it becomes high level in response to an operation such as pressing. The clear signal output from the clear switch 304 is transmitted to the main board 11 via a predetermined connector or signal line, for example, and is transmitted from the main board 11 to the payout control board 15. When the clear switch 304 is not operated, the output of the clear signal is stopped (set to high level or low level). Note that the clear switch 304 may have a configuration other than a push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is a sub-side mainly composed of a random number setting function used in a special game, a function of inputting a signal from a switch arranged at a predetermined position, an effect control board 12, a payout control board 15, and the like. It has a function of outputting and transmitting a control command as an example of command information to the control board as a control signal, a function of outputting various information to the hall management computer, and the like. In addition, the main board 11 performs on / off control of each LED (for example, segment LED) constituting the first special symbol display device 4A and the second special symbol display device 4B, and thereby the first special diagram and the second special diagram. Variable display of a predetermined display pattern such as controlling the variable display of the normal symbol display 20 and controlling the variable symbol display of the normal symbol display 20 by controlling the lighting / extinguishing / coloring control of the normal symbol display 20. It also has a function to control. As shown in FIG. 2, for example, the main board 11 includes a game control microcomputer 100, a control clock generation circuit 111, a random number clock generation circuit 112, a switch circuit 114, and a solenoid circuit 115. . A game start switch 31 may be installed on the main board 11.

  Here, the control clock generation circuit 111 generates a control clock CCLK that becomes an oscillation signal having a predetermined frequency outside the game control microcomputer 100. The control clock CCLK generated by the control clock generation circuit 111 is supplied to the clock circuit 502 via a control external clock terminal EXC of the game control microcomputer 100 as shown in FIG. 5, for example. The random number clock generation circuit 112 generates a random number clock RCK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the game control microcomputer 100. The random number clock RCK generated by the random number clock generation circuit 112 is supplied to, for example, the random number circuits 509A and 509B (see FIG. 5) via the random number external clock terminal ERC of the game control microcomputer 100. As an example, the oscillation frequency of the random number clock RCK generated by the random number clock generation circuit 112 may be set to be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111. Alternatively, the oscillation frequency of the random number clock RCK generated by the random number clock generation circuit 112 may be higher than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111.

  The switch circuit 114 takes in detection signals from various switches for detecting game balls and transmits them to the microcomputer 100 for game control. The solenoid circuit 115 transmits a solenoid drive signal from the game control microcomputer 100 to the solenoids 81 and 82. The game start switch 31 has, for example, a push button structure, and the pachinko gaming machine 1 closes the gaming machine frame 3 so that the player can not normally touch the pachinko gaming machine 1 in a state in which the player plays a normal game. What is necessary is just to be arrange | positioned. Then, for example, when the pachinko gaming machine 1 is turned on or when the system is reset, the pachinko gaming machine 1 is operated to instruct the game start after the initial setting. Note that the game start switch 31 may have a configuration other than the push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  As shown in FIG. 2, wiring for transmitting detection signals from the gate switch 21, the first start port switch 22 </ b> A, the second start port switch 22 </ b> B, and the count switch 23 is connected to the main board 11. The gate switch 21, the first start port switch 22A, the second start port switch 22B, and the count switch 23 have an arbitrary configuration that can detect a game ball as a game medium, such as a sensor. What is necessary is just to have. The main board 11 includes a first special symbol display device 4A, a second special symbol display device 4B, a normal symbol display device 20, a first hold display device 25A, a second hold display device 25B, and a general drawing hold display device 25C. Wiring for transmitting a command signal for performing display control such as is connected. Further, the main board 11 is connected to wiring for transmitting command signals for performing drive control, such as a solenoid 81 for an ordinary electric accessory and a solenoid 82 for a prize winning door.

  Various control commands are transmitted between the main board 11 and the effect control board 12, for example, by performing serial communication only in a single direction from the main board 11 to the effect control board 12 via the relay board 18. Is done. The effect control board 12 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the relay board 18, and receives the image display device 5, speakers 8L, 8R. In addition, various circuits for controlling electric parts (production device) for production such as light emitters such as the game effect lamp 9 are mounted. That is, the effect control board 12 has a function of controlling the display operation in the image display device 5, the sound output operation from the speakers 8L and 8R, the lighting operation and the extinguishing operation in the light emitter such as the game effect lamp 9 and the like. . The effect control board 12 is connected to wiring for transmitting a control signal to the sound control board 13 and the lamp control board 14, wiring for transmitting an image data signal to the image display device 5, and the like.

  The main board 11 may be provided with a main board side connector corresponding to the relay board 18, for example, and an output buffer circuit may be connected between the main board side connector and the game control microcomputer 100. . This output buffer circuit can pass a control signal only in the direction from the main board 11 to the effect control board 12 via the relay board 18, for example, and prevents the signal input from the relay board 18 to the main board 11. . Therefore, there is no room for signals to be transmitted from the production control board 12 or the relay board 18 side to the main board 11 side. Note that the relay board 18 may not be provided between the main board 11 and the effect control board 12. Thereby, the freedom degree of wiring routing between the main board | substrate 11 and the production | presentation control board 12 can be raised.

  For example, the relay board 18 may be provided with a transmission direction regulating circuit in a wiring for transmitting a control signal from the main board 11 to the effect control board 12. The transmission direction regulating circuit includes a diode having an anode connected to the main board connector corresponding to the main board 11 and a cathode connected to the presentation control board connector corresponding to the presentation control board 12, and one end connected to the cathode of the diode. And the other end of which is connected to the ground (GND). With this configuration, the transmission direction regulating circuit can prevent the signal from being input from the effect control board 12 to the relay board 18 and pass the signal only in the direction from the main board 11 to the effect control board 12. Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In this embodiment, a transmission direction regulating circuit is provided in the wiring for transmitting a control signal in the relay board 18, and an output buffer circuit is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing, illegal signal input to the main board 11 from the outside can be prevented.

  Various control commands and notification signals are transmitted between the main board 11 and the payout control board 15 by, for example, bidirectional serial communication. The payout control board 15 is a sub-side control board independent of the main board 11, receives a control command and a notification signal transmitted from the main board 11, and controls the payout operation of the game ball by the payout motor 51. Various circuits are installed. That is, the payout control board 15 has a function of controlling the award ball payout operation by the payout motor 51. The payout control board 15 may have a function of controlling the ball lending operation by controlling the driving of the payout motor 51 in accordance with the communication result with the card unit via the interface board, for example. The payout control board 15 receives wiring for receiving detection signals from the full tank switch 26 and the ball break switch 27, and detection signals from the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. Wiring for is connected. In addition, a wiring for transmitting a command signal for performing payout control of the game ball in the payout motor 51 and a command signal for performing display control in the error display LED 74 are transmitted to the payout control board 15. Wiring for communication with the card unit is connected via the interface board.

  Here, the full tank switch 26 is installed on the side wall of the surplus ball passage that communicates between the striking ball supply tray and the surplus ball receiving tray, for example, below the back of the game board 2, and detects the full tank of the surplus ball receiving tray. Is. A lot of game balls based on award balls or ball lending requests are paid out, the batting supply tray becomes full, and after the game balls reach the contact point, when the game balls are paid out, the game balls pass through the surplus ball passage. It is led to the extra ball tray. When the game ball is further paid out, for example, a predetermined sensing lever presses the full switch 26 to turn on.

  In addition, the ball break switch 27 is installed downstream of the guide rail that guides the game ball to the payout device in which the payout motor 51 is installed, for example, on the back of the game board 2, and via a curve rod downstream of the guide rail. This is for detecting the presence or absence of game balls in two rows of ball passages communicated with each other. As an example, the ball break switch 27 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path, and the maximum payout number (for example, 100) It is possible to confirm that at least 25 pieces corresponding to a circle are secured. The guide rail guides a game ball from a storage tank that stores a game ball as a supply ball above the back of the game board 2 to a payout device, and a payout motor 51 is provided below the ball passage. The payout device in which is installed is fixed.

  The error release switch 73 is a switch for releasing the error state by software reset when the payout control microcomputer 150 is controlled to a predetermined error state. The error display LED 74 is composed of, for example, a 7-segment LED, and is used to display error codes corresponding to various errors based on an error flag set by the payout control microcomputer 150.

  The launch control board 17 shown in FIG. 2 is for controlling the launch operation of the game ball by a predetermined launch device in accordance with the operation amount of the operation knob 30. For example, the firing control board 17 has wiring for transmitting a drive signal from the power supply board 10 or the main board 11, wiring for transmitting a connection signal from the card unit via the payout control board 15 and the interface board, and an operation knob 30. Are connected to the firing motor 61. Note that the connection signal from the card unit may be branched at the dispensing control board 15 and transmitted to the firing control board 17, or the launch control may be performed from the card unit via the interface board and not via the dispensing control board 15. It may be transmitted to the substrate 17. The firing control board 17 adjusts the driving force of the firing motor 61 in accordance with the operation amount of the operation knob 30. For example, the launch motor 61 elastically deforms the launch spring by a driving force adjusted by the launch control board 17, and transmits the biasing force of the launch spring to the hitting hammer to hit the game ball, thereby operating the game ball on the operation knob 30. It is fired toward the game area at a speed corresponding to the operation amount.

  The control command transmitted from the main board 11 to the effect control board 12 via the relay board 18 is, for example, an effect control command transmitted as an electric signal. In this embodiment, the effect control command is set for transmission by the CPU 505 (see FIG. 5) included in the game control microcomputer 100 mounted on the main board 11, and the game control microcomputer is based on the setting. It is transmitted to the effect control board 12 by the second channel transmission circuit of the serial communication circuit 511 (see FIG. 5) included in 100. In the following description, the transmission operation of the effect control command from the main board 11 to the effect control board 12 includes a series of operations by the CPU 505 and the serial communication circuit 511 provided in the game control microcomputer 100. To do. In this case, on the side of the effect control board 12, for example, the CPU of the effect control microcomputer 120 performs an interrupt process based on a reception interrupt request generated when communication data in the serial signal format transmitted from the main board 11 is received. By executing, the effect control command may be captured and stored in a predetermined buffer (for example, a reception command buffer for effect). The effect control command may be transmitted from the main board 11 to the effect control board 12 via the relay board 18 by a plurality of signal lines (for example, eight effect control signal lines). In this case, in addition to the signal line for transmitting the effect control command, a signal line for transmitting the capture signal (effect control INT signal) for requesting the capture of the effect control command may be wired.

  The effect control command includes, for example, a display control command used for controlling an image display operation in the image display device 5, a voice control command used for controlling sound output from the speakers 8L and 8R, and a game effect lamp 9. The lamp control command used for controlling the lighting operation of the light emitter is included. The display control command has, for example, a 2-byte structure, and the first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit of the MODE data (bit number [7]) is always “1”, and the first bit of the EXT data is “0”. Note that the form of the display control command is an example, and other command forms may be used. In this example, the display control command has a 2-byte configuration, but the number of bytes constituting the display control command may be 1 or a plurality of 3 or more.

  The control command transmitted from the main board 11 to the payout control board 15 is, for example, a payout control command transmitted as an electrical signal. The payout control command is set to transmit the payout control command by the CPU 505 (see FIG. 5) provided in the game control microcomputer 100 mounted on the main board 11, and the game control is performed based on the setting. It is transmitted to the payout control board 15 by the first channel transmission / reception circuit of the serial communication circuit 511 (see FIG. 5) included in the microcomputer 100 for use. In the following description, the transmission operation of the payout control command from the main board 11 to the payout control board 15 includes a series of operations by the CPU 505 and the serial communication circuit 511 provided in the game control microcomputer 100. To do. Also, for example, a payout notification command as an electrical signal is transmitted from the payout control board 15 to the main board 11. The payout notification command is set so that the payout notification command is transmitted by the CPU of the payout control microcomputer 150 mounted on the payout control board 15, and the payout control microcomputer 150 is set based on the setting. It is transmitted to the main board 11 by a serial communication circuit provided. In the following description, it is assumed that the transmission operation of the payout notification command from the payout control board 15 to the main board 11 includes a series of operations by the CPU and serial communication circuit provided in the payout control microcomputer 150. . In addition, in the following description, not only a command of a predetermined operation from one of the main board 11 and the payout control board 15 to the other but also a notification signal for notifying the other of the operation state of the other is a payout control command or a payout It shall be included in the notification command.

  The payout control command transmitted from the main board 11 to the payout control board 15 may include a payout number designation command and an ACK feedback command. The payout number designation command is a command indicating the number of prize balls to be paid out. The ACK feedback command becomes a reception confirmation acceptance signal indicating that the prize ball ACK command transmitted from the payout control board 15 to the main board 11 is received on the main board 11 side.

  The payout notification command transmitted from the payout control board 15 to the main board 11 may include a prize ball ACK command, a payout error notification command, and a payout error cancel command. The winning ball ACK command is a reception confirmation signal indicating that the payout number specifying command transmitted from the main board 11 to the payout control board 15 is received on the payout control board 15 side. The payout error notification command is a command for notifying the main board 11 that an abnormality relating to the payout of the game ball has occurred on the payout control board 15 side. The payout error cancel command is a command for notifying the main substrate 11 side that the error that has occurred on the payout control board 15 side has been cancelled.

  In addition, between the main board | substrate 11 and the payout control board 15, it is not limited to what transmits / receives a command by serial communication, You may transmit / receive a command by parallel communication using a several signal wire | line. Further, instead of the payout error notification command and the payout error cancel command transmitted from the payout control board 15 to the main board 11, a payout error state signal indicating an error occurrence state in the payout control board 15 is sent to the main board 11. You may input into one of the provided input ports. For example, the payout error state signal is turned on when an error occurs in the payout control board 15, and is turned off when no error occurs or when the error is released. In this case, on the main board 11 side, a payout error state signal is fetched every time a timer interrupt occurs, and the fetch result is stored. The payout error state signal has changed from the off state to the on state by taking the exclusive OR of the signal state captured by the current timer interrupt and the signal state captured and stored by the previous timer interrupt. It may be possible to detect that the error has been changed from the on state to the off state (indicating the time when the error is released). When an error occurs in the payout control board 15 or when the error is released, an error has occurred in the payout operation by transmitting an effect control command prepared for each from the main board 11 to the effect control board 12 It may be instructed to start or end the notification operation for notifying the user. The payout error state signal is not limited to one input to one of the input ports provided on the main board 11, and for example, a payout control board 15 such as a full signal, a ball out signal, a prize ball case error signal, or a door open signal. May be input to the main board 11 to detect when an error occurs or when an error is released as in the case of the payout error state signal. Then, by transmitting an effect control command corresponding to the type of the detected error from the main board 11 to the effect control board 12, the start or end of the notification operation corresponding to the detected error is instructed. It may be.

  FIG. 5 shows a configuration example of the game control microcomputer 100 mounted on the main board 11. The game control microcomputer 100 shown in FIG. 5 is, for example, a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset controller 504A, an interrupt controller 504B, and a CPU ( Central Processing Unit) 505, ROM (Read Only Memory) 506, RAM (Random Access Memory) 507, timer circuit 508, 16-bit random number circuit 509A, 8-bit random number circuit 509B, and free-run counter 509C And a PIP (Parallel Input Port) 510, a serial communication circuit 511, and an address decoding circuit 512.

  FIG. 6 shows an example of an address map in the game control microcomputer 100. As shown in FIG. 6, the area from address 0000H to address 2FFFH is allocated to the ROM 506 and includes a user program area and a program management area. The subscript H indicates a hexadecimal number, and the same applies to the following description. FIG. 7A shows an example of the usage and contents of the main part of the program management area in the ROM 506. The area from address F000H to address F3FFH is a work area assigned to the RAM 507, and can be assigned to an I / O map or a memory map. The area from address FE00H to address FEBFH is a built-in register area assigned to the built-in registers of the game control microcomputer 100. FIG. 7B shows an example of the usage and contents of the main part of the built-in register area.

  The program management area is a storage area for storing information necessary for the CPU 505 to execute the user program. As shown in FIG. 7A, the program management area includes a header KHDR, a reset setting KRES, an interrupt initial setting KIIS, a 16-bit random number initial setting 1st KRL 1 to a 16-bit random number initial setting 3rd KRL3, an 8-bit random number initial setting 1KRS1, 8-bit random number initial setting second KRS2, security time setting KSES, and the like are included.

  The header KHDR stored in the program management area indicates the internal data read setting in the game control microcomputer 100. FIG. 8A illustrates the correspondence between setting data and operation in the header KHDR. Here, in the game control microcomputer 100, the ROM read prevention function and the bus output mask function can be set. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 506 provided in the game control microcomputer 100. When the read prohibition is set, the data stored in the ROM 506 cannot be read. The bus output mask function is an address bus output, data bus output, and control signal in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for internal data of the game control microcomputer 100. This function makes it impossible to read internal data from an external device by masking the output. As shown in FIG. 8A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 8A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The reset setting KRES stored in the program management area indicates the setting of the reset operation in the game control microcomputer 100. FIG. 8B shows an example of setting contents in the reset setting KRES. The bit number [7] of the reset setting KRES is setting data for setting an operation when an internal reset occurs in the game control microcomputer 100. The internal reset in the game control microcomputer 100 is caused by a predetermined factor such as a time-out signal output from the watchdog timer 520 provided in the reset controller 504A, or the prohibition of running outside the designated area (IAT). Is a reset generated by.

  In the example shown in FIG. 8B, when the bit value in the bit number [7] of the reset setting KRES is “0”, the reset operation when the internal reset occurs is set to the user reset. When a user reset is executed, for example, the interrupt controller 504B, the CPU 505, the timer circuit 508, the free-run counter 509C, the PIP 510, and the serial communication circuit 511 are initialized, and the user program is reset from the user program reset address (ROM 506 address 0000H). Run the program again. On the other hand, when the bit value in the bit number [7] of the reset setting KRES is “1”, the reset operation when the internal reset occurs is set to the system reset. When the system reset is executed, all internal circuits in the game control microcomputer 100 including, for example, the 16-bit random number circuit 509A and the 8-bit random number circuit 509B are initialized, and the reset address of the user program Re-execute the user program.

  The bit number [6] of the reset setting KRES is setting data for setting the activation method of the watchdog timer 520 provided in the reset controller 504A. In the example shown in FIG. 8B, when the bit value in the bit number [6] of the reset setting KRES is “0”, the operation state of the gaming control microcomputer 100 shifts from the security mode to the user mode. As a result, the watchdog timer 520 is automatically started. On the other hand, when the bit value is “1”, a user program (an initial setting program for game control and a game control processing program) based on the control code read from the ROM 506 by the CPU 505 of the game control microcomputer 100. ) To start the watchdog timer 520 by software. In this way, by storing in advance the setting data in which the bit value in the bit number [6] of the reset setting KRES stored in the program management area of the ROM 506 is “1”, the software by executing the user program The watchdog timer 520 can be activated by a predetermined WDT activation control code to validate the reset operation, or the watchdog timer 520 can be deactivated by the predetermined WDT stop control code to invalidate the reset operation.

  The bit number [5-4] of the reset setting KRES is setting data for setting a reference clock used for setting the timeout time of the watchdog timer 520. In the example shown in FIG. 8B, depending on whether the bit value in the bit number [5-4] of the reset setting KRES is “00”, “01”, “10”, or “11”. A reference clock with a different period is set. The bit number [3-0] of the reset setting KRES is setting data for setting a timeout time of the watchdog timer 520 by being used for multiplication with a setting period corresponding to the bit value in the bit number [5-4]. is there. In the example shown in FIG. 8B, when the bit value in the bit number [3-0] of the reset setting KRES is “0000”, the monitoring time measurement by the watchdog timer 520 is prohibited and the watchdog is disabled. Use it. On the other hand, when those bit values are “1000”, the timeout period of the watchdog timer 520 is set by multiplying the set period by “8”. When those bit values are “1111”, the time-out time of the watchdog timer 520 is set by multiplying the set period by “15”.

  As described above, by setting the bit values in the bit number [5-4] and the bit number [3-0] of the reset setting KRES, the monitoring time measured by the watchdog timer 520 has a plurality of predetermined types. Can be set from In the example shown in FIG. 8B, when the bit value in the bit number [5-4] of the reset setting KRES is “11” and the bit value in the bit number [3-0] is “1111”, the monitoring time The maximum time that can be set as is set. As an example, when the frequency of the internal system clock SCLK is 10.0 MHz, the longest monitoring time is about 50.33 seconds. As another example, when the frequency of the internal system clock SCLK is 12.0 MHz, the longest monitoring time is about 41.94 seconds.

  Interrupt initial settings KIIS stored in the program management area indicate initial settings related to handling of maskable interrupts generated in the game control microcomputer 100. FIG. 9A shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of maskable interrupt factor priorities is set. In the example shown in FIG. 9A, if any of “00H” to “02H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt factor from the timer circuit 508 is given the highest priority. A combination of priorities is set. On the other hand, if either “03H” or “04H” is specified, a combination of priorities that gives the highest priority to the maskable interrupt factor from the serial communication circuit 511 is set. If either “05H” or “06H” is designated, a combination of priorities that gives the highest priority to maskable interrupt factors from the random number circuits 509A and 509B is set. Note that even if the priority combination has the highest priority for maskable interrupt factors from the same circuit, if the specified value is different, the type of maskable interrupt factor that has the highest priority, the priority combination in the second or lower order, etc. will differ. ing.

  16-bit random number initial setting 1st KRL1 to 16-bit random number initial setting 3rd KRL3 stored in the program management area indicate initial settings for the 16-bit random number circuit 509A. FIG. 9B shows an example of setting contents in the 16-bit random number initial setting first KRL1. FIG. 9C shows an example of setting contents in the 16-bit random number initial setting third KRL3. In this embodiment, the 16-bit random number circuit 509A can independently generate 16-bit pseudo random numbers of the four channels ch0 to ch3.

  Bit number [7] of the 16-bit random number initial setting first KRL1 sets the method of starting the 16-bit random number circuit 509A in order to generate the 16-bit random number of the channel ch1 The random number circuit start for the 16-bit random number channel ch1 Setting data. In the example shown in FIG. 9B, when the bit value in the bit number [7] of the 16-bit random number initial setting first KRL1 is “0”, the maximum value in the 16-bit random number of the channel ch1 is set to the user program (software ) Is activated, a circuit for generating a 16-bit random number of channel ch1 is activated. On the other hand, when the bit value is “1”, the operation state of the gaming control microcomputer 100 shifts from the security mode to the user mode, thereby generating a 16-bit random number of the channel ch1. The circuit is automatically activated.

  The bit number [6] of the 16-bit random number initialization first KRL1 is a random number update clock RGK (see FIG. 15) used for updating numerical data that becomes a random value when generating a 16-bit random number of the channel ch1. This is random number update clock setting data for the 16-bit random number channel ch1 for setting whether to use the internal system clock SCLK or to divide the random number clock RCK by two (RCK / 2). In the example shown in FIG. 9B, when the bit value at the bit number [6] of the 16-bit random number initial setting first KRL1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. On the other hand, in the case of “1”, the setting is made such that the random number clock RCK divided by two (RCK / 2) is used as the random number update clock RGK.

  The 16-bit random number initial setting 1st KRL1 bit number [5-4] sets whether or not to change the random number update rule when generating the 16-bit random number of channel ch1, and the change method in the case of changing 16 This is random number update rule setting data for the bit random number channel ch1. In the example shown in FIG. 9B, when the bit value in the bit number [5-4] of the 16-bit random number initial setting first KRL1 is “00”, the random number update rule is not changed, and “01” is set. Is set to change the random number update rule by software. When it is “10”, the random number update rule is automatically changed from the second round. When it is “11”, The random number update rule is automatically changed from the first round.

  In the example shown in FIG. 9B, the bit numbers [3], [2], and [1-0] of the 16-bit random number initial setting first KRL1 are the random number circuit start setting data and the random number for the 16-bit random number channel ch0, respectively. This is update clock setting data and random number update rule setting data. That is, the bit number [3-0] of the 16-bit random number initial setting first KRL is the same as the case of initializing the 16-bit random number of the channel ch1 by the bit number [7-4]. Is the setting data for performing the initial setting.

  Note that the bit numbers [7], [6], and [5-4] of the 16-bit random number initial setting second KRL2 are the random number circuit start setting data, random number update clock setting data, and random number update rule for the 16-bit random number channel ch3, respectively. Setting data. Bit numbers [3], [2], and [1-0] of the 16-bit random number initial setting second KRL2 are the random number circuit start setting data, random number update clock setting data, and random number update rule setting data for the 16-bit random number channel ch2, respectively. It has become.

  Bit number [7] and bit number [6] of 16-bit random number initial setting 3rd KRL3 set a start value in numerical data to be a 16-bit random number of channel ch3. Random number start value setting data for 16-bit random number channel ch3 It is. In the example shown in FIG. 9C, when the bit value in the bit number [7] of the 16-bit random number initial setting third KRL3 is “0”, the start value is set to “0000H” which is a predetermined default value. On the other hand, in the case of “1”, a value based on the ID number, which is unique identification information given to each game control microcomputer 100, is set as the start value. Further, in the example shown in FIG. 9C, when the bit value [6] of the 16-bit random number initial setting third KRL3 is “0”, the start value is not changed at every system reset. On the other hand, when “1” is set, the start value is changed every time the system is reset.

  When the start value is set to a value based on the ID number, a part or all of the calculation for performing a predetermined scramble process on the ID number and the calculation such as addition / subtraction / multiplication / division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value. Further, when the bit value in the bit number [6] of the 16-bit random number initial setting third KRL3 is “1”, the count in a predetermined free-run counter (for example, the free-run counter 509C shown in FIG. 5) is performed every system reset. A value set based on the value may be used as the start value. Further, when the bit values [7] and [6] of the 16-bit random number initial setting third KRL3 are both “1”, the bit number is set based on the ID number and the count value in the free-run counter. Can be used as the start value.

  Bit number [5] and bit number [4] of the 16-bit random number initial setting third KRL3 set the start value in the numerical data that becomes the 16-bit random number of the channel ch2 The random number start value setting data for the 16-bit random number channel ch2 It is. That is, the bit number [5] and the bit number [4] of the 16-bit random number initial setting third KRL3 are the same as the case where the 16-bit random number of the channel ch3 is initialized by the bit number [7] and the bit number [6]. And setting data for initial setting of a 16-bit random number of channel ch2. Bit number [3] and bit number [2] of the 16-bit random number initial setting third KRL3 are random number start value setting data for the 16-bit random number channel ch1. Bit number [1] and bit number [0] of 16-bit random number initial setting third KRL3 are random number start value setting data for 16-bit random number channel ch0.

  The 8-bit random number initial setting 1st KRS1 and the 8-bit random number initial setting 2nd KRS2 stored in the program management area indicate the initial setting for the 8-bit random number circuit 509B. In this embodiment, the 8-bit random number circuit 509B can independently generate 8-bit pseudo random numbers of the four channels ch0 to ch3. The 8-bit random number initial setting first KRS1 is a random number circuit start setting data, a random number update clock setting data, a random number update rule setting data for the 8-bit random number channel ch1, a random number circuit start setting data for the 8-bit random number channel ch0, and a random number update. Clock setting data and random number update rule setting data are included. The 8-bit random number initial setting second KRS2 is a random number circuit start setting data, a random number update clock setting data, a random number update rule setting data for the 8-bit random number channel ch3, a random number circuit start setting data for the 8-bit random number channel ch2, and a random number update. Clock setting data and random number update rule setting data are included. That is, the 8-bit random number initial setting 1st KRS1 and the 8-bit random number initial setting 1st KRS2 perform the initial setting for the 16-bit random numbers of the channel ch0 to the channel ch3 by the 16-bit random number initial setting 1st KRL1 and the 16-bit random number initial setting 2nd KRL2. Similarly, the setting data for performing the initial setting for the 8-bit random numbers of channel ch0 to channel ch3.

  The security time setting KSES stored in the program management area indicates a setting for extending the security mode time (security mode time) that is the operation state of the game control microcomputer 100 when the power is turned on. Here, when the operation state of the game control microcomputer 100 is the security mode, a predetermined security check process is executed to check whether or not the content stored in the ROM 506 has been changed. FIG. 10 shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES indicates a time setting when the security mode time is extended by a random time every system reset. In the example shown in FIG. 10, if the bit value in the bit number [7-6] of the security time setting KSES is “00”, the random time extension is not performed. On the other hand, if the bit value is “01”, the short mode is set, if “10”, the middle mode is set, and if “11”, the long mode is set. Here, when the short mode, the middle mode, or the long mode is designated, for example, the count value of the free-run counter built in the game control microcomputer 100 is used as the game control microcomputer 100 when a system reset occurs. Is stored in a predetermined built-in register (variable security mode time register). Then, by using the stored value of the variable security time register as it is at the time of initialization, or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function), the security mode time The extension time at the time of extending may be determined at random.

  As an example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 816 μs (microseconds) in the short mode, and 0 to 26.112 ms (milliseconds) in the middle mode. In the long mode, and the extension time is randomly determined in the range of 0 to 8355.584 ms. As another example, when the frequency of the internal system clock SCLK is 12.0 MHz, the extension time is randomly determined in the range of 0 to 510 μs in the short mode and in the range of 0 to 16.32 ms in the middle mode. In the long mode, the extension time is randomly determined in a range of 0 to 522.24 ms.

  The variable security mode time register only needs to be backed up using a backup power source common to the backup location on the main board 11, such as a backup area in the RAM 507 of the game control microcomputer 100. Alternatively, the variable security mode time register may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 507 or the like. In this way, the variable security mode time register is backed up by the backup power supply, so that the stored value of the variable security mode time register is saved for a predetermined period even when the power supply is stopped. Note that the timing at which the count value in the free-run counter is read and stored in the variable security mode time register is not limited to when a system reset occurs, and may be any predetermined timing. Alternatively, the free run counter may be backed up by a backup power source, and the extension time for extending the security mode time may be determined at random using the stored value read from the free run counter at the initial setting.

  Also, the short time, middle mode, and long mode are set by the bit value [7-6] of the security time setting KSES, and the bit value [4-0] of the security time setting KSES is set to By setting a value other than “0001”, the extension time added to the fixed time can be set. In this case, both the extension time corresponding to the bit value in the bit number [4-0] and the extension time randomly determined based on the bit value in the bit number [7-6] are fixed times. The security mode time during which the game control microcomputer 100 is in the security mode is determined by the addition.

  The external bus interface 501 provided in the game control microcomputer 100 shown in FIG. 5 is an interface function between an external bus and an internal bus of the chip constituting the game control microcomputer 100, an address bus, a data bus, and each control signal. A bus interface having a direction control function and the like. For example, the external bus interface 501 is connected to an external memory, an external input / output device or the like externally attached to the game control microcomputer 100, and address signals, data signals, various control signals, etc. with these external devices As long as it transmits and receives. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to the internal data of the game control microcomputer 100 from an external device via the external bus interface 501, and for example, a game control program (game control processing program) stored in the ROM 506 And a circuit for limiting inappropriate external reading of internal data such as fixed data. Here, a circuit analysis device such as an in-circuit emulator (ICE; InCircuit Emulator) may be connected to the external bus interface 501 as an external device.

  As an example, according to the contents of the header KHDR stored in the program management area of the ROM 506, it is possible to switch between prohibiting or permitting reading of stored data in the ROM 506. For example, when the header KHDR is bus output mask invalid data, the ROM 506 can be read by an external device, and external reading of internal data is permitted. On the other hand, if the header KHDR is bus output mask valid data, the ROM 506 can be read from the external device by masking the address bus output, data bus output and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that internal data cannot be read from the external device. . Further, when the header KHDR is ROM read prohibition data, the ROM 506 itself may not be read, and reading of stored data in the ROM 506 may be prevented. For example, in a ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, if the ROM for mass production is used, the bus output mask valid data is written in the header KHDR, so that the ROM 506 can be read by the CPU 505 and the like inside the game control microcomputer 100, while the external device It is only necessary to prevent the ROM 506 from being read.

  As another example, the internal resource access control circuit 501A is requested by an external device connected to the external bus interface 501 to read out internal data of the game control microcomputer 100 such as part or all of the stored data in the ROM 506. Detect that. When this read request is detected, the internal resource access control circuit 501A determines whether or not reading of the internal data of the game control microcomputer 100 is permitted. For example, it is assumed that encryption processing is performed on part or all of the storage data in the ROM 506. In this case, if the read request from the external device is a read request for the encryption processing program or key data stored in the ROM 506, the internal resource access control circuit 501A rejects the read request, and the game control micro Reading of the internal data of the computer 100 is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 506 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be turned off. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 506). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from an external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 506. When an authentication code is input from the external device, the authentication code is compared with the authentication code stored in the internal device. If they match, a read request is accepted and the internal data of the game control microcomputer 100 is read. To give permission. On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and reading of the internal data of the game control microcomputer 100 is prohibited. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. Thereby, it is possible to read out the internal data of the game control microcomputer 100 using a correct authentication code known in advance by an inspection organization or the like, and to properly inspect the validity of the internal data. become.

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 506 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the reading prohibition flag is in the off state, reading of the ROM 506 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. That's fine. That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A does not have a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read internal data of the game control microcomputer 100 such as data stored in the ROM 506. At this time, if the reading prohibition flag is on, the reading request from the external device is rejected, and reading of the internal data of the gaming control microcomputer 100 is prohibited. On the other hand, if the read prohibition flag is OFF, a read request from an external device is accepted and reading of the internal data of the game control microcomputer 100 is permitted. With such a configuration, a provider who creates a game control processing program for game control and stores it in the ROM 506 can load a program that has been debugged from the ROM 506 with the read prohibition flag off. Can be read. Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 506 can be restricted thereafter, and by the user of the pachinko gaming machine 1 or the like Reading of the ROM 506 can be prevented. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  Note that the read prohibition flag is not set irreversibly but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, external reading of the ROM 506 may be restricted by erasing the data stored in the ROM 506 (for example, flash erasure).

  The clock circuit 502 included in the game control microcomputer 100 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In this embodiment, the control clock CCLK generated by the control clock generation circuit 111 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 505 that control the progress of the game in the game control microcomputer 100. The internal system clock SCLK is also supplied to random number circuits 509A and 509B. Furthermore, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the game control microcomputer 100. It is desirable that the internal system clock SCLK is not output to the outside of the game control microcomputer 100. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 505) of the game control microcomputer 100 from the outside, and numerical data that becomes a random value Can be prevented from being specified from the outside when the software is updated by software.

  The unique information storage circuit 503 included in the game control microcomputer 100 is a circuit that stores a plurality of types of unique information that is internal information of the game control microcomputer 100, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 506 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 506, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the game control microcomputer 100 is manufactured, and represents a different numerical value for each chip constituting the game control microcomputer 100. The ID number is an 8-byte number assigned when the game control microcomputer 100 is manufactured, and indicates a different numerical value for each chip constituting the game control microcomputer 100. Here, the chip individual number may be read from the user program, while the ID number may be set so as not to be read from the user program. The unique information storage circuit 503 may be included in the ROM 506 by using a predetermined area of the ROM 506, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 505 by using a built-in register of the CPU 505, for example.

  The reset controller 504A included in the game control microcomputer 100 is for controlling various resets generated inside or outside the game control microcomputer 100. The reset controlled by the reset controller 504A includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  The reset controller 504A uses the internal information register CIF (address FE25H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. It enables recording of abnormalities in the bit random number and random number clock RCK. FIG. 11A shows a configuration example of the internal information register CIF. FIG. 11B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF.

  The internal information data CIF7 to CIF4 stored in the bit number [7-4] of the internal information register CIF correspond to the 16-bit random numbers of the channels ch3 to ch0, and are random numbers indicating the presence or absence of abnormality in the random number value update operation. This is an update abnormality instruction. In the example shown in FIG. 11B, the bit value in each of the internal information data CIF7 to CIF4 is “0” when an abnormality in the update operation is not detected for the 16-bit random numbers of channel ch3 to channel ch0. On the other hand, when an abnormality is detected in the 16-bit random number update operation, the bit value in any of the internal information data CIF7 to CIF4 becomes “1” corresponding to the channel in which the abnormality is detected. More specifically, if the channel in which an abnormality is detected in the 16-bit random number update operation is channel ch3, the internal information data CIF7 is “1”, and if the channel is channel 2, the internal information data CIF6 is “1”. If it is channel ch1, the internal information data CIF5 is “1”, and if it is channel ch0, the internal information data CIF4 is “1”.

  The internal information data CIF3 stored in the bit number [3] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCK. In the example shown in FIG. 11B, when the frequency abnormality of the random number clock RCK is not detected, the bit value of the internal information data CIF3 becomes “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 11B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”. As a first example of the operation using the internal information data CIF2, the CPU 505 of the game control microcomputer 100 checks the bit value of the internal information data CIF2 when the power is turned on, and the bit value is “1” (set). If not, it is determined that the power is not turned on normally. At this time, for example, by transmitting a predetermined effect control command toward the effect control board 12, an illegal signal input action is performed aiming at a big hit gaming state immediately after the power is turned on in the pachinko gaming machine 1. You may notify that there exists possibility with a production | presentation apparatus etc. Further, as a second example of the operation using the internal information data CIF2, when the pachinko gaming machine 1 notifies the probability variation state only when the power is turned on and does not inform the probability variation state normally, the game control microcomputer 100 when the power is turned on. The CPU 505 or the like may check the bit value of the internal information data CIF2, and if the bit value is not “1” (set), the gaming state may not be notified.

  Whether internal information data CIF1 stored in bit number [1] of internal information register CIF is a user reset due to a timeout of watchdog timer (WDT) 520 incorporated in reset controller 504A is the reset factor generated immediately before. This is a watchdog timeout instruction that indicates In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to timeout of the watchdog timer 520 (no timeout occurs), the bit value of the internal information data CIF1 becomes “0”, while When a user reset is caused by a timeout of the dog timer 520 (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 11B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  A watchdog timer 520 is built in the reset controller 504A. The watchdog timer 520 is a time-out signal for restarting the game control microcomputer 100 in a reset state when the game control microcomputer 100 cannot execute the user program normally and a predetermined monitoring time has elapsed. Is output. Note that the watchdog timer 520 may be externally attached to the reset controller 504A while being incorporated in the game control microcomputer 100. Alternatively, the watch dog timer 520 may be externally attached to the game control microcomputer 100.

  FIG. 12 shows a configuration example of the watchdog timer 520. The activation method of the watchdog timer 520 is set by the bit value in the bit number [6] of the reset setting KRES stored in the program management area of the ROM 506. In this embodiment, the bit value in the bit number [6] of the reset setting KRES is set in advance in order to activate the watchdog timer 520 by software by executing the user program and enable the reset operation. Setting data “1” is stored. Further, the bit value in the bit number [5-4] of the reset setting KRES is set so that the time-out time as the monitoring time measured by the watchdog timer 520 becomes the longest time among a plurality of settable monitoring times. The setting data in which the bit value in the bit number [3-0] of the reset setting KRES is set to “1111” in advance is stored together with the setting data set to “11” in advance.

  The watchdog timer 520 shown in FIG. 12 includes a WDT control circuit 533, a count clock generation circuit 535, a 16-bit up counter 536, and an output control circuit 537. The WDT control circuit 533 is a circuit that controls the operation of the watchdog timer 520. The WDT control circuit 533 sets the reference clock generated by the count clock generation circuit 535 and the time-out in the 16-bit up counter 536 to operate the watchdog timer 520 based on the reset setting KRES of the program management area. Set the time.

  Further, the WDT control circuit 533 has a predetermined WDT activation control code set in the WDT start register WST (address FE23H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. 7B. Thus, the software by the execution of the user program can be switched so that the watchdog timer 520 is activated and the reset operation is validated, or the watchdog timer 520 is deactivated and the reset operation is invalidated. FIG. 13A shows a configuration example of the WDT start register WST. FIG. 13B shows an example of setting contents by WDT start data stored in the WDT start register WST.

  In the example shown in FIGS. 13A and 13B, when “CCH” is written in the WDT start register WST by the CPU 505, the watchdog timer 520 is activated to enable the reset operation due to the elapse of the timeout time. . On the other hand, when “33H” is written to the WDT start register WST by the CPU 505, the watchdog timer 520 is stopped and the reset operation due to the elapse of the timeout time is invalidated. As described above, the data indicating the value of “CCH” serving as the WDT activation control code is written to the WDT start register WST, whereby the watchdog timer 520 is activated. On the other hand, the data indicating the value of “33H” serving as the WDT stop control code is written into the WDT start register WST, whereby the watchdog timer 520 is stopped.

  Further, the WDT control circuit 533 is configured by setting predetermined WDT clear data in the WDT clear register WCL (address FE24H) among the built-in registers provided in the game control microcomputer 100 as shown in FIG. 7B. The watchdog timer 520 count is cleared and restarted. FIG. 14A shows a configuration example of the WDT clear register WCL. FIG. 14B shows an example of setting contents by WDT clear data stored in the WDT clear register WCL.

  In the example shown in FIGS. 14A and 14B, when “55H” is written to the WDT clear register WCL by the CPU 505 and then “AAH” is written by the CPU 505, the WDT control circuit 533 is increased by 16 bits. The count value of the counter 536 is cleared and the count operation is restarted. Thus, the measurement of the timeout time as the monitoring time in the watchdog timer 520 is initialized and restarted by sequentially writing WDT clear data having different values of “55H” and “AAH” in the WDT clear register WCL. Can do. Note that the WDT clear data consisting of “55H” and “AAH” does not need to be written continuously for 2 bytes, but it is necessary to write in this order.

  The count clock generation circuit 535 generates a reference clock for setting a timeout time using the internal system clock SCLK. The 16-bit up counter 536 counts the reference clock generated by the count clock generation circuit 535. When the count value reaches a predetermined value corresponding to the timeout time, the output control circuit 537 outputs a timeout signal. On the other hand, when the CPU 505 writes the WDT clear data to the WDT clear register WCL in a predetermined order before the timeout time elapses, the count value is cleared and restarted in the 16-bit up counter 535. For example, when the CPU 505 executes a process that becomes an infinite loop and the operation state of the game control microcomputer 100 shifts to the standby state, the watch dog timer 520 is activated to enable the reset operation due to the elapse of the timeout time. At this time, since WDT clear data is not written to the WDT clear register WCL, the count value of the 16-bit up counter 535 reaches a predetermined value and a timeout occurs. The output control circuit 537 outputs the timeout signal from the 16-bit up counter 535 to the reset circuit of the reset controller 504A.

  The interrupt controller 504B provided in the game control microcomputer 100 is for controlling various interrupt requests generated inside or outside the game control microcomputer 100. Interrupts controlled by the interrupt controller 504B include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 505 is in an interrupt-disabled state. is there. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 505, and multiple interrupts can be executed by setting priority. The maskable interrupt INT is caused by the fact that a low level signal is input to the external maskable interrupt terminal XINT (also used as the input port PI5) for a certain period of time, and that a timeout occurs in the timer circuit included in the timer 508. Multiple types of interrupt factors such as the occurrence of an interrupt factor due to data reception or data transmission in the serial communication circuit 511, or the occurrence of an interrupt factor due to the acquisition of numerical data as a random value in the random number circuits 509A and 509B May be determined in advance.

  The interrupt controller 504B includes an interrupt mask register IMR (address FE26H), an interrupt wait monitor register IRR (address FE27H), and an interrupt monitor monitor among the built-in registers included in the game control microcomputer 100 as shown in FIG. Interrupt control and reset management are performed using ISR (address FE28H) or the like. The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The in-interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS.

  The CPU 505 provided in the game control microcomputer 100 executes a user program (game control processing program for game control) based on a control code read from the ROM 506, thereby executing a game control in the pachinko gaming machine 1. CPU. When such game control is executed, a fixed data reading operation in which the CPU 505 reads fixed data from the ROM 506, a variable data writing operation in which the CPU 505 writes various variable data to the RAM 507 and temporarily stores the data, and the CPU 505 is temporarily stored in the RAM 507. The CPU 505 receives the various data from the outside of the game control microcomputer 100 via the external bus interface 501, the PIP 510, the serial communication circuit 511, and the like. A transmission operation for outputting various signals to the outside of the game control microcomputer 100 via the external bus interface 501 and the serial communication circuit 511 is also performed.

  As described above, in the game control microcomputer 100, the CPU 505 executes control in accordance with the program stored in the ROM 506. Therefore, the game control microcomputer 100 (or CPU 505) executes (or performs processing) hereinafter. Specifically, the CPU 505 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 11.

  The ROM 506 provided in the game control microcomputer 100 stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The ROM 506 stores a security check program 506A. The CPU 505 reads the security check program 506A stored in the ROM 506 when the game control microcomputer 100 shifts to the security mode in response to the power-on of the pachinko gaming machine 1 or the occurrence of a system reset. A security check process is executed to check whether or not the change has been made. Note that the security check program 506A may be stored in a built-in memory different from the ROM 506. Further, the security check program 506A may correspond to a security check process for inspecting the storage content of an external memory externally attached to the game control microcomputer 100 via the external bus interface 501, for example.

  A RAM 507 provided in the game control microcomputer 100 provides a work area for game control. Here, at least a part of the RAM 507 may be a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 507 is stored for a predetermined period.

  The timer circuit 508 provided in the game control microcomputer 100 is configured, for example, by incorporating an 8-bit programmable timer with three channels (PTC0 to PTC2), and enables real-time interrupt generation and time measurement. Each programmable timer PTC0-PTC2 has a timer value that is updated in response to a change in the count clock signal generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is.

  The game control microcomputer 100 includes, as random number circuits, for example, a random number circuit 509A that generates numerical data that is a 16-bit random number, and a random number circuit 509B that generates numerical data that is an 8-bit random number. In this embodiment, on the main board 11 side, a random number value MR1 for determining a special figure display result, a random value MR2 for determining a jackpot type, a random value MR3 for determining a variation pattern type, and a random value for determining a variation pattern Numerical data indicating each of MR4 and random number value MR5 for determining a normal map display result may be controlled so that it can be counted (updated). In addition, in order to improve a game effect, random numbers other than these may be used. Such random numbers used to control the progress of the game are also referred to as game random numbers.

  Based on the numerical data extracted from the random number circuits 509A and 509B, the CPU 505 uses a random counter different from the random number circuits 509A and 509B, for example, a random counter provided in a predetermined area (game control counter setting unit or the like) of the RAM 507. The numerical data indicating some or all of the random number values MR1 to MR5 may be counted by processing or updating various numerical data by software. Alternatively, the CPU 505 counts (updates) a part of numerical data indicating the random number values MR1 to MR5 by software without using the random number circuits 509A and 509B, for example, using only a random counter provided in the game control counter setting unit. ). As an example, numerical data extracted by the CPU 505 from a 16-bit random number circuit 509A serving as hardware is processed by software to update numerical data indicating the random value MR1 for determining the special figure display result. The numerical data indicating the random number values MR2 to MR5 may be updated by software by the CPU 505 using a random counter or the like.

  Alternatively, the CPU 505 counts numerical data indicating the random value MR1 for determining the special figure display result by using a random counter or without using a random counter based on the numerical data extracted from the 16-bit random number circuit 509A. To do. On the other hand, the CPU 505 uses the random counter based on the numerical data extracted from the 8-bit random number circuit 509B, or without using the random counter, the random value MR2 for determining the big hit type and the variable pattern type determining Numerical data indicating the random value MR3, the random value MR4 for determining the variation pattern, and the random value MR5 for determining the normal display result may be counted independently.

  The random value MR1 for determining the special figure display result is determined whether the variable display result of the special symbol or the like in the special figure game is controlled as a big hit game state, whether the variable display result is "small hit" or not. This is a random value used to determine whether or not to control the gaming state. For example, the random number value MR1 for determining the special figure display result takes a value in the range of “0” to “65535”. The random value MR2 for determining the big hit type is a random value used for determining the big hit type as one of a plurality of types when the variable display result is “big hit”. For example, the random value MR2 for determining the big hit type takes a value in the range of “0” to “99”.

  The random number value MR3 for determining the variation pattern type is a random value used to determine the variation pattern type of the decorative design as one of a plurality of types prepared in advance. For example, the random value MR3 for determining the variation pattern type takes a value in the range of “0” to “241”. Here, each variation pattern type may be configured to include one or a plurality of variation patterns classified based on, for example, a rendering operation executed during variable display of decorative symbols. Note that some of the plurality of variation pattern types may be configured to include a common variation pattern, and all of the variation patterns included in one variation pattern type may be the other variation pattern. Some may be configured to be included in the type. The random number value MR4 for determining the variation pattern is a random value used for determining one of a plurality of types of variation patterns of the decorative pattern prepared in advance. For example, the random number MR4 for determining the variation pattern takes a value in the range of “0” to “997”. The random number value MR5 for determining the normal figure display result is a random value used for determining whether or not the variable symbol display result of the normal symbol in the normal figure game is “per normal figure”. For example, the random number value MR5 for determining the normal display result takes a value in the range of “3” to “14”.

  FIG. 15 is a block diagram illustrating an example of a circuit configuration corresponding to the channel ch0 in the 16-bit random number circuit 509A. As shown in FIG. 15, a circuit for generating a 16-bit random number corresponding to channel ch0 includes a random number update clock selection circuit 551, a random number generation circuit 553A, a random number activation setting circuit 553B, a start value setting circuit 553C, and a random number sequence. A change circuit 554A, a random number sequence change setting circuit 554B, a maximum value comparison circuit 555, hard latch selectors 558A and 558B, hard latch random number value registers 559A and 559B, and a soft latch random number value register 559S are configured.

  For example, the random number update clock selection circuit 551 determines whether the bit value in the bit number [2] (in the case of channel ch0) of the 16-bit random number initial setting first KRL1 is “0” or “1”. The clock SCLK or the random number clock RCK divided by two (RCK / 2) is selected and output as the random number update clock RGK. The random number update clock RGK output from the random number update clock selection circuit 551 is input to the clock terminal of the random number generation circuit 553A and is used for incrementing the count value in the random number generation circuit 553A.

  The internal system clock SCLK or the random number clock RCK divided by two (RCK / 2) selected by the random number update clock selection circuit 551 may be input to the clock terminal of a predetermined clock flip-flop. In the clock flip-flop, the reverse phase output terminal (inverted output terminal) is connected to the data input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal), while the latch clock is output from the negative phase output terminal (inverted output terminal). In this case, when the signal state of the clock signal input to the clock terminal changes in a predetermined manner, the clock flip-flop is connected from the positive phase output terminal (non-inverted output terminal) and the negative phase output terminal (inverted output terminal). The signal state in the output signal is changed. For example, the clock flip-flop has a rising timing at which the signal state of the clock signal changes from low level to high level, or a falling timing at which the signal state of the clock signal changes from high level to low level. At either timing, the input signal at the data input terminal is captured. At this time, from the positive phase output terminal (non-inverted output terminal), the input signal captured at the data input terminal is output without being inverted, while from the negative phase output terminal (inverted output terminal), The input signal captured at the data input terminal is inverted and output. Thus, the random-phase update clock RGK having an oscillation frequency that is ½ of the oscillation frequency of the clock signal is output from the positive phase output terminal (non-inverted output terminal) of the clock flip-flop, while the negative phase output terminal (inverted) From the output terminal, a latch phase clock (inverted signal) of the random number update clock RGK, that is, a latching clock having the same frequency as the random number update clock RGK and a phase different from the random number update clock RGK by π (= 180 °) is output. .

  The latch clock output from the clock flip-flop is branched at a predetermined branch point, and a plurality of latch clocks having the same oscillation frequency and changing signal states with a common cycle are generated. Also good. Of the plurality of latch clocks generated in this way, the first latch clock may be a random number acquisition clock used to generate the random number latch signal LL1 based on the input of the first start winning signal SS1. . Of the plurality of latch clocks, the second latch clock may be a random number acquisition clock used to generate the random number latch signal LL2 based on the input of the second start winning signal SS2.

  The oscillation frequency of the random number clock RCK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other, and one of the oscillation frequencies is the other oscillation frequency. It is never an integer multiple of. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clock are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 505. That is, the clock flip-flop serves as a random number update clock RGK for updating the count value or a latch clock serving as a plurality of random number acquisition clocks based on the random number clock RCK generated by the random number clock generation circuit 112. Then, an oscillation signal whose signal state changes with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) is generated.

  The random number generation circuit 553A is composed of a 16-bit counter, for example, and based on an input such as a random number update clock RGK output from the random number update clock selection circuit 551, a predetermined initial value within a predetermined range in which numerical data can be updated. Is a circuit that cyclically updates from a predetermined value to a predetermined final value. For example, the random number generation circuit 553A responds to the falling edge of the random number update clock RGK, which is an input signal to a predetermined clock terminal, from the initial value set within the range from “0” to “65535” to “65535”. The numerical data is counted up so that “1” is added to “1”. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The random number activation setting circuit 553B starts random number generation that differs depending on whether the bit value in the bit number [3] (for channel ch0) of the 16-bit random number initial setting first KRL1 is “0” or “1”, for example. When the condition is satisfied, a setting is made to start a 16-bit random number generation operation. More specifically, when the corresponding bit value is “0”, when the maximum value in the 16-bit random number is designated by the user program (software), the random number generation circuit 553A is activated and the 16-bit random number Start the generation operation. On the other hand, if the corresponding bit value is “1”, the random number generation circuit 553A is activated to generate a 16-bit random number when the operation state of the gaming control microcomputer 100 shifts from the security mode to the user mode. Start operation.

  The start value setting circuit 553C sets the start value in the count value generated by the random number generation circuit 553A in accordance with the bit value in the bit number [1-0] (for channel ch0) of the 16-bit random number initial setting third KRL3, for example. Set. For example, the start value setting circuit 553C sets the start value to the default value “0000H” if the corresponding bit value is “00” or “01”, and the system reset if the bit value is “00”. While the start value is not changed every time, if the bit value is “01”, the start value is changed every time the system is reset. If the corresponding bit value is “10” or “11”, the start value is set to a value based on the ID number. If the bit value is “10”, the start value is not changed every time the system is reset. On the other hand, if the bit value is “11”, the start value is changed at every system reset.

  When the start value is changed at each system reset, the count value of the free-run counter 509C is used as it is at the time of initial setting, or the count value is obtained by substituting it into a predetermined arithmetic function (for example, a hash function). The start value may be determined at random by using the measured value. The free-run counter 509 </ b> C only needs to be backed up using a backup power source common to the backup location on the main board 11, such as a backup area in the RAM 507 of the game control microcomputer 100. Alternatively, the free-run counter 509C may be backed up by a power source provided separately from a backup power source used for a backup area or the like in the RAM 507. In this way, the free-run counter 509C is backed up by the backup power source, so that the count value in the free-run counter 509C is stored for a predetermined period even when the power supply is stopped.

  The free-run counter 509C is not limited to the one backed up by the backup power source. For example, when a system reset occurs, the count value of the free-run counter 509C is stored in a predetermined built-in register (for example, a random number start value register). May be backed up by a backup power source. Then, the initial value is randomly determined by using the stored value of the random number start value register as it is or by using the value obtained by substituting the stored value into a predetermined arithmetic function. Also good. In this case, the timing at which the count value in the free-run counter 509C is read and stored in the random number start value register is not limited to when a system reset occurs, and may be any predetermined timing. The free-run counter 509C may be a dedicated free-run counter that is built in the random number circuits 509A and 509B and is used to randomly determine the start value of the numerical data. That is, the free-run counter 509C may be provided as a separate configuration from the free-run counter used for randomly determining the extension time when extending the security time. Alternatively, a free-run counter 509C, which is built in the game control microcomputer 100 but is provided outside the random number circuits 509A and 509B, is used for random determination of the extension time when extending the security time. A common counter may be used. In this case, in the process of determining the start value of the numerical data and the process of randomly determining the extension time in the security time, for example, the calculation function for substituting the count value is different from each other, or one of the determinations is made In the process, the count value is used as it is, while in the other determination process, the value obtained by substituting the count value into a predetermined arithmetic function is used. It may be different.

  The free-run counter 509C may incorporate, for example, four channels (PCC0 to PCC3) of 8-bit programmable counters. Each of the programmable counters PCC0 to PCC3 only needs to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3.

  The free-run counter 509C may be included in the random number circuits 509A and 509B, or may be included in the internal circuit of the game control microcomputer 100 although it is not included in the random number circuits 509A and 509B. In addition, the free-run counter 509C may be the same counter as the free-run counter used for randomly determining the extended time for extending the security time for each system reset, or provided separately. It may be a counter.

  The random number sequence change circuit 554A is a circuit that allows the permutation of numerical data generated by the random number generation circuit 553A to be changed to a permutation according to a predetermined random number update rule. For example, the random number sequence change circuit 554A executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553A. Further, the random number sequence changing circuit 554A can change the permutation of numerical data, for example, by changing a bit scramble key or a bit scramble table used for bit scramble processing.

  The random number sequence change setting circuit 554B changes the random number update rule in the random number sequence change circuit 554B in accordance with, for example, the bit value in the bit number [1-0] (in the case of channel ch0) of the 16-bit random number initial setting first KRL1. It is a circuit for setting. For example, the random number sequence change setting circuit 554B sets the random number update rule not to be changed if the corresponding bit value is “00”, and responds to a change request in software if the bit value is “01”. The random number update rule is changed. If the bit value is “10”, the random number update rule is automatically changed from the second round. If the bit value is “11”, the random number update rule is automatically changed from the first round.

  The random number sequence changing circuit 554B is for game control as shown in FIG. 7B when the corresponding bit value is “01” in the 16-bit random number initial setting first KRL1 and the like and the random number update rule is changed by software. Among the built-in registers provided in the microcomputer 100, the random number update rule RDSC (address FE73H) is used to control the change of the random number update rule. FIG. 16A shows a configuration example of the random number sequence change register RDSC corresponding to the 16-bit random number of the channel ch0. FIG. 16B shows the setting contents of the random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates the presence / absence of a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 16B, when there is no random number sequence change request by software, the bit value of the random number sequence change request data RDSC0 is “0”, while when there is a random number sequence change request, The bit value is “1”.

  FIG. 17 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553A is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. Then, change the random number update rule. In the operation example shown in FIG. 17, the random number sequence RSN output from the random number sequence changing circuit 554A is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 505 executing the user program stored in the ROM 506.

  Then, in response to the bit number [1-0] of the 16-bit random number initial setting first KRL1 being “01”, the random number sequence change setting circuit 554B reads the random number sequence change request data RDSC0, and the bit value is “ In response to 1 ″, a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 554B selects one of a plurality of types of random number update rules prepared in advance, for example, in response to the count value permutation RCN output from the random number generation circuit 553A reaching a predetermined final value. The random number update rule is changed, for example, by selecting. In the operation example shown in FIG. 17, the random number sequence change circuit 554A outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553A, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence changing circuit 554A outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 554B reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 554A is “65535 → 65534 →. Become.

  When the CPU 505 executes the user program stored in the ROM 506 and the bit value “1” is written again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 17, when the random number sequence change circuit 554A outputs numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. Thereafter, the random number sequence changing circuit 554A outputs “0 → 2 →... → 65534 → 1 →... → 65535” as the random number sequence RSN according to the changed random number update rule.

  FIG. 18 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553A being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 554B automatically generates a random number update rule. To change. In the operation example shown in FIG. 18, the random number sequence RSN output from the random number sequence change circuit 554A is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number sequence change circuit 554A reaches a predetermined final value, the random number sequence change setting circuit 554B determines a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule according to the above. Alternatively, the random number sequence change setting circuit 554B may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 18, the random number sequence RSN output from the random number sequence change circuit 554A becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 554A becomes “0 → 2 →... → 65534 → 1 →. In the operation example shown in FIG. 18, the random number sequence RSN output from the random number sequence change circuit 554A is “65534 → 0 →. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 554A becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 554A becomes “4 → 3 →... → 465553”.

  As described above, the random number sequence change circuit 554A changes the count value permutation RCN output from the random number generation circuit 553A based on a random number update rule predetermined by the setting of the random number sequence change setting circuit 554B. A random number sequence RSN in which data is updated by a predetermined procedure can be output.

  The maximum value comparison circuit 555 compares the maximum value of the random number preset by the user with the random number sequence RSN output from the random number sequence change circuit 554A, and if there is an output value greater than the maximum value, the random number generation circuit 553A Is instructed to reset and restart. The maximum value comparison circuit 555 sets a random number maximum value by using a random number maximum value setting register RMX (address FE67-FE72H) among the built-in registers provided in the game control microcomputer 100 as shown in FIG. 7B. To do. FIGS. 19A and 19B show a configuration example of the random number maximum value setting register RL0MX corresponding to the 16-bit random number of the channel ch0 in the random number maximum value setting register RMX. The CPU 505 writes, for example, random number maximum value setting data indicating the maximum value of the random number specified in advance by the user program in the random number maximum value setting register RL0MX. When random number maximum value setting data is written in the random number maximum value setting register RL0MX, the maximum value is set for the 16-bit random number of the channel ch0. The maximum value of the 16-bit random number may be set to any value in the range of “256” to “65535”, for example. For example, if the bit value in the bit number [3] (in the case of channel ch0) of the 16-bit random number initial setting first KRL1 is “0”, the maximum value can be set for the 16-bit random number. By setting, a 16-bit random number generation operation can be started by a user program (software).

  Hard latch selector 558A selects a signal to be output as random number latch signal LL1 from input signals at input port PI0 to input port PI5 of PIP510. The hard latch selector 558A uses a hard latch selection register RL0LS0 included in the hard latch selection register RLS (address FE5B-FE61H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. 7B. The signal to be output as the random number latch signal LL1 is selected. Hard latch selector 558B selects a signal to be output as random number latch signal LL2 from input signals at input port PI0 to input port PI5 of PIP510. The hard latch selector 558B selects a signal to be output as the random number latch signal LL2 using the hard latch selection register RL0LS1 included in the hard latch selection register RLS. FIG. 20A shows a configuration example of the hard latch selection register RL0LS used as the hard latch selection register RL0LS0 and the hard latch selection register RL0LS1. FIG. 20B shows an example of setting contents in each bit of the hard latch selection data stored in the hard latch selection register RL0LS.

  The hard latch selection data RL03LS stored in the bit number [3] of the hard latch selection register RL0LS indicates a condition for fetching a random value by hardware. In the example shown in FIG. 20B, when the bit value of the hard latch selection data RL03LS is “0”, the corresponding hard latch random number value register (for example, one of the hard latch random number value registers 559A and 559B) is stored. Reading the value sets the next value to be latchable. On the other hand, when the bit value of the latch selection data RL03LS is “1”, the next value is set to be latchable without reading the stored value of the corresponding hard latch random value register.

  The hard latch selection data RL02LS to RL00LS stored in the bit numbers [2-0] of the hard latch selection register RL0LS are external terminals of signals output as corresponding random number latch signals (for example, one of the random number latch signals LL1 and LL2). Setting data for selecting an input. In the example shown in FIG. 20B, an input at any of the input ports PI0 to PI5 can be selected as an external terminal input in accordance with the values of the latch selection data RL02LS to RL00LS.

  In this embodiment, the first start winning signal SS1 from the first start port switch 22A is input to the input port PI0. The hard latch selector 558A selects the first start winning signal SS1 input to the input port PI0 based on the stored value of the hard latch selection register RL0LS0, and outputs it as the random number latch signal LL1. The random number latch signal LL1 may be output in synchronization with the first latching clock. In this embodiment, the second start winning signal SS2 from the second start port switch 22B is input to the input port PI1. The hard latch selector 558B selects the second start winning signal SS2 input to the input port PI1 based on the stored value of the hard latch selection register RL0LS1, and outputs it as the random number latch signal LL2. Note that the random number latch signal LL2 may be output in synchronization with the second latch clock.

  The first start winning signal SS1 and the second start winning signal SS2 are not limited to those directly transmitted from the first start port switch 22A and the second start port switch 22B. As an example, the time during which the output signal from the first start port switch 22A and the output signal from the second start port switch 22B are in the ON state is measured, and the measured time is set to a predetermined time (for example, 3 milliseconds). A timer circuit for outputting the first start winning signal SS1 and the second starting winning signal SS2 may be provided.

  The hard latch random number registers 559A and 559B are registers for storing numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 as random number values. The hard latch random number registers 559A and 559B are both 16-bit (2-byte) registers and can store 16-bit random values corresponding to the channel ch0, for example.

  In response to the fact that the random number latch signal LL1 supplied from the hard latch selector 558A is turned on, the hard latch random number value register 559A converts the numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 into a random value. And store as The hard latch random value register 559A may be in a readable (enable) state when the register read signal supplied from the CPU 505 is turned on, and may output the stored numerical data to an internal bus or the like. On the other hand, when the register read signal is in the OFF state, the same value (for example, “65535H” or the like) may always be output to make the reading impossible (disabled) state. Further, the hard latch random value register 559A may be in a state in which it cannot receive the register read signal when the random number latch signal LL1 is in the ON state. Further, the hard latch random value register 559A is set so that it cannot receive the random number latch signal LL1 when the register read signal is turned on before the random number latch signal LL1 is turned on. Also good.

  In response to the fact that the random number latch signal LL2 supplied from the hard latch selector 558B is turned on, the hard latch random number value register 559B converts the numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 into a random value. And store as The hard latch random value register 559B may be in a readable state (enable) when the register read signal supplied from the CPU 505 is turned on, and may output the stored numerical data to an internal bus or the like. On the other hand, when the register read signal is in the OFF state, the same value (for example, “65535H” or the like) may always be output to make the reading impossible (disabled) state. Further, the hard latch random value register 559B may be in a state in which it cannot receive the register read signal when the random number latch signal LL2 is in the ON state. Further, the hard latch random value register 559B is set so that it cannot receive the random number latch signal LL2 when the register read signal is turned on before the random number latch signal LL2 is turned on. Also good.

  The hard latch random value register 559A and the hard latch random value register 559B are random number hard latch flag registers RHF (addresses FE82 to FE84H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. The random number interrupt control register RIC (addresses FE64 to FE66H) is used to enable operation management and interrupt control at the time of random number latching. The random number hard latch flag register RHF is a register for storing a random number latch flag indicating whether or not numerical data to be a random number value is latched corresponding to each of the hard latch random number value register 559A and the hard latch random number value register 559B. . For example, the random number hard latch flag register RHF stores data indicating the state (on or off) of the random number latch flag corresponding to each of the hard latch random number register 559A and the hard latch random number register 559B. When numerical data is captured and stored in the hard latch random value register 559A or the hard latch random value register 559B, the storage of new numerical data may be restricted by turning on the corresponding random number latch flag. In this case, when the numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B is read, the corresponding random number latch flag is turned off, so that storage of new numerical data is permitted. It only has to be done. The random number interrupt control register RIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random number value is latched in the hard latch random number value register 559A or the hard latch random number value register 559B.

  FIG. 21A shows a configuration example of the random number hard latch flag register RHF. FIG. 21B shows an example of setting contents in each bit that becomes the hard latch flag RLHF0 stored in the random number hard latch flag register RHF. The hard latch flag data RL03HF and RL02HF stored in the bit number [3-2] of the random number hard latch flag register RHF is whether or not numerical data is taken into the hard latch random number value register 559B that becomes the hard latch random number value register RL0HV1. Is a random number latch flag indicating. In the example shown in FIG. 21B, when the numerical data is not captured in the hard latch random value register RL0HV1 (559B) (no random number is captured), the bit values of the hard latch flag data RL03HF and RL02HF are both "0" is cleared and the random number latch flag is cleared to the OFF state. On the other hand, when numeric data is fetched (with random number fetching), those bit values are set to "1" and the random number latch flag is set to the ON state. Is done. The hard latch flag data RL01HF and RL00HF stored in the bit number [1-0] of the random number hard latch flag register RHF is whether or not the numerical data is taken into the hard latch random number value register 559A that becomes the hard latch random number value register RL0HV0. Is a random number latch flag indicating. In the example shown in FIG. 21B, when the numerical data is not captured in the hard latch random value register RL0HV0 (559A) (no random value capture), the bit values of the hard latch flag data RL01HF and RL00HF are both "0" is cleared and the random number latch flag is cleared to the OFF state. On the other hand, when numeric data is fetched (with random number fetching), those bit values are set to "1" and the random number latch flag is set to the ON state. Is done.

  When the bit value in the bit number [3] of the hard latch selection register RL0LS shown in FIGS. 20A and 20B is “0”, when each random number latch flag is on, Storage of new numerical data in the associated hard latch random value register RL0HV0 (559A) or hard latch random value register RL0HV1 (559B) is restricted (prohibited). That is, when the bit values of the hard latch flag data RL01HF and RL00HF indicating whether numerical data has been taken into the hard latch random value register RL0HV0 (559A) are both “1” and the random number latch flag is in the ON state, The numerical data stored in the hard latch random number value register RL0HV0 (559A) cannot be changed, and storage (capture) of new numerical data is restricted (prohibited). Further, when the bit values of the hard latch flag data RL03HF and RL02HF indicating whether or not numerical data has been taken into the hard latch random number value register RL0HV1 (559B) are both “1” and the random number latch flag is in the ON state, The numerical data stored in the hard latch random number value register RL0HV1 (559B) cannot be changed, and storage (capture) of new numerical data is restricted (prohibited). On the other hand, when each random number latch flag is OFF, storage of new numerical data in the hard latch random number value register RL0HV0 (559A) or the hard latch random number value register RL0HV1 (559B) associated with the random number latch flag is performed. Allowed. That is, when the bit values of the hard latch flag data RL01HF and RL00HF are both “0” and the random number latch flag is in the OFF state, the numerical data stored in the hard latch random number value register RL0HV0 (559A) can be changed. Storage of new numerical data is permitted. When the bit values of the hard latch flag data RL03HF and RL02HF are both “0” and the random number latch flag is in the OFF state, the numerical data stored in the hard latch random number value register RL0HV1 (559B) can be changed. Storage of new numerical data is permitted.

  Note that the bit values of the hard latch flag data RL03HF to RL00HF are “0”, the corresponding random number latch flag is cleared to the off state, while being “1”, the positive logic is set to the on state. The present invention is not limited to this, and it may be a negative logic that turns on when the corresponding random number latch flag is turned off when it is “1” and turned on when it is “0”. That is, each random number latch flag is turned on when numerical data is stored in the corresponding hard latch random value register RL0HV0 (559A) or hard latch random value register RL0HV1 (559B), and storage of new numerical data is restricted (prohibited). On the other hand, when the corresponding hard latch random number value register RL0HV0 (559A) or hard latch random number value register RL0HV1 (559B) is read, it is turned off and storage of new numerical data is permitted. I just need it.

  FIG. 22A shows a configuration example of the hard latch interrupt control register RLIC0 corresponding to the 16-bit random number of the channel ch0 included in the random number interrupt control register RIC. FIG. 22B shows an example of setting contents in each bit of the hard latch interrupt control data stored in the hard latch interrupt control register RLIC0. The hard latch interrupt control data RL03IE and RL02IE stored in the bit number [3-2] of the hard latch interrupt control register RLIC0 is obtained when numerical data is taken into the hard latch random number value register 559B that becomes the hard latch random number value register RL0HV1. This shows the interrupt control setting for enabling or disabling the interrupts that occur. In the example shown in FIG. 22 (B), when interrupts at the time of fetching into the hard latch random number value register RL0HV1 (559B) are prohibited (interrupt prohibited), the bit values of the hard latch interrupt control data RL03IE and RL02IE are both set. On the other hand, when this interrupt is permitted (interrupt permitted), the bit value thereof is set to “1”. The hard latch interrupt control data RL01IE and RL00IE stored in the bit numbers [1-0] of the hard latch interrupt control register RLIC0 are obtained when the numerical data is taken into the hard latch random value register 559A that becomes the hard latch random value register RL0HV0. This shows the interrupt control setting for enabling or disabling the interrupts that occur. In the example shown in FIG. 22B, when the interrupt at the time of fetching into the hard latch random number value register RL0HV0 (559A) is prohibited (interrupt disabled), the bit values of the hard latch interrupt control data RL01IE and RL00IE are both set. On the other hand, when this interrupt is permitted (interrupt permitted), the bit value thereof is set to “1”.

  The soft latch random value register 559S is a register that stores numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 as a random value by a user program (software). The soft latch random value register 559S is a 16-bit (2-byte) register, and may store a 16-bit random value corresponding to the channel ch0, for example.

  The random number soft latch signal is input to the soft latch random value register 559S using the random number soft latch register RDSL (address FE74H) among the built-in registers included in the game control microcomputer 100 as shown in FIG. Is done. FIG. 23A shows a configuration example of the random number soft latch register RDSL corresponding to the channel ch0. FIG. 23B shows the setting contents of random number soft latch data stored in the random number soft latch register RDSL. The random number soft latch data RDSL0 stored in the bit number [0] of the random number soft latch register RDSL indicates the presence / absence of a random value latch request when the 16-bit random number of the channel ch0 is latched by software. In the example shown in FIG. 23B, when there is no random number latch request by software, the bit value of the random number soft latch data RDSL0 is “0”, while when there is a random number latch request by software, The bit value is “1”.

  The soft latch random value register 559S responds to the bit value of the random number soft latch data RDSL0 stored in the random number soft latch register RDSL being “1”, and the random number sequence RSN output from the maximum value comparison circuit 555. The numerical data at is taken in as a random value and stored. The soft latch random value register 559S uses the random number soft latch flag register RDSF (address FE75H) among the built-in registers of the game control microcomputer 100 as shown in FIG. Enable. The random number soft latch flag register RDSF is a register that stores a random number soft latch flag indicating whether or not numerical data serving as a random number value is latched in the soft latch random number value register 559S. FIG. 24A shows a configuration example of the random number soft latch flag register RDSF. FIG. 24B shows the setting contents of the soft latch flag data stored in the random number soft latch flag register RDSF. As for the soft latch flag data RDSF0 stored in the bit number [0] of the random number soft latch flag register RDSF, whether or not the 16-bit random number of the channel ch0 is taken into the soft latch random value register 559S that becomes the soft latch random value register RL0SV. It becomes a random number soft latch flag indicating.

  In the example shown in FIG. 24B, when the numerical data is not captured in the soft latch random value register RL0SV (no random number is captured), the bit value of the soft latch flag data RDSF0 becomes “0” and the random number is stored. On the other hand, when the soft latch flag is cleared to the off state, when numerical data is fetched (with random number fetching), the bit value becomes “1” and the random soft latch flag is set to the on state. When the random number soft latch flag is on, storage of new numerical data in the soft latch random number register RL0SV is restricted (prohibited). That is, when the bit value of the soft latch flag data RDSF0 indicating whether or not numerical data has been taken into the soft latch random value register RL0SV is “1” and the random soft latch flag is in the ON state, the soft latch random value register The numerical data stored in RL0SV cannot be changed, and storage (capture) of new numerical data is restricted (prohibited). On the other hand, when the random number soft latch flag is off, storage of new numerical data in the soft latch random number value register RL0SV is permitted. That is, when the bit value of the soft latch flag data RDSF0 is “0” and the random number soft latch flag is in the OFF state, the numerical data stored in the soft latch random number register RL0SV can be changed, and a new numerical value can be changed. Data storage (capture) is permitted.

  In the 16-bit random number circuit 509A, a channel for independently generating a 16-bit random number may be provided for the channels ch1 to ch3 as well as the channel ch0. Note that two 16-bit (2-byte) hard latch random value registers 559A, 559B are provided corresponding to the channel ch0, while a 16-bit (2-byte) hard latch random number corresponding to each of the channels ch1 to ch3. Only one numeric register may be provided.

  The 8-bit random number circuit 509B may be provided with a circuit for independently generating an 8-bit random number corresponding to each of the channels ch0 to ch3. For example, the circuit for generating the 8-bit random number corresponding to the channel ch0 may be any circuit as long as the circuit shown in FIG. 15 is configured so as to be compatible with the generation of the 8-bit random number. A random number generation circuit, a random number activation setting circuit, a random number sequence change circuit, a random number sequence change setting circuit, a maximum value comparison circuit, a hard latch selector, a hard latch random number value register, and a soft latch random number value register.

  In the configuration example shown in FIG. 5, random number circuits 509 </ b> A and 509 </ b> B are built in the game control microcomputer 100. On the other hand, the random number circuits 509A and 509B may be externally attached to the game control microcomputer 100 as random number circuit chips different from the game control microcomputer 100. In this case, the first start winning signal SS1 from the first start port switch 22A is branched inside the switch circuit 114, and one is input to the input port PI0 of the PIP 510 provided in the game control microcomputer 100, and the other May be input to the input terminal of the hard latch selector 558A included in the random number circuit 509A. Further, the second start winning signal SS2 from the second start port switch 22B is branched inside the switch circuit 114, and one is input to the input port PI1 of the PIP 510 provided in the game control microcomputer 100, and the other is input. What is necessary is just to input into the input terminal of the hard latch selector 558B with which random number circuit 509A is provided. For example, the random number update clock selection circuit provided in the random number circuit 509A includes the internal system clock SCLK output from the clock circuit 502 provided in the game control microcomputer 100 via the system clock output terminal CLKO. The hard latch random number value register RL0HV0 and the hardware are input via an address bus, a data bus, a control signal line, and the like connected to the external bus interface 501 provided in the game control microcomputer 100. It suffices to read out the numerical data stored in the latch random value register RL0HV1.

  Further, even when the random number circuits 509A and 509B are externally attached to the game control microcomputer 100, the hard latch random value register RL0HV0 and the hard latch random number value register RL0HV1 depending on the state (on / off) of each random number latch flag. It is only necessary to limit (prohibit) or permit storage of new numerical data in the. Among the built-in registers shown in FIG. 7B, for example, hard latch select register RLS, random number interrupt control register RIC, random number maximum value setting register RMX, random number sequence change register RDSC, random number soft latch register RDSL, random number soft latch flag register RDSF The various registers used by the random number circuits 509A and 509B, such as the soft latch random value register RSV, the random number hard latch flag register RHF, and the hard latch random value register RHV, are not built in the game control microcomputer 100, and are used for game control. The random number circuits 509A and 509B externally attached to the microcomputer 100 may be incorporated. In this case, the CPU 505 of the game control microcomputer 100 may write and read various registers incorporated in the random number circuits 509A and 509B via the external bus interface 501 and the like, for example.

  The PIP 510 provided in the game control microcomputer 100 shown in FIG. 5 is, for example, an input-only port having a width of 8 bits. PI7 is included. The input port PI5 is also used as an external maskable interrupt terminal XINT connected to the interrupt controller 504B. The input port PI6 is also used as an external non-maskable interrupt terminal XNMI connected to the interrupt controller 504B. The input port PI7 is also used as the reception terminal RX0 used by the serial communication circuit 511. Use settings of the input port PI5 to the input port PI7 are instructed by function settings stored in the program management area.

  The PIP 510 performs state management of the input ports PI0 to PI7 using an input port register among the built-in registers provided in the game control microcomputer 100. The input port register is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input port PI0 to the input port PI7.

  The serial communication circuit 511 provided in the game control microcomputer 100 is a circuit that handles communication data in, for example, full duplex, asynchronous, standard NRZ (Non Return to Zero) format. As an example, the serial communication circuit 511 can only transmit serial data in a single direction between the external communication circuit and the first channel transmission / reception circuit capable of transmitting and receiving serial data bidirectionally with the external circuit. And a second channel transmission circuit. The first channel transmission / reception circuit included in the serial communication circuit 511 may be used for bidirectional serial communication with the payout control microcomputer 150 mounted on the payout control board 15. The second channel transmission circuit included in the serial communication circuit 511 may be used for unidirectional (only transmission) serial communication with the effect control microcomputer 120 mounted on the effect control board 12. Thereby, the signal input with respect to the main board | substrate 11 from the production control board | substrate 12 side can be prohibited, and an improper act can be prevented.

  In the serial communication circuit 511, for example, four types of errors such as an overrun error, break code error, framing error, and parity error may occur when communication data is received. As long as it can be generated. The overrun error is an error that occurs when the next communication data is received before the received communication data is read by the user program. A break code error is an error that occurs when a predetermined break code is detected during reception of communication data. The framing error is an error that occurs when the stop bit in the received communication data is “0”. The parity error is an error that occurs when the parity of the received communication data does not match a predetermined parity when the parity function is set to be used.

  The serial communication circuit 511 may include a first interrupt control circuit and a second interrupt control circuit. The first interrupt control circuit is a circuit for managing an interrupt generation factor in the first channel transmission / reception circuit included in the serial communication circuit 511 and controlling a communication interrupt request. Interrupts controlled by the first interrupt control circuit include a first channel transmission interrupt and a first channel reception interrupt. The first channel transmission interrupt includes an interruption due to transmission completion and an interruption due to transmission data empty. The first channel reception interrupt includes an interruption due to reception data full and an interruption due to the occurrence of a reception error such as a break code error, an overrun error, a framing error, and a parity error. The second interrupt control circuit is a circuit for managing an interrupt generation factor in the second channel receiving circuit included in the serial communication circuit 511 and controlling a communication interrupt request. The interrupt controlled by the second interrupt control circuit is a second channel transmission interrupt. The second channel transmission interrupt includes an interruption due to transmission completion and an interruption due to transmission data empty.

  The address decoding circuit 512 provided in the game control microcomputer 100 is a circuit for decoding each functional block in the game control microcomputer 100 and decoding a chip select signal that is a decode signal for an external device. . By the chip select signal, an internal circuit of the game control microcomputer 100 or an external device as a peripheral device is selectively operated effectively and can be accessed from the CPU 505.

  In the ROM 506 provided in the game control microcomputer 100, in addition to the game control user program and the control code to be the security check program 506A, various selection data and table data used for controlling the progress of the game, etc. Is stored. For example, the ROM 506 stores data constituting a plurality of determination tables, determination tables, setting tables, and the like prepared for the CPU 505 to perform various determinations, determinations, and settings. The ROM 506 also has a variation pattern in which the CPU 505 stores a plurality of types of table data constituting a plurality of command tables used for transmitting control signals serving as various control commands from the main board 11 and a plurality of types of decorative pattern variation patterns. Table data constituting the table is stored.

  In the RAM 507 provided in the game control microcomputer 100, for example, a game control data holding area is provided as an area for holding various data used for controlling the progress of the game in the pachinko gaming machine 1 and the like. The game control data holding area includes a first special figure hold storage unit, a second special figure hold storage unit, a start data storage unit, a game control flag setting unit, a game control timer setting unit, and a game control counter setting. And a game control buffer setting unit.

  The first special figure holding storage unit has established the first start condition in response to the occurrence of the start winning in response to the game ball passing (entering) through the first start winning opening formed by the normal winning ball apparatus 6A. 1 The reserved data of the special figure game (the special figure game using the first special figure by the first special symbol display device 4A) in which the start condition is not satisfied is stored. As an example, the first special figure reservation storage unit associates with the reservation number in the order of winning in the first start winning opening, and determines the special figure display result obtained by the CPU 505 based on the establishment of the first start condition by the winning. The numerical data indicating the random value MR1 and the numerical data indicating the jackpot type determining random value MR2 are reserved data and stored until the number reaches a predetermined upper limit value (for example, “4”).

  The second special figure holding storage unit satisfies the second start condition in response to the occurrence of the start winning due to the game ball passing (entering) through the second start winning opening formed by the normally variable winning ball apparatus 6B. The hold data of the special figure game in which the second start condition is not satisfied (the special figure game using the second special figure by the second special symbol display device 4B) is stored. As an example, the second special figure holding storage unit determines the special figure display result determined by the CPU 505 based on the establishment of the second starting condition associated with the winning in association with the holding number in the order of winning in the second starting winning opening. The numerical data indicating the random value MR1 and the numerical data indicating the jackpot type determining random value MR2 are reserved data and stored until the number reaches a predetermined upper limit value (for example, “4”).

  The start data storage unit stores start data indicating which game ball has won in either the first start winning opening or the second starting winning opening, so that the order of winning of each game ball can be specified. As an example, an area corresponding to the upper limit value (for example, “8”) of the total reserved storage number is secured in the start data storage unit, and “first” start data corresponding to winning in the first start winning opening, Alternatively, “second” start data corresponding to winning in the second start winning opening is stored in association with the hold number according to the winning order of each game ball.

  The first special figure reservation storage unit, the second special figure reservation storage unit, and the start data storage unit may be provided separately, or a storage area that is a combination of these may be provided. As an example, a storage area including eight areas obtained by combining the start data storage area and the random value storage area may be provided. In such a configuration, continuous addresses in the RAM 507 may be assigned to the start data storage area and the random value storage area. In this case, for example, the start data is set in the start data storage area at the head of the empty area by updating the value of the pointer that specifies the address of the data storage destination based on the total number of reserved storage. At this time, in order to specify the head of the free space, for example, a value obtained by adding 1 to the value obtained by multiplying the total number of reserved memories by the number of data in one piece of reserved data (numerical data indicating start data and random number values) (start data storage) A value obtained by adding one area) is specified as an address offset value. The pointer value may be updated in accordance with the offset value thus specified. In this configuration, a total of two data storage areas, one start data storage area and one random value storage area, are provided corresponding to one hold data. Therefore, a value obtained by adding 1 to a value obtained by doubling the total number of reserved memories is specified as an address offset value. As an example, when the total number of reserved memories is “3”, “+7” (a value obtained by doubling the total number of reserved memories “3” and adding 1) is specified and corresponds to this offset value. The start data is set in the start data storage area. If a total of three data storage areas including one start-up data storage area and two random number value storage areas are provided corresponding to one reserved data, the total number of reserved memories is tripled. A value obtained by adding 1 (a value obtained by adding one start data storage area) may be specified as the offset value of the address.

  Further, when the initial position of the pointer for designating the data storage destination address is used as the start data storage area corresponding to the hold number “1”, a value obtained by multiplying the total hold storage number by the number of data in one hold data is The address offset value may be specified. For example, when two data storage areas, one start data storage area and one random value storage area, are provided corresponding to one hold data, the value obtained by doubling the total hold storage number is The address offset value may be specified. When a total of three data storage areas including one start-up data storage area and two random number value storage areas are provided corresponding to one hold data, a value obtained by multiplying the total hold storage number by three is obtained. The address offset value may be specified. After the start data is set in the start data storage area in this way, 1 is added to the value of the pointer specifying the address, and numerical data indicating the random number value is stored in the random value storage area of the address pointed to by the pointer after the addition. That's fine.

  The game control flag setting unit is provided with a plurality of types of flags that can be updated in accordance with the progress of the game in the pachinko gaming machine 1. For example, the game control flag setting unit stores data indicating a flag value and data indicating an on state or an off state for each of a plurality of types of flags. As an example, the game control flag setting unit may be provided with a special figure process flag, a common figure process flag, a big hit flag, a small hit flag, a probability change flag, a time reduction flag, and the like.

  The special figure process flag indicates the progress of the special figure game using the first special figure by the first special symbol display device 4A, the progress of the special figure game using the second special figure by the second special symbol display device 4B, and the like. In the step S95 of FIG. 30 executed for control and the special symbol process shown in FIG. 31, which process is to be selected and executed is instructed. The ordinary symbol process flag is selected and executed in the ordinary symbol process shown in step S96 of FIG. 30 executed to control the progress of the ordinary symbol game using the ordinary symbol by the ordinary symbol display 20. Tell what to do.

  The big hit flag is set to an on state corresponding to the determination result that the special figure display result is “big hit” when the special figure game is started. On the other hand, it is cleared and turned off in response to, for example, that the jackpot symbol is stopped and displayed as a confirmed special symbol in the special symbol game. The small hit flag is set to an on state corresponding to the determination result that the special figure display result is “small hit” when the special figure game is started. On the other hand, it is cleared and turned off in response to, for example, the small hit symbol being stopped and displayed as the confirmed special symbol in the special symbol game. The probability change flag is set to an on state in response to the gaming state in the pachinko gaming machine 1 being controlled to a probability change state, while being cleared to an off state in response to the end of the probability change state. . The time reduction flag is set to the on state in response to the gaming state in the pachinko gaming machine 1 being controlled to the time reduction state, and is cleared to the off state in response to the completion of the time reduction state. .

  The game control timer setting unit is provided with various timers used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control timer setting unit stores data indicating timer values in each of a plurality of types of timers. As an example, the game control timer setting unit may be provided with a game control process timer, a special figure variation timer, a common figure variation timer, a backup monitoring timer, and the like.

  The game control process timer is for measuring, for example, the time for controlling the progress of the big hit game state or the small hit game state on the main board 11 side. As a specific example, the game control process timer stores, as a game control process timer value, data indicating a timer value corresponding to the time measured to control the progress of the big hit game state or the small hit game state. It is used as a down counter that counts down automatically. Alternatively, the game control process timer is used as an up-counter that stores data indicating a timer value corresponding to an elapsed time from a predetermined time point, such as a big hit game state or a small hit game state start point, and periodically counts up. May be.

  The special figure variation timer is for measuring, on the main board 11 side, a time for controlling the progress of the special figure game such as a special figure variation time which is the execution time of the special figure game. As a specific example, the special figure variation timer stores data indicating a timer value corresponding to the time measured in order to control the progress of the special figure game as a special figure fluctuation timer value and periodically counts down. Used as a counter. Alternatively, the special figure variation timer may be used as an up counter that stores data indicating a timer value corresponding to the elapsed time from the start time of the special figure game and periodically counts up.

  The universal map change timer is for measuring, on the main board 11 side, a time for controlling the progress of the normal game, such as the normal map change time which is the execution time of the normal game. As a specific example, the normal fluctuation timer stores data indicating a timer value corresponding to the time measured to control the progress of the normal figure game as a normal fluctuation timer value, and periodically counts down. Used as a counter. Alternatively, the normal time variation timer may be used as an up counter that stores data indicating a timer value corresponding to the elapsed time from the start time of the normal time game and periodically counts up.

  The backup monitoring timer is for measuring an elapsed time after the power-off signal transmitted from the power monitoring circuit 303 mounted on the power board 10 is turned on. As an example, when the main board 11 detects a power-off signal output based on a decrease in the power supply voltage VSL supplied from the power supply monitoring circuit 303, measurement of the elapsed time by the backup monitoring timer is started. . The measurement by the backup monitoring timer is continued until the output of the power-off signal is stopped. When the elapsed time measured by the backup monitoring timer reaches a predetermined time, a predetermined preparation process corresponding to the stop of power supply, such as a process for protecting data in the backup area in the RAM 507, is executed.

  The game control counter setting unit is provided with a plurality of types of counters for counting a count value used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control counter setting unit stores data indicating the count value in each of a plurality of types of counters. As an example, the game control counter setting unit may be provided with a random counter, a first reserved memory counter, a second reserved memory counter, a round number counter, and the like.

  The random counter of the game control counter setting unit counts a part of numerical data indicating a random value used for controlling the progress of the game so that the CPU 505 can update it by software separately from the random number circuits 509A and 509B. Is for. For example, numerical data indicating the random number values MR1 to MR5 are stored as random count values in the random counter of the game control counter setting unit. As for the random number values MR2 to MR5, numerical data indicating each random number value is updated regularly or irregularly according to the execution of software by the CPU 505.

  The first reserved memory counter is for counting the first special figure reserved memory number that is the number of stored reserved data in the first special figure reserved memory unit. For example, in the first reserved memory counter, data indicating the count value corresponding to the first special figure reserved memory number is stored as the first reserved memory count value, and corresponding to the increase or decrease of the first special figure reserved memory number Updated (for example, 1 addition or 1 subtraction). The second reserved memory counter is for counting a second special figure reserved memory number that is the number of stored reserved data in the second special figure reserved memory unit. For example, in the second reserved memory counter, data indicating a count value corresponding to the second special figure reserved memory number is stored as a special figure reserved memory count value, and updated in accordance with an increase or decrease in the special figure reserved memory number ( For example, 1 addition or 1 subtraction). In addition, a total reserved memory counter for counting the total number of reserved memories may be provided separately from the first and second reserved memory counters. Alternatively, the total number of reserved memories may be specified by adding the first reserved memory count value and the second reserved memory count value.

  The round number counter is for counting the number of rounds executed in the big hit gaming state. For example, in the round number counter, data indicating a count initial value “1” at the start of the big hit gaming state is set as the round number count value. When one round is completed and the next round is started, the round count value is incremented by 1 and updated. The round number counter may also count the number of executions of the variable winning operation in the small hit gaming state.

  The game control buffer setting unit is provided with various buffers that temporarily store data used for controlling the progress of the game in the pachinko gaming machine 1. For example, the game control buffer setting unit stores data indicating buffer values in each of a plurality of types of buffers. As an example, the game control buffer setting unit may be provided with a transmission command buffer, a variation special figure designation buffer, a jackpot type buffer, a switch-on buffer, and the like.

  The transmission command buffer is used to temporarily store setting data for transmitting a control command from the main board 11 to the sub-side control board. For example, the transmission command buffer is configured to include a plurality of (for example, “12”) buffer areas, and setting data indicating storage addresses in the ROM 506 of the command table corresponding to the control command to be transmitted is stored in each buffer area. The In addition, a buffer area where setting data is written and read in the transmission command buffer may be specified by a transmission command pointer or the like, and a plurality of buffer areas may be used as a ring buffer.

  The variable special symbol designation buffer includes a special symbol game using the first special symbol by the first special symbol display device 4A and a special symbol game using the second special symbol by the second special symbol display device 4B. A buffer value indicating whether the special figure game is executed is stored. As an example, the value of the fluctuation special figure designation buffer (fluctuation special figure designation buffer value) is “1” in response to the execution of the special figure game using the first special figure by the first special symbol display device 4A. Set to Further, the variable special figure designation buffer value is set to “2” in response to the execution of the special figure game using the second special figure by the second special symbol display device 4B. Then, the variable special figure designation buffer value is set to “0” in response to the completion of the special figure game.

  In the big hit type buffer, the variable display form of the decorative pattern when the variable display result is “big hit” is set to one of a plurality of types of big hit types such as “non-probable change”, “probable change”, and “surprise change”. The corresponding value is stored as a jackpot type buffer value. As an example, when the jackpot type is “non-probable change”, the big hit type buffer value is set to “0”, and when the jackpot type is “probable change”, the big hit type buffer value is set to “1”. When “Random” is selected, the big hit type buffer value is set to “2”.

  The switch-on buffer stores a plurality of bit values corresponding to each switch such as the gate switch 21, the first and second start opening switches 22 </ b> A and 22 </ b> B, and the count switch 23, and the state of the detection signal transmitted from each switch (ON (Or “OFF”), each bit value (for example, “0” corresponding to OFF, “1” corresponding to ON, etc.) is set to be changeable. That is, each bit value of the switch-on buffer is set to “1” when the on-state of a switch associated with the switch is detected in advance, and is set to “0” when the off-state of the switch is detected.

  As shown in FIG. 2, an effect control microcomputer 120 is mounted on the effect control board 12. The effect control board 12 includes a VDP (Video Display Processor) 121 that generates image data in response to a drawing command from the effect control microcomputer 120, the image display device 5, speakers 8L and 8R, and a game effect lamp 9. An effect data memory 122 for storing various data used for controlling the effect operation by the effect device such as a light emitter is also mounted. The effect control microcomputer 120 is a one-chip microcomputer having the same configuration as the game control microcomputer 100, for example, and includes an external bus interface, a clock circuit, a unique information storage circuit, a reset controller, an interrupt controller, a CPU, a ROM, A RAM, a timer circuit, a random number circuit, a free-run counter, a PIP, a serial communication circuit, an address decoding circuit, and the like may be provided. Further, part or all of the configuration of the effect control microcomputer 120 may be different from the configuration of the game control microcomputer 100. As an example, in the case where all the numerical data serving as random number values used on the side of the effect control board 12 are updated by software, the effect control microcomputer 120 may not include the random number circuit. Further, the serial communication circuit only needs to be provided with a receiving circuit capable of receiving at least an effect control command transmitted from the main board 11, and data and commands for the image display device 5, the audio control board 13, and the lamp control board 14 are provided. Signal transmission may be performed using an external bus interface or an address decoding circuit.

  In the effect control microcomputer 120, the CPU executes the effect control program read from the ROM, thereby executing a process for controlling the effect operation by the effect electrical component (effect device). At this time, a fixed data reading operation in which the CPU reads fixed data from the ROM, a variable data writing operation in which the CPU writes various fluctuation data in the RAM and temporarily stores the data, and various fluctuation data in which the CPU is temporarily stored in the RAM. Fluctuating data reading operation for reading out, receiving operation for receiving various signals input from the outside of the production control microcomputer 120 via the external bus interface, PIP, serial communication circuit, etc., CPU for external bus interface, serial communication circuit, etc. A transmission operation for outputting various signals to the outside of the effect control microcomputer 120 is also performed. It should be noted that the one-chip microcomputer constituting the production control microcomputer 120 only needs to incorporate a RAM in addition to at least the CPU, and the ROM, random number circuit, PIP, and the like are incorporated even if they are externally attached. May be used. A control signal, which is an effect control command transmitted from the main board 11 via the relay board 18, is supplied to a predetermined serial reception terminal provided in the effect control microcomputer 120, and the serial signal built in the effect control microcomputer 120. What is necessary is just to receive in a communication circuit. Or the control signal used as an effect control command may be transmitted / received in parallel in a direction from the main board 11 to the effect control board 12 via a plurality of signal lines (for example, eight effect control signal lines). .

  The VDP 121 has an image data processing function such as a high-speed drawing function and a moving image decoding function for displaying various images in the display area of the image display device 5, and an image according to a display control command from the effect control microcomputer 120. An image processor that executes data processing. Note that the VDP 121 may be a graphics processing unit (GPU), a graphics controller LSI (GCL), or a microprocessor for image processing, more commonly referred to as a digital signal processor (DSP). The effect data memory 122 may be configured using a non-volatile recording medium such as a semiconductor memory such as a flash memory, a magnetic memory, or an optical memory.

  On the voice control board 13, for example, an input / output driver, a voice synthesis IC, a voice data ROM, an amplifier circuit, a volume, and the like are mounted. As an example, in the voice control board 13, the sound number data indicated in the sound effect signal transmitted from the effect control board 12 is input to the voice synthesis IC via the input / output driver. The voice synthesis IC generates voice and sound effects corresponding to the sound number data and outputs them to the amplifier circuit. The amplifier circuit outputs an audio signal obtained by amplifying the output level of the speech synthesis IC to a level corresponding to the volume set by the volume to the speakers 8L and 8R. The voice data ROM stores control data corresponding to the sound number data, and the voice synthesis IC reads out the control data corresponding to the sound number data to generate voice and sound effects. The data stored in the audio data ROM may be composed of data indicating the output mode of audio and sound effects in a predetermined period in time series.

  For example, an input / output driver and a lamp driver are mounted on the lamp control board 14. As an example, in the lamp control board 14, the electrical decoration signal transmitted from the effect control board 12 is input to the lamp driver via the input / output driver. The lamp driver amplifies the electric decoration signal and supplies it to the game effect lamp 9 and the like.

  On the payout control board 15, a payout control microcomputer 150, a switch circuit 151, and the like are mounted. The switch circuit 151 receives detection signals from various switches and sensors, such as the full tank switch 26, the ball-out switch 27, the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. The switch circuit 151 takes these detection signals and transmits them to the payout control microcomputer 150. The payout control microcomputer 150 is, for example, a one-chip microcomputer similar to the game control microcomputer 100, and includes an external bus interface, a clock circuit, a specific information storage circuit, a reset controller, an interrupt controller, a CPU, a ROM, a RAM, and a timer. A circuit, a random number circuit, a free-run counter, a PIP, a serial communication circuit, an address decoding circuit, and the like may be provided. Further, part or all of the configuration of the payout control microcomputer 150 may be different from the configuration of the game control microcomputer 100. As an example, when numerical data that is a random number value is not used on the payout control board 15 side, the payout control microcomputer 150 may not include a random number circuit. Further, in the serial communication circuit, it is only necessary to provide at least one transmission / reception circuit capable of bidirectional serial communication with the main board 11, and data for the payout motor 51, the error display LED 74, and the launch control board 17. The command signal may be transmitted using an external bus interface or an address decoding circuit.

  In the payout control microcomputer 150, the CPU executes a payout control program read from the ROM, thereby executing processing for controlling the payout operation by the payout device including the payout motor 51 and the like. At this time, a fixed data reading operation in which the CPU reads fixed data from the ROM, a variable data writing operation in which the CPU writes various fluctuation data in the RAM and temporarily stores the data, and various fluctuation data in which the CPU is temporarily stored in the RAM. Data reading operation for reading out, receiving operation for receiving various signals input from the outside of the payout control microcomputer 150 via the external bus interface, PIP, serial communication circuit, etc., CPU for external bus interface, serial communication circuit, etc. A transmission operation for outputting various signals to the outside of the payout control microcomputer 150 is also performed. It should be noted that the one-chip microcomputer constituting the payout control microcomputer 150 may include at least RAM in addition to the CPU, and ROM, PIP, and the like may be externally attached or incorporated. Good.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply from the power supply board 10 is started and the reset signal to the game control microcomputer 100 becomes high level (off state), the game control microcomputer 100 is activated, Based on the security check program 506A read from the ROM 506 by the CPU 505, a security check process as shown in the flowchart of FIG. At this time, the operation state of the game control microcomputer 100 is the security mode, and the game control user program stored in the ROM 506 is not yet executed.

  When the security check process shown in FIG. 25 is started, the CPU 505 first executes a process for determining a time (security time) when the game control microcomputer 100 is in the security mode by executing the security check process. . At this time, the CPU 505 reads the bit value in the bit number [5-0] of the security time setting KSES stored in the program management area of the ROM 506 (step S1). Then, a fixed extension time corresponding to the read value is set (step S2). In the process of step S2, for example, as shown in FIG. 10, a fixed security time that differs depending on the bit value in the bit number [5-0] of the security time setting KSES may be set as the fixed extension time.

  After executing the process of step S2, the bit value in the bit number [7-6] of the security time setting KSES is read (step S3). Then, it is determined whether or not the read value is “00” (step S4). At this time, when it is determined that the read value is other than “00” (step S4; No), a variable extension time determined corresponding to the read value is set (step S5). In the process of step S5, for example, as shown in FIG. 10, the variable security time in any of the short mode, the middle mode, and the long mode is set corresponding to the bit value in the bit number [7-6] of the security time setting KSES. What is necessary is just to set as variable extension extension time. The security time may be set by adding the fixed extension time set by the process of step S2 and the variable extension time set by the process of step S5. Here, the variable setting time is a time component that changes every time the security check process is executed in the security time, and the bit value in the bit number [7-6] of the security time setting KSES is “01” (short). Mode), “10” (middle mode), or “11” (long mode).

  For example, when the count value in the free-run counter 509C or the like is stored in the variable security time register built in the game control microcomputer 100 when the system reset occurs, in the process of step S5, the variable security time By using the stored value of the register as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable setting time is within a predetermined time range for each system reset. It may be determined so as to change randomly. Thus, when the bit value in the bit number [7-6] of the security time setting KSES is a value other than “00”, the security time as the execution time of the security check process is set as the security based on the occurrence of the system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  On the other hand, when it is determined in step S4 that the read value is “00” (step S4; Yes), the process of step S5 is not executed. In this case, the fixed extension time set by the process of step S2 may be set as the security time.

  Thereafter, the security code stored in the predetermined area of the ROM 506 is read (step S6). Here, in a predetermined area of the ROM 506, a security code of a calculation result obtained by calculating the data of the stored content by a predetermined calculation formula is stored in advance. As a security code generation method, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 506, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing in step S6, the encrypted arithmetic expression is decrypted and restored (step S7). Thereafter, the storage code in the predetermined area of the ROM 506 is calculated by the arithmetic expression decrypted in step S7 to specify the security code (step S8). At this time, the storage data used for the calculation for specifying the security code is, for example, program data corresponding to a part or all of the user program different from the security check program 506A in the storage data of the ROM 506, or predetermined table data It is sufficient if it is a part or all of the fixed data that constitutes. Then, the security code read in step S6 is compared with the security code specified in step S8 (step S9). At this time, it is determined whether or not the security codes match in the comparison result (step S10).

  If the security codes do not match in step S10 (step S10; No), it is determined that an unauthorized change has been made to the ROM 506, and the operation of the CPU 505 is shifted to a halt state (HALT). On the other hand, if the security codes match in step S10 (step S10; Yes), it is determined whether the security time set based on the processing in step S2 or step S5 has elapsed (step S10). S11). If the security time has not elapsed (step S11; No), the process of step S11 is repeatedly executed and waits until the security time elapses. On the other hand, if it is determined in step S11 that the security time has elapsed (step S11; Yes), for example, the value of the program counter built in the CPU 505 is set to the start address (address 0000H) of the user program in the ROM 506. The execution of the game control main process is started by setting or the like. At this time, the execution of the game control is started from the beginning of the control code constituting the user program stored in the ROM 506, so that the operation state of the game control microcomputer 100 shifts from the security mode to the user mode, and the game Execution of the control main process is started.

  26 and 27 are flowcharts showing an example of a game control main process executed by the CPU 505 of the game control microcomputer 100. FIG. Each process described below is executed by the CPU 505 provided in the game control microcomputer 100. Further, an interrupt request based on various interrupt factors generated by the timer circuit 508, random number circuit 509, serial communication circuit 511, etc. included in the game control microcomputer 100 causes the CPU 505 to execute predetermined interrupt processing by the interrupt controller 504B. belongs to. The concept including the CPU 505 and various circuits other than the CPU 505 is sometimes referred to as a game control microcomputer 100. When the game control main process is started, the CPU 505 executes a predetermined initial setting process, sets the interrupt prohibition (step S21 in FIG. 26), and sets the interrupt mode (step S22). For example, in step S22, the value (1 byte) of the specific register (I register) of the game control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output from the built-in device are synthesized. As a result, the interrupt mode [2] of the maskable interrupt in which the interrupt address is generated is set. When an interrupt that can be masked occurs, the CPU 505 performs a setting for automatically disabling the interrupt, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S23). Further, the internal register is set (initialized) as shown in FIG. 7B (step S24). As an example, in the process of step S24, operation settings in the serial communication circuit 511 may be performed by initializing settings in a predetermined communication setting register. Subsequent to the processing in step S24, the timer circuit 508 and the PIP 510 may be set. Thereafter, for example, by checking the terminal state at a predetermined input port included in the PIP 510, it is determined whether or not the power-off signal is in an off state (step S25). In the pachinko gaming machine 1, when power supply is started, output voltages of various power sources such as a VSL (+30 V) power source gradually reach a specified value. At this time, the CPU 505 can confirm the stability of the power supply voltage by confirming the OFF state (high level) of the power-off signal by the process of step S25. In order to prevent erroneous detection due to the influence of noise or the like, the confirmation of the power-off signal may be continuously executed a predetermined number of times (for example, 5 times).

  If the power-off signal is in the on state (low level) in step S25 (step S25; Yes), settings for starting the watch dog timer 520 provided in the reset controller 504A are performed (step S26). In this embodiment, the bit value in the bit number [6] of the reset setting KRES shown in FIG. 8B is set in advance to be “0”. Thus, the user program determines whether to activate the watchdog timer 520 and enable the reset operation according to the occurrence of timeout, or stop the watchdog timer 520 and invalidate the reset operation according to the occurrence of timeout. Set to switchable by (software). In addition, the bit value in the bit number [5-4] of the reset setting KRES is set to “11” in advance, and the bit value in the bit number [3-0] of the reset setting KRES is set to “1111” in advance. Set as follows. Thereby, the timeout time that is the monitoring time measured by the watchdog timer 520 is the longest time among a plurality of types that can be set as the monitoring time.

  Based on such settings, in the process of step S26, the CPU 505 writes “CCH” as WDT start data in the WDT start register WST shown in FIG. Thus, when it is determined by the process of step S25 that the power-off signal is on, measurement of the monitoring time by the watchdog timer 520 is started, and the reset operation due to occurrence of timeout is validated.

  After starting the watchdog timer 520 by the process in step S26, the CPU 505 repeatedly executes the infinite loop process to shift the control state to the standby state. Since the watchdog timer 520 is not cleared and restarted after shifting to the standby state in this way, a reset operation due to the occurrence of a timeout is performed when the elapsed monitoring time is measured. Therefore, if the power supply voltage cannot be stabilized even after a predetermined time has elapsed since the start of power supply to the pachinko gaming machine 1 and the power-off signal remains on, a time-out in the watchdog timer 520 occurs. The game control microcomputer 100 can be restarted by performing a reset operation due to the occurrence of the above.

Here, the period of the watchdog the monitoring time measured by the timer 520 timeout period, maximum time ^{_{2 25 × T SCLK × 15 (}} T SCLK among a plurality of types that can be set as a monitoring time the internal system clock SCLK ). Therefore, for example, when the power supply is completely stopped for a predetermined period due to, for example, the power switch of the pachinko gaming machine 1 being cut off, the power is supplied to the CPU 505 of the game control microcomputer 100 before the time-out occurs due to the elapse of the monitoring time. Can be stopped so that the reset operation due to the occurrence of a timeout is not performed. In this way, it can be prevented that the power switch is erroneously reset when the power switch is turned off.

  When the power-off signal is in the off state (high level) in step S25 (step S25; No), the signal state of the switch signal (clear signal) transmitted from the clear switch 304 installed on the power supply board 10 or the like Based on the above, it is determined whether or not the clear switch 304 is turned on (step S27). In the process of step S27, the clear signal transmitted from the clear switch 304 may be checked a plurality of times, and it may be determined that the clear switch 304 has been turned on when the clear signal is continuously turned on. For example, once it is confirmed that the state of the clear signal is off, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or may be a plurality of times. In addition, it is possible to check twice and check again when the check results do not match.

  If the clear signal is on in step S27 (step S27; Yes), for example, the clear flag received also in a predetermined area (such as a game control flag setting unit) of the RAM 507 is set to the on state (step S28). On the other hand, when the clear signal is in the off state (step S27; No), the process of step S28 is skipped and the clear flag remains in the off state.

  Thereafter, a delay process for delaying the start timing of the game control process for controlling the progress of the game by executing the software is set (step S29). As a specific example, an initialization weight count designation value is set in a wait counter provided in a predetermined area (such as a game control counter setting unit) of the RAM 507. Subsequently, the delay process based on the setting in step S29 is started, and the setting relating to the execution of the delay process is updated (step S30), for example, the count value in the wait counter is decremented by one. Then, for example, it is determined whether or not a predetermined delay time has elapsed by determining whether or not the count value in the wait counter has reached a predetermined delay end determination value (step S31). Here, the data indicating the delay end determination value may be stored in advance in the ROM 506 or the like. For example, the delay end determination value is from when the game control process becomes executable until at least execution of various processes for payout control by the payout control microcomputer 150 mounted on the payout control board 15 is started. A predetermined reference value may be used so that the delay time becomes longer than the time.

  If the delay time has not elapsed in step S31 (step S31; No), the process returns to step S30. If the delay time has elapsed (step S31; Yes), access to the RAM 507 is permitted (step S31). S32). Subsequently, the game control microcomputer 100 determines whether or not the clear flag is on (step S33). When the clear flag is off (step S33; No), data check of the RAM 507 is performed to determine whether or not the check result is normal (step S34). In the process of step S34, for example, a checksum is calculated using data stored in a specific area of the RAM 507, and the calculated checksum is compared with the checksum stored in the main checksum buffer. Here, the main checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 507 is different from the data when the power supply is stopped, so that the check result is determined to be not normal.

  When the check result in step S34 is normal (step S34; Yes), for example, it is determined whether or not a main backup flag provided in a predetermined area (such as a game control flag setting unit) of the RAM 507 is turned on (step S34). S35). The state of the main backup flag is set in the game control flag setting unit or the like when the power supply is stopped. The main backup flag setting location is backed up by the backup power source, so that the state of the main backup flag is saved even when the power supply is stopped. In step S35, for example, if “55H” is set in the game control flag setting section as the value of the main backup flag, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state). Note that the determination as to whether or not the main backup flag is turned on as in step S35 is performed prior to the determination of the check result as in step S34, and the data check of the RAM 507 is performed when the main backup flag is turned on. You may make it determine whether a result is normal.

  When the main backup flag is on in step S35 (step S35; Yes), after the main backup flag is cleared and turned off (step S36), the internal state of the game control microcomputer 100 is supplied with power. The setting at the time of recovery for returning to the state when stopped is performed (step S37). As a specific example, in the process of step S37, the start address of the backup setting table stored in the ROM 506 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 507. Here, the work area of the RAM 507 is backed up by a backup power source, and initialization data for an area that may be initialized among the work areas may be set in the backup time setting table. When the process of step S37 is executed, a setting for transmitting a recovery notification command to the effect control board 12 is performed (step S38). As a specific example, in the process of step S38, the start address of the backup command transmission table stored in the ROM 506 is set as a pointer, and control data for command transmission is played based on the contents of the backup command transmission table. The restoration notification command is transmitted from the main board 11 to the effect control board 12 by setting it in the effect transmission command buffer included in the transmission command buffer of the control buffer setting unit.

  In this way, it is determined whether or not a predetermined recovery condition is satisfied that the clear flag is OFF, the data check result of the RAM 507 is normal, and the main backup flag is ON. When the recovery condition is satisfied, the recovery setting for returning to the internal state when the previous power supply is stopped can be performed.

  On the other hand, when the clear flag is on in step S33 (step S33; Yes), when the check result is not normal in step S34 (step S34; No), or when the main backup flag is off in step S35. If there is (step S35; No), the RAM 507 is initialized (step S39). Subsequent to the processing in step S39, settings at the time of initialization for setting the internal state of the game control microcomputer 100 to an initial state are performed (step S40). As a specific example, in the process of step S40, the start address of the initialization setting table stored in the ROM 506 is set as a pointer, and the contents of the initialization setting table are sequentially set in the work area in the RAM 507. . In the process of step S40, a predetermined initial count value (eg, “200”) is set in a command transmission number counter provided in the game control counter setting unit. When the processes of steps S39 and S40 are executed, settings for transmitting an initialization notification command to the effect control board 12 (step S41), and a payout initialization command to the payout control board 15 are sent. Are set (step S42). As a specific example, in the process of step S41, the start address of the initialization effect presentation command transmission table stored in the ROM 506 is set as a pointer, and the command transmission is performed based on the contents of the initialization presentation effect command transmission table. An initialization notification command is transmitted from the main board 11 to the effect control board 12 by setting the control data in the effect transmission command buffer included in the transmission command buffer of the game control buffer setting unit. In the process of step S42, the start address of the payout command transmission table at initialization stored in the ROM 506 is set as a pointer, and control data for command transmission is played based on the contents of the payout command transmission table at initialization. The payout initialization command is transmitted from the main board 11 to the payout control board 15 by setting it in the payout transmission command buffer included in the transmission command buffer of the control buffer setting unit.

  After executing the process of step S38 or step S42, a timer interrupt is generated every predetermined time (for example, 2 milliseconds) by setting a register of the timer circuit 508 provided in the game control microcomputer 100, for example. The internal setting of the game control microcomputer 100 is performed (step S43). Thereafter, for example, the CPU 505 reads the bit value in the bit number [7], bit number [3], etc. of the 16-bit random number initial setting first KRL1 stored in the program management area of the ROM 506 (step S44 in FIG. 27). At this time, it is determined whether or not the read value is “0” for each bit value (step S45).

  If there is a bit value whose read value is “0” in step S45 (step S45; Yes), the setting is made to activate the random number circuits 509A and 509B by setting the maximum value in the numerical data that becomes the random value. (Step S46). For example, the bit value in the bit number [3] of the 16-bit random number initial setting first KRL1 shown in FIG. 9B is set to be “0” in advance. In this case, a circuit that generates a 16-bit random number of channel ch0 in the 16-bit random number circuit 509A can be activated by setting a random number maximum value in a user program (software). Based on such setting, in the process of step S46, the CPU 505 stores predetermined numerical data in the random number maximum value setting register RL0MX corresponding to the 16-bit random number of the channel ch0 shown in FIGS. 19A and 19B. Write as a value. Thus, generation of a 16-bit random number corresponding to channel ch0 is started by setting the maximum random number in the user program (software).

  When the read value is “1” instead of “0” in step S45 (step S45; No), the serial communication circuit is initialized (step S47) after executing the process of step S46. Thereafter, initial setting relating to interrupt processing executed based on the interrupt request is performed (step S48). Then, the game control microcomputer 100 sets the interrupt permitted state (step S49), and waits for the occurrence of various interrupts. At this time, a game random number update process for updating the game random number is executed (step S50), and whether or not the power-off signal is turned on (low level) is determined (whether or not it is output). This is performed (step S51).

  If the power-off signal is off (high level) in step S51 (step S51; No), the process returns to step S50 and waits for the occurrence of various interrupts. On the other hand, when the power-off signal is turned on (low level) in step S51 (step S51; Yes), main-side power-off processing is executed (step S52). Thereafter, as in the process of step S26 shown in FIG. 26, after setting for starting the watchdog timer 520 (step S53), the control state is shifted to the standby state by repeatedly executing the infinite loop process. Let Since the watchdog timer 520 is not cleared and restarted after shifting to the standby state in this way, a reset operation due to the occurrence of a timeout is performed when the elapsed monitoring time is measured. Therefore, for example, after the game control process for controlling the progress of the game in the pachinko gaming machine 1, such as a game control timer interruption process (FIG. 30), becomes a control state that can be executed, the power supply voltage in the pachinko gaming machine 1 decreases. When the power-off signal is turned on due to (instantaneous power interruption), the game control microcomputer 100 can be restarted by performing a reset operation due to occurrence of a timeout in the watchdog timer 520.

Here, watchdog time measured by the timer 520 to become time-out period is set to be the maximum time 2 ²⁵ × T _SCLK × 15 among the plurality of types that can be set as the monitoring time. Therefore, for example, when the power supply is completely stopped for a predetermined period due to, for example, the power switch of the pachinko gaming machine 1 being cut off, the CPU 505 and the reset controller of the game control microcomputer 100 before the time-out occurs due to the elapse of the monitoring time. Since the power supply to 504A is stopped, it is possible to limit the reset operation due to the occurrence of timeout. In this way, it can be prevented that the power switch is erroneously reset when the power switch is turned off.

  In the game control main process shown in FIG. 26 and FIG. 27, after setting to activate the watchdog timer 520 by the process of step S26 or step S53, the control state is shifted to the standby state by repeatedly executing the infinite loop process. Let After shifting to the standby state, even if the power-off signal is turned off, the game control microcomputer 100 is restarted by performing a reset operation due to occurrence of a timeout. On the other hand, even after the transition to the standby state, when the power-off signal is turned off, the standby state may be terminated and the game control process may be executed.

As an example, after the process of step S24 shown in FIG. 26 is executed, the process shown in FIG. 28A may be executed. In this case, after setting the CPU 505 to activate the watchdog timer 520 by the process of step S25A, the CPU 505 determines whether or not the power-off signal is in an on state by the process of step S25. At this time, if the power-off signal is in the on state, the process waits until a predetermined time elapses by the process of step S25B, and then returns to the process of step S25. Therefore, the processing of step S25 and step S25B is repeatedly executed until the power- off signal is turned off . When the watchdog timer 520 measures that the time-out time that is the monitoring time has elapsed without the power- off signal being turned off, a reset operation due to the occurrence of time-out is performed.

  On the other hand, when it is determined in step S25 shown in FIG. 28A that the power-off signal is in the OFF state, the setting for stopping the watchdog timer 520 is performed in step S25C. The process may proceed to step S27 shown in FIG. In the process of step S25C, the CPU 505 writes “33H” as WDT stop data in the WDT start register WST shown in FIG. Thus, when it is determined in step S25 that the power-off signal is off prior to the occurrence of the timeout, the monitoring time measurement by the watchdog timer 520 is stopped and the reset operation due to the occurrence of the timeout is invalidated. May be used.

  Even when it is determined in step S51 shown in FIG. 27 that the power-off signal is in the on state, after waiting for a predetermined time to elapse, it is again determined whether the power-off signal is in the on state. You may check. In this case, when it is first determined that the power-off signal is in the on state, the main-side power-off processing in step S52 is executed, while the power-off signal is determined to be in the on state even after waiting for a predetermined time. When this is done, the watchdog timer 520 may be activated to enable the reset operation due to the occurrence of a timeout. If it is determined that the power-off signal is in the OFF state after waiting for a predetermined time, an interrupt may be permitted after setting for stopping the watchdog timer 520 as in the process of step S25C.

  Also, in the process of step S26 shown in FIG. 26, the process of step S53 shown in FIG. 27, or the process of step S25A shown in FIG. It is not limited to what activates. For example, it is determined whether or not a predetermined WDT activation condition is satisfied. If the WDT activation condition is satisfied, the reset operation due to the occurrence of a timeout is validated. The reset operation due to the occurrence may be invalidated.

  In this case, for example, a process as shown in FIG. 28B may be executed as the process of steps S26, S53, and S25A. In the process shown in FIG. 28B, the CPU 505 reads the bit value (stored value) in the bit number [1] of the internal information register CIF shown in FIG. 11A (step S71). Then, it is determined whether or not the read value is “1” (step S72). As shown in FIG. 11B, in the internal information data CIF1 stored in the bit number [1] of the internal information register CIF, whether or not the reset factor generated immediately before is due to the timeout of the watchdog timer 520. Is shown. Therefore, if the value of the internal information data CIF1 read in step S71 is “1”, it can be determined that the reset operation due to the occurrence of timeout has been performed.

  When it is determined in step S72 that the read value is not “1” but “0” (step S72; No), “CCH” is written as WDT start data in the WDT start register WST (step S73). The watchdog timer 520 is activated to enable the reset operation due to the occurrence of timeout. On the other hand, when it is determined in step S72 that the read value is “1” (step S72; Yes), the watchdog timer 520 is stopped by writing “33H” as WDT stop data in the WDT start register WST. Then, the reset operation due to the occurrence of timeout is invalidated (step S74).

  In this way, when the reset factor generated immediately before is due to the timeout of the watchdog timer 520, the reset operation due to the occurrence of the timeout is invalidated by executing the process of step S74. As a result, it is possible to prevent an inadvertent reset operation from being repeatedly performed because the stability of the power supply voltage cannot be confirmed. When it is determined in step S72 that the read value is “1”, the processing shown in FIG. 28B may be terminated without executing the processing in steps S73 and S74.

  In the game control main process shown in FIG. 26 and FIG. 27, the process of steps S44 to S46 is performed by determining the power-off signal by the process of step S26, permitting access to the RAM 507 by the process of step S32, and further by steps S33 to S35. By setting the random number maximum value in the random number circuits 509A and 509B at the timing after performing the restoration determination by the processing of step S48 and before timing of the interrupt initial setting by the processing of step S48, the user program ( Software) to start random number generation. Here, the timing for starting the generation of random numbers by the user program (software) may be arbitrarily set based on the specifications of the pachinko gaming machine 1 and the like. For example, the random number circuits 509A and 509B may be activated to start generation of random numbers at the timing prior to the determination of the power-off signal by the process of step S26, by executing the processes of steps S44 to S46. Alternatively, the processes of steps S44 to S46 are executed at a timing after the determination of the power-off signal by the process of step S26 and before the access permission to the RAM 507 is performed by the process of step S32. The random number circuits 509A and 509B may be activated to start generation of random numbers. Alternatively, the process of steps S44 to S46 is executed at a timing after the access permission to the RAM 507 by the process of step S32 and before the recovery determination by the process of steps S33 to S35, and the random number circuit 509A is executed. 509B may be activated to start random number generation. Alternatively, the random number circuits 509A and 509B may be activated to start generation of random numbers by executing the processes of steps S44 to S46 at a timing after the interrupt initial setting by the process of step S48.

  FIG. 29 is a flowchart showing an example of the main-side power-off process executed in step S52 of FIG. In the main-side power-off process shown in FIG. 29, in the game control microcomputer 100, first, the CPU 505 sets the interrupt prohibition (step S151). Subsequently, for example, the CPU 505 initializes the settings related to the drive control of the solenoids 81 and 82 by setting clear data to a predetermined bit of an output port provided in the game control microcomputer 100 (step S152). At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. After executing the process of step S152, for example, check data is generated by calculating the checksum using the data stored in the specific area of the RAM 507 (step S153) and provided in the game control flag setting unit. The main backup flag is set to the on state (step S154).

  As an example, in the process of step S153, the start address of the predetermined area in the RAM 507 is set as the checksum calculation start address, and the checksum calculation count is set corresponding to the final address of the predetermined area. The predetermined area of the RAM 507 specified by the checksum calculation start address and the address used for setting the checksum calculation count may be a content storage area that is predetermined as a storage area in which the content should be stored even when power supply is stopped. That's fine. Then, the stored data in this content storage area is sequentially read and exclusive OR is calculated. For example, after setting the checksum calculation start address to the pointer, the storage data of the address pointed to by the pointer is read in the RAM 507, and the exclusive OR with the checksum data whose initial value is “00” is calculated. The calculation result is stored as new checksum data. At this time, the pointer value is incremented by 1 and the checksum calculation count is decremented by 1. Subsequently, if the checksum calculation count is a value other than “0”, the stored data at the address pointed to by the pointer is read, and an exclusive OR operation with the checksum data is performed, or the pointer value is set to 1. The process of adding and subtracting 1 from the number of checksum calculations may be repeated until the number of checksum calculations reaches “0”. When the checksum calculation count reaches “0”, each bit value of the checksum data is inverted, and the obtained value is stored in the main checksum buffer and stored. The data stored in the main checksum buffer in this way is used as parity data to be checked when the power is turned on.

  Thereafter, in the game control microcomputer 100, for example, the CPU 505 sets an access prohibition value in a predetermined RAM access register, and thereafter prohibits access to the RAM 507 (step S155). Exit. When the power supply voltage decreases, the stored contents of the RAM 507 may be erroneously changed due to a runaway operation of the CPU 505 or the like, or signal levels (voltage levels) on various signal lines becoming unstable. There is sex. Therefore, by setting the state in which access to the RAM 507 is prohibited by the processing of step S155, it is possible to prevent erroneous change (damage) of the storage contents in the backup storage area provided in the RAM 507.

  When such a main-side power-off process is executed, or after the process of step S53 shown in FIG. 27 is executed, a process for clearing the random number latch flag may be executed. For example, it is determined whether any one of the bit values of the hard latch flag data RL00HF to RL03HF stored in the random number hard latch flag register RHF shown in FIG. If there is a bit that is “1”, the hard latch random number registers 559A and 559B corresponding to the random number latch flag are read to set the bit values of the hard latch flag data RL00HF to RL03HF to “0”. Clear the random number latch flag to turn it off. As a result, the bit value in the bit number [3] of the hard latch selection register RL0LS shown in FIGS. 20A and 20B is “0”, and reading of the stored value is a condition for taking in the hard latch random number value. Even in this case, the hard latch random number value registers 559A and 559B can be set in a state in which storage of new numerical data is permitted. Note that the hard latch random number value registers 559A and 559B may be read regardless of the bit values in the hard latch flag data RL00HF to RL03HF.

  Such processing for clearing the random number latch flag is not limited to that executed when the power supply voltage is lowered due to the power-off signal being turned on. For example, in the game control main process shown in FIG. 26 and FIG. 27 executed in response to the start of power supply, determination of a power-off signal by the process of step S26 and access to the RAM 507 by the process of step S32 Predetermined by the user program (software), such as permission, recovery determination by the processing of steps S33 to S35, random number generation start setting by the processing of steps S44 to S46, and timing associated with the interrupt initial setting by the processing of step S48 It may be executed at an arbitrary timing.

  In the game control main process shown in FIGS. 26 and 27, the signal state of the switch signal transmitted from the game start switch 31 installed on the main board 11 is set before the interrupt-permitted state is set by the process of step S49. Based on the above, it may be determined whether or not the game start switch 31 has been turned on. In this case, the switch signal transmitted from the game start switch 35 may be checked a plurality of times, and it may be determined that the game start switch 31 has been turned on when the switch signal is continuously turned on. In addition, the process of checking the on operation of the game start switch 31 is executed only when starting from an initial state without recovery (cold start), for example, when the processes of steps S39 to S42 are executed, For example, when the processing of steps S36 to S38 is executed, at the time of starting to restore the gaming state before power interruption (at the time of hot start), for example, a game control timer interrupt regardless of the operation of the game start switch 31 You may make it progress to the process which controls progress of a game like a process. Here, if a random counter provided in a predetermined area (game control counter setting unit or the like) is backed up by a backup power source in the RAM 507 provided in the game control microcomputer 100, the power is cut off at the time of hot start. Since updating of numerical data to be a random number value is started using the stored data in the previous random counter, it is difficult to specify the random value stored in the random counter from the operation start timing of the pachinko gaming machine 1. On the other hand, at the time of cold start, for example, the random counter is cleared (initialized) in the process of step S39, so that updating of the random number value is started from a certain initial value (for example, “0” or the like) There is a possibility that the random value stored in the random counter is specified from the operation start timing of the pachinko gaming machine 1.

  Therefore, at a cold start, the game start switch 31 is kept waiting until it is turned on, so that it is difficult to specify the random value stored in the random counter from the operation start timing of the pachinko gaming machine 1. Thereby, especially when a random number value for jackpot determination (for example, random number value MR1 for special figure display result determination) is updated by software, a so-called “hanging board” is connected to start operation timing of the pachinko gaming machine 1 Even if a fraudulent signal is input at the timing when a predetermined time has elapsed since then, it is possible to prevent the occurrence of a fraudulent big hit gaming state. Further, when it is determined that the game start switch 31 is not turned on, a game random number update process may be executed to update the random number value stored in the random counter by software. Accordingly, in addition to the elapsed time from the timing when the game start switch 31 is turned on, the elapsed time from the operation start timing of the pachinko gaming machine 1 to when the game start switch 31 is turned on cannot be specified. Even at cold start, it becomes difficult to specify the random value stored in the random counter, and it is possible to reliably prevent actions such as illegally generating a big hit gaming state by aiming or inputting illegal signals it can.

  After the processing in step S49 is executed and the interrupt is permitted, for example, a plurality of maskable interrupt factors are simultaneously generated in the timer circuit 508, the random number circuits 509A and 509B, or a part or all of the serial communication circuit 511, for example. When interrupted, the interrupt controller 504B accepts an interrupt factor with a high priority based on the designation by the bit value [2-0] of the interrupt initial setting KIIS. When the interrupt controller 504B receives an interrupt factor, an interrupt request signal in an on state is output to, for example, an I class interrupt (IRQ) terminal provided in the CPU 505. When an on-state interrupt request signal is input to the IRQ terminal by the CPU 505, the generated interrupt factor is identified based on, for example, the result of checking the data stored in the internal register, and the vector address corresponding to the identified interrupt factor By executing the program having the first address as the interrupt address, interrupt processing based on each interrupt factor can be started.

  If any of the four types of errors such as an overrun error, break code error, framing error, and parity error occurs during reception of communication data by the first channel transmission / reception circuit included in the serial communication circuit 511, the first A channel receive interrupt occurs. At this time, the CPU 505 may execute a predetermined serial communication error interrupt process. In this serial communication error interrupt processing, for example, the bit values corresponding to the predetermined bit number in the predetermined first channel communication setting register and the predetermined bit number in the second channel communication setting register are both set to “0”. For example, the transmission function and the reception function in the serial communication circuit 511 may be set not to be used. Here, the first channel communication setting register and the second channel communication setting register may be included in the built-in registers of the game control microcomputer 100. Further, when an error occurs during reception of communication data by the first channel transmission / reception circuit, control may be performed to prohibit the payout of game balls by the payout device including the payout motor 51. Thereby, when an abnormality such as a reception error of communication data occurs, it is possible to prevent an excessive payout of game balls that are prize balls.

  In the game control microcomputer 100, for example, based on the interrupt controller 504B receiving an interrupt request from the timer circuit 508, the CPU 505 executes the game control timer interrupt process shown in the flowchart of FIG. In the game control timer interrupt process shown in FIG. 30, the CPU 505 first sets the interrupt disabled state, and then executes a predetermined switch process, whereby each game ball detection switch 21, 22A, The state of the detection signal (winning detection signal) input from 22B, 23, etc. is determined (step S91). As an example, in the switch processing, it is determined whether or not the ON state has continued for a predetermined time (for example, 4 milliseconds) in the detection signals from the respective switches 21, 22A, 22B, 23, and the like. In a switch-on buffer provided in a predetermined area of the RAM 507 (such as a game control buffer setting unit), the bit value associated with the switch that has detected the ON state may be set to “1”.

  Subsequent to the switch process in step S91, a predetermined main-side error process is executed to perform abnormality diagnosis of the pachinko gaming machine 1, and a warning can be generated if necessary according to the diagnosis result (step S92). . For example, in the main-side error processing, settings for notifying the occurrence of an abnormal operation may be performed in response to excessive prize balls, insufficient prize balls, or other operation errors. After that, by executing a predetermined information output process, for example, data such as jackpot information, starting information, probability variation information supplied to a hall management computer installed outside the pachinko gaming machine 1 is output (step) S93).

  Subsequent to the information output process, a game random number update process is executed (step S94). Thereafter, the CPU 505 executes special symbol process processing (step S95). In the special symbol process, the value of the special symbol process flag provided in a predetermined area (such as a game control flag setting unit) of the RAM 507 is updated according to the progress of the game in the pachinko gaming machine 1, and the first special symbol display device Various processes are selected and executed in order to perform control of display operation in 4A and the second special symbol display device 4B and setting of opening / closing operation of the big prize opening in the special variable winning ball device 7 in a predetermined procedure.

  Following the special symbol process, the normal symbol process is executed (step S96). The CPU 505 controls the display operation (for example, turning on / off the segment LED) on the normal symbol display 20 by executing the normal symbol process, thereby allowing the normal symbol variable display and the normal variable winning ball apparatus 6B to move. Enables setting of the tilting movement of the blade. After executing the normal symbol process, the CPU 505 executes a prize ball process for setting the number of prize balls according to the input of the winning detection signal based on the execution result of the switch process in step S91, for example (step S97). ). Subsequent to the prize ball process, the main side communication control process is executed, so that a control command is transmitted from the main board 11 to a sub-side control board such as the effect control board 12 or the payout control board 15 or the payout control is performed. Communication control for receiving a control command transmitted from the board 15 is performed (step S98).

  As an example, in the main side communication control process, the serial communication circuit corresponds to the setting in the command transmission table specified by the storage data of the payout transmission command buffer included in the transmission command buffer provided in the game control buffer setting unit. The payout control command can be transmitted, for example, by sending a transmission operation instruction to the first channel transmission / reception circuit included in 511. Further, the stored contents of the payout reception command buffer provided in the game control buffer setting unit or the like are checked to determine whether or not the reception command is stored. When the reception command is stored, the reception command is read out. The reception command is stored in the payout reception command buffer based on the first channel reception interrupt generated in response to reception of communication data as a payout notification command by the first channel transmission / reception circuit in the serial communication circuit 511. What is necessary is just to be performed by the interrupt process performed. As another example, in the main-side communication control process, the second channel transmission included in the serial communication circuit 511 corresponding to the setting in the command transmission table specified by the storage data of the effect transmission command buffer included in the transmission command buffer. The production control command can be transmitted, for example, by sending a transmission operation instruction to the circuit. After executing such a main-side communication control process, the game control timer interrupt process is terminated after the interrupt is permitted.

  In the game random number update processing executed in step S50 of FIG. 27 or step S94 of FIG. 30, for example, the stored data in a predetermined area of the random counter included in the game control counter setting unit is updated, etc. 1 may be added to the random value MR2. As a result, the random number MR2 for determining the big hit type is updated to be incremented by one each time the game random number update process is executed. In the game random number update processing, among the numerical data indicating the random numbers MR1 to MR5 that are the game random numbers, the numerical data indicating the random values MR3 to MR5 are sequentially set as the random numbers to be updated. Here, for example, for the random values MR3 to MR5, an addition value, an addition determination value, or a maximum determination value may be determined. As an example, the range of the addition value is set to “0” to “7”, the addition determination value is “8”, and the maximum determination value is “242” corresponding to the random value MR3 for determining the variation pattern type. That's fine. Corresponding to the random number MR4 for determining the variation pattern, the range of the addition value may be set to “0” to “7”, the addition determination value is “8”, and the maximum determination value is “998”.

  The added value is a value to be added to each random number value in response to one timer interruption or the like, and the value only needs to be different every time the game random number update process is executed. For example, the addition value is obtained on the basis of numerical data that becomes a random value for determining the addition value, and an area for storing the addition value as a temporary variable may be provided in the RAM 507 or the like. The addition determination value is a value used to acquire an addition value corresponding to each random value by comparison with a random value for determining the addition value. More specifically, after the random value for determining the addition value is read as the initial value of the addition value corresponding to each random value, until it is determined that the current addition value is smaller than the addition determination value, A value obtained by subtracting the addition determination value from the current addition value is updated as a new addition value. The random number determination value is a value used to determine whether each updated random number value obtained by adding the finally obtained addition value is within a range of possible values. When each updated random number value exceeds the corresponding random number determination value, a value obtained by subtracting the random number determination value from the updated random number value is set as a new random number value. For example, the numerical data indicating the random value MR2 may be updated so as to be incremented by one each time a timer interrupt occurs in the game control microcomputer 100.

  In the game random number update process, numerical data indicating a random value for determining an addition value is read, and it is determined whether or not the read value is less than an addition determination value determined for each random value to be updated. If it is less than the addition determination value, the read value is set to the addition value. On the other hand, if it is equal to or greater than the addition determination value, a value obtained by subtracting the addition determination value from the read value is set as the addition value. Thereafter, the addition value is added to the random number value to be updated to obtain a random number value after addition. At this time, it is determined whether the random number value after addition is less than the maximum determination value determined for each random number value to be updated. If it is less than the maximum judgment value, the random number value after addition is set to the updated random number value. On the other hand, if it is equal to or greater than the maximum determination value, a value obtained by subtracting the maximum determination value from the added random number value is set as the updated random number value. The updated random number value thus set is set in a predetermined area for storing the random number value to be updated by the random counter, thereby completing the update of the random number value.

  FIG. 31 is a flowchart showing an example of processing executed in step S95 shown in FIG. 30 as the special symbol process. In this special symbol process, the CPU 505 first executes a start winning determination process (step S131). FIG. 32 is a flowchart illustrating an example of the start winning determination process executed in step S131.

  When the start winning determination process shown in FIG. 32 is started, the CPU 505 first checks the detection state of the game ball in the first start port switch 22A (step S201). As an example, in the process of step S201, a bit stored in a predetermined switch-on buffer provided in a predetermined area (such as a game control buffer setting unit) of the RAM 507 is loaded and the bit associated with the first start port switch 22A is loaded. Specify whether the value is “0” or “1”. At this time, if the checked bit value is “0”, the first start port switch 22A indicates that the game ball is not detected and is in an off state, while if it is “1”, the first start port switch 22A. Indicates that the game ball is on due to detection. As another example, in the process of step S201, for example, by confirming the input state of a predetermined port such as the input port PI0 included in the PIP 510, it is determined whether or not the detection signal transmitted from the start port switch 22A is on. Identify. At this time, if the detection signal is in the off state, the first start port switch 22A indicates that the game ball is not detected and is in the off state, while if it is on, the first start port switch 22A detects the game ball. It is shown that it is in an ON state by detecting it. In this case, by repeatedly checking the input state of the predetermined port a plurality of times (for example, twice), it is specified that the first start port switch 22A is on when the detection signal is continuously on. May be. Subsequent to the process of step S201, a predetermined first start opening winning table is selected and set in the use table (step S202).

  The first starting entry winning table includes the first reserved memory counter address, the address of the hard latch random number value register 559A, the first special figure reserved memory section address, the first starting winning designation command table address, the start data (first), and the like. Consists of specified table data. The first reserved memory counter address is an address assigned to the first reserved memory counter. The first reserved memory counter is provided in a predetermined area (such as a game control counter setting unit) of the RAM 507 and counts the first special figure reserved memory number. The address of the hard latch random number register 559A is an address (for example, the head address) assigned to the hard latch random value register 559A in the built-in register area shown in FIG. The first special figure reservation storage unit address is an address (for example, a head address) assigned to the first special figure reservation storage unit. The first start winning designation command table address is the address (for example, the top address) of the first starting winning designation command table stored in the ROM 506. The start data (first) is “first” start data that is stored in the start data storage unit and indicates that the game ball has passed (entered) through the first start winning opening. In the process of step S202, the storage address (first address) of the first start opening winning table in the ROM 506 is stored in a predetermined table pointer so that the first starting opening winning table can be referred to as a use table. . Hereinafter, in the process of selecting various tables and setting them in the use table, the same setting may be performed.

  Following the processing in step S202, it is determined whether or not the first start port switch 22A is in the ON state based on the check result in step S201 (step S203). At this time, if the first start port switch 22A is in an ON state (step S203; Yes), a predetermined start port passing process is executed (step S204). In addition, when it is determined in step S203 that the first start port switch 22A is in the OFF state (step S203; No), after the start port passing process is executed in step S204, the second start port switch The detection state of the game ball in 22B is checked (step S205). The process in step S205 may be any process as long as the process in step S201 is adapted to the second start port switch 22B. Subsequently, a predetermined second start opening winning table is selected and set in the use table (step S206).

  The second starting entry winning table includes the second reserved memory counter address, the address of the hard latch random number value register 559B, the second special figure reserved memory unit address, the second starting winning designation command table address, the starting data (second), etc. Consists of specified table data. The second reserved memory counter address is an address assigned to the second reserved memory counter. The second reserved memory counter is provided in a predetermined area (such as a game control counter setting unit) of the RAM 507 and counts the second special figure reserved memory number. The address of the hard latch random value register 559B is an address assigned to the hard latch random value register 559B in the built-in register area shown in FIG. 7B. The second special figure reservation storage unit address is an address assigned to the second special figure reservation storage unit. The second start winning designation command table address is an address of the second starting winning designation command table stored in the ROM 506. The start data (second) is “second” start data that is stored in the start data storage unit and indicates that the game ball has passed (entered) through the second start winning opening.

  Further, based on the check result in step S205, it is determined whether or not the second start port switch 22B is in an ON state (step S207). If the second start port switch 22B is in the ON state (step S207; Yes), the start opening passage process is executed in the same manner as in step S204 (step S208), and then the start winning determination process is terminated. On the other hand, when it is determined in step S207 that the second start port switch 22B is in the OFF state, the start winning determination process is terminated without executing the start port passing process in step S207.

  The start-port passage process executed in step S204 or step S208 may be a process realized by a control code included in a user program (game control process program for game control) prepared in advance as a common process routine. That's fine. In this starting port passage processing, the first starting port winning table set in step S202 or the second starting port winning table set in step S206 is used. One of various processes corresponding to the case where the game ball passes (enters) the first start winning opening and the various processes corresponding to the case where the game ball passes (enters) the second start winning opening is executed. be able to.

  FIG. 33 is a flowchart illustrating an example of processing executed in step S204 or step S208 in FIG. In this starting port passage processing, the CPU 505 first reads the stored storage count value corresponding to the starting winning port through which the game ball has passed (entered) (step S501). That is, when the game ball passes (enters) the first start winning opening, the first hold memory count value is read, while when the game ball passes (enters) the second start winning opening, the second hold storage count is read. Read the count value. At this time, for example, in the first reserved storage counter address specified in the first start opening winning table set in the process of step S202 shown in FIG. 32, or in the second starting opening winning table set in the process of step S206. Corresponding to the designated second reserved storage counter address, it is only necessary to specify the storage address of the RAM 507 from which the reserved storage count value is read.

  Subsequently, it is determined whether or not the read value in the process of step S501 is greater than or equal to a predetermined upper limit value (eg, “4”) (step S502). At this time, if it is less than the upper limit value (step S502; No), the pending storage count value read out in the process of step S501 is updated so as to add 1 (step S503). Further, the storage position of the holding data in the special figure holding storage unit corresponding to the start winning opening through which the game ball has passed (entered) is specified (step S504). That is, when the game ball passes (enters) the first start winning opening, the storage position of the hold data in the first special figure holding storage unit is specified, while the game ball passes (enters) the second start winning opening. ), The storage position of the holding data in the second special figure holding storage unit is specified. At this time, for example, the first special drawing reservation storage unit address specified in the first starting opening winning table set in the process of step S202 shown in FIG. 32, or the second starting opening winning set set in the process of step S206. By adding an address addition value corresponding to the reserved storage count value read out in the processing of step S501 or the like to the second special figure reservation storage unit address specified in the table, the first special figure serving as the storage position of the reserved data is obtained. It suffices if the storage address of the figure reservation storage unit or the second special figure reservation storage unit can be specified.

  After the process of step S504 is executed, a random value register from which numerical data serving as the random value MR1 for determining the special figure display result is read is specified (step S505). That is, when the game ball passes (enters) the first start winning opening, the hard latch random value register 559A is used as a reading source of numerical data, while the game ball passes (enters) the second start winning opening. In this case, the hard latch random number value register 559B is used as a numerical data reading source. At this time, for example, the address of the hard latch random number value register 559A specified in the first start opening winning table set in the process of step S202 shown in FIG. 32, or the second start opening winning set set in the process of step S206. Corresponding to the address of the hard latch random number value register 559B specified in the table, it is only necessary to identify the address of the random number value register from which the numerical data is read out.

  Then, by reading the random value register specified in step S505, numerical data that becomes a random value is extracted (step S506). That is, when the hard latch random number value register 559A is set as the reading source in the process of step S505, the numerical data is read and extracted from the hard latch random number value register 559A included in the random number circuit 509A. On the other hand, when the hard latch random number value register 559B is set as the reading source in the process of step S505, the numerical data is read and extracted from the hard latch random number value register 559B included in the random number circuit 509A. At this time, the random number latch flag corresponding to the hard latch random number value register 559A or the hard latch random number value register 559B from which the numerical data has been read is turned off. That is, when the hard latch random number register 559A is set as the reading source in the process of step S505, the bit values of the hard latch flag data RL00HF and RL01HF are changed from “1” to “0” by reading the numerical data in the process of step S506. The random number latch flag associated with the hard latch random number value register 559A is turned off. On the other hand, when the hard latch random number register 559B is set as the reading source in the process of step S505, the bit values of the hard latch flag data RL02HF and RL03HF are changed from “1” by reading the numerical data in the process of step S506. The value is changed to “0”, and the random number latch flag associated with the hard latch random number value register 559B is turned off. In the process of step S505, numerical data indicating the random number MR2 for determining the big hit type is read and extracted from a random counter or the like provided in a predetermined area (such as a game control counter setting unit) of the RAM 507. Based on the numerical data thus read out, numerical data indicating the random number value MR1 for determining the special figure display result and numerical data indicating the random value MR2 for determining the jackpot type are specified as the pending data in the process of step S504. It is stored in the storage position of the special figure hold storage unit (step S507).

  The numerical data read from the hard latch random value register 559A and the hard latch random value register 559B is directly used as the special figure display result determination random number MR1 as the first special figure reservation storage unit or the second special figure reservation storage. Or may be stored after a predetermined processing. As an example, numerical data extracted from the random number circuit 509 is temporarily stored in a 16-bit general-purpose register of the CPU 505 or the like. Subsequently, a refresh register value that is a stored value of a refresh register built in the CPU 505 is read as numerical data that becomes a random number value for processing. In this case, the refresh register value may be added to the upper byte in the general-purpose register, while the lower byte may be left as it is. Here, instead of adding the refresh register value, predetermined arithmetic processing such as subtraction, logical sum, and logical product may be executed. Alternatively, the refresh register value may be added to the lower byte in the general-purpose register. Further, the upper byte and the lower byte of the numerical data extracted from the random number circuit 509A or the like may be exchanged and stored as the upper byte or the lower byte in the general-purpose register. Furthermore, after the refresh register value is added to the high-order byte or low-order byte in the general-purpose register, or without performing arithmetic processing such as addition to the high-order byte or low-order byte in the general-purpose register, the high-order byte and the low-order byte are switched. It may be. Of the upper byte and lower byte of the numerical data extracted from the random number circuit 509A or the like, the data of a specific bit may be replaced with the data of another bit. In this case, for example, in the bus connecting the hard latch random number register 559A or the hard latch random number register 559B in the random number circuit 509A and the upper byte or lower byte of the general-purpose register, the data of a specific bit is transferred to another bit. The wiring may be crossed so as to replace the data. Thereafter, the CPU 505 performs an AND operation on the stored value of the general-purpose register and a predetermined logical value (for example, “FFFFH”), or outputs the stored value of the general-purpose register as it is and stores it in a predetermined area of the RAM 507. Thus, numerical data indicating the 16-bit random value MR1 may be set. For example, when setting numerical data indicating a 14-bit random number value, a 14-bit value can be acquired by performing an AND operation on the stored value of the general-purpose register and “7F7FH”. . Further, a logical sum operation may be executed instead of the logical product operation. At this time, the area of the RAM 507 in which numerical data indicating the random number value MR1 is stored may be included in, for example, a random counter provided in the game control counter setting unit. Alternatively, the stored value of the general-purpose register may be output to the first special figure reservation storage unit or the second special figure reservation storage unit, and may be stored data indicating the random value MR1.

  Further, numerical data indicating a random value for determining the addition value may be set based on the stored value of the general-purpose register. As an example, when the numerical data indicating the random value for determining the addition value takes a value in the range of “0” to “7”, the logical value of the storage value of the general-purpose register and “C0C0H” is calculated, Numerical data indicating a 4-bit random value may be set by storing it in a predetermined area of the RAM 507.

  Subsequent to the processing in step S507, setting for transmitting a start winning designation command to the effect control board 12 is performed (step S508). That is, when the game ball passes (enters) the first start prize opening, the transmission setting of the first start prize designation command is performed, while when the game ball passes (enters) the second start prize opening. The transmission setting for the second start winning designation command is performed. At this time, for example, the first start winning designation command table address designated in the first starting prize winning table set in the process of step S202 shown in FIG. 32, or the second start winning prize set in the process of step S206. The second start winning designation command table address designated by the table may be set in the buffer area designated by the transmission command pointer in the transmission command buffer provided in the game control buffer setting unit. The start winning designation command set in this way is performed from the main board 11 to the effect control board 12 by executing the main side communication control process of step S98 shown in FIG. 30 after the special symbol process process is completed, for example. Is transmitted. Hereinafter, the same setting may be performed in the process of performing the setting for transmitting various control commands to the sub-side control board such as the effect control board 12.

  After executing the process of step S508, the start data is stored (step S510). That is, when the game ball passes (enters) the first start winning opening, the "first" start data corresponding to the winning to the first starting winning opening is set at the head of the empty entry in the start data storage unit. set. On the other hand, when the game ball passes (enters) the second start winning opening, the “second” starting data corresponding to the winning to the second starting winning opening is stored in the empty entry in the start data storage unit. Set to the beginning. Then, for example, by setting the storage address of the reserved memory count notification command table in the ROM 506 in the buffer area specified by the transmit command pointer in the transmit command buffer, etc., to transmit the reserved memory count notification command to the effect control board 12. Is set (step S511), the process at the time of passing through the start port is terminated.

  If it is determined in step S502 that the read value is greater than or equal to the upper limit value (step S502; Yes), the random number latch flag is cleared by reading the hard latch random number registers 559A and 559B (step S512), and then the process is started. End the mouth passage process. Here, in the process of step S512, the numerical data stored in the hard latch random value register 559A is read out in response to the game ball passing (entering) the first start winning opening, while the game ball is stored in the second game ball. The numerical data stored in the hard latch random value register 559B is read in response to passing (entering) the start winning opening. At this time, similarly to the process of step S505, for example, the hard latch random number value register 559A address specified in the first start opening winning table set in the process of step S202 shown in FIG. 32, or set in the process of step S206. Corresponding to the hard latch random number value register 559B address specified in the second start opening prize table, the address of the random number value register from which the numerical data is read can be specified.

  When the first start winning signal SS1 or the second start winning signal SS2 is input from the first start port switch 22A or the second start port switch 22B to the random number circuit 509A without passing through the CPU 505 or the like, the first special figure Regardless of the number of reserved data stored in the reserved storage section or the second special figure reserved storage section, the hard latch random number value register 559A or the hard latch is provided in response to the input of the first start winning signal SS1 or the second starting winning signal SS2. Numeric value data to be a random number value is stored in the random value register 559B. At this time, for example, when the bit value in the bit number [3] of the hard latch selection register RL0LS shown in FIGS. 20A and 20B is “0”, the hard latch random value register in which the numerical data is stored is stored. The corresponding random number latch flag is turned on, and storage of new numerical data is restricted. Therefore, when the number of stored data is greater than or equal to the upper limit value, if the numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B is left without being read, the first start winning opening and the second When a new game ball passes (enters) through the start winning opening, new numerical data corresponding to the passage (entrance) of this game ball is taken into the hard latch random value register 559A or the hard latch random value register 559B and stored. In some cases, the numerical data stored corresponding to the game ball that has passed (entered) first is read out, and an accurate random value cannot be obtained. Therefore, even when the number of stored data has reached the upper limit value, the process of step S512 is executed, and the random number latch flag is cleared by reading the random number value register, thereby corresponding to the passage (entrance) of a new game ball. Thus, it is possible to obtain numerical data that is an accurate random value. Note that the numerical data read from the hard latch random value register 559A or the hard latch random value register 559B by the process of step S512 is not used for the determination process of whether or not the special figure display result is “big hit”. Instead, it can be discarded (erased) as it is.

  After the start winning determination process including the start-port passing process as described above is executed in step S131 of FIG. 31, a special-purpose process flag provided in a predetermined area (such as a game control flag setting unit) of the RAM 507. Depending on the value, any one of the processes of step S140 to step S150 is selected and executed.

  The special symbol normal process of step S140 is executed when the value of the special symbol process flag is “0”. In this special symbol normal process, the first special symbol display device 4A and the second special symbol display device are based on the presence / absence of reserved data stored in the first special symbol reservation storage unit and the second special symbol reservation storage unit. It is determined whether or not to start the special game with 4B. Also, in the special symbol normal processing, whether the variable display result of the special symbol, the decorative symbol, the color symbol, etc. is set to “big hit” or “small hit” based on the numerical data indicating the random value MR1 for determining the special symbol display result. No is determined (predetermined) before the variable display result is derived and displayed. Further, in the special symbol normal process, in response to the variable display result of the special symbol in the special symbol game, the confirmed special symbol (big hit symbol, the special symbol game by the first special symbol display device 4A and the second special symbol display device 4B) Either a small hit symbol or a lost symbol) is set.

  The variation pattern setting process of step S141 is executed when the value of the special figure process flag is “1”. This variation pattern setting process includes a pre-decision result on whether or not the variable display result is “big hit” or “small hit”, a reach decision result on whether or not the variable display state of the decorative symbol is in the reach state, etc. The process includes determining a variation pattern type as one of a plurality of types, and determining a variation pattern as a plurality of types in accordance with the determination result of the variation pattern type.

  The special symbol variation process of step S142 is executed when the value of the special symbol process flag is “2”. This special symbol variation process includes a process for setting the special symbol to be varied in the first special symbol display device 4A and the second special symbol display device 4B, and an elapsed time after the special symbol starts to vary. It includes processing to measure For example, each time the special symbol variation process is executed in step S142, the value (special diagram variation timer value) in the special diagram variation timer provided in the game control timer setting unit is decremented or incremented by one. Regardless of whether the game is a special game using the first special symbol in the first special symbol display device 4A or a special game using the second special symbol in the second special symbol display device 4B, a common timer is used. The elapsed time is measured. It is also determined whether or not the measured elapsed time has reached a special figure fluctuation time corresponding to the fluctuation pattern. As described above, the special symbol variation processing uses the special symbol variation in the special symbol game using the first special symbol in the first special symbol display device 4A and the second special symbol in the second special symbol display device 4B. This is a process for controlling the variation of special symbols in the special figure game by a common processing routine. When the elapsed time since the start of the special symbol variation reaches the special symbol variation time, the value of the special symbol process flag is updated to “3”.

  The special symbol stop process in step S143 is executed when the value of the special symbol process flag is “3”. In this special symbol stop process, the first special symbol display device 4A or the second special symbol display device 4B stops the change of the special symbol, and the fixed special symbol which is the variable symbol display result is stopped and displayed. A process for setting is included. Then, a determination is made as to whether or not either the big hit flag or the small hit flag provided in the game control flag setting unit is on. Is updated to “4”, and when the small hit flag is on, the value of the special figure process flag is updated to “8”. When both the big hit flag and the small hit flag are off, the value of the special figure process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S144 is executed when the value of the special figure process flag is “4”. This pre-opening process for the big winning opening is a process for starting the execution of the round in the big winning gaming state and setting the opening for the big winning opening based on the fact that the variable display result is “big hit” Etc. are included. At this time, for example, an upper limit of a period during which the big prize opening is in an open state may be set corresponding to the setting of the maximum number of big prize opening times. As an example, when the maximum value of the number of times of winning the big winning opening is set to “15” corresponding to the 15 round big hit state, the upper limit of the period during which the big winning opening is opened is set to “29 seconds”. On the other hand, if the maximum value for the number of times a big winning opening is opened is set to “2” corresponding to the two round big hit state, the upper limit of the period during which the big winning opening is opened is set to “0.5 seconds”. Set to.

  The special winning opening opening process in step S145 is executed when the value of the special figure process flag is “5”. This process during opening of the big winning opening is based on the process of measuring the elapsed time since the big winning opening is opened, the elapsed time measured, the number of game balls detected by the count switch 23, and the like. Processing for determining whether or not it is time to return the winning opening from the open state to the closed state is included. When the big prize opening is changed from the closed state to the open state, a process for starting the supply of the solenoid driving signal to the solenoid 82 for the big prize opening door may be executed. On the other hand, when returning the prize winning port to the closed state, a process of stopping the supply of the solenoid drive signal to the solenoid 82 for the prize winning door may be executed.

  The special winning opening opening post-processing in step S146 is executed when the value of the special figure process flag is “6”. The post-opening process for the big prize opening includes a process for determining whether or not the number of executions of the round in which the big prize opening is in an open state has reached the maximum number of open big prize openings, This includes a process for making a setting for transmitting an end designation command when hit.

  The big hit end process in step S147 is executed when the value of the special figure process flag is “7”. In the jackpot ending process, an ending effect as an effect operation for notifying the end of the jackpot gaming state is executed by an effect electrical component (effect device) such as the image display device 5, the speakers 8L and 8R, and the game effect lamp 9. A process of waiting until a waiting time corresponding to a period of time elapses, a process of performing various settings corresponding to the end of the big hit gaming state, and the like.

  The small hit release pre-processing in step S148 is executed when the value of the special figure process flag is “8”. This pre-opening process for small hits is a setting for starting the execution of the variable winning action in the small hit game state and opening the big winning opening based on the fact that the variable display result is “small hit”, etc. The processing to perform is included. At this time, for example, the maximum value of the number of times that the big prize opening is opened is “0” because the variable display result is “small hit”, and the upper limit of the period during which the big prize opening is opened is set to “0. “5 seconds” may be set.

  The small hit releasing process in step S149 is executed when the value of the special figure process flag is “9”. In the small hit opening process, the process of measuring the elapsed time since the big prize opening is in the open state, and the timing for returning the big prize opening from the open state to the closed state based on the measured elapsed time, etc. The process etc. which determine whether or not were included are included.

  The small hit end process in step S150 is executed when the value of the special figure process flag is “10”. In this small hit end process, a period in which an effect operation for notifying the end of the small hit game state is executed by an electric component (effect device) for effects such as the image display device 5, the speakers 8L and 8R, and the game effect lamp 9 The process of waiting until the waiting time corresponding to the elapses is included. Here, when the small hit gaming state is finished, the state of the pachinko gaming machine 1 before the small hit gaming state is continued without changing the state of the probability change flag and the short time flag.

  FIG. 34 is a flowchart showing an example of the process executed in step S140 of FIG. 31 as the special symbol normal process. In this special symbol normal process, the CPU 505 first determines whether or not there is a special symbol game hold memory, for example, by determining whether or not there is valid start data stored in the start data storage unit (step S221). . Here, if valid start data such as “first” start data or “second” start data is stored in the top entry of the start data storage unit, it indicates that there is a special memory for the special game. Yes. Note that the method for determining whether or not the special figure game is stored on hold is not limited to checking the stored contents of the start data storage unit. For example, the total reserved memory count value stored in the game control counter setting unit is a value other than “0”, or at least one of the first reserved memory count value and the second reserved memory count value is “0”. Corresponding to a value other than "", it may be possible to specify that there is a special memory for the special game.

  In response to the presence of valid start data stored in step S221, when it is determined that there is a special figure game hold memory (step S221; Yes), the start data is read from the start data storage unit (step S222). ). Here, the start data stored in association with the hold number “1” in the start data storage unit may be read.

  In this embodiment, the first start condition and the second start condition are not distinguished from each other, and it is assumed that the special game corresponding to the previously established start condition is executed sequentially. On the other hand, for example, the special figure game using the second special figure may be executed with priority over the special figure game using the first special figure. In this case, for example, instead of the process of step S221, it is determined whether or not the second reserved storage count value is “0”. If the second pending storage count value is a value other than “0”, the same processing as that performed when “second” start data is read from the start data storage unit may be executed. On the other hand, when the second reserved memory count value is “0”, it is determined whether or not the first reserved memory count value is “0”. The same process as when the “first” start data is read from the start data storage unit may be executed. As described above, when one of the special game using the first special figure and the special game using the second special figure is executed with priority over the other, the first reserved memory count value and the second special game are used. Since the special symbol for starting the variable display can be determined based on the reserved storage count value, the configuration of the start data storage unit may not be provided.

  Alternatively, it is determined which one of the first reserved memory count value and the second reserved memory count value is larger, and the special game using a special symbol corresponding to the larger count value is preferentially executed. You may make it do. In this case, the first hold storage count value is compared with the second hold storage count value, and if the first hold storage count value is larger, the “first” start data from the start data storage unit When the second hold storage count value is larger, the same process as when the “second” start data is read from the start data storage unit is executed. It is sufficient to execute the process. If the first reserved memory count value and the second reserved memory count value match, the special game using the first special figure may be executed with priority, or the second special figure will be used. The special figure game that has been played may be given priority. In this way, by giving priority to the special figure game using the special symbol corresponding to the person with the larger reserved memory count value, it is possible to reduce the occurrence of invalid start winnings.

  After executing the process of step S222, the stored contents of the start data stored in the start data storage unit in entries lower than the hold number “1” (for example, entries corresponding to the hold numbers “2” to “8”) Are shifted upward by one entry (step S223). Then, it is determined whether the content of the start data read in step S222 is “first” or “second” (step S224).

  If it is determined in step S224 that the content of the start data is “first” (step S224; first), a special figure game using the first special figure by the first special symbol display device 4A is started. In response to the establishment of the first start condition, the variable special figure designation buffer value stored in the game control buffer setting unit is set to “1” (step S225). On the other hand, when it is determined in step S224 that the content of the start data is “second” (step S224; second), the special game using the second special figure by the second special symbol display device 4B. In response to the establishment of the second start condition for starting the process, the variable special figure designation buffer value is set to “2” (step S226).

  After executing one of the processes in steps S225 and S226, the hold data is read from the special figure hold storage unit corresponding to the start data read in step S222 (step S227). For example, when the start data is “first”, the random number value MR1 for determining the special figure display result is used as the hold data stored in association with the hold number “1” in the first special figure hold storage unit. And numerical data indicating the jackpot type determination random value MR2 are respectively read. On the other hand, when the start data is “second”, the hold data stored in association with the hold number “1” in the second special figure hold storage unit is used for determining the special figure display result. The numerical data indicating the random number value MR1 and the numerical data indicating the random number value MR2 for determining the jackpot type are respectively read out.

  Subsequent to the processing of step S227, the pending storage number count value corresponding to the start data is updated to be decremented by 1, and the entry (ie, the entry number lower than the hold number “1” ( For example, the storage contents of the hold data stored in the hold numbers “2” to “4”) are shifted up by one entry (step S228). For example, when the start data is “first”, the first hold storage count value is decremented by 1, and the storage content of the hold data in the first special figure hold storage unit is shifted up by one entry. On the other hand, when the start data is “second”, the second hold storage count value is decremented by 1, and the storage content of the hold data in the second special figure hold storage unit is increased by one entry. Shift.

  After that, select and set the special figure display result determination table according to the start data as the use table for determining whether the variable display result is “big hit” or “small hit” (Step S229). For example, if the start data is “first”, the first special figure display result determination table is set as the use table, while if the start data is “second”, the second special figure display result determination table is used as the use table. Set as. The CPU 505 refers to the special figure display result determination table set in this way, and based on the numerical data indicating the random number value MR1 for special figure display result determination included in the pending data read in step S227, The special figure display result is determined as one of a plurality of types (step S230).

  In the first special figure display result determination table and the second special figure display result determination table, a numerical value (determined value) to be compared with the random value MR1 for determining the special figure display result indicates the special figure display result as “big hit” and “ It is only necessary to be assigned to the determination result of “small hit” or “losing”. FIG. 35A shows an example of determining the special figure display result by the process of step S230. As described above, whether the special figure display result is “big hit”, “small hit”, or “losing” is the numerical data or the special figure display result determination table indicating the random value MR1 for determining the special figure display result. And may be determined at a predetermined rate. In the determination example shown in FIG. 35A, the determination ratio of whether or not the special figure display result is “big hit” is varied depending on the presence or absence of probability variation control in the probability variation state. The CPU 505 may determine that the probability variation control is being performed when the probability variation flag provided in a predetermined area (such as a game control flag setting unit) of the RAM 507 is on.

  As shown in FIG. 35 (A), when the probability variation control is performed in the probability variation state, the special figure display result is “a higher rate than when the probability variation control is not performed in the normal state or the short time state”. "Big hit" is decided. Therefore, for example, by the big hit end process in step S147 shown in FIG. 31, the probability change control is performed based on the fact that the probability change flag is set to the on state corresponding to the case where the big hit type is “probability change” or “surprise”. When the probability change state is performed, the special figure display result is more likely to be a “hit” and more likely to be a big hit game state than when the probability change control is not performed in the normal state or the short time state. In the determination example shown in FIG. 35A, when the variation special chart is the first special chart, the special figure display result is determined to be “small hit” at a predetermined ratio. On the other hand, when the fluctuation special figure is the second special figure, the special figure display result is not determined to be “small hit”. It is sufficient that the fluctuation special map can identify whether it is “first” or “second” from the start data.

  When the game state is a certain change state or a short time state, the high variable control is performed, so that the normally variable winning device 6B can be changed to the first variable in an advantageous opening mode in which the game ball easily passes (enters) through the second start winning opening. It may be changed between a state (open state or expanded open state) and a second variable state (closed state or normal open state). When such a high opening control is performed, by limiting the result of the special figure display so that it is not determined to be “small hit” based on the fact that the game ball has passed (entered) through the second start winning opening, It is possible to prevent a decrease in the entertainment interest due to the delay. When the fluctuation special chart is the second special figure, the special figure display result may be determined as “small hit” at a lower rate than when the fluctuation special figure is the first special figure. Also good.

  Thereafter, the CPU 505 determines whether or not the special figure display result determined by the process of step S230 is “big hit” (step S231). At this time, when it is determined that it is not “big hit” (step S231; No), it is determined whether or not the special figure display result is “small hit” (step S232). When it is determined that the game is “small hit” (step S232; Yes), the small hit flag provided in the game control flag setting unit is set to the on state (step S233).

  When it is determined in step S231 that the game is a “hit” (step S231; Yes), the big hit flag provided in the game control flag setting unit is set to the on state (step S234). At this time, a predetermined big hit type determination table is selected and set as a use table for determining the big hit type as one of a plurality of types (step S235). The CPU 505 refers to the jackpot type determination table set in this manner, and determines the jackpot type as “based on the numerical data indicating the random number MR2 for determining the jackpot type included in the pending data read in step S227. One of a plurality of types such as “non-probability change”, “probability change”, and “surprising accuracy” is determined (step S236).

  FIG. 35B shows an example of determining the jackpot type by the process of step S236. In this determination example, the determination ratio of the jackpot type is varied depending on whether the variation special chart is the first special chart or the second special chart. More specifically, when the variation special chart is the first special chart, the big hit type is determined to be “surprise” at a predetermined rate. On the other hand, when the variation special chart is the second special chart, the big hit type is not determined to be “surprise”. That is, the big hit type is determined to be “surprise” only when the variation special chart is the first special figure. In this manner, different jackpot types may be determined according to special symbols variably displayed in the special figure game. In addition, the ratio at which the big hit type is determined to be “probable change” is higher when the fluctuation special chart is the second special figure than when the fluctuation special figure is the first special figure. Thus, the predetermined jackpot type may be determined at a different rate depending on the special symbol variably displayed in the special game.

  When the game state is a certain change state or a short time state, the high variable control is performed, so that the normally variable winning device 6B can be changed to the first variable in an advantageous opening mode in which the game ball easily passes (enters) through the second start winning opening. It may be changed between a state (open state or expanded open state) and a second variable state (closed state or normal open state). When such a high opening control is performed, if the special figure display result is determined to be “big hit” based on the fact that the game ball has passed (entered) through the second start winning opening, By limiting so that it is not determined to be “accuracy”, it is possible to prevent a decrease in gaming interests due to an extended game. When the fluctuation special chart is the second special figure, the big hit type may be determined to be “surprise” at a lower rate than when the fluctuation special figure is the first special figure.

  Corresponding to the jackpot type determined in step S236 in this way, for example, by setting the jackpot type buffer value which is the stored value of the jackpot type buffer provided in the game control buffer setting unit, it is determined in the process of step S236. The big hit type is stored (step S237). As an example, if the big hit type is “non-probable change”, the big hit type buffer value may be “0”, “probable change” may be “1”, and “surprise” may be “2”.

  If it is determined in step S232 that it is not “small hit” (step S232; No), or after performing any of the processing in steps S233 and S237, whether to control to the big hit gaming state or the small hit gaming state? A determined special symbol is set in accordance with the result of the prior determination as to whether or not, and further according to the determination result of the jackpot type in the case of the jackpot game state (step S238). As an example, when it is determined in step S232 that the special figure display result is not “small hit”, a lost pattern is obtained corresponding to the pre-determined result indicating that the special figure display result is “lost”. The special symbol of the symbol indicating “−” is set to the confirmed special symbol. On the other hand, if it is determined in step S232 that the special figure display result is “small hit”, the small figure corresponding to the pre-determined result indicating that the special figure display result is “small hit”. The special symbol of the number indicating “5” as the symbol is set as the confirmed special symbol. If it is determined in step S231 that the special figure display result is “big hit”, the big hit symbols “1”, “3”, “7” are set according to the determination result of the big hit type in step S236. Among the special symbols of the numbers indicating "", one of the special symbols is set as the confirmed special symbol. That is, according to the determination result that the big hit type is “non-probable change”, the special symbol indicating the number “3” that becomes the non-probable big hit symbol is set as the confirmed special symbol. Further, according to the determination result that the jackpot type is “probability change”, the special symbol indicating the number “7” that becomes the probability change big hit symbol is set as the confirmed special symbol. In accordance with the determination result that the big hit type is “accuracy”, the special symbol indicating the number of the big hit symbol “1” is set as the confirmed special symbol.

  After the confirmed special symbol is set in step S238, the value of the special symbol process flag is updated to “1” which is a value corresponding to the variation pattern setting process (step S239), and then the special symbol normal process is terminated. . If it is determined in step S221 that no valid start data is stored, and it is determined that there is no special game hold storage (step S221; No), a predetermined demonstration display setting is performed. (Step S240), the special symbol normal process is terminated. In the demonstration display setting in step S240, a customer waiting demonstration designation command for designating demonstration display (demonstration screen display) by displaying a predetermined effect image on the image display device 5, for example, is sent from the main board 11 to the effect control board 12. In contrast, it is determined whether or not the transmission has been completed. At this time, if the transmission has been completed, the demonstration display setting is ended as it is. On the other hand, if not yet transmitted, the transmission setting of the customer waiting demonstration designation command is performed by setting the storage address of the customer waiting demonstration designation command table in the ROM 506 in the transmission command buffer, for example.

  FIG. 36A is a flowchart illustrating an example of a process executed in step S141 in FIG. 31 as the variation pattern setting process. In this variation pattern setting process, the CPU 505 first determines whether or not the big hit flag is on (step S261). If the big hit flag is ON (step S261; Yes), the variation pattern corresponding to the big hit when the special figure display result is “big hit” is determined (step S262).

  If the big hit flag is off in step S261, it is determined whether or not the small hit flag is on (step S263). If the small hit flag is ON (step S263; Yes), the variation pattern corresponding to the small hit when the special figure display result is “small hit” is determined (step S264). On the other hand, when the small hit flag is off (step S263; No), the variation pattern corresponding to the time of loss when the special figure display result is “lost” is determined (step S265).

  FIG. 36B shows a variation pattern in this embodiment. In this embodiment, among the cases where the variable display result (special drawing display result) is “losing”, the decorative display variable display mode is “non-reach” that does not become the reach mode, and the reach mode is “ A plurality of variation patterns are prepared in advance for each of the cases of “reach” and when the variable display result (special display result) is “big hit” or “small hit”. Yes.

  In the processing of steps S262, S264, and S265, the variation pattern may be determined after the variation pattern type is determined. When determining the variation pattern type, a random value MR3 for determining the variation pattern type is extracted from, for example, a random counter provided in the game control counter setting unit. Then, by referring to the variation pattern type determination table prepared in advance, the variation pattern type is determined as one of a plurality of types based on the extracted random value MR3 for determining the variation pattern type. In the variation pattern type determination table, a numerical value (determination value) to be compared with the random value MR4 for determining the variation pattern type is assigned to one of a plurality of predetermined variation pattern types. The assignment of the decision value to each variation pattern type may differ depending on the jackpot type when the variable display result is “big hit”, for example. Further, a part or all of the determined values may be assigned to different variation pattern types depending on the jackpot type. In addition, the assignment of the decision value to each variation pattern type is performed by, for example, the special figure holding memory number (the first special figure holding memory number, the second special figure holding memory number, or the total holding when the variable display result is “lost”). Any one of the stored numbers) or the presence / absence of time-shortening control may be used. Also, some or all of the determined values may be assigned to different variation pattern types depending on the number of special figure reservations stored and the presence / absence of time reduction control.

  In the processing of steps S262, S264, and S265, the variation pattern may be determined after determining the variation pattern type or without determining the variation pattern type. When determining the variation pattern, the random value MR4 for determining the variation pattern is extracted from, for example, a random counter provided in the game control counter setting unit. Then, by referring to the variation pattern determination table prepared in advance, the variation pattern to be used is determined as one of a plurality of types based on the extracted random value MR4 for determining the variation pattern. In the variation pattern determination table, a numerical value (decision value) to be compared with the random value MR4 for determining the variation pattern is assigned to one of a plurality of predetermined variation patterns. The assignment of the determination value to each variation pattern may be different depending on, for example, the determination result of the variable display result or the determination result of the variation pattern type. When determining the variation pattern without determining the variation pattern type, the big hit type when the variable display result is “big hit” and the special figure holding memory when the variable display result is “lost” Depending on the number (the first special figure reserved memory number, the second special figure reserved memory number, or the total reserved memory number) or the presence or absence of time-saving control, the determination values may be assigned differently to each variation pattern. .

  After executing any of the processes of steps S262, S264, and S265, a special figure change time that is a variable symbol display time is set (step S266). The special figure change time, which is the variable display time of the special symbol, is the time required from the start of the change of the special symbol in the special figure game until the fixed special symbol that becomes the variable display result (special display result) is derived and displayed. It is. As shown in FIG. 36B, the special figure fluctuation time is determined in advance corresponding to a plurality of fluctuation patterns prepared in advance. The CPU 505 can set the timing at which the variable symbol display result of the special symbol or the decorative symbol is derived by setting the special symbol variation time.

  Following the process of step S266, a special game using the first special figure in the first special symbol display device 4A and a special game using the second special figure in the second special symbol display device 4B are started. The setting for starting the variation of the special symbol is performed so as to start one of the special symbol games for which the condition is satisfied (step S267). As an example, if the variation special figure specified by the start data is “first”, a setting for transmitting a drive signal for updating the display of the first special figure in the first special symbol display device 4A is performed. On the other hand, if the fluctuation special figure specified by the start data is “second”, a setting for transmitting a drive signal for updating the display of the second special figure in the second special symbol display device 4B is performed.

  After executing the process of step S267, command transmission setting is performed at the start of the special symbol fluctuation (step S268). For example, when the variation map specified by the start data is “first”, the CPU 103 sends a first variation start command, a variation pattern designation command, and a variable display result notification from the main substrate 11 to the effect control substrate 12. In order to sequentially transmit the command and the first pending storage number notification command, a storage address (first address) in the ROM 506 of the first change start command table prepared in advance is designated. On the other hand, when the variation map specified by the start data is “second”, the CPU 505 sends a second variation start command, variation pattern designation command, variable display result notification from the main board 11 to the effect control board 12. In order to sequentially transmit the command and the second pending storage number notification command, the storage address in the ROM 506 of the second variation start command table prepared in advance is designated.

  The first variation start command and the second variation start command use the variation start in the special symbol game using the first special symbol in the first special symbol display device 4A and the second special symbol in the second special symbol display device 4B. This is an effect control command for designating the start of fluctuation in the special figure game. The variation pattern designation command is variably displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R in the image display device 5 in response to the variable display of the special symbols in the special symbol game. This is an effect control command for designating a variation pattern such as a decorative design. The variable display result notification command is an effect control command for designating a variable display result such as a special symbol or a decorative symbol. The first reserved memory number notification command and the second reserved memory number notification command are effect control commands for notifying the first special figure reserved memory number and the second special figure reserved memory number.

  After executing the process of step S268, the value of the special figure process flag is updated to “2” (step S269), and the variation pattern setting process is terminated. When the value of the special figure process flag is updated to “2” in step S269, when the next timer interrupt occurs, the special symbol variation process in step S142 shown in FIG. 31 is executed.

  FIG. 37 is a flowchart showing an example of the process executed in step S143 of FIG. 31 as the special symbol stop process. In the special symbol stop process, the CPU 505 first determines whether or not the big hit flag is on (step S281). At this time, if the big hit flag is on (step S281; Yes), the big hit start production waiting time is set (step S282). For example, in the process of step S282, a timer initial value determined in advance corresponding to the jackpot start time production waiting time may be set in the game control process timer provided in the game control timer setting unit.

  Subsequent to the process of step S282, a setting for transmitting a hit start designation command from the main board 11 to the effect control board 12 is performed (step S283). For example, in the process of step S283, setting data indicating the storage address in the ROM 506 of the hit start specifying command table prepared in advance for transmitting the hit start specifying command may be stored in the transmission command buffer. Thereafter, the big hit flag is cleared and turned off (step S284). In addition, a setting for ending the probability variation state and the time reduction state is performed (step S285). For example, in step S285, processing for clearing the probability variation flag and the time reduction flag to turn it off, processing for clearing the special figure fluctuation count counter for counting the number of times the special figure game is executed in the probability variation state and time reduction status, and the like. It only has to be executed. Then, after updating the value of the special symbol process flag to “4” which is a value corresponding to the pre-opening process for the special winning opening (step S286), the special symbol stop process is terminated.

  If the big hit flag is off in step S281 (step S281; No), it is determined whether the small hit flag is on (step S287). At this time, if the small hit flag is on (step S287; Yes), a small hit start production waiting time is set (step S288). For example, in the process of step S288, a timer initial value determined in advance corresponding to the small hitting start time production waiting time may be set in the game control process timer.

  Subsequent to the process in step S288, as in the process in step S283, a setting for transmitting a hit start designation command from the main board 11 to the effect control board 12 is performed (step S289). Thereafter, the small hit flag is cleared and turned off (step S290). Then, the value of the special figure process flag is updated to “8”, which is a value corresponding to the small hit release pre-processing (step S291).

  If the small hit flag is off in step S287 (step S287; No), the value of the special figure process flag is updated to “0” which is a value corresponding to the special symbol normal process (step S292). . After executing one of the processes in steps S291 and S292, it is determined whether or not to end the probability variation state or the time reduction state (step S293). For example, in the process of step S293, the value of the special figure fluctuation number counter (special figure fluctuation number count value) is updated by, for example, subtracting 1 or adding 1, and the updated special figure fluctuation number count value is a predetermined value. It is determined whether or not the special game state end determination value is met. At this time, if it matches the special game state end determination value, the probability variation state or the time reduction state may be terminated by clearing the probability variation flag or the time reduction flag, etc., and controlled to the normal state. On the other hand, if it does not match the special game state end determination value, the state of the probability variation flag or the time reduction flag may be maintained and the process of step S293 may be ended. After executing the end determination of the probability variation state or the short time state, the special symbol stop process ends. Note that the end determination based on the special figure variation count value may be performed only in the short-time state, and the probability variation state may be continued until the next variable display result becomes “big hit”. . Alternatively, for example, by extracting numerical data indicating a random value for probability variation state end determination from a random counter provided in the game control counter setting unit and referring to a probability variation state end determination table stored in advance in the ROM 506 or the like, It may be determined whether or not to end the probability variation state.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, when the power supply voltage is supplied from the power supply board or the like, the CPU of the effect control microcomputer 120 is activated, and the effect control main process as shown in the flowchart of FIG. 38 is executed. Also in the production control microcomputer 120, the security check process may be executed by the CPU when the power is turned on or the system is reset, and the production control microcomputer 120 may be in the security mode. In this case, after it is determined in the security check process that no unauthorized changes have been made to the ROM, after the security time has elapsed, the process shifts to a user mode in which execution of the effect control main process is started. That's fine. When the effect control main process shown in FIG. 38 is started, the CPU of the effect control microcomputer 120 first executes a predetermined initialization process (step S401) and is built in or externally attached to the effect control microcomputer 120. The RAM is cleared, various initial values are set, and the timer circuit incorporated in the production control microcomputer 120 is set.

  Thereafter, the effect random number update process is executed (step S402), and numerical data indicating random values counted by a random counter provided in the RAM of the effect control microcomputer 120 as various random values used for effect control. Is updated by software. Subsequently, it is determined whether or not the timer interrupt flag is on (step S403). The timer interrupt flag is set to the on state every time a predetermined time (for example, 2 milliseconds) elapses based on, for example, the register setting of the timer circuit in the effect control microcomputer 120.

  On the side of the effect control board 12, an interrupt for receiving an effect control command from the main board 11 is generated separately from the timer interrupt that occurs every time a predetermined time elapses. This interrupt may be an interrupt generated when the received data is full in the serial communication circuit included in the production control microcomputer 120, for example. Alternatively, when a signal line for transmitting an effect control INT signal is wired between the main board 11 and the effect control board 12, an interrupt is generated when the effect control INT signal is turned on. Also good. In response to the occurrence of such an interrupt, the CPU of the production control microcomputer 120 automatically sets the interrupt prohibition, but if a CPU that does not automatically enter the interrupt prohibition state is used, an interrupt prohibition instruction (DI It is desirable to issue an order). The CPU of the effect control microcomputer 120 executes, for example, a predetermined command reception interrupt process in response to an interrupt due to reception data full or an interrupt due to the effect control INT signal being turned on. In this command reception interrupt process, communication data stored in a communication data register or the like provided corresponding to the serial communication circuit of the effect control microcomputer 120 is fetched. Alternatively, in the command reception interrupt process, a predetermined input port that receives a control signal transmitted from the main board 11 via the relay board 18 among the input ports included in the PIP or the like included in the effect control microcomputer 120. A control signal that becomes an effect control command may be captured. The effect control command fetched at this time is stored in an effect control command reception buffer provided in the RAM of the effect control microcomputer 120, for example. As an example, when the production control command has a 2-byte configuration, the first byte (MODE) and the second byte (EXT) are sequentially received and stored in the production control command reception buffer. Thereafter, the CPU of the effect control microcomputer 120 sets the interrupt permission, and then ends the command reception interrupt process.

  If the timer interrupt flag is off in step S403 (step S403; No), the process returns to step S402. On the other hand, if the timer interrupt flag is on in step S403 (step S403; Yes), the timer interrupt flag is cleared and turned off (step S404), and command analysis processing is executed (step S405). . In the command analysis process executed in step S405, for example, after reading various effect control commands transmitted from the game control microcomputer 100 of the main board 11 and stored in the effect control command reception buffer, the reading is performed. Settings and control corresponding to the issued effect control command are performed.

  After executing the command analysis process in step S405, an effect control process is executed (step S406). In the effect control process, for example, an effect image display operation in the display area of the image display device 5, an audio output operation from the speakers 8L and 8R, and a lighting operation in the game effect lamp 9 and the decoration LED are performed. With respect to the control content of the effect operation using the (effect device), determination, determination, setting, etc. according to the effect control command and the like transmitted from the main board 11 are performed.

  FIG. 39 is a flowchart showing an example of the process executed in step S406 of FIG. 38 as the effect control process. In the effect control process shown in FIG. 39, the CPU of the effect control microcomputer 120, for example, in the following steps S160 to S160, depending on the value of the effect process flag provided in the RAM of the effect control microcomputer 120 or the like. One of the processes in step S166 is selected and executed.

  The decorative symbol variation start waiting process in step S160 is a process executed when the value of the effect process flag is “0”. In the decorative symbol variation start waiting process, the image display device 5 depends on whether one of the first variation start command and the second variation start command is received as the variation start command transmitted from the main board 11. Starts variable display of decorative symbols on the “left”, “middle”, and “right” decorative symbol displays 5L, 5C, and 5R provided in the display area, and variable display of color symbols on the color symbol display unit. The process of determining whether or not to perform is included. At this time, if it is determined to start variable display, the value of the effect process flag is updated to “1”.

  The decorative symbol variation setting process in step S161 is a process executed when the value of the effect process flag is “1”. In this decorative symbol variation setting process, the start of the special symbol game using the first special symbol by the first special symbol display device 4A or the start of the special symbol game using the second special symbol by the second special symbol display device 4B. In order to perform various production operations including variable display of decorative designs and color designs in response to the The process of determining the presence or absence, etc., and selecting and setting any one of a plurality of types of effect control patterns prepared in advance as the use pattern according to the determination result is included. After such determination and setting are performed, the value of the production process flag is updated to “2”.

  The decorative symbol variation process in step S162 is a process executed when the value of the effect process flag is “2”. In the decorative symbol variation processing, for example, an effect control pattern to be used corresponding to a value of an effect control process timer (effect control process timer value) provided in the RAM of the effect control microcomputer 120 or the like A process for reading out various control data from, and performing various effects control during variable display of decorative symbols is included. Then, in response to, for example, that the effect control process timer value has reached a predetermined variable display end value (for example, “0”) or that a decorative symbol stop command transmitted from the main board 11 has been received. A final decorative symbol as a final stop symbol that is a variable display result of the symbol is displayed in a completely stopped state. If the effect control process timer value is set to the variable display end value and the fixed decorative symbol is displayed in a completely stopped state, the variable display time corresponding to the variation pattern specified by the variation pattern designation command has elapsed. Sometimes, without depending on the effect control command from the main board 11, it is possible to determine and display the variable display result by autonomously deriving and displaying the determined decorative symbol on the effect control board 12 side. When the finalized decorative symbol is displayed as a complete stop, the value of the effect process flag is updated to “3”.

  The decorative symbol variation end process in step S163 is a process executed when the value of the effect process flag is “3”. This decoration symbol variation end process includes a process of determining whether or not a hit start designation command transmitted from the main board 11 has been received. At this time, if it is determined that the hit start designation command has been received, the value of the rendering process flag is updated to “4” when the variable display result specified from the hit start designation command is “big hit”. Is done. On the other hand, when the variable display result specified from the hit start designation command is “small hit”, the value of the effect process flag is updated to “5”. Further, when a predetermined time has elapsed without receiving the hit start designation command, the value of the effect process flag is updated to “0” in response to the variable display result being “lost”.

  The big hit control effect process in step S164 is a process executed when the value of the effect process flag is “4”. In the effect processing during the big hit control, for example, an effect control pattern corresponding to the fact that the variable display result is “big hit” or the like is set, and an effect image based on the set content is displayed in the display area of the image display device 5. Or by outputting sound number data to the sound control board 13 and outputting sound and sound effects from the speakers 8L and 8R, and turning on the game effect lamp 9 and the decoration LED by outputting an electric decoration signal to the lamp control board 14 This includes processing for controlling various performance operations in the big hit gaming state such as turning off / off / flashing. Then, for example, the value of the effect process flag is updated to “6” in response to receiving a hit end designation command transmitted from the main board 11.

  The effect process during small hit control in step S165 is a process executed when the value of the effect process flag is “5”. In the effect process during the small hit control, for example, an effect control pattern is set in response to the variable display result being “small hit”, and an effect image based on the set content is displayed on the image display device 5. Displaying in the area, outputting sound and sound effects from the speakers 8L and 8R by outputting the sound number data to the sound control board 13, and outputting the electric decoration signal to the lamp control board 14 for the game effect lamp 9 and decoration Processing for controlling various performance operations in the small hit gaming state such as turning on / off / flashing the LED is included. Then, for example, the value of the effect process flag is updated to “6” in response to receiving a hit end designation command transmitted from the main board 11.

  The ending effect process in step S166 is a process executed when the value of the effect process flag is “6”. In this ending effect process, an effect control pattern or the like corresponding to the end of the big hit game state or the small hit game state is set, and an effect image based on the set content is displayed in the display area of the image display device 5. In addition, sound and sound effects are output from the speakers 8L and 8R by outputting the sound number data to the sound control board 13, and the game effect lamp 9 and the decoration LED are turned on / off by outputting an electric decoration signal to the lamp control board 14. This includes processing for controlling various performance operations corresponding to the end of the big hit gaming state or the small hit gaming state, such as blinking / flashing. Then, the value of the effect process flag is updated to “0” in response to the end of the effect operation.

  Hereinafter, a specific operation example in the pachinko gaming machine 1 will be described. In the pachinko gaming machine 1, a special figure game using the first special figure by the first special symbol display device 4A and a special figure game using the second special figure by the second special symbol display device 4B are executed, Corresponding to the variable display of special symbols in these special symbol games, the ornaments are displayed on the “left”, “middle”, and “right” decorative symbol display portions 5L, 5C, and 5R included in the display area of the image display device 5. Variable display of symbols is executed. And, for example, based on the variable display result in a special game such as a fixed special symbol or the variable display result of a decorative symbol such as a combination of fixed decorative symbols, a predetermined game value such as being controlled to a big hit gaming state is given. It becomes possible. The game value that can be imparted by the pachinko gaming machine 1 is advantageous to a player who is controlled to the big hit game state and the game winning ball is easy to enter (win) by changing the big prize opening from the closed state to the open state. What is necessary is just to be in a state or to generate a right to be in an advantageous state for the player. In addition, for example, the maximum number of rounds that can be executed in the big hit gaming state, the upper limit number of special figure games that can be executed in the short time state, the big hit probability in the probability variation state, and control to the big hit gaming state without being controlled in the normal state Arbitrary matters related to the advantageous degree of the game in the pachinko gaming machine 1, such as the number of consecutive times that is the number of times played reaches a predetermined number, or a combination of some or all of them, the gaming value in the pachinko gaming machine 1 Can be.

  In the game control microcomputer 100, for example, the CPU 505 performs a special-purpose display result determination disturbance based on the numerical data read from the hard latch random value register 559 A and the hard latch random value register 559 B of the random number circuit 509 A in step S 506 of FIG. Using the numerical data indicating the numerical value MR1, the special figure display result is determined as “big hit”, “small hit”, or “lost” in step S230 of FIG. In the random number circuit 509A, for example, the random number sequence change circuit 554A changes the count value permutation RCN output from the random number generation circuit 553A based on a random number update rule predetermined by the setting of the random number sequence change setting circuit 554B. Subsequently, after being compared with a random number maximum value set by a user program (software) or the like in the maximum value comparison circuit 555, a random number sequence RSN in which numerical data is updated by a predetermined procedure is output. Then, based on the first start winning signal SS1 from the first start port switch 22A input to the input port PI0 being turned on, the numerical data constituting the random number sequence RSN is disturbed in the hard latch random number value register 559A. Captured and stored as a numerical value. Also, based on the fact that the second start winning signal SS2 from the second start port switch 22B input to the input port PI1 is turned on, the numerical data constituting the random number sequence RSN is disturbed in the hard latch random value register 559B. Captured and stored as a numerical value.

  FIG. 40 is a timing chart for explaining the operation of the random number circuit 509A. FIG. 40A shows a control clock CCLK generated by a control clock generation circuit 111 mounted on the main board 11. FIG. 40B shows the random number clock RCK generated by the random number clock generation circuit 112. Note that the various signals shown in FIG. 40 are negative logic signals that are turned off at a high level and turned on at a low level. As shown in FIGS. 40A and 40B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCK are different from each other. It does not become an integral multiple of the other oscillation frequency.

  As shown in FIG. 40B, the random number clock RCK falls from a high level to a low level at timings T10, T11, T12,. The random number clock RCK is divided by two and then input to the random number update clock selection circuit 551 of the random number circuit 509A. When such a random number clock RCK divided by two (RCK / 2) is selected by the random number update clock selection circuit 551, the random number update clock RGK has timings T10, T12 as shown in FIG. , T14,..., Fall from a high level to a low level, and become a signal having an oscillation frequency that is ½ of the oscillation frequency of the random number clock RCK. For example, if the oscillation frequency of the random number clock RCK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Since the oscillation frequency of the random number clock RCK is neither an integral multiple nor a fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK. Different frequency.

  The random number generation circuit 553A updates the numerical data in the count value permutation RCN in response to, for example, the falling edge of the random number update clock RGK. The random number sequence changing circuit 554A changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553A based on the setting of the random number update rule by the random number sequence change setting circuit 554B as a random number sequence RDN. Output. The random number sequence RDN is output as the random number sequence RSN after being compared with the maximum random number value by the maximum value comparison circuit 555. Thus, the numerical data in the random number sequence RSN is updated in response to the falling edge of the random number update clock RGK, for example, as shown in FIG.

  The oscillation frequency of the random number clock RCK generated by the random number clock generation circuit 112 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other. Does not become an integral multiple of the other oscillation frequency. Therefore, even when the oscillation frequency of the random number update clock RGN used in the random number circuit 509A is half the oscillation frequency of the random number clock RCK, the oscillation frequency of the control clock CCLK and the oscillation frequency of the control clock CCLK The oscillation frequency of the internal system clock SCLK that is ½ of this is different. In this way, synchronization between the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK is prevented. From the operation timing of the CPU 505, the random number circuit 509A and the random number generation circuit 553A and the random number sequence change circuit 554B It becomes difficult to specify the update timing of the numerical data in the random number sequence RSN generated by the maximum value comparison circuit 555. Similarly, an 8-bit random number sequence is generated for the 8-bit random number circuit 509B. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of numerical data serving as random number values in the random number circuits 509A and 509B from the operation timing of the CPU 505.

  The hard latch selector 558A captures the first start winning signal SS1 and outputs the random number latch signal LL1 if the capture method is designated as signal input to the input port PI0. For example, the first start winning signal SS1 whose signal state changes between the off state (high level) and the on state (low level) at the timing shown in FIG. Is taken into the hard latch selector 558A at the falling timings T11, T13, T15,... A random number latch signal LL1 whose state changes between an off state and an on state is output. Here, the first start winning signal SS1 transmitted from the first start opening switch 22A is turned off when the start winning of the game ball at the first start winning opening formed by the normal winning ball apparatus 6A is detected. Change to ON state. The random number latch signal LL1 output from the hard latch selector 558A is supplied to the hard latch random number value register 559A and used to acquire numerical data in the random number sequence RSN output from the maximum value comparison circuit 555. In this way, the hard latch selector 558A generates a random number latch signal LL1 for obtaining numerical data as a random value based on the detection of the start winning of the game ball at the first start winning opening. It is generated separately from the case where the start winning of the game ball is detected.

  The hard latch selector 558B captures the second start winning signal SL2 and outputs the random number latch signal LL2 if the capture method is designated as signal input to the input port PI1. For example, the second start winning signal SS2 whose signal state changes between the off state (high level) and the on state (low level) at the timing shown in FIG. 40I is the latch clock RC2 (from the clock flip-flop). Is taken into the hard latch selector 558B at the timing T11, T13, T15,... At which the output latch clock RC0 is branched), and then the signal at the timing T13, T15 as shown in FIG. A random number latch signal LL2 whose state changes between an off state and an on state is output. Here, the second start winning signal SS2 transmitted from the second start opening switch 22B is turned off when the start winning of the game ball at the second start winning opening formed by the normal variable winning ball apparatus 6B is detected. Changes from ON to ON. The random number latch signal LL2 output from the hard latch selector 558B is supplied to the hard latch random number value register 559B and used to acquire numerical data in the random number sequence RSN output from the maximum value comparison circuit 555. Thus, the hard latch selector 558B generates a random number latch signal LL2 for obtaining numerical data as a random value based on the detection of the start winning of the game ball at the second start winning opening. It is generated separately from the case where the start winning of the game ball is detected.

  Latching clocks RC1 and RC2 whose signal states change with a common cycle by branching latch clocks RC0 generated by clock flip-flops common to each other and branching them to latch clocks RC1 and RC2 Are used to generate a random number latch signal LL1 and a random number latch signal LL2 for obtaining numerical data to be a random number value. As a result, the circuit configuration of the random number circuits 509A and 509B can be simplified, and the manufacturing cost of the pachinko gaming machine 1 can be reduced.

  The hard latch random value register 559A takes in numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 in response to the falling edge of the random number latch signal LL1 input from the hard latch selector 558A to the clock terminal. (Latch) and update the numerical data to be stored data. The hard latch random value register 559B takes in numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 in response to the falling edge of the random number latch signal LL2 input from the hard latch selector 558B to the clock terminal. (Latch) and update the numerical data to be stored data.

  For example, as shown in FIG. 40 (G), when a falling edge is generated in which the random number latch signal LL1 changes from the OFF state to the ON state at timing T11, the maximum value comparison circuit 555 outputs at this timing T11. As shown in FIG. 40H, the numerical data in the random number sequence RSN that has been read is taken into the hard latch random number value register 559A and acquired as numerical data that becomes a random value. Thereby, in the hard latch random number value register 559A, on the basis of the detection of the starting winning of the game ball at the first starting winning opening, the numerical data used as the random number value is used as the starting winning of the gaming ball at the second starting winning opening. It can be acquired and stored separately from when it is detected.

  For example, as shown in FIG. 40 (J), when a falling edge occurs in which the random number latch signal LL2 changes from the OFF state to the ON state at the timing T13, the maximum value comparison circuit 555 at the timing T13. As shown in FIG. 40 (K), the numerical data in the random number sequence RSN output from is taken into the hard latch random number value register 559B and acquired as numerical data that becomes a random value. Accordingly, the hard latch random value register 559B uses the numerical data used as the random number value based on the detection of the start winning of the game ball at the second start winning opening as the start winning of the game ball at the first start winning opening. It can be acquired and stored separately from when it is detected.

  Thus, the hard latch random number value register 559A stores numerical data in the random value RSN in response to the falling edge of the random number latch signal LL1 output from the hard latch selector 558A. The hard latch random number register 559B stores numerical data in the random number sequence RSN in response to the falling edge of the random number latch signal LL2 output from the hard latch selector 558B.

  As described above, in the 16-bit random number circuit 509A, the random number update clock selection circuit 551, the random number generation circuit 553A, the random number sequence change circuit 554A, the maximum value comparison circuit 555, and the like are used for the start winning of the game ball at the first start winning opening. Based on the combination of the hard latch selector 558A and the hard latch random value register 559A configured to acquire numerical data that becomes a random value based on the numerical value data that becomes a random value based on the starting winning of the game ball at the second starting winning opening It may be made common to the combination of the hard latch selector 558B and the hard latch random value register 559B configured to acquire. In this case, the random number update clock RGK supplied to the random number generation circuit 553A and used for updating the numerical data in the count value permutation RCN and the numerical data in the random number sequence RSN is disturbed based on the start winning of the game ball at the first start winning opening. A common random number update clock signal is used for a configuration for acquiring numerical data that is a numerical value and a configuration for acquiring numerical data that is a random value based on the start winning of a game ball at the second start winning opening. Thereby, the circuit configuration in the random number circuit 509A can be simplified, and the manufacturing cost of the pachinko gaming machine 1 can be reduced. Further, when the first start winning signal SS1 is turned on due to the detection of the start winning of the game ball at the first start winning opening, and when the start winning of the game ball at the second start winning opening is detected. Thus, the numerical data in the common random number sequence RSN is stored as a random value when the second start winning signal SS2 is turned on. Thereby, the fairness of the game in the pachinko gaming machine 1 can be ensured.

  In the random number hard latch flag register RHF shown in FIG. 21A, the numerical data fetching and reading operations in the hard latch random number register 559A, and the numeric data fetching and reading operations in the hard latch random number register 559B. In response, the corresponding bit value changes to “0” and “1”. FIG. 41 is a timing chart for explaining changes in the hard latch flag RLHF0 stored in the random number latch flag register RHF.

  As shown in FIG. 41 (A), at the timing T20 when the random number latch signal LL1 and the random number latch signal LL2 fall, the hard latch random number value register 559A and the hard latch random number value register 559B as shown in FIG. In response to the numerical data being captured and stored, the corresponding bit value in the hard latch flag RLHF0 changes from “0” to “1” as shown in FIG. For example, when numerical data is stored in the hard latch random value register 559A in response to the random number latch signal LL1 being turned on (low level) at timing T20, the bit values of the hard latch flag data RL01HF and RL00HF Change from “0” to “1”, the random number latch flag corresponding to the hard latch random number value register 559A is turned on. When numerical data is stored in the hard latch random value register 559B in response to the random number latch signal LL2 being turned on (low level) at timing T20, the bit values of the hard latch flag data RL03HF and RL02HF Change from “0” to “1”, the random number latch flag corresponding to the hard latch random number value register 559B is turned on.

  When the random number latch flag is turned on in this way, storage of new numerical data in the corresponding hard latch random number value register 559A or hard latch random number value register 559B can be restricted. For example, when the bit value [3] in the hard latch selection register RL0LS shown in FIGS. 20A and 20B is “0”, the bit values of the hard latch flag data RL01HF and RL00HF are both “ When the value changes from “0” to “1”, the random number latch flag corresponding to the hard latch random number register 559A is turned on, and storage of new numerical data in the hard latch random number register 559A is restricted. When the bit value [3] of the hard latch selection register RL0LS shown in FIGS. 20A and 20B is “0”, the bit values of the hard latch flag data RL03HF and RL02HF are both “ When the value changes from “0” to “1”, the random number latch flag corresponding to the hard latch random number value register 559B is turned on, and storage of new numerical data in the hard latch random number value register 559B is restricted. Therefore, one or both of the first start winning signal SS1 and the second starting winning signal SS2 are input to one or both of the hard latch random value register 559A and the hard latch random value register 559B in which the corresponding random number latch flag is in the ON state. Even when one or both of the random number latch signal LL1 and the random number latch signal LL2 for taking in the numerical data in response to is input, the new numerical data included in the random number sequence RSN cannot be stored.

  Thereby, after the numerical data is temporarily stored in the hard latch random value register 559A or the hard latch random value register 559B, before the numerical data is read from the CPU 505 or the like, for example, the first start winning signal SS1 or the second Even when the start winning signal SS2 is erroneously turned on due to noise or the like, the numerical data already stored is updated, and it is possible to prevent reading of an inaccurate random number value. Also, the first start prize signal SS1 and the second start prize signal SS2 are intentionally turned on from the outside, or the random number latch signal LL1 and the random number latch signal LL2 are intentionally turned on from the outside. Accordingly, it is possible to prevent an illegal act such as modifying numerical data already stored. On the other hand, when the numerical data once stored in the hard latch random value register 559A or the hard latch random value register 559B is not read from the CPU 505 or the like for a long time, the first start winning signal SS1 or the second start winning prize is subsequently obtained. When the signal SS2 is normally turned on, accurate numerical data corresponding to the passage (entrance) of the game ball at the first start winning opening and the second starting winning opening is stored in the hard latch random number value register 559A and the hard latch disturbance. It cannot be stored in the numerical register 559B.

  Therefore, for example, the CPU 505 of the game control microcomputer 100 executes a predetermined random value register reading process as shown in FIG. 41D when a predetermined random value reading condition is satisfied. Then, reading of the hard latch random number register 559A and the hard latch random number register 559B is performed to turn off the random number latch flag, thereby setting a state in which new numerical data storage is permitted. The random number read condition is that the CPU 505 starts executing the game control in the pachinko gaming machine 1 or the special game when the game ball passes (enters) the first start winning opening and the second starting winning opening. What is necessary is just to include a part or all of the fact that the number of reserved storage has reached a predetermined upper limit. In the operation example shown in FIG. 41, the hard latch flag RLHF0 is turned off as shown in FIG. 41C in response to the completion of the random number value register reading process shown in FIG. 41D at timing T25. Is set.

  As an example, the CPU 505 executes a predetermined security check process or the like when the system reset of the gaming control microcomputer 100 is canceled based on the start of power supply in the pachinko gaming machine 1, and then executes a user program from the ROM 506. The control code indicating (game control game control program for game control) is read and the execution of the game control is started. At this time, the CPU 505 may read the numerical data stored in the hard latch random number register 559A or the hard latch random value register 559B by executing a random number register read process, and set the corresponding random number latch flag to the OFF state. . Note that the CPU 505 may read only the random number value register in which the random number latch flag is on based on the result of checking the bit values of the hard latch flag data RL00HF to RL03HF. Alternatively, each random number latch flag may be turned off by reading numerical data from both the hard latch random value register 559A and the hard latch random value register 559B, regardless of whether the random number latch flag is on.

  When the power of the pachinko gaming machine 1 is turned on, various power supply voltages gradually rise to specified values, such as the power supply voltage VSL and the power supply voltage VCC shown in FIGS. 4B and 4C, for example. During such an increase in the power supply voltage, some of the various circuits such as the built-in circuit of the game control microcomputer 100 may operate normally, while the other components may not operate normally. As an example, when the power supply voltage is unstable, the first start winning signal SS1 and the second starting winning signal SS2 are erroneously turned on. For example, the hard latch random number value register 559A and the hard latch disturbance in the random number circuit 509A. There is a possibility that numerical data is captured and stored in the numerical register 559B, and the corresponding random number latch flag is turned on, which limits the storage of new numerical data. Further, after the execution of the game control by the CPU 505 or the like is started, the random number latch signal LL1 or the random number latch signal LL2 is stored in the hard latch random number value register at a predetermined timing before the switch process of step S91 shown in FIG. 30 is performed. An illegal act of obtaining numerical data indicating a special figure display result determination random number MR1 with the special figure display result as “big hit” and controlling it to the big hit gaming state by inputting to 559A or the hard latch random value register 559B May be made. As described above, when the storage of new numerical data is restricted when the random number latch flag is turned on, the game ball passes (enters) the start winning opening such as the first starting winning opening and the second starting winning opening. It is possible to prevent erroneous numerical data due to noise or the like from being taken in and stored in the hard latch random number value register 559A or the hard latch random number value register 559B after the start winning is generated, while the power supply voltage is If numerical data is fetched and stored in the hard latch random value register 559A or the hard latch random value register 559B due to malfunction or fraud due to instability of the game, even if a start prize is subsequently generated, this start prize is generated. Numeric data already stored before the timing is acquired as a random value and used to determine the special figure display result. There is likely to be.

  Therefore, when the system reset in the gaming control microcomputer 100 is released and the gaming control is started, the random number latch flag may be set to the off state to allow the storage of new numerical data. As a result, for example, numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B erroneously in a state where the power supply voltage is unstable such as when the power is turned on in the pachinko gaming machine 1 is acquired as a random value. Therefore, it can be prevented that the information is used for various decisions in game control. In addition, after the execution of the game control is started, an illegal act of inputting a random number latch signal and controlling it to the big hit game state before the state of the first start port switch 22A or the second start port switch 22B is checked. Can be prevented.

  As another example, an on-state power-off signal is output from the power supply monitoring circuit 303 mounted on the power supply board 10 based on a decrease in the predetermined power supply voltage in the pachinko gaming machine 1, such as the power supply voltage VSL. When the CPU 505 determines in step S51 shown in FIG. 27 that the power-off signal is on, the CPU 505 executes the main-side power-off processing in step S52 to operate the pachinko gaming machine 1 due to a decrease in power supply voltage. Prepare for instability or shutdown. Along with the execution of the main-side power-off process, which is the power supply stop process, the watchdog timer 520 is activated in the process of step S53 to enable the reset operation due to the occurrence of a timeout, and then the infinite loop process is repeatedly executed. Enter standby state. Here, after it is determined that the power-off signal is in the ON state by the process of step S51, before the time-out of the watchdog timer 520 occurs, the random value register read process is executed, thereby executing the hard latch random number value. The numerical data stored in the register 559A or the hard latch random number value register 559B may be read to turn off the corresponding random number latch flag. Thus, it may be determined as one of the random value read conditions that it is determined that the power-off signal is in the ON state after the execution of the user program is started.

  Furthermore, as another example of the random number value reading condition, the number of reserved memories in the special game reaches a predetermined upper limit value when the game ball passes (enters) the first start winning opening and the second starting winning opening. There is a case. Here, for example, after it is determined in step S203 shown in FIG. 32 that the first start port switch 22A is on, the read value of the first hold storage counter is set to a predetermined upper limit value in step S502 shown in FIG. (For example, “4”) or more, if it is determined to be greater than or equal to (for example, “4”), all the entries (for example, entries corresponding to the holding numbers “1” to “4”) have the holding data. Since the stored number of reserved data in the first special figure reservation storage unit has reached the upper limit storage number, new reserved data cannot be stored in the first special figure reservation storage unit. Further, for example, after it is determined in step S207 shown in FIG. 32 that the second start port switch 22B is in the ON state, the read value of the first hold storage counter is greater than or equal to a predetermined upper limit value in step S502 shown in FIG. Is determined, the pending data is stored in all entries in the second special figure reservation storage unit, and the number of stored pending data in the second special figure reservation storage unit reaches the upper limit storage number. For this reason, new hold data cannot be stored in the second special figure hold storage unit. In such a case, in general, the start condition of the special game based on the game ball passing (entering) through the first start winning opening and the second starting winning opening is not established, and the prize ball is paid out. Only done.

  For this reason, it may be considered not to read out numerical data that is a random value generated by the random number circuit 509A. However, in the random number circuit 509A, the hard latch random number value register 559A is responsive to the first start winning signal SS1 and the second starting winning signal SS2 being turned on regardless of the number of stored data. In addition, numerical data serving as a random value is captured and stored in the hard latch random value register 559B, and the corresponding random number latch flag is turned on. Then, when the game ball passes (enters) through the first start winning opening and the second starting winning opening next time, even if the first start winning signal SS1 and the second start winning signal SS2 are turned on and input, Since storage of new numerical data in the hard latch random value register 559A and the hard latch random value register 559B is restricted, it may not be possible to acquire an accurate random value corresponding to the occurrence of the start prize.

  On the other hand, when the CPU 505 of the game control microcomputer 100 determines in step S502 shown in FIG. 33 that the read value of the hold storage counter is equal to or greater than the predetermined upper limit value (step S502; Yes), step The processing of S512 is executed, and the numerical data stored in the hard latch random value register 559A and the hard latch random value register 559B is read to turn off the corresponding random number latch flag, and then the process at the time of passing through the start port is ended. . In the process of step S512, the hard latch random number value register 559A is read when the first start port winning table is set in step S202 of FIG. 32, while the second start port is read in step S206 of FIG. When the winning table is set, the hard latch random value register 559B is read. Thus, for example, when a plurality of display devices that variably display special symbols, such as the first special symbol display device 4A and the second special symbol display device 4B, are provided, the reserved memory number of the special symbol game reaches the upper limit value. When a game ball that passes (enters) a start winning opening associated with a special symbol is detected, numerical data is read from the random value register associated with the starting winning opening and new numerical data is stored. On the other hand, the numerical data is not read from the random value register not associated with the starting winning opening. As a result, when a game ball passes (enters) one of a plurality of start winning openings, the operation of updating or obtaining numerical data that becomes a random value corresponding to another starting winning opening is affected. Can not be.

  FIG. 42 is a timing chart illustrating an operation example in the case where the power supply voltage VSL decreases during execution of game control. First, for example, based on the start of power supply to the pachinko gaming machine 1, the timing T30 before the timing T31 when the power supply voltage VSL shown in FIG. 42A reaches the predetermined value VSL1 (+22 V as an example) Thus, power supply voltage VCC shown in FIG. 42B reaches predetermined value VCC1 (+4.5 V as an example). At this timing T30, the reset signal shown in FIG. 42E changes from the on state to the off state. Subsequently, when the power supply voltage VSL reaches the predetermined value VSL1 at timing T31, the power-off signal shown in FIG. 42C is changed from the on state to the off state. Thereafter, at timing T32, power supply voltage VSL shown in FIG. 42A is assumed to be lower than predetermined value VSL1. At this time, based on the determination that the power-off signal shown in FIG. 42C is in the ON state (low level) (step S51 in FIG. 27; Yes), the main-side power-off process in step S52 is performed. Along with the execution, the watchdog timer 520 is activated by the process of step S53. Thus, the reset operation due to occurrence of timeout is validated.

After the process of step S53 shown in FIG. 27 is executed, the infinite loop process is repeatedly executed. Therefore, for example, at the timing T33, even when the power supply voltage VSL shown in FIG. 42A returns to the predetermined value VSL1, the game control process (game control timer interrupt process, etc.) is not executed, and it waits until a timeout occurs. It becomes a state. Thereafter, when a time-out occurs due to the elapse of the longest time 2 ²⁵ × T _SCLK × 15 that can be set as the time-out time to be monitored by the watchdog timer 520, the watchdog timer 520 outputs a time-out signal. As a result, a reset operation due to occurrence of a timeout is performed. At this time, the execution of the game control is started from the head of the control code indicating the user program (game control processing program for game control) stored in the ROM 506 based on, for example, the specified contents in the predetermined vector table. The game control main process as shown in FIGS. 26 and 27 is executed from the beginning. As a result, when the power supply voltage supplied to the pachinko gaming machine 1 drops (instantaneous power failure) in a short period of time, it is possible to appropriately recover from the instantaneous power supply interruption by performing a reset operation due to the occurrence of a timeout. it can. Further, since the watchdog timer 520 is stopped until the process of step S53 shown in FIG. 27 is executed or when the process of step S53 is not executed, the count value measured by the watchdog timer 520 is periodically set. There is no need to clear (initialize) and restart, and the control burden for controlling the progress of the game can be reduced.

  FIG. 43 is a timing chart showing an operation example when the stability of the power supply voltage cannot be confirmed when the pachinko gaming machine 1 is turned on. In the operation example shown in FIG. 43, similarly to the operation example shown in FIG. 42, the power supply voltage VCC shown in FIG. 43B reaches the predetermined value VCC1 at the timing T30. Accordingly, the reset signal illustrated in FIG. 43E is changed from the on state to the off state. On the other hand, in the operation example shown in FIG. 43, since the power supply voltage VSL does not reach the predetermined value VSL1 at the timing T31, it is determined that the power-off signal shown in FIG. 43C is in the on state (low level). (Step S25 in FIG. 26; Yes). In accordance with this determination result, the watchdog timer 520 is activated by the process of step S26. Thus, the reset operation due to occurrence of timeout is validated.

After the process of step S26 shown in FIG. 26 is executed, the infinite loop process is repeatedly executed. Therefore, for example, at timing T35, even when the power supply voltage VSL shown in FIG. 43A reaches the predetermined value VSL1, the game control process (game control timer interrupt process, etc.) is not executed and waits until a timeout occurs. It becomes a state. Thereafter, when a time-out occurs due to the elapse of the longest time 2 ²⁵ × T _SCLK × 15 that can be set as the time-out time to be monitored by the watchdog timer 520, the watchdog timer 520 outputs a time-out signal. As a result, a reset operation due to occurrence of a timeout is performed. At this time, the execution of the game control is started from the head of the control code indicating the user program (game control processing program for game control) stored in the ROM 506 based on, for example, the specified contents in the predetermined vector table. The game control main process as shown in FIGS. 26 and 27 is executed from the beginning. As a result, when the power supply voltage supplied when the power to the pachinko gaming machine 1 is turned on falls in a short period of time (instantaneous power interruption), the power supply voltage is instantaneously stopped by performing a reset operation due to the occurrence of a timeout. Can be recovered properly. In addition, since the watchdog timer 520 is stopped until the process of step S26 shown in FIG. 26 is executed or when the process of step S26 is not executed, the count value measured by the watchdog timer 520 is periodically set. There is no need to clear (initialize) and restart, and the control burden for controlling the progress of the game can be reduced.

  The processes in steps S25 and S26 shown in FIG. 26 are executed before the access to the RAM 507 is permitted by the process in step S32. As a result, when the power supply voltage supplied when the power of the pachinko gaming machine 1 is turned on is unstable such as a drop (instantaneous power interruption) in a short period of time, the stored contents in the storage area for backup provided in the RAM 507 are erroneous The reset operation due to the occurrence of a timeout can be validated and the power supply can be properly recovered from the momentary power interruption while preventing the change (damage).

  The bit number [5-4] of the reset setting KRES shown in FIG. 8B is set so that the time-out time that is the monitoring time in the watchdog timer 520 is the longest time that can be set among a plurality of predetermined types. And a bit value in bit number [3-0] is set in advance. Thus, the time-out time in the watchdog timer 520 is set to be longer than, for example, the time when the power supply voltage VSL is lower than the voltage value capable of generating the power supply voltage VCC after the power cut-off signal is turned on due to the stop of power supply. Just do it. Since the watchdog timer 520 operates using the power supply voltage VCC as a drive voltage, the time-out time is set to be longer than the operable time of the watchdog timer 520 when power supply is stopped due to power supply switch disconnection or the like. Therefore, when the power supply is stopped due to the power switch of the pachinko gaming machine 1 being cut off, etc., if the power supply voltage decreases as it is and the supply is stopped, before the reset operation is performed before a timeout occurs, The watchdog timer 520 and other circuit components will not operate. Therefore, when the power supply is properly stopped by cutting off the power switch or the like, the reset operation can be prevented from being erroneously performed, and the power supply can be appropriately recovered from the instantaneous power supply interruption.

  When the game ball passes (enters) through the first start winning port or the second start winning port, the CPU 505 determines whether the game ball has passed (entered) in step S204 or step S208 shown in FIG. Execute common start-up passage processing. Then, in a common processing routine, such as the processing of step S501 to step S512 shown in FIG. 33, regardless of the start winning opening through which the game ball has passed, by executing the processing of step S505 and step S506 in particular, the random number circuit Among the hard latch random value register 559A and the hard latch random value register 559B provided in 509A, numerical data that becomes a random value is obtained from the random value register corresponding to the first start winning opening or the second starting winning opening through which the game ball has passed. read out. In the pachinko gaming machine 1 provided with a plurality of start winning ports such as the first starting winning port and the second starting winning port, the random number value can be read out by making it possible to read the numerical data as a random value by such a common processing routine. Therefore, it is possible to prevent an excessive increase in the amount of programs for acquiring numerical data.

  In the main board 11, the security check program 506A stored in the ROM 506 or the like is stored in the ROM 506 or the like when the initial power is supplied from the power board 10 (when power is turned on without a backup power source) or when the CPU 505 is restarted after a system reset occurs. Is read out and executed, the gaming control microcomputer 100 enters the security mode. At this time, for example, a security check process as shown in FIG. 25 is executed as a process corresponding to the security check program 506A. Here, the security time during which the game control microcomputer 100 is in the security mode is different from a certain fixed time according to the setting data stored in advance in the security time setting KSES stored in the program management area of the ROM 506. A time component can be included.

  For example, according to the bit value [5-0] of the security time setting KSES, any one of a plurality of fixed extension times that can be selected in advance in addition to the fixed time by setting as shown in FIG. 8B. Can be set as a time component included in the security time (step S2 in FIG. 25). If the bit value in the bit number [7-6] of the security time setting KSES is a value other than “00” (step S4; No), the short mode, middle mode, long mode as shown in FIG. Corresponding to one of the modes, a variable extension time that changes in a predetermined time range every time the initial setting process is executed based on system reset or power-on can be set as a time component included in the security time. (Step S5).

  Until the security time thus set elapses (step S11; No), the execution of the game control main process by the user program stored in the ROM 506 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuits 509A and 509B may be prevented from being started during the period in which the game control microcomputer 100 is in the security mode. As a result, it becomes difficult to specify the operation start timing of the random number circuits 509A and 509B and the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, etc. By aiming based on the analysis result or by inputting a fraud signal at a predetermined timing by connecting a so-called “hanging board”, it is possible to reliably prevent acts such as illegally generating a big hit gaming state.

  As an example, the bit value in the bit number [5-0] of the security time setting KSES is set to a different value for each model of the pachinko gaming machine 1. In this case, the fixed extension time set in step S2 shown in FIG. 25 can be made different for each model of the pachinko gaming machine 1, and the random number circuits 509A, 509B It becomes difficult to specify the operation start timing. Further, by setting the bit value in the bit number [7-6] of the security time setting KSES to “01”, “10”, or “11”, the variable extension time set in step S5 is Different for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuits 509A and 509B from the operation start timing of the pachinko gaming machine 1.

  For example, on the basis of the input of a predetermined signal such as the first start winning signal SS1 or the second starting winning signal SS2 being turned on, a procedure predetermined by the random number generation circuit 553A, the random number sequence changing circuit 554A, etc. by the random number circuit 509A The hard latch flag data RL00HF to RL03HF stored in the random number hard latch flag register RHF when the numerical data included in the random number sequence RSN updated in step S5 is stored in the hard latch random number register 559A or the hard latch random number register 559B. Is changed from “0” to “1”. When the bit value [3] of the corresponding hard latch selection register RL0LS is “0”, the random number corresponding to the hard latch random value register 559A or the hard latch random number value register 559B that stores numerical data. When the latch flag is turned on, storage of new numerical data is restricted. On the other hand, for example, when the CPU 505 executes the processing of step S506 shown in FIG. 33, numerical data that becomes a random value is read from the hard latch random value register 559A or the hard latch random value register 559B at the read timing of the random value. When issued, the random number latch flag corresponding to the hard latch random number value register 559A or the hard latch random number value register 559B from which the numerical value data has been read is turned off, and storage of new numerical data is permitted. As a result, the numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B based on the input of a predetermined signal is not altered by noise or the like before being read by the CPU 505 or the like. Numerical data that becomes a random value can be acquired.

  When the execution of the game control is started by the CPU 505 of the game control microcomputer 100 or the like, each random number latch flag is turned off by reading the numerical data from the hard latch random number value register 559A or the hard latch random number value register 559B. Can be set. Accordingly, when power supply is resumed after the power supply in the gaming machine such as the pachinko gaming machine 1 is stopped or the power supply voltage is unstable such as when the power is turned on, the hard latch random number register 559A or the hardware It is possible to prevent the numerical data stored in the latch random value register 559B from being acquired as a random value.

  When a game ball that has passed (entered) the first start winning opening is detected and it is determined in step S203 shown in FIG. 32 that the first start opening switch 22A is on, in step S204, the second start winning is also received. When a game ball that has passed (entered) through the mouth is detected and it is determined in step S207 shown in FIG. 32 that the second start port switch 22B is turned on, in step S208, a start prize that has passed (entered) the game ball. Regardless of the mouth, a common start-up passage process is executed. Then, in a common processing routine, such as the processing of step S505 and step S506 shown in FIG. 33, regardless of the start winning opening through which the game ball has passed, the hard latch random number value register 559A or the hard latch random number value register provided in the random number circuit 509A Among the 559B, numerical data serving as a random number value is read out from the random value register corresponding to the first start winning opening or the second starting winning opening through which the game ball has passed. Thereby, in the pachinko gaming machine 1 provided with a plurality of start winning ports such as the first starting winning port and the second starting winning port, for example, an excessive increase in the program amount can be prevented.

  In response to the determination that the read value of the hold storage counter is equal to or greater than the upper limit value in step S502 shown in FIG. 33, the first special figure hold storage unit and the second special figure hold at the read timing of the random number value. When the number of reserved data stored in the storage unit has reached the upper limit storage number, in the process of step S512, the hard latch random value register 559A corresponding to the first start winning port or the second starting winning port through which the game ball has passed or By reading the numerical data to be a random number value from the hard latch random value register 559B, the corresponding random number latch flag is set to the OFF state. As a result, after the number of reserved data stored in the first special figure reservation storage unit or the second special figure reservation storage unit reaches the upper limit storage number, for example, the random number value is read out after the number is less than the upper limit storage number. Sometimes, an accurate random value based on the input of a predetermined signal such as the first start prize signal SS1 or the second start prize signal SS2 can be acquired.

  When the bit value in the bit number [7-6] of the security time setting KSES shown in FIGS. 7A and 10 is set to a value other than “00”, an initial setting process is executed based on a system reset or power-on. A variable extension time that changes in a predetermined time range every time is set as a time component included in the security time. Further, according to the bit value in the bit number [5-0] of the security time setting KSES shown in FIG. 7 (A) or FIG. Set as a time component included in the security time. As a result, it becomes difficult to specify the operation start timing of the random number circuits 509A and 509B and the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, etc. By aiming based on the analysis result or by inputting a fraud signal at a predetermined timing by connecting a so-called “hanging board”, it is possible to reliably prevent acts such as illegally generating a big hit gaming state.

  For example, in the 16-bit random number circuit 509A, the random number sequence change circuit 554A changes the count value permutation RCN output from the random number generation circuit 553A based on a predetermined random number change rule, whereby numerical data is determined in a predetermined procedure. Are updated cyclically from the initial update value to a predetermined final update value. Then, when the bit value in the bit number [6] of the 16-bit random number initialization third KRL3 shown in FIGS. 7A and 9C is “1”, the random number value generated by the random number circuit 509A The start value of the numerical data is changed at every system reset. For the 8-bit random number circuit 509B, the start value of the random number value may be changed in the same manner. As a result, even if the operation start timing of the random number circuits 509A and 509B can be specified, it becomes difficult to specify the numerical data read from the hard latch random number value register included in the random number circuits 509A and 509B. Aiming based on the analysis result of the control processing program or the input of an illegal signal due to the connection of a so-called “hanging board” can be surely prevented.

  More specifically, the count value serving as the initial value determination data is updated by the free-run counter 509C or the like separately from the operation of the CPU 505 of the game control microcomputer 100. Based on the setting by the start value setting circuit 553C of the random number circuits 509A and 509B, the start value of the numerical data that becomes the random value is determined using the count value of the free-run counter 509C. This makes it difficult to specify numerical data that is a random value from the operation mode of the CPU 505 of the game control microcomputer 100, and is based on aiming based on the analysis result of the game control processing program or connection of a so-called “hanging board”. It is possible to reliably prevent an illegal signal from being input.

  In the external bus interface 501 provided in the game control microcomputer 100, the internal resource access control circuit 501A allows external data other than the internal circuit such as the CPU 505 to externally read the internal data of the game control microcomputer 100 such as data stored in the ROM 506. Limited. Thereby, it is possible to prevent a game control processing program such as a game control user program stored in the ROM 506 from being read from the outside of the game control microcomputer 100 and provided for analysis or the like. Further, it is possible to reliably prevent aiming based on the analysis result of the game control processing program and input of an illegal signal due to connection of a so-called “hanging board”.

  The random number circuits 509A and 509B built in or externally attached to the game control microcomputer 100 are provided with frequency monitoring circuits, and the input state of the random number clock RCK supplied from the random number clock generation circuit 112 is compared with the internal system clock SCLK. Thus, when a frequency abnormality in the random number clock RCK is detected, the bit value at a predetermined bit number in the internal information register CIF may be set to “1”. Then, the CPU 505 determines that the number of times that the bit value at the predetermined bit number in the internal information register CIF is continuously “1” in the game control main process has reached a predetermined clock abnormality determination value, for example. May be determined that an abnormality has occurred in the operating state of the random number circuits 509A and 509B. Thereby, it is possible to reliably prevent an illegal act by inputting an illegal signal as the random number clock RCK.

  The CPU 505 of the game control microcomputer 100 executes a predetermined random value register read process when the system reset of the game control microcomputer 100 is released based on the start of power supply in the pachinko gaming machine 1 or the like. Thus, the numerical data stored in the hard latch random value register 559A and the hard latch random value register 559B may be read and the corresponding random number latch flag may be turned off. As a result, it is possible to prevent the numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B from being erroneously acquired as a random value when the power supply voltage is unstable, such as when the power is turned on. .

  Further, in response to the determination that the power cut-off signal is in the on state in step S51 shown in FIG. Until 100 is in an operation stop state, the process of step S25 and step S25B shown in FIG. 28A may be executed to repeatedly determine the input state of the power-off signal. Then, when it is determined in step S25 that the power-off signal has been turned off and has not been input, a predetermined random number value is set before game control is started from the beginning of the control code stored in the ROM 506. A register read process may be executed to turn off the random number latch flag that is on. As a result, for example, numerical data stored in the hard latch random value register 559A or the hard latch random value register 559B erroneously in a state where the power supply voltage is unstable such as when the predetermined power supply voltage such as the power supply voltage VSL is lowered is obtained as a random value. Can be prevented.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not have to include all the technical features shown in the above embodiment, and the part described in the above embodiment so as to solve at least one problem in the prior art. It may be provided with the following structure. As a specific example, in the above embodiment, the watchdog timer 520 is activated by the process of step S26 shown in FIG. 26 to enable the reset operation due to the occurrence of timeout, and the process of step S53 shown in FIG. It has been described that the watchdog timer 520 is activated to enable the reset operation due to the occurrence of a timeout. On the other hand, the watchdog timer 520 is activated by one of the processes in step S26 and step S53 to enable the reset operation due to the occurrence of a timeout, but the other process is not executed. It may be.

  In the above embodiment, the pachinko gaming machine 1 provided with the first special symbol display device 4A and the second special symbol display device 4B has been described, but only one special symbol display device may be provided. . In this case, for example, the combination of the hard latch selector 558B and the hard latch random number value register 559B included in the random number circuit 509A shown in FIG.

  In the above embodiment, in the 16-bit random number circuit 509A, the random number update clock selection circuit 551, the random number generation circuit 553A, the random number sequence change circuit 554A, the maximum value comparison circuit 555, and the like start the game ball at the first start winning opening. A combination of a hard latch selector 558A and a hard latch random value register 559A configured to acquire numerical data that becomes a random value based on a winning, and a numerical value that becomes a random value based on the starting winning of the game ball at the second starting winning opening The description has been given assuming that the combination of the hard latch selector 558B and the hard latch random value register 559B configured to acquire data is shared. However, the present invention is not limited to this, and in the random number sequence RSN depending on whether the game ball starts winning at the first start winning opening or the game ball starting winning at the second start winning opening. You may comprise so that the numerical data used as a random value may be acquired from numerical data. As an example, in the 16-bit random number circuit 509A, a 16-bit hard latch random value register 559A is provided corresponding to the channel ch0, and numerical data that becomes a random value based on the starting winning of the game ball at the first starting winning opening is obtained. get. On the other hand, a 16-bit hard latch random value register 559B is provided corresponding to the channel ch1 whose random value is updated independently of the channel ch0, and the random value is determined based on the starting winning of the game ball at the second starting winning opening. Numerical data may be acquired.

  Further, the first start winning opening formed by the normal winning ball apparatus 6A and the second starting winning opening formed by the ordinary variable winning ball apparatus 6B are not limited to those provided as a plurality of start areas, for example, three A plurality of starting areas as described above may be provided. In this case, a start condition for executing a special game using different special symbols may be established based on the detection of a start winning game ball in each start area. The random number circuit 509A is provided with a plurality of hard latch random number registers such as three or more corresponding to the number of start areas, and a random number latch flag corresponding to each random number register may be provided. . Or, for example, a special game using the same special symbol is executed based on the detection of a start winning game ball in a part (at least two) of the starting areas of three or more starting areas. The starting condition for doing so may be satisfied. In addition, even if a start winning of a game ball is detected in any start area among a plurality of start areas, a special game using a common (or one set) special symbol is executed. The start condition may be satisfied. In this case, the start condition for starting the special game may be established in the same order as the order in which the start winnings of the game balls are detected in the plurality of start areas. Alternatively, a priority is given to a plurality of start areas, and a start condition for starting a special game based on detection of a start winning game ball in a start area having a high priority is set as a start area having a low priority. The starting condition based on the detection of the start winning of the game ball may be established with priority.

  When a reset operation is performed due to the occurrence of a timeout in the watchdog timer 520, numerical data is read from the hard latch random value register 559A or the hard latch random value register 559B, and each random number latch flag is set to an OFF state. These processes may be executed. As a result, for example, in the pachinko gaming machine 1, when the power supply is momentarily stopped, the numerical data erroneously stored in the hard latch random value register 559A or the hard latch random value register 559B with the power supply voltage being unstable becomes the random value. Can be prevented from being acquired.

  The fixed extension time set in step S2 of FIG. 25 may be determined as one of a plurality of fixed extension times for each system reset, for example, by setting in a user program stored in the ROM 506. In this case, the fixed extension time set in step S2 is defined to be longer than the longest variable extension time that can be set in step S5. Then, after a rough extension time is determined in step S2, a detailed extension time may be determined in step S5. As a result, the security time for entering the security mode when the power of the pachinko gaming machine 1 is turned on or when the system is reset can be greatly changed every time the system is reset, and the random number circuits 509A and 509B from the operation start timing of the pachinko gaming machine 1. It becomes more difficult to specify the operation start timing and numerical data to be updated.

  The fixed extension time added to the fixed time may be determined using an ID number assigned to each chip constituting the game control microcomputer 100. As an example, an extension time corresponding to the calculated value is executed by executing a part or all of an operation for performing a predetermined scramble process on the ID number and an operation such as addition / subtraction / multiplication / division using the ID number. May be set. In this case, the extension time may be randomly determined for each system reset, for example, by changing an arithmetic expression used for determining the extension time for each system reset. Furthermore, the count value of the free run counter, the ID number, and the like, for example, the arithmetic expression for determining the extension time using the ID number is determined corresponding to the count value of the free run counter stored at the time of system reset. The extended time may be determined randomly at each system reset by using a combination of the above. In addition, when changing the start value of the random number generated by the random number circuits 509A and 509B at each system reset, the random number start can be started by using a combination of the count value of the free-run counter and the ID number. The value may be determined.

  The clock signal supplied to the CPU 505 of the gaming control microcomputer 100 and the clock signal supplied to the random number circuits 509A and 509B are generated using an oscillation signal generated by one oscillator included in the common clock generation circuit. It may be generated. In this case, for example, a frequency divider for generating the random number clock RCK and the control clock CCLK is provided so that the latch clock and the control clock CCLK or the internal system clock SCLK are less likely to be synchronized. What is necessary is just to set the frequency division ratio in each frequency divider. A part or all of the control clock generation circuit 111 and the random number clock generation circuit 112 may be provided inside the game control microcomputer 100 or provided outside the game control microcomputer 100. May be.

  The oscillation signal that becomes the random number update clock RGK or the latching clock may be generated outside the random number circuits 509A and 509B such as the random number clock generation circuit 112, for example. Alternatively, a circuit for generating the random number update clock RGK and a circuit for generating the latch clock RC0 may be separately provided in the random number circuits 509A and 509B. As an example, a random number update clock RGK is generated by a flip-flop similar to the clock flip-flop, while an inversion circuit for inverting the signal state of the random number update clock RGK is provided, and a signal output from the inversion circuit is used for latching It may be used as a clock.

  When restricting external reading of the ROM 506 or the like, for example, the connection terminal for externally reading out the data stored in the ROM 506 in the game control microcomputer 100 cannot be connected to the external device in the provider of the pachinko gaming machine 1. It may be sealed.

  In the above embodiment, as the variation pattern setting process of step S141 shown in FIG. 31, regardless of which of the first start condition and the second start condition is satisfied, the process as shown in the flowchart of FIG. Was described as being executed. However, the present invention is not limited to this, and when the first start condition is satisfied and when the second start condition is satisfied, a process different from each other is executed, and the variation pattern type is selected from a plurality of types. It is also possible to determine whether or not one of a plurality of types of variation patterns. In this case, the process for determining the variation pattern type and the process for determining the variation pattern are varied depending on which of the first start condition and the second start condition is satisfied, while the variation pattern type The numerical data indicating the random number value MR3 for determination and the numerical data indicating the random value MR4 for determining the variation pattern are common numerical data regardless of which of the first start condition and the second start condition is satisfied. May be used.

  Further, as the variation pattern type determination table, a table in which the allocation of the determination value to each variation pattern type is made different depending on which of the first start condition and the second start condition is satisfied may be prepared in advance. Then, in the variation pattern setting process executed in response to the establishment of the first start condition, a variation pattern type determination table corresponding to the establishment of the first start condition is selected as a use table, and a random value for determining the variation pattern type Based on MR3, the variation pattern type is determined as one of a plurality of types. On the other hand, in the variation pattern setting process executed in response to the establishment of the second start condition, a variation pattern type determination table that is different from the case where the first start condition is established according to the establishment of the second start condition. It may be selected as a usage table and the variation pattern type may be determined as one of a plurality of types based on the random value MR3 for determining the variation pattern type common to the case where the first start condition is satisfied.

  Further, regarding the determination process for determining whether or not the variable display state of the decorative symbols is to be the reach state, different processes are executed when the first start condition is satisfied and when the second start condition is satisfied. It may be. In this case, the process for determining whether or not to reach the reach state is different depending on which of the first start condition and the second start condition is satisfied, while the numerical data indicating the random number value for reach determination is as follows: Regardless of which of the first start condition and the second start condition is satisfied, common numerical data may be used.

  In the above-described embodiment, the small hit game state is controlled based on the fact that the variable display result is “small hit”, and the game state is not changed after the small hit game state ends. On the other hand, when the variable display result is “big hit”, it is controlled to the two round big hit state based on the fact that the big hit type becomes “surprise”, and after the two round big hit state is finished, it is controlled to the positive change state. Explained as being. However, the present invention is not limited to this, and instead of or in addition to the case where the big hit type is “accurate” or the variable display result is “small hit”, A case of “suddenly normal” may be provided. As an example, “suddenly short time” and “suddenly normal” are included in the jackpot type when the variable display result is “big jackpot”. In this case, the jackpot type determination table includes table data that assigns the random value MR2 for determining the jackpot type to the jackpot type of “suddenly short time” or “suddenly normal” according to the variable special figure designation buffer value. What is necessary is just to be comprised. When the variable display result is “big hit” and the big hit type is “suddenly short”, the two round big hit state is controlled in the same way as the big hit type is “surprise”, and the two round big hit state ends. After that, unlike the case where the big hit type is “accuracy”, it is controlled to the short time state. On the other hand, when the variable display result is “big hit”, when the big hit type is “suddenly normal”, the two round big hit state is controlled in the same way as when the big hit type is “surprise”, and the two round big hit state ends. After that, unlike the case where the jackpot type is “surprise”, the normal state is controlled. Thereby, a player's expectation with respect to the gaming state controlled after the end of the two round big hit state can be enhanced, and the gaming interest can be improved.

  When such “sudden shortening” and “sudden normal” are provided, a variation pattern type and variation pattern different from those other than “sudden shortening” and “sudden normal” may be determined. As a result, although the big hit type is “suddenly short” or “suddenly normal”, the same effect operation as in the case of being controlled to the 15 round big hit state is performed despite being controlled to the 2 round big hit state. It can prevent the player from feeling distrust. In addition, when the big hit type is "Suddenly short" or "Suddenly normal", when the variable display result is "Small hit", or when the big hit type is "Sudden", the common variation pattern type It may be possible to make a decision. As a result, when determining the fluctuation pattern, the big hit type is “Suddenly short” or “Suddenly normal”, or the variable display result is “Small hit” or the big hit type is “Abrupt”. Regardless of whether this is the case, a common variation pattern determination table can be used, and the data capacity can be reduced.

  In the above-described embodiment, it has been described that the game state such as the probability change state or the time-short state can be controlled after the big hit gaming state based on the variable display result being “big hit”. In the probability variation state and the short-time state, it is described that the control that is advantageous to the player is performed by increasing the possibility of the game ball entering the second start winning opening and easily establishing the second start condition. . However, the present invention is not limited to this. For example, in the probability variation state, the probability variation control is continuously performed, and the advantageous release control that increases the possibility that the game ball enters the second start winning opening is performed. The high base state and the high probability low base state in which the probability variation control is performed but the advantageous release control is not performed may be included. Also, in the short-time state, a low-accuracy base state where the special figure fluctuation time is shortened and advantageous opening control is performed, and a low-accuracy low-base state where the special figure fluctuation time is shortened but advantageous opening control is not performed. May be included. As an example, depending on whether the big hit type is “probability change” or “surprise accuracy”, after the big hit gaming state is finished, it is controlled to either the high probability high base state or the high probability low base state. May be. As another example, depending on whether the big hit type is “probability change” or “surprise accuracy”, the ratio of being controlled to either the high probability high base state or the high probability low base state after the big hit gaming state is ended , They may be different from each other.

  When the big hit type is “Crush Probability”, when determining the variation pattern type to be one of multiple types, whether to control to the high probability high base state or the high probability low base state after the big hit gaming state ends Accordingly, different variation pattern types may be determined. As an example, when the big hit type is determined to be “surprise” in step S236 shown in FIG. 34, it is determined whether to control to the high probability high base state or the high probability low base state after the big hit gaming state is finished. A determination process is performed to At this time, if it is determined to control to the high accuracy low base state, the common variation pattern type is determined when the big hit type is “surprise” and the variable display result is “small hit”. . On the other hand, when it is determined to control to the high-accuracy and high-base state, it is sufficient to determine the dedicated variation pattern type only when the big hit type is “surprise”. As a result, when the big hit type is “surprise” and the high probability low base state is reached after the big hit gaming state is finished, the variable display result is displayed as an effect operation during variable display of the decorative pattern or an effect operation in the two round big hit state. After the production operation common to the case of “small hit” is performed, the highly accurate and low base state can be obtained. On the other hand, when the big hit type is “surprising” and the high hitting high base state is reached after the big hit gaming state is finished, the big hit type is “accurate” as a directing operation during variable display of a decorative symbol or a two round big hit state. After the dedicated performance operation is performed only in the case of “

  In the embodiment described above, the “left”, “middle”, and “right” decorative symbol display areas 5L, 5C, and 5R are provided in the display area of the image display device 5, and the decorative symbol display areas 5L, 5C, and 5R are provided. In the above description, it is assumed that one decorative symbol is stopped and displayed so that the final decorative symbol that is the final stop symbol is stopped and displayed on one predetermined effective line. However, the present invention is not limited to this. For example, in the “left”, “middle”, and “right” decorative symbol display areas 5L, 5C, and 5R, three locations of “upper”, “middle”, and “lower” are provided. It is also possible that the decorative symbols can be stopped and displayed, and the finalized decorative symbols that will be the final stopped symbols are stopped and displayed on five or eight active lines.

  In addition, the device configuration of the pachinko gaming machine 1, the data configuration, the processing shown in the flowchart, the various display operations including the display operation of the display image in the display area of the image display device 5, etc. depart from the spirit of the present invention. Any change or modification can be made without departing from the scope. In addition, the gaming machine of the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of a winning ball, but responds to detection of a winning ball by enclosing the gaming ball. It can also be applied to enclosed game machines that give points.

  In the above embodiment, as an example of the gaming machine, the description has been given using the pachinko gaming machine 1 having a function of variably displaying special symbols and decorative symbols and a function of displaying various effect images. However, at least a part of the configuration and functions of the pachinko gaming machine 1 in the above embodiment can be applied to other gaming machines such as a slot machine. In this case, for example, a detection signal from a start lever switch provided in the slot machine is input to an input port PI0 provided in the PIP 510 illustrated in FIG. The start lever switch outputs a detection signal that is turned on when an operation on the start lever for starting a game is detected by rotating a plurality of reels. In the 16-bit random number circuit 509A, for example, the combination of the hard latch selector 558A and the hard latch random number value register 559A shown in FIG. 15 is used, and numerical data in the random number sequence RSN output from the maximum value comparison circuit 555 is used as a random value. On the other hand, the combination of the hard latch selector 558B and the hard latch random number value register 559B may be set to non-use while being configured to be obtainable.

  Inside the casing of the slot machine, there is provided a variable display device in which a plurality of (for example, three) reels having a plurality of kinds of symbols arranged on the outer periphery are arranged in parallel in the horizontal direction. The front door of the slot machine is provided with an image display device having a display function similar to that of the image display device 5 in the above embodiment. On the outer periphery of each reel, a plurality of types of symbols that can be distinguished from each other, such as “red 7”, “white 7”, “BAR”, “JAC”, “watermelon”, “cherry”, and “bell”, are predetermined. It is drawn in the order. The symbols drawn on the outer peripheral portion of each reel are displayed on the upper, middle, and lower three stages on the variable display device. Each reel rotates in response to a predetermined operation (for example, a pressing operation) on the start lever, so that the design of each reel is displayed while being continuously changed. In this way, a plurality of symbols serving as a plurality of types of identification information are variably displayed.

  When the rotation of each reel is stopped, the player operates a plurality of stop switches installed corresponding to each reel. Note that if the stop switch is not operated even after a predetermined time has elapsed after the rotation of the reel is started, the rotation of the reel may be automatically stopped.

  At a predetermined position of the front door in the slot machine, for example, an insertion slot into which a game medium such as a medal can be inserted, a BET switch for setting (BET) a game medium as one unit (for example, one medal) as a bet number, 1 MAXBET switch for setting the maximum number of bets that can be bet on a game (for example, three medals), stored as credit (number of game media stored as player-owned game value) A settlement switch for settlement of game media and game media used for setting the number of bets is provided.

  When playing a game in a slot machine, first, a game medium is inserted from an insertion slot, or a bet number is set using credits. When using credits, the BET switch or MAXBET switch is operated. When the number of bets is set in this way, one of a plurality of pay lines corresponding to the number of bets becomes valid, the start lever operation is valid, that is, the game can be executed, and the variable display The execution condition is met. Note that when a re-gamer winning such as replay occurs in the previous game, the next game can be executed continuously, and the variable display execution condition is satisfied. When the start lever is operated in such a state that the game can be executed, each reel rotates corresponding to the fact that the variable display start condition is satisfied, and the symbols continuously vary. While the symbols vary due to the rotation of each reel, various effect operations are executed by the display operation of the effect image in the image display device, the sound output operation from the speaker, the lighting operation of the game effect lamp, and the like. For example, in the image display device, the same symbol as the symbol drawn on the outer peripheral portion of each reel, or the symbol associated with the symbol that is different from the symbol of each reel, is variably displayed as effect identification information. Just do it. Further, even after the change of the symbols is ended, various effect operations such as an effect operation for notifying the occurrence of a prize and an effect operation for demonstration may be executed. When any of the plurality of stop switches is operated in this state, the rotation of the corresponding reel is stopped, and the display result is derived and displayed so as to be visible.

  Then, when the rotation of all the reels is stopped, one game is finished, and a combination of symbols called a predetermined combination on one of the activated pay lines is stopped as a display result of each reel. Will win a prize. The types of winning combinations are roughly divided into small roles with medals, re-players that can start the next game without the need to set the number of bets, and special cases that have a transition in gaming state. There is a role, and the winning combination is determined according to the gaming state. In the slot machine, each winning combination determined according to the gaming state is based on a random number value extracted from a random number circuit similar to the 16-bit random number circuit 509A in the above embodiment at the timing when the start lever is operated. An internal lottery is performed to determine whether or not to allow the occurrence. The fact that winning in this internal lottery and winning is permitted is also referred to as “internal winning”. Of the winning of each role, the winning of a small role or replaying role is valid only in the game for which the winning is determined, but the winning of special role has all the roles allowed to be generated by the internal lottery. It is effective until. In other words, once the occurrence of a special winning combination is allowed, even if the special winning combination cannot be generated in each game, the winning is carried over to the next game.

  The gaming state in the slot machine includes a specific gaming state and a normal gaming state. The specific gaming state may include AT (assist time), CT (challenge time), RT (replay time), ART (assist replay time), etc. in addition to the regular bonus and the big bonus. In the regular bonus game state, for example, small roles such as JAC, cherry, watermelon, and bell are determined as winning combinations and are subject to lottery in the internal lottery. In the game state of the big bonus, in a predetermined small role game, for example, small roles such as cherry, watermelon and bell, and special roles such as regular bonus (or JACIN) are determined as winning roles. It is a lottery target in the internal lottery in the role game. In the AT gaming state, a winning condition for a specific combination that can not make a winning appear unless an operation matching the winning conditions such as the stop order and stop timing of each reel is performed. In the CT gaming state, each reel becomes uncontrolled within a certain range, so that it becomes possible to win a specific small role aimed. In the gaming state of RT, a replay player such as replay wins with a high probability. In the ART gaming state, the AT gaming state and the RT gaming state are combined. In the normal gaming state, for example, small roles such as cherry, watermelon and bell, re-playing roles such as replay, special bonuses such as big bonus and regular bonus are determined in advance as winning roles. It is a lottery target in the lottery.

  The slot machine includes a power supply board having a configuration and functions common to the power supply board 10 in the above embodiment, a main board having a configuration and functions common to the main board 11, and a structure common to the effect control board 12. And an effect control board including functions, a payout control board including configurations and functions common to the payout control board 15, and the like. Each control board may include a different configuration and function from the control board in the above embodiment according to the progress of the game in the slot machine and the contents of the effects.

  The main board of the slot machine is mounted with a game control microcomputer having the same configuration and functions as the game control microcomputer 100 in the above embodiment. For example, the game control microcomputer has a CPU that can execute the same control as the CPU 505 in the above embodiment, a ROM that can store user programs and fixed data similar to the ROM 506, and a work area similar to the RAM 507. It is sufficient that a RAM that can be provided is incorporated. In addition, the reset controller 504A (including the watchdog timer 520) in the above embodiment has a part or all common reset controller, and the random number circuit 509A and 509B partly or entirely common is for game control. It may be built in or externally attached to the microcomputer.

  As an example, the CPU built in the game control microcomputer included in the slot machine executes a process corresponding to step S26 shown in FIG. 26, thereby allowing access to the RAM in the initial setting process. When it is first determined that the power-off signal is in the on state, the watchdog timer may be activated to enable the reset operation due to the occurrence of a timeout. In addition, the CPU built in the game control microcomputer provided in the slot machine executes a process corresponding to step S53 shown in FIG. 27, whereby the main-side power-off according to the fact that the power-off signal is on. As the process is executed, the watchdog timer may be activated to enable the reset operation due to the occurrence of a timeout.

  Slot machines are not limited to those that can play games using medals and credits. For example, slot machines that use pachinko balls to play games, and can play using credits without medals being discharged to the outside. The present invention can also be applied to a complete credit type slot machine and an image type slot machine in which a variable display device displays an image showing a symbol.

  Programs and data for realizing part or all of the configuration and functions of the pachinko gaming machine 1 and the slot machine are limited to a form distributed and provided by a removable recording medium to a computer device or the like. Instead of this, a form distributed by pre-installing in a storage device such as a computer device may be adopted. Furthermore, some or all of the programs and data for realizing the present invention can be downloaded from other devices on a network connected via a communication line or the like by providing a communication processing unit. You may take the form to distribute.

  As described above, in the gaming machine such as the pachinko gaming machine 1 in the above embodiment, the bit value in the bit number [6] of the reset setting KRES stored in the program management area of the ROM 506 is set to “1”. Thus, the user program (software) can be switched between starting and stopping of the watchdog timer 520. When the CPU 505 of the game control microcomputer 100 determines in step S51 shown in FIG. 27 that the power-off signal is on, the CPU 505 performs the infinite loop processing after executing the main-side power-off processing in step S52. In addition to shifting to the standby state to be repeatedly executed, the watchdog timer 520 is activated and the reset operation due to the occurrence of timeout is validated in the process of step S53 accompanying the execution of the main-side power-off process. Thus, when the progress of the game in the pachinko gaming machine 1 is controlled by starting the watchdog timer 520 after it is determined that the power-off signal is in the on state, the monitoring time of the watchdog timer 520 is periodically measured. There is no need to clear (initialize) and restart. Thereby, it is possible to appropriately recover from the instantaneous power supply in the gaming machine such as the pachinko gaming machine 1 while reducing the control burden for controlling the progress of the game.

  Further, the CPU 505 of the game control microcomputer 100 starts the process of step S25 before the access to the RAM 507 is permitted by the process of step S32 shown in FIG. 26 when the power supply in the pachinko gaming machine 1 is started. It is determined whether the power-off signal is in an on state by the processing. At this time, if it is determined that the power-off signal is in the on state, the watchdog timer 520 is activated in the process of step S26 accompanying the transition to the standby state in which the infinite loop process is repeatedly executed, and a time-out occurs. Enable reset action by occurrence. As described above, when the progress of the game in the pachinko gaming machine 1 is controlled by starting the watchdog timer 520 after it is determined that the power-off signal is in the on state at the time of starting the power supply or executing the reset operation. It is not necessary to periodically clear (initialize) the measurement of the monitoring time in the watchdog timer 520 and restart it. Thereby, it is possible to appropriately recover from an instantaneous power supply interruption in a gaming machine such as the pachinko gaming machine 1 while reducing a control burden for controlling the progress of the game.

  For example, in the reset setting KRES shown in FIG. 8B, the monitoring time measured by the watchdog timer 520 is set in advance by setting the bit values in the bit numbers [5-4] and [3-0]. It can be set from a plurality of types. By setting such that the bit value in the bit number [5-4] of the reset setting KRES is “11” and the bit value in the bit number [3-0] is “1111”, the timeout time as the monitoring time is set. Set the maximum time that can be set. Thereby, for example, when the power supply is completely stopped for a predetermined period due to, for example, the power switch of the pachinko gaming machine 1 being cut off, the reset operation due to the occurrence of a timeout is restricted so as to be reset erroneously. While preventing this, it is possible to appropriately recover from an instantaneous power supply interruption in a gaming machine such as the pachinko gaming machine 1.

  In the process of step S26 shown in FIG. 26 and the process of step S53 shown in FIG. 27, the process shown in FIG. 28B is executed, so that the reset factor immediately before is due to the timeout of the watchdog timer 520. When it is determined that there is, the watchdog timer 520 may be stopped to invalidate the reset operation due to the occurrence of a timeout. As a result, the power supply voltage in the gaming machine such as the pachinko gaming machine 1 cannot be confirmed, and thus the inadvertent reset operation is prevented from being repeatedly executed, and the power supply in the gaming machine is properly recovered from the instantaneous interruption. Can be made.

  The CPU 505 of the game control microcomputer 100 sequentially measures WDT clear data having different values “55H” and “AAH” in the WDT clear register WCL, thereby measuring the time-out time that is the monitoring time of the watchdog timer 520. Clear (initialize) and restart (restart). As a result, when the power supply instantaneously stops in a gaming machine such as the pachinko gaming machine 1, it is possible to prevent the measurement of the monitoring time from being erroneously initialized due to noise or the like, and the instantaneous power supply interruption in the gaming machine Can be recovered properly.

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4A, 4B ... Special symbol display device 5 ... Image display device 6A ... Ordinary winning ball device 6B ... Ordinary variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp 10 ... Power supply board 11 ... Main board 12 ... Production control board 13 ... Audio control board 14 ... Lamp control board 15 ... Dispensing control board 18 ... Relay board 20 ... Normal symbol display 21 ... Gate switch 22A, 22B: Start switch 23 ... Count switch 31 ... Game start switch 41 ... Pass gate 100 ... Game control microcomputer 301 ... Transformer circuit 302 ... DC voltage generation circuit 303 ... Power supply monitoring circuit 304 ... Clear switch 501 ... External bus Interface 501A ... Internal resource access Limiting circuit 502 ... Clock circuit 503 ... Unique information storage circuit 504A ... Reset controller 504B ... Interrupt controller 505 ... CPU
506 ... ROM
506A: Security check program 507: RAM
508 ... Timer circuits 509A, 509B ... Random number circuit 510 ... PIP
511 ... Serial communication circuit 512 ... Address decoding circuit 520 ... Watchdog timer 533 ... WDT control circuit 535 ... Count clock generation circuit 536 ... 16-bit up counter 537 ... Output control circuit 551 ... Random number update clock selection circuit 553A ... Random number generation circuit 553B ... Random number activation setting circuit 553C ... Start value setting circuit 554A ... Random number sequence change circuit 554B ... Random number sequence change setting circuit 555 ... Maximum value comparison circuit 558A, 558B ... Hard latch selector 559A, 559B ... Hard latch random number value register 559S ... Soft latch Random value register

Claims (1)

A gaming machine capable of performing a game and giving a game value,
A game control microcomputer for executing a game control process for controlling the progress of the game in accordance with the control program after executing the initial setting process based on the storage content of the nonvolatile memory ;
Power supply monitoring means for monitoring the state of a predetermined power source used in the gaming machine and outputting a detection signal based on the detection condition relating to the stop of the supply of power to the gaming machine being satisfied;
Resetting means for measuring a predetermined monitoring time and resetting the gaming control microcomputer when it is measured that the monitoring time has elapsed;
Reset setting means for setting to enable or disable the operation of the reset means according to a control program ;
Start time determining means for determining whether or not a detection signal is output from the power supply monitoring means when power supply to the gaming machine is started;
A start time setting means for setting the reset means when power supply to the gaming machine is started,
The monitoring time measured by the reset means is initialized by writing a predetermined value according to the control program,
The game control microcomputer is:
When shifting to the standby state after executing the power supply stop process according to the detection signal from the power supply monitoring unit, the reset setting unit validates the operation of the reset unit and then shifts to the standby state. Disconnection control means,
Security check means for executing a security check for checking whether or not the storage content of the nonvolatile memory has been changed in the initial setting process;
Period setting means capable of variably setting the period of the initial setting process,
The predetermined value is not written in the standby state,
After shifting to the standby state, the monitoring time measured by the reset means is not initialized even when the detection signal from the power supply monitoring means is not input.
A gaming machine characterized by that.

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