JP2016157844A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve reduction in a process time for dicing a chip with high accuracy and achieve improvement in alignment accuracy.SOLUTION: In a semiconductor device and a manufacturing method of the same, a groove 13 is formed entirely around a periphery of a rear face 12 of an upper chip 10, which faces a lower chip 20 and a connection face 12a on the inner side of the groove 13 is sized with high accuracy. Shapes and sizes of a hydrophilic region and a hydrophobic region which are formed in the lower chip 20 are unambiguously determined by a mask at the time of exposure to be sized with high accuracy. Accordingly, since the hydrophilic region of the lower chip 20, which is sized with high accuracy reaches a state of being coated with water droplets 30, when the connection face 12a is sized with high accuracy and the upper chip 10 is mounted on the water droplets 30, the upper chip 10 is positioned against the lower chip 20 with high accuracy.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device that electrically connects an upper chip and a lower chip via micro bumps formed on the upper and lower chips, and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, an alignment technique based on self-assembly is used when stacking chips on which a semiconductor element is formed on a wafer. Specifically, water is wetted in the hydrophilic region by dropping water onto a lower chip having a hydrophilic region surrounded by a hydrophobic region, and alignment is performed by placing an accurately processed upper chip on the hydrophilic region. Yes.

  For example, in Patent Document 1, after arranging and aligning the chip on the temporary substrate, a support substrate (wafer) is prepared, the support substrate and the temporary substrate are aligned, and then the support substrate and the chip are brought close to each other. The chip is transferred to the support substrate. The alignment of the chip on the temporary substrate is performed by self-organization based on the surface tension of water. Specifically, after separating the chips with high accuracy, by attaching water droplets to the hydrophilic region of the temporary substrate and mounting the chip on the water droplets, based on self-organization due to the surface tension of water The chip is aligned at a desired position on the temporary substrate. In this way, a structure is realized in which chips are stacked at desired positions on the support substrate.

  However, the transfer method disclosed in Patent Document 1 requires two alignments when bonding to the temporary substrate and transferring the chip to the support substrate, so that the alignment accuracy can be improved. difficult. Further, since the chip is aligned on the temporary substrate after being singulated with high precision, the process for singulating the chip with high precision takes time.

  On the other hand, in Non-Patent Document 1, a hydrophilic region and a hydrophobic region are formed on the wafer surface, a water droplet is attached on the hydrophilic region, and then a chip singulated with high precision is mounted thereon. Thus, alignment using self-organization based on the surface tension of water has been proposed. Micro bumps are formed on one side of the wafer side of the chip and one side of the chip side of the wafer. Electrical alignment is achieved by crimping the micro bumps of the chip and the wafer while aligning based on the surface tension of the water droplets. Connected.

  In such a method, since the chip is directly aligned with the wafer, the alignment need not be performed twice, and the alignment accuracy can be improved.

JP 2010-225803 A

IEEE TRANSACTIONS ON ELECTRON DEVICES. Vol.59. No.11, Nov. 2012

  However, even in the method of Non-Patent Document 1, since the chip must be singulated with high accuracy and then mounted on the water droplets attached to the hydrophilic region of the wafer, the chip is singulated with high accuracy. The process takes time. In other words, when dicing chips, it is necessary to perform dicing so that the dimensions between the end faces of the chips are maintained with high accuracy. Therefore, high-precision dicing is required and the dicing is long. It will be time. In particular, when the density of the micro bumps is increased due to miniaturization or the like, the micro bumps repel water, thereby affecting the surface tension of water and causing a problem of misalignment.

  In view of the above points, the present invention provides a semiconductor device capable of shortening the process time for separating chips with high accuracy and improving alignment accuracy, and a method for manufacturing the same. With the goal.

  In order to achieve the above object, in the invention described in claims 1 to 14, a substrate (20, 25), a plurality of first micro bumps (21) provided on a surface (22) of the substrate, and a substrate The semiconductor chip (10) to be mounted and the back surface (12) of the semiconductor chip are arranged and connected to each of the plurality of first micro bumps, thereby electrically and physically connecting the semiconductor chip and the substrate. A plurality of second micro-bumps (11), and the semiconductor chip has a groove (13) in an outer peripheral portion surrounding the connection surface, with a region including the second micro-bump on the back surface as a connection surface (12a). It is characterized by being formed.

  As described above, a groove portion that surrounds the outer periphery of the back surface of the semiconductor chip facing the substrate is formed. For this reason, the inner connecting surface can be dimensioned with high accuracy. Further, the shape and size of the hydrophilic region and the hydrophobic region formed on the substrate are uniquely determined by the mask at the time of exposure, and the size is determined with high accuracy. Therefore, since water droplets can be applied to the hydrophilic area of the substrate that has been dimensioned with high precision, when the semiconductor chip is mounted on the water droplet, if the connection surface is dimensioned with high precision, the semiconductor chip is attached to the substrate. Positioning with high accuracy. Therefore, it is possible to improve the alignment accuracy.

  Further, when sizing the connection surface of the semiconductor chip with high accuracy, the groove portion has a depth in the middle of the thickness of the semiconductor chip and does not reach the depth of the thickness of the semiconductor chip. For this reason, the process time for forming the groove is short. Then, when the semiconductor chip is divided into individual pieces, dicing may be performed in the groove formed part way through the thickness of the semiconductor chip, and high-precision dicing is not required. For this reason, it is possible to shorten the process time for separating the semiconductor chip while sizing the connection surface with high accuracy.

  Specifically, as in the invention described in claim 15, by preparing a substrate provided with first micro bumps and forming a hydrophobic film (28) surrounding the first micro bumps on the substrate, After preparing a semiconductor wafer (15) provided with a step of making the region where the hydrophobic film is formed in the substrate into a hydrophobic region and the region where the hydrophobic film is not formed as a hydrophilic region, and the second micro bumps, Forming a groove (13) so as to surround a region to be a connection surface including the second micro-bump on the semiconductor wafer, and forming a hydrophobic film (18) in the groove, The step of forming a hydrophobic region in the groove and the region serving as a connection surface as a hydrophilic region, the step of dicing the semiconductor wafer by dicing in the groove to form a semiconductor chip, and the hydrophilic in the substrate After placing the water droplet (30) in the region, a step of mounting the semiconductor chip on the water droplet, and a step of connecting the first micro bump on the substrate and the second micro bump on the semiconductor chip, A semiconductor device having the above structure can be manufactured.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is the figure which looked at the upper chip | tip 10 with which the semiconductor device concerning 1st Embodiment of this invention is provided from the back surface 12 side. It is II-II 'sectional drawing in FIG. FIG. 3 is a diagram illustrating a manufacturing process of the lower chip 20 in FIG. 2. FIG. 3 is a diagram showing a manufacturing process of the upper chip 10 in FIG. 2. It is the figure which showed the bonding process of the lower chip | tip 20 manufactured at the manufacturing process of FIG. 3, and the upper chip | tip 10 manufactured at the manufacturing process of FIG. It is the figure which showed the relationship between the ratio X of the distance from the outer edge side micro bump to each side of the contact surface 12a with respect to the dimension of an outer edge side micro bump, and the contact angle in a hydrophilic region. It is the figure which showed the relationship between ratio S2 / S1 of the area S2 of the microbump 11 with respect to the total area S1 which added the total area of the microbump 11, and the area of the connection surface 12a, and the contact angle in a hydrophilic region. It is the figure which looked at the upper chip | tip 10 with which the semiconductor device concerning 2nd Embodiment of this invention is provided from the back surface 12 side. It is IX-IX 'sectional drawing in FIG. It is the figure which looked at the upper chip | tip 10 with which the semiconductor device concerning 3rd Embodiment of this invention is provided from the back surface 12 side. It is the figure which looked at the upper chip | tip 10 with which the semiconductor device concerning 4th Embodiment of this invention is provided from the back surface 12 side. It is the figure which looked at the upper chip | tip 10 with which the semiconductor device concerning 5th Embodiment of this invention is provided from the back surface 12 side. It is the figure which looked at the upper chip | tip 10 with which the semiconductor device demonstrated by other embodiment is provided from the back surface 12 side. It is XIV-XIV 'sectional drawing in FIG. It is sectional drawing of the semiconductor device demonstrated by other embodiment. It is sectional drawing of the semiconductor device demonstrated by other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Here, a description will be given of a structure in which two semiconductor chips are bonded as a semiconductor device constituting a chip stacking unit in which semiconductor chips are mounted on a substrate. Hereinafter, the configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 2. Note that, in the cross-sectional view of the semiconductor device illustrated in FIG. 2, each part is illustrated in a simplified manner.

  The semiconductor device has an upper chip 10 corresponding to the semiconductor chip shown in FIG. 1, and the upper chip 10 is mounted on a lower chip 20 corresponding to a substrate as shown in FIG. The micro bumps (second micro bumps) 11 formed on the upper chip 10 and the micro bumps (first micro bumps) 21 formed on the lower chip 20 are joined, and the upper chip 10 and the micro bumps 11 and 21 are joined together. Electrically and physically connected to the lower chip 20.

  Both the upper chip 10 and the lower chip 20 are obtained by dividing a semiconductor wafer on which, for example, a semiconductor element or an electric circuit is formed, and the micro bumps 11 and 21 provide electrical connection between the semiconductor element and the outside. It is a connection member for performing. For example, a silicon wafer is used as the semiconductor wafer, and a semiconductor element is formed by performing a general semiconductor process on the silicon wafer. And after performing the formation process of the micro bump 11 with respect to the silicon wafer after semiconductor element formation, the upper chip | tip 10 is comprised by dividing into a chip unit.

  As shown in FIG. 1 and FIG. 2, the upper chip 10 has a top surface of a rectangular shape (square). A groove 13 that surrounds the outer periphery of the back surface 12 is formed on the back surface 12 of the upper chip 10, that is, the outer edge portion of one surface of the upper chip 10 that faces the lower chip 20. The groove 13 is configured by removing the upper chip 10 by a predetermined thickness on the back surface 12. The inner portion surrounded by the groove 13 in the back surface 12 of the upper chip 10, that is, the dimension of each side of the one surface (hereinafter referred to as the connection surface) 12 a on which the plurality of micro bumps 11 are arranged is highly accurate. Dimensions are determined. On the other hand, the width of the groove 13 may be different on each side of the rectangle formed by the upper chip 10. The depth of the groove 13 is also arbitrary, but is preferably 1 μm or more.

  When the vertical direction on the paper surface of FIG. 1 is the vertical direction and the horizontal direction is the horizontal direction, the micro bumps are formed inside the rectangle formed by the upper chip 10 on the back surface of the upper chip 10, that is, on one surface of the upper chip 10 facing the lower chip 20. 11 are arranged in a matrix having equal intervals in the vertical and horizontal directions. The distance from each side of the connection surface 12a to the outer edge side micro bump located on the outermost side of the connection surface 12a of the micro bumps 11 is the dimension of the outermost micro bump (the length of one side or the diameter). ) Or more. That is, the micro bumps 11 are avoided from being arranged on the outer edge side of the chip that is easily affected by the surface tension of water.

  The area of each microbump 11 is arbitrary. However, the total area S1 obtained by adding the total area of the microbumps 11 and the area of the connection surface 12a viewed from the normal direction of the back surface 12 shown in FIG. The ratio S2 / S1 is preferably 0.6 or less. By setting it as such a structure, the quantity of the micro bump 11 which repels water can be restrict | limited, and the influence on the alignment by the micro bump 11 repelling water can be suppressed.

  Here, as the upper chip 10, a semiconductor wafer that is divided into chips is taken as an example, but a semiconductor wafer that is divided into chips is resin-sealed, and a micro bump is formed on the back surface side. A chip on which etc. are formed may also be used.

  The lower chip 20 also has a top surface that is rectangular (square). The outer dimension of the lower chip 20 is not particularly limited as long as the arrangement space of the microbumps 21 is secured, but in the present embodiment, the outer dimension is larger than that of the upper chip 10. In the case of such a dimensional relationship, for example, by pulling out a circuit part electrically connected to the microbump 21 to a part of the lower chip 20 that protrudes outward from the upper chip 10, an electrical connection with the outside is achieved through this part. Connection can be made possible.

  The micro bumps 21 of the lower chip 20 are arranged at positions corresponding to the micro bumps 11 of the upper chip 10. That is, on the surface of the lower chip 20, that is, one surface of the lower chip 20 facing the upper chip 10, the micro bumps 21 are arranged in a matrix form with equal vertical and horizontal intervals inside the rectangle formed by the lower chip 20. As shown in FIG. 2, each micro bump 11 of the upper chip 10 is joined to each corresponding micro bump 21 of the lower chip 20.

  With such a structure, the semiconductor device according to the present embodiment is configured. Next, with reference to FIGS. 3 to 5, a method for manufacturing the semiconductor device according to the present embodiment will be described. 3 shows the formation process of the lower chip 20, FIG. 4 shows the formation process of the upper chip 10, and FIG. 5 shows the bonding process of the upper chip 10 and the lower chip 20.

  First, the formation process of the lower chip 20 will be described with reference to FIG.

[Step shown in FIG. 3 (a)]
A semiconductor wafer 25 used for forming the lower chip 20 is prepared. That is, a silicon wafer or the like on which a semiconductor element or a circuit unit provided in the lower chip 20 is formed is prepared. At this time, the surface side of the semiconductor wafer 25, that is, the surface on the side where the upper chip 10 is disposed in the subsequent process is covered with an insulating hydrophilic film 20a such as silicon dioxide, silicon nitride, hydrophilic polyimide, or PCB (epoxy). It is covered. Subsequently, a seed layer (underlayer) 21 a made of Cu or the like is formed on one surface of the semiconductor wafer 25 on the side where the microbumps 21 are formed, for example, by sputtering or the like. And after apply | coating the resist 26 to the surface of the seed layer 21a, exposure and image development are performed by the photo process using the mask which is not shown in figure, and the opening part 26a is formed in the formation plan position of the microbump 21 among the resists 26.

[Step shown in FIG. 3B]
A plating process is performed using the resist 26 as a mask to form the remainder of the microbumps 21 on the exposed surface of the seed layer 21a, and then the resist 26 is removed. Then, the seed layer 21a is patterned by etching using the remaining part of the microbump 21 as a mask. Thereby, the micro bump 21 is configured.

[Step shown in FIG. 3 (c)]
After applying a resist 27 so as to cover the microbumps 21, a portion of the resist 27 outside the microbumps 21 is removed. Specifically, the resist 27 is left in a portion corresponding to the connection surface 12a in the upper chip 10, and the semiconductor wafer 25 is exposed outside, that is, a portion corresponding to the groove 13 and further outside.

[Step shown in FIG. 3 (d)]
A hydrophobic film 28 is formed by applying a hydrophobic material such as carbon fluoride (CF) on the upper surfaces of the resist 27 and the exposed portions of the semiconductor wafer 25. The material of the hydrophobic film 28 is arbitrary, but it is preferable that the contact angle of the hydrophobic film 28 with respect to the water droplet 30 is 60 degrees or more. Further, it is preferable to select a material for which the contact angle difference between the hydrophobic film 28 and the surface of the semiconductor wafer 25 (hydrophilic film 20 a) with respect to the water droplet 30 is 10 degrees or more as the material of the hydrophobic film 28. In this way, the water droplet 30 can be suitably repelled by the hydrophobic film 28, and the difference in wettability of the water droplet 30 between the hydrophobic region and the hydrophilic region can be increased.

[Step shown in FIG. 3 (e)]
By removing the resist 27 with an organic solvent such as NMP (N-methyl-2-pyrrolidone), the hydrophobic film 28 on the resist 27 is removed by lift-off, leaving the hydrophobic film 28 only on the upper surface of the semiconductor wafer 25. A portion where the hydrophobic film 28 is formed becomes a hydrophobic region in the lower chip 20, and a portion inside the portion becomes a hydrophilic region.

  Next, the formation process of the upper chip 10 will be described with reference to FIG.

[Steps shown in FIGS. 4A and 4B]
First, as a process shown in FIG. 4A, a semiconductor wafer 15 used for forming the upper chip 10 is prepared. At this time, the back surface side of the semiconductor wafer 15, that is, the surface of one surface directed to the lower chip 20 in a subsequent process is covered with an insulating hydrophilic film 10 a such as silicon dioxide, silicon nitride, hydrophilic polyimide, or PCB (epoxy). doing.

  Thereafter, a seed layer (underlying layer) 11a is formed, and a resist 16 is applied to the surface of the seed layer. Then, an opening 16a is formed in the resist 16 at a position where the micro bump 11 is to be formed. This step is the same as in FIG. Thereafter, as shown in FIG. 4B, a micro bump is formed by performing a plating process for forming the remaining portion of the micro bump 11 on the surface of the seed layer 11a and a patterning process of the seed layer 11a as in FIG. 3B. 11 is formed.

[Step shown in FIG. 4 (c)]
After the resist 17 is applied so as to cover the microbumps 11, a predetermined width outside the microbumps 11 in the resist 17 is removed. Specifically, the resist 17 is removed at the portion corresponding to the groove portion 13 in the upper chip 10, and the resist 17 is left outside the portion corresponding to the connection surface 12 a and the groove portion 13, thereby the portion corresponding to the groove portion 13. The semiconductor wafer 15 is exposed.

[Step shown in FIG. 4 (d)]
By performing anisotropic etching such as RIE (Reactive Ion Etching) using the resist 17 as a mask, the groove 13 is formed in the semiconductor wafer 15. Thereby, the groove part 13 and the connection surface 12a inside it are comprised.

  At this time, the groove 13 may have a depth up to the middle of the thickness of the semiconductor wafer 15, for example, a depth of 1 μm or more. Since the formation position of the groove 13 is uniquely determined by the mask pattern used when the resist 17 is exposed, the dimensions of each side of the connection surface 12a located inside the groove 13 are also uniquely determined, and the dimensions are highly accurate. The decision has been made. Further, the groove 13 formed by anisotropic etching has a substantially flat bottom, and has a lower surface roughness Ra than when machining such as dicing is performed.

[Step shown in FIG. 4 (e)]
A hydrophobic film 18 is formed by applying a hydrophobic material such as carbon fluoride (CF) to the exposed portions of the resist 17 and the semiconductor wafer 15, that is, the upper surface of the groove 13. The material of the hydrophobic film 18 is arbitrary, but it is preferable that the hydrophobic film 18 has a contact angle of 60 degrees or more with respect to the water droplet 30. In addition, it is preferable to select a material having a contact angle difference of 10 degrees or more between the hydrophobic film 18 and the connection surface 12 a (hydrophilic film 10 a) of the water droplet 30 as the material of the hydrophobic film 18. In this way, the water droplet 30 can be suitably repelled by the hydrophobic film 18 and a difference in wettability of the water droplet 30 between the hydrophobic region and the hydrophilic region can be increased.

[Step shown in FIG. 4 (f)]
By removing the resist 17 with an organic solvent such as NMP, the hydrophobic film 18 on the resist 17 is removed by lift-off, leaving the hydrophobic film 18 only in the groove 13. The portion where the hydrophobic film 18 is formed becomes a hydrophobic region in the upper chip 10, and the connection surface 12a on the inner side becomes a hydrophilic region.

[Step shown in FIG. 4 (g)]
The upper chip 10 singulated by dicing the semiconductor wafer 15 in the groove 13 is configured. At this time, since the groove 13 is formed by etching and can be dimensioned with high accuracy using a mask, there is no need for high-accuracy dimensioning for dicing.

  In this manner, the semiconductor wafer 25 for forming the lower chip 20 before dicing and the upper chip 10 after dicing are configured. Thereafter, the upper chip 10 and the semiconductor wafer 25 are bonded together by performing the process shown in FIG.

[Step shown in FIG. 5A]
A water droplet 30 is applied to the surface of the lower chip 20. At this time, since the water does not get wet in the hydrophobic region of the surface of the lower chip 20, the water droplet 30 is attached only to the hydrophilic region. Then, the upper chip 10 is mounted on the water droplet 30. As a result, the upper chip 10 is placed at the center position of the water drop 30 due to the surface tension of the water on the water drop 30 so that the micro bumps 11 of the upper chip 10 and the micro bumps 21 of the lower chip 20 coincide. Aligned state.

  When the upper chip 10 is mounted on the water droplet 30, if the depth of the groove portion 13 is shallow, the water droplet 30 may hang down to the groove portion 13 side. For this reason, it is preferable that the depth of the groove 13 is somewhat deep. For example, if the depth of the groove 13 is 1 μm or more, it is possible to accurately suppress the water droplet 30 from drooping toward the groove 13.

[Step shown in FIG. 5B]
The micro bumps 11 and 21 are thermocompression-bonded by applying heat and pressure so as to sandwich the upper chip 10 and the lower chip 20 with the upper chip 10 mounted on the water droplet 30. Thereby, the upper chip 10 and the lower chip 20 are electrically and physically connected via the micro bumps 11 and 21. The water droplets 30 are removed by evaporation during heating and pressurization.

  Thereafter, after removing the hydrophobic film 18 by ashing, the lower chip 20 is separated into individual pieces by dicing, whereby a semiconductor device having the upper chip 10 and the lower chip 20 is completed.

  As described above, in the present embodiment, the groove portion 13 that surrounds the outer periphery of the back surface 12 facing the lower chip 20 side of the upper chip 10 is formed, and the inner connecting surface 12a is dimensioned with high accuracy. I try to do it. In addition, the shape and size of the hydrophilic region and the hydrophobic region formed in the lower chip 20 are uniquely determined by the mask at the time of exposure, and the size is determined with high accuracy. Accordingly, since the water droplet 30 is applied to the hydrophilic region of the lower chip 20 that is dimensioned with high accuracy, the upper chip 10 is mounted on the water droplet 30 if the connection surface 12a is dimensioned with high accuracy. When this is done, the upper chip 10 is positioned with high accuracy relative to the lower chip 20.

  Therefore, it is possible to improve the alignment accuracy. Further, when the connecting surface 12a of the back surface 12 of the upper chip 10 is dimensioned with high accuracy, the groove portion 13 is set to a depth in the middle of the thickness of the upper chip 10, and the depth up to the thickness of the upper chip 10 is assumed. Absent. For this reason, the process time for forming the groove 13 is short. Then, when the upper chip 10 is separated into pieces, dicing may be performed in the groove portion 13 formed up to the middle of the thickness of the upper chip 10, and highly accurate dicing is not required. For this reason, it is possible to shorten the process time for separating the upper chip 10 while sizing the connection surface 12a with high accuracy.

  Therefore, it is possible to shorten the process time for dividing the chip with high accuracy and to improve the alignment accuracy.

  In particular, in this embodiment, the distance from each side of the connection surface 12a to the outer edge side microbump located on the outermost side of the connection surface 12a among the microbumps 11 is determined by the dimension of the outer edge side microbump (the length of one side). Alternatively, it is set to 1/2 or more of the diameter. As a result, the influence of the surface tension of water can be further suppressed, and the alignment accuracy can be further improved.

  Further, the ratio S2 / S1 of the total area S2 of the microbumps 11 to the total area S1 obtained by adding the total area of the microbumps 11 and the area of the connection surface 12a is set to 0.6 or less. Thereby, the quantity of the micro bump 11 which flips water can be restrict | limited, the influence on the alignment by the micro bump 11 flipping water can be suppressed, and alignment precision can be improved.

  Specifically, in order to increase the alignment accuracy, the difference S between the contact angle in the hydrophobic region and the contact angle in the hydrophilic region needs to be 80 ° or more. The physical limit value of the contact angle in the hydrophobic region has been confirmed to be 120 °, and the contact angle in the hydrophilic region needs to be 40 ° or less in order to make the difference S 80 ° or more. It becomes. The relationship between the ratio X of the distance from the outer edge side micro bump to each side of the contact surface 12a with respect to the dimension of the outer edge side micro bump and the contact angle in the hydrophilic region is expressed as shown in FIG. In order to achieve this, the ratio X needs to be ½ or more. Therefore, as described above, it is possible to further improve the alignment accuracy by setting the distance from each side of the connection surface 12a to the outer edge side micro bump to be 1/2 or more of the dimension of the outer edge side micro bump. Become.

  FIG. 6 shows the result of the entire hydrophilic region. From this result, it is possible to derive a tendency that the hydrophilicity at the chip end surface decreases as the distance from the micro bump 11 to the chip end surface becomes narrower.

  Similarly, the relationship between the ratio S2 / S1 of the area S2 of the microbump 11 to the total area S1 obtained by adding the total area of the microbump 11 and the area of the connection surface 12a and the contact angle in the hydrophilic region as shown in FIG. expressed. From this figure, the ratio S2 / S1 needs to be 0.6 (= 3/5) or more in order to make the contact angle less than 40 °. Therefore, as described above, the alignment accuracy can be further improved by setting the ratio S2 / S1 to 0.6 or less.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the layout of the micro bumps 11 and 21 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only different portions from the first embodiment will be described. .

  As shown in FIGS. 8 and 9, in the present embodiment, the density per unit area of the micro bumps 11 and 21 is decreased from the center position of the upper chip 10 and the lower chip 20 toward the outer peripheral side. Yes. Specifically, the distance between the micro bumps 11 and 21 is increased as the position is closer to the groove 13, and the distance between the micro bumps 11 and 21 is decreased as the distance from the groove 13 is increased.

  When the upper tip 10 and the lower tip 20 are aligned using the surface tension of the water droplet 30, the accuracy is improved as the hydrophilicity of the surface in contact with the water droplet 30 is improved. However, since the micro bumps 11 and 21 have water repellency, it is difficult to improve accuracy in the structure in which the micro bumps 11 and 21 are laid out at high density.

  Here, among the micro bumps 11 and 21, a part that particularly affects the alignment accuracy due to water repellency is located in the vicinity of the outer peripheral part of the upper chip 10 and the lower chip 20. Therefore, even if the total area of the micro bumps 11 and 21 is equal to that of the first embodiment, the density per unit area of the portion located in the vicinity of the outer peripheral portion of the upper chip 10 and the lower chip 20 is small. If it becomes, the influence resulting from water repellency can be suppressed and alignment accuracy can be improved.

  On the other hand, as in the present embodiment, the density per unit area of the micro bumps 11 and 21 is decreased from the center position of the upper chip 10 and the lower chip 20 toward the outer peripheral side. Therefore, the influence resulting from the water repellency of the portion located in the vicinity of the outer peripheral portion of the upper chip 10 and the lower chip 20 can be suppressed, and the alignment accuracy can be improved.

(Third embodiment)
A third embodiment of the present invention will be described. In this embodiment, the layout of the micro bumps 11 and 21 is changed with respect to the first embodiment, and the others are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described. .

  As shown in FIG. 10, in the present embodiment, a dense group in which the density per unit area of the micro bumps 11 and 21 is increased at the center position of the upper chip 10 and the lower chip 20 and the outer peripheral position. There is a depopulated group with a smaller density. In the case of this embodiment, in the dense group, for example, 3 × 3 micro bumps 11 are arranged in the vertical direction and the horizontal direction of FIG. 10 and the same number is arranged in the depopulated group. Also, the interval between the micro bumps 11 is made small. By adopting such a configuration, the distance between the micro bumps 11 and 21 is increased as the position is closer to the groove 13, and the distance between the micro bumps 11 and 21 is decreased as the distance from the groove 13 is increased. .

  As described above, even if the density per unit of the micro bumps 11 and 21 is changed between the center position of the upper chip 10 and the lower chip 20 and the outer peripheral position, the vicinity of the outer peripheral portion of the upper chip 10 and the lower chip 20. The influence resulting from the water repellency of the portion located in the region can be suppressed. Therefore, as in the second embodiment, the alignment accuracy can be improved.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In this embodiment, the layout of the micro bumps 11 and 21 is changed with respect to the first to third embodiments, and the rest is the same as the first to third embodiments. Only portions different from the embodiment will be described. Here, the structure of the second embodiment will be described as an example, but the configuration of the present embodiment can also be applied to the structures of the first and third embodiments.

  As shown in FIG. 11, in this embodiment, the units of the micro bumps 11 and 21 are located on both sides of a straight line extending in the vertical direction of the paper passing through the center position of the upper chip 10 and the lower chip 20, that is, on the right and left sides of the paper. The density per area is changed. On the left side of the drawing, the density per unit area of the micro bumps 11 and 21 is higher than that on the right side. The in-plane distribution of the weight of the upper chip 10 is different between the right side and the left side of the paper, and the density per unit area of the micro bumps 11 and 21 is low on the right side of the paper where the weight is relatively heavy compared to the left side of the paper. Has been.

  When the weight of the upper chip 10 mounted on the water droplet 30 has an in-plane distribution, the influence on the alignment due to the micro bumps 11 and 21 repelling water is greater than the heavier one than the lighter one. . For this reason, on the heavier side, the density per unit area of the micro bumps 11 and 21 is lower than that of the lighter side, so that the influence on the alignment caused by the micro bumps 11 and 21 splashing water can be suppressed. Thereby, the influence on the alignment based on the in-plane distribution of weight can be further suppressed, and the alignment accuracy can be further improved.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In this embodiment, the layout of the micro bumps 11 and 21 is changed with respect to the first to fourth embodiments, and the others are the same as those of the first to third embodiments. Only portions different from the embodiment will be described. In addition, although the structure of 1st Embodiment is mentioned as an example and demonstrated here, the structure of this embodiment is applicable also to the structure of 2nd-4th embodiment.

  As shown in FIG. 12, in this embodiment, the area of the micro bumps 11 and 21 is larger at the center position of the upper chip 10 and the lower chip 20 than at the outer side. Specifically, the area of the micro bumps 11, 21 is the largest at the center position of the upper chip 10 and the lower chip 20, and is made smaller toward the groove 13.

  In at least one of the upper chip 10 and the lower chip 20, there may be a current distribution in the chip surface. For example, when a power element is arranged on the upper chip 10 or the lower chip 20, a structure in which a larger current flows than other positions is adopted. In such a case, it is necessary to increase the area of the micro bumps 11 and 21 through which a large current flows.

  However, as the area of the micro bumps 11 and 21 increases, the influence on the alignment due to the micro bumps 11 and 21 repelling water increases. For this reason, in the present embodiment, a large current element such as a power element, through which a large current flows, is arranged at the center position of the upper chip 10 or the lower chip 20, and the upper one of the micro bumps 11 and 21 having a larger area is arranged. The chip 10 and the lower chip 20 are arranged at the center position. Thereby, the influence on the alignment by the micro bumps 11 and 21 repelling water can be suppressed. Therefore, the alignment accuracy can be further improved.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above embodiments, after forming the hydrophobic film 18 to form the hydrophobic region in the groove 13 of the upper chip 10, the hydrophobic film 18 is removed after the upper chip 10 is bonded to the lower chip 20. Yes. Similarly, after forming a hydrophobic film 28 for forming a hydrophobic region on the outer edge of the lower chip 20, the upper chip 10 is bonded to the lower chip 20, and then the hydrophobic film 18 is removed. However, this is only an example. As shown in FIGS. 13 and 14, after the upper chip 10 and the lower chip 20 are bonded together, the hydrophobic film 18 may be left on the upper chip 10. good.

  In the example shown in FIG. 5, since the hydrophobic films 18 and 28 of the upper chip 10 and the lower chip 20 are simultaneously removed by ashing, not only the hydrophobic film 18 of the upper chip 10 but also the hydrophobic film of the lower chip 20. 28 remains, but there is no particular problem. As described above, when the hydrophobic films 18 and 28 are not removed, the ashing process can be eliminated, so that the manufacturing process of the semiconductor device can be further simplified.

  Further, as shown in FIG. 15, a groove 23 similar to the groove 13 of the upper chip 10 may be formed on the surface 22 of the lower chip 20 on the upper chip 10 side. In this case, it is preferable that the inner surface surrounded by the groove 23 in the lower chip 20 is the connection surface 22a, and the connection surface 12a of the upper chip 10 and the connection surface 22a of the lower chip 20 have the same shape and the same dimensions. However, the dimensions may be different. For example, as shown in FIG. 16, the dimensional variation of both the connection surfaces 12a and 22a resulting from processing accuracy may occur. However, if the dimensional variation of the connecting surfaces 12a and 22a on one side as viewed from the center position of the chips 10 and 20 is within 10 μm, the alignment accuracy is hardly lowered, so that high alignment accuracy can be obtained. it can.

  Moreover, in the said embodiment, although it was set as the lower chip | tip 20 which separated the board | substrates, such as a circuit board comprised with the semiconductor wafer 25, into pieces, it does not necessarily need to be separated into pieces and may be a state with a board | substrate. .

DESCRIPTION OF SYMBOLS 10 Upper chip 20 Lower chip 11, 21 Micro bump 12a, 22a Connection surface 13, 23 Groove part 15, 25 Semiconductor wafer 18, 28 Hydrophobic film 30 Water drop

Claims (15)

Substrates (20, 25);
A plurality of first micro bumps (21) provided on a surface (22) of the substrate;
A semiconductor chip (10) mounted on the substrate;
A plurality of second micro bumps disposed on the back surface (12) of the semiconductor chip and connected to each of the plurality of first micro bumps to electrically and physically connect the semiconductor chip and the substrate. (11)
The semiconductor device is characterized in that a groove portion (13) is formed in an outer peripheral portion surrounding the connection surface, with the region including the second micro bumps in the back surface as a connection surface (12a) in the semiconductor chip. .   The distance between the first micro bumps and the distance between the second micro bumps are increased as the first micro bumps and the second micro bumps move from the center position of the semiconductor chip toward the outer edge side. The semiconductor device according to claim 1, wherein:   The first micro bump and the second micro bump are a dense group in which the areas of the first and second micro bumps per unit area are densely arranged at a central position of the semiconductor chip, 3. The semiconductor device according to claim 1, wherein the semiconductor device is a depopulated group in which the density is arranged sparser than the dense region on the outer edge side of the center position.   The outer edge side microbump closest to the groove part among the second microbumps and the groove part are separated from each other by 1/2 or more of the dimension of the outer edge side microbump. The semiconductor device according to any one of the above.   The ratio S2 / S1 of the total area S2 of the second micro bumps to the total area S1 obtained by adding the total area of the second micro bumps and the area of the connection surface is 0.6 or less. The semiconductor device according to claim 1.   6. The density per unit area of the first micro bump and the second micro bump is changed on both sides of a straight line passing through a central position of the semiconductor chip. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein a hydrophobic film is formed on a bottom of the groove.   The semiconductor device according to claim 7, wherein a contact angle difference with respect to water between the connection surface and the hydrophobic film is 10 degrees or more.   9. The semiconductor device according to claim 1, wherein a contact angle of the hydrophobic film with respect to water is 60 degrees or more.   The semiconductor device according to claim 1, wherein a depth of the groove is 1 μm or more.   11. The area of the first micro bump and the second micro bump is larger at the center position of the semiconductor chip than at the outer edge side of the center position. The semiconductor device according to any one of the above.   12. The semiconductor device according to claim 1, wherein a surface of the connection surface of the semiconductor chip is covered with an insulating hydrophilic film (10a).   13. The groove portion (23) surrounding the first micro bump is formed on a surface of the substrate on the side on which the semiconductor chip is mounted. 13. Semiconductor device.   The connection surface (22a) inside the groove formed on the substrate and the connection surface of the semiconductor chip have the same shape, and are formed on the substrate on one side when viewed from the center position of the semiconductor chip. The semiconductor device according to claim 1, wherein a dimensional difference between a connection surface inside the groove and a connection surface of the semiconductor chip is 10 μm or less. A method of manufacturing a semiconductor device according to claim 1,
Preparing the substrate provided with the first micro bumps;
By forming a hydrophobic film (28) surrounding the first micro-bump on the substrate, a region where the hydrophobic film is formed in the substrate is made a hydrophobic region, and a region where the hydrophobic film is not formed is made hydrophilic. A process of making an area;
After preparing the semiconductor wafer (15) provided with the second micro bump, the groove (13) is formed so as to surround the region to be the connection surface including the second micro bump with respect to the semiconductor wafer. And a process of
Forming a hydrophobic film (18) in the groove, thereby forming the groove in the semiconductor wafer as a hydrophobic region and a region serving as the connection surface as a hydrophilic region;
The step of dicing the semiconductor wafer by performing dicing in the groove and configuring the semiconductor chip;
Placing the semiconductor chip on the water droplet after disposing the water droplet (30) in the hydrophilic region of the substrate;
Connecting the first micro bumps on the substrate and the second micro bumps on the semiconductor chip. A method for manufacturing a semiconductor device, comprising:

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