JP2016146377A - 電子装置及び電子装置の製造方法 - Google Patents
電子装置及び電子装置の製造方法 Download PDFInfo
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- JP2016146377A JP2016146377A JP2015021951A JP2015021951A JP2016146377A JP 2016146377 A JP2016146377 A JP 2016146377A JP 2015021951 A JP2015021951 A JP 2015021951A JP 2015021951 A JP2015021951 A JP 2015021951A JP 2016146377 A JP2016146377 A JP 2016146377A
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- Prior art keywords
- layer
- solder
- electrode
- electronic device
- bonding
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Abstract
Description
図1は第1の実施の形態に係る電子装置の第1例を示す図である。図1には、第1の実施の形態に係る電子装置の第1例の要部断面を模式的に図示している。
電子部品10は、電極11を有している。電極11には、例えば、銅(Cu)若しくはCuを含む材料、又は、ニッケル(Ni)若しくはNiを含む材料が用いられる。尚、電極11には、単層構造又は積層構造の電極層、そのような電極層上にバリアメタル層を設けた積層構造を用いることができる。
電子部品20は、電子部品10と対向するように設けられ、半田40及び接合層30Aを介して電子部品10(その電極11)に電気的に接続されている。
しかし、電極と半田とが互いの成分を含有する金属間化合物を介して強固に接合され、衝撃や応力等の力によって電極やその周辺に破壊が生じていると、少なくともその電極を備えた電子部品の交換を要する。このような電極の部分の破壊が、電子部品群が搭載される回路基板側で生じている場合には、回路基板の交換、或いは回路基板とそれに搭載される電子部品群を含めた電子装置全体の交換を要することが起こり得る。このような交換は、電子装置のリペアコストの増大を招く可能性がある。
ここで、上記図1に示した電子装置1Aでは、電極11と半田40との間に接合層30Aを介在させ、電極11と半田40との間に、一定の接合強度を確保しながら、互いの成分を含有する金属間化合物が生成されることを抑制する。これにより、半田40に力が加わった際に、比較的半田40で破壊が生じ易くなるようにし、半田40から電極11に過剰な力が伝わることを抑制して、電極11やその周辺に破壊が生じることを抑制する。このようにすることで、電子装置1Aにリペアを要するような故障が生じた場合にも、リペアコストの増大を抑えて、リペアを実施することが可能になる。
図2に示す電子装置1Bは、電子部品10の電極11と半田40との間に、単層構造の接合層30Bを有している点で、上記電子装置1Aと相違する。
まず、第2の実施の形態について説明する。
図3に示す電子装置100Aは、電子部品である回路基板110及び半導体チップ120、並びに、接合層130及び半田140を有している。
基板112には、ガラスエポキシやポリイミド等の有機絶縁材料、又は、ガラスやセラミック等の無機絶縁材料、シリコン(Si)等の半導体材料が用いられる。基板112には、ここでは図示を省略するが、配線、ビア等の導体部が設けられ、この導体部に、電極111が電気的に接続されている。
電極層111aには、例えば、Cuが用いられる。電極層111aには、Cuのほか、Ni、アルミニウム(Al)等を用いることもできる。電極層111aは、単層構造のほか、同種又は異種の材料を積層した積層構造とすることもできる。
半導体チップ120は、電極121を有している。半導体チップ120は、ここでは図示を省略するが、半導体基板を用いて形成されたトランジスタ等の回路素子、及び、回路素子に電気的に接続された配線、ビア等の導体部を含み、このような導体部に電極121が電気的に接続されている。半導体チップ120は、回路基板110と対向するように設けられ、半田140及び接合層130を介して、電極121と電極111とが電気的に接続されている。
図4は第2の実施の形態に係る電子装置の製造方法の第1例を示す図である。図4(A)には、接合前の回路基板と半導体チップの一例の要部断面を模式的に図示している。図4(B)には、接合時の回路基板と半導体チップの一例の要部断面を模式的に図示している。図4(C)には、接合後の回路基板と半導体チップの一例の要部断面を模式的に図示している。
回路基板110は、図4(A)に示すように、基板112、電極111(電極層111a及びバリアメタル層111b)、並びに、保護膜113を有する。電極111の電極層111a上に設けるバリアメタル層111bにNiを用いる場合には、電極層111a上に、例えば、無電解めっきにより、厚さ4μm〜6μm程度のバリアメタル層111bが形成される。尚、この場合、バリアメタル層111bには、Niと共に、めっき液に含まれるリン(P)が僅かに含有され得る。
この図4に示すような方法により、電極111のバリアメタル層111bと、半田140との間に、PdAg含有層の第1層131とInAu含有層の第2層132とを含む接合層130が設けられた、電子装置100Aが得られる。
図5は第2の実施の形態に係る電子装置の製造方法の第2例を示す図である。図5(A)には、接合前の回路基板と半導体チップの一例の要部断面を模式的に図示している。図5(B)には、接合時の回路基板と半導体チップの一例の要部断面を模式的に図示している。図5(C)には、接合後の回路基板と半導体チップの一例の要部断面を模式的に図示している。
この図5に示すような方法によっても、電極111のバリアメタル層111bと、半田140との間に、PdAg含有層の第1層131とInAu含有層の第2層132とを含む接合層130が設けられた、電子装置100Aが得られる。
図6は第2の実施の形態に係る電子装置の別例を示す図である。図6には、第2の実施の形態に係る電子装置の別例の要部断面を模式的に図示している。
このようにして半田141aが搭載された半導体チップ120を用い、例えば、上記図4の例に従い、電極11上にPd層133及びAu層134を設けた回路基板110との接合を行うことで、上記図6のような電子装置100Bを得ることができる。
図8は接合部の断面組織の一例を示す図である。
図8には、NiPdAu電極上に上記組成条件のInSnAg半田を150℃で接合した時における電極と半田の接合部の断面について元素分析を行った結果を示している。図8において、指定の元素が含有されていない場合は黒く表示されており、指定の元素が含有されている場合はその含有量に応じて白く表示されている。図8(A)はAgの分析結果、図8(B)はPdの分析結果、図8(C)はInの分析結果、図8(D)はAuの分析結果、図8(E)はSnの分析結果、図8(F)はNiの分析結果である。
図9には、NiAu電極上に上記組成条件のInSnAg半田を150℃で接合した時における電極と半田の接合部の断面について元素分析を行った結果を示している。図9において、指定の元素が含有されていない場合は黒く表示されており、指定の元素が含有されている場合はその含有量に応じて白く表示されている。図9(A)及び図9(B)はそれぞれ接合初期のSn(図9(A))及びNi(図9(B))の分析結果、図9(C)及び図9(D)はそれぞれ接合後期のSn(図9(C))及びNi(図9(D))の分析結果である。
一方、電極と半田の接合部にPdAg含有層のみを設けようとしても、Pdは半田内部に拡散してしまうことが知られており、電極と半田の接合部にはPdAg含有層を安定的に存在させることができない。InAu含有層は、Pdの半田内部への拡散を抑え、PdAg含有層を形成するのに寄与する。
図10には、高速シェア試験後の破断面の走査型電子顕微鏡(Scanning Electron Microscope;SEM)像を例示している。高速シェア試験は、NiPdAu電極上にInSnAg半田、InSn共晶半田、SnAgCu半田をそれぞれ接合した試料について、3000mm/sのシェア速度で行った。図10(A)はNiPdAu電極上にInSnAg半田を接合した試料の破断面のSEM像である。図10(B)はNiPdAu電極上にInSn共晶半田を接合した試料の破断面のSEM像である。図10(C)はNiPdAu電極上にSnAgCu半田を接合した試料の破断面のSEM像である。
図11は高速シェア試験の結果の一例を示す図である。
図12は第3の実施の形態に係る電子装置の一例を示す図である。図12には、第3の実施の形態に係る電子装置の一例の要部断面を模式的に図示している。
半導体チップ310は、半導体基板を用いて形成されたトランジスタ等の回路素子(図示せず)を含み、その回路素子に電気的に接続された導体部である配線314及びビア315、並びに、そのような導体部に電気的に接続された複数の電極311を有している。半導体チップ310の表面には、各電極311の少なくとも一部が露出するように保護膜313が設けられている。
図14は第3の実施の形態に係る電子装置の製造方法の第2例を示す図である。図14には、半導体チップを実装したインターポーザと回路基板とを接合する工程の別例の要部断面を模式的に図示している。
尚、電極331上にPdAg層365及びInAu層366を積層する方法に替えて、Pd層、Ag層、In層及びAu層を積層する方法を用いることもできる。
(付記1) 第1電極を有する第1電子部品と、
前記第1電極の上方に設けられた半田と、
前記第1電極と前記半田との間に設けられ、Pd、Ag及びInを含有する第1接合層と
を含むことを特徴とする電子装置。
前記第1電極の上方に設けられ、Pd及びAgを含有する第1層と、
前記第1層の上方に設けられ、Inを含有する第2層と
を含むことを特徴とする付記1に記載の電子装置。
(付記4) 前記第1層は、PdAg合金層又はPdAgIn合金層であることを特徴とする付記2又は3に記載の電子装置。
(付記6) 前記第2層は、InAu合金層又はInAuPd合金層であることを特徴とする付記2乃至5のいずれかに記載の電子装置。
前記半田は、Snを含有することを特徴とする付記1乃至6のいずれかに記載の電子装置。
電極層と、
前記電極層の上方に設けられたバリアメタル層と
を含むことを特徴とする付記1乃至7のいずれかに記載の電子装置。
前記半田と前記第2電極との間に設けられ、Pd、Ag及びInを含有する第2接合層と
を更に含むことを特徴とする付記1乃至8のいずれかに記載の電子装置。
加熱により前記半田を溶融し、前記電極と前記半田の間に、Pd、Ag及びInを含有する接合層を形成する工程と
を含むことを特徴とする電子装置の製造方法。
加熱により前記半田を溶融し、前記電極と前記半田の間に、Pd、Ag及びInを含有する接合層を形成する工程と
を含むことを特徴とする電子装置の製造方法。
(付記14) 前記接合層は、
前記電極の上方に設けられ、Pd及びAgを含有する第1層と、
前記第1層の上方に設けられ、Inを含有する第2層と
を含むことを特徴とする付記10乃至13のいずれかに記載の電子装置の製造方法。
10,20 電子部品
11,111,121,311,321a,321b,331 電極
30A,30B,130,150,360 接合層
31,131,151,361 第1層
32,132,152,362 第2層
40,140,141,141a,141aa,142,340,350,351,352 半田
110,330 回路基板
111a 電極層
111b バリアメタル層
112,322,332 基板
113,313,323,333 保護膜
120,310 半導体チップ
133,153,363 Pd層
134,154,364 Au層
135,365 PdAg層
136,366 InAu層
200a,200b,200c,200d,200e,200f 領域
250b,250c 亀裂
314,324,334 配線
315,325,335 ビア
320 インターポーザ
Claims (7)
- 第1電極を有する第1電子部品と、
前記第1電極の上方に設けられた半田と、
前記第1電極と前記半田との間に設けられ、Pd、Ag及びInを含有する第1接合層と
を含むことを特徴とする電子装置。 - 前記第1接合層は、
前記第1電極の上方に設けられ、Pd及びAgを含有する第1層と、
前記第1層の上方に設けられ、Inを含有する第2層と
を含むことを特徴とする請求項1に記載の電子装置。 - 前記第1層は、Pdを主成分とすることを特徴とする請求項2に記載の電子装置。
- 前記第2層は、Inを主成分とすることを特徴とする請求項2又は3に記載の電子装置。
- 前記半田を介して前記第1電極に対向する第2電極を有する第2電子部品と、
前記半田と前記第2電極との間に設けられ、Pd、Ag及びInを含有する第2接合層と
を更に含むことを特徴とする請求項1乃至4のいずれかに記載の電子装置。 - 電子部品の電極の上方に設けられた、Pdを含有する層の上方に、In及びAgを含有する半田を設ける工程と、
加熱により前記半田を溶融し、前記電極と前記半田の間に、Pd、Ag及びInを含有する接合層を形成する工程と
を含むことを特徴とする電子装置の製造方法。 - 電子部品の電極の上方に、Pd及びAgを含有する層を介して設けられた、Inを含有する層の上方に、半田を設ける工程と、
加熱により前記半田を溶融し、前記電極と前記半田の間に、Pd、Ag及びInを含有する接合層を形成する工程と
を含むことを特徴とする電子装置の製造方法。
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