JP2016134516A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can achieve downsizing and has excellent radiation property and excellent reliability; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 1 includes a semiconductor chip 20 having an element formation surface 22 where a semiconductor element is formed and a support substrate 21 for supporting the semiconductor chip 20. The semiconductor device 1 includes an electrode 35 formed on the element formation surface 22 of the semiconductor chip 20 and an encapsulation resin 3 which covers the element formation surface 22 and a lateral face 24 of the semiconductor chip 20 and a lateral face 27 of the support substrate 21. The electrode 35 formed on the element formation surface 22 of the semiconductor chip 20 is exposed from the encapsulation resin 3 to form an external terminal 13. A rear face 26 of the support substrate 21 forms an exposed surface 11 exposed outward from the encapsulation resin 3.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Patent Document 1 discloses a semiconductor device including a substrate, a rewiring formed on the substrate, a sealing film that covers the upper surface and side surfaces of the substrate, and a resin film that includes a support film that covers the lower surface of the substrate. doing.

JP 2011-181858 A

  An object of the present invention is to provide a semiconductor device that can be miniaturized, has excellent heat dissipation, and is excellent in reliability, and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to the present invention includes an element forming surface on which a semiconductor element is formed, a back surface located on the opposite side of the element forming surface, and a side surface connecting the element forming surface and the back surface. Covering the element forming surface and the side surface of the substrate so as to expose the electrode, and an electrode formed on the element forming surface so as to be electrically connected to the semiconductor element. And a resin that exposes the back surface.

  According to this configuration, the back surface of the substrate forms an exposed surface exposed to the outside from the resin. Therefore, the heat generated in the substrate, particularly the semiconductor element, can be dissipated to the outside from the back surface of the substrate. Thereby, since the temperature rise in a semiconductor device can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. As a result, it is possible to provide a semiconductor device having excellent heat dissipation and excellent reliability. In addition, since the resin covering the element formation surface and the side surface of the substrate can also serve as a package, a small semiconductor device can be provided.

The back surface of the substrate forming the exposed surface preferably has an area larger than the area of the element forming surface. According to this configuration, the heat generated in the substrate can be effectively dissipated to the outside. Thereby, since the temperature rise in a semiconductor device can be suppressed effectively, the reliability of a semiconductor device can be improved further.
The electrode may form an external terminal in a region surrounded by a periphery of the element formation surface in a plan view as viewed from the normal direction of the element formation surface. According to this configuration, it is possible to provide a Fan-in type semiconductor device in which an external terminal is formed in a region surrounded by the periphery of the element formation surface in plan view.

The semiconductor device is electrically connected to the electrode, and in a plan view viewed from the normal direction of the element formation surface, a rewiring that extends outside a region surrounded by a periphery of the element formation surface; and the rewiring And an external terminal that is at least partially located outside the region surrounded by the periphery of the element formation surface in the plan view.
According to this configuration, since the resin is formed so as to cover the side surface of the substrate, the region on the resin outside the substrate can be used as a region for forming the rewiring in a plan view. Therefore, the arrangement of the external terminals that are electrically connected to the rewiring is not limited to the region immediately above the element formation surface of the substrate. Thus, a Fan-Out type semiconductor device in which external terminals are formed in a region outside the element formation surface of the substrate can be provided. With the Fan-Out type, a large number of external terminals can be provided.

  The substrate connects a first surface as the element formation surface, a first back surface located on the opposite side of the element formation surface, the first surface and the first back surface, and A semiconductor chip having a first side surface forming a part, a second surface bonded to the first back surface of the semiconductor chip to support the semiconductor chip, and located on the opposite side of the second surface, A support substrate having a second back surface that forms the back surface of the substrate, and a second side surface that connects the second surface and the second back surface and forms part of the side surface of the substrate.

According to this configuration, since the semiconductor chip is supported by the support substrate from the first back surface side and the first side surface is covered with the resin, it is not exposed to the outside from the resin. Thereby, since the influence from the outside with respect to a semiconductor chip can be reduced, the electrical property of a semiconductor chip can be kept favorable.
Further, heat generated in the semiconductor chip can be dissipated to the outside from the back surface (exposed surface) of the support substrate. Thereby, since the temperature rise in a semiconductor device can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. Thereby, the semiconductor device which has the outstanding heat dissipation and was excellent in reliability according to it can be provided. In addition, since the resin that covers the semiconductor chip and the support substrate can also serve as a package, the semiconductor device can be downsized.

  The support substrate preferably has an area larger than the area of the semiconductor chip in a plan view as viewed from the normal direction of the element formation surface. According to this configuration, since the back surface (exposed surface) of the support substrate has an area larger than the area of the element formation surface of the semiconductor chip, heat generated in the semiconductor chip can be effectively dissipated to the outside. Can do. Thereby, since the temperature rise in a semiconductor device can be suppressed effectively, the reliability of a semiconductor device can be improved further.

  The support substrate preferably includes the same type of semiconductor material as the semiconductor chip. According to this configuration, since the thermal expansion coefficients of the semiconductor chip and the support substrate can be made substantially equal, the bonding between the semiconductor chip and the support substrate can be stably maintained regardless of the temperature change. Therefore, it is possible to provide a highly reliable semiconductor device with high durability against thermal cycles. In addition, since the thermal coupling between the semiconductor chip and the support substrate can be stably maintained, the heat generated in the semiconductor chip can be favorably transmitted to the support substrate, so that the reliability of the semiconductor device can be improved.

  The support substrate is preferably an impurity-free silicon substrate. According to this configuration, the support substrate has a high resistivity (for example, a resistivity higher than that of the semiconductor chip). Such a support substrate can effectively suppress the inflow of current from the semiconductor chip. Thereby, the fluctuation | variation of the undesirable electrical characteristic in a semiconductor chip can be suppressed, and generation | occurrence | production of the heat | fever in a support substrate can be suppressed collectively. In addition, since the impurity-free silicon substrate has good thermal conductivity (for example, about the same as that of a semiconductor chip), the second back surface (exposed surface) exposed to the outside is quickly conducted by conducting heat generated in the semiconductor chip. Efficiently dissipate from. Thereby, the temperature rise of the semiconductor device can be effectively suppressed, and therefore a highly reliable semiconductor device can be provided.

  The substrate may further include a metal film interposed between the semiconductor chip and the support substrate and bonding the semiconductor chip to the support substrate. According to this configuration, the semiconductor chip can be fixed on the support substrate via the metal film. Thereby, it can suppress that a semiconductor chip peels from a support substrate. Since the thermal conductivity of the metal film is high, the thermal conduction between the semiconductor chip and the support substrate is good. Therefore, the heat generated in the semiconductor chip can be satisfactorily transmitted to the support substrate. Further, even when there is a difference in the coefficient of thermal expansion between the semiconductor chip and the support substrate, the difference in thermal expansion / shrinkage between them can be absorbed by the ductility of the metal film. Therefore, the bonding between the semiconductor chip and the support substrate is highly durable against thermal cycling. Accordingly, since the mechanical coupling and the thermal coupling between the semiconductor chip and the support substrate can be maintained, the reliability of the semiconductor device can be improved.

The metal film preferably contains solder or a metal adhesive. If the metal film is solder or a metal adhesive, the semiconductor chip can be satisfactorily fixed to the support substrate. Thereby, it can suppress effectively that a semiconductor chip peels from a support substrate.
The resin preferably covers the entire area of the first side surface of the semiconductor chip and the entire area of the second side surface of the support substrate. According to this configuration, the semiconductor chip and the support substrate can be well protected by the resin.

  The substrate may be a semiconductor chip. In this case, the element formation surface may be a first main surface of the semiconductor chip, and the back surface may be a second main surface opposite to the first main surface of the semiconductor chip. According to this configuration, since the second main surface of the semiconductor chip forms an exposed surface exposed from the resin to the outside, the heat generated in the semiconductor chip can be dissipated to the outside. Thereby, since the temperature rise in a semiconductor device can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. As a result, it is possible to provide a semiconductor device having excellent heat dissipation and excellent reliability. Further, since the resin covering the element formation surface and the side surface of the semiconductor chip can also serve as a package, the semiconductor device can be reduced in size.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a plurality of semiconductor chips each having an element formation surface on which a semiconductor element is formed, and having electrodes formed on the element formation surface; A step of preparing a support substrate in which a plurality of chip placement regions are set, and a step of forming a trench on the surface side of the support substrate so as to partition the chip placement region set on the surface of the support substrate A step of arranging the plurality of semiconductor chips in the plurality of chip arrangement regions on the support substrate, respectively, and covering the support substrate with a resin so as to fill the trench and cover the plurality of semiconductor chips. Thus, a sealing structure forming step for forming a sealing structure in which the plurality of semiconductor chips are sealed with the resin, and the electric power formed on the semiconductor chip are performed. And exposing the semiconductor chip to a plurality of semiconductor devices each sealed with the resin by cutting the sealing structure along the trench. And a singulation process.

  According to this method, in the sealing structure forming step, the semiconductor chip is not exposed to the outside from the resin because the element forming surface and side surfaces are covered with the resin and the back surface side is supported by the support substrate. Thereby, since the influence from the outside with respect to a semiconductor chip is reduced, the electrical property of a semiconductor chip can be kept favorable. On the other hand, since the singulation process is performed in a state where the back surface of the support substrate is exposed to the outside from the resin, in the semiconductor device, the back surface of the support substrate is an exposed surface exposed from the resin to the outside.

  As a result, the heat generated in the semiconductor chip can be dissipated from the exposed surface of the support substrate to the outside, so that the temperature increase in the semiconductor device can be suppressed, so that fluctuations in the electrical characteristics of the semiconductor element accompanying the temperature increase can be suppressed. . As a result, it is possible to manufacture a semiconductor device having excellent heat dissipation and correspondingly high reliability. Furthermore, since the resin which covers the element formation surface and side surface of the semiconductor chip and the side surface of the support substrate can also serve as a package, the semiconductor device can be reduced in size.

In the step of preparing the support substrate, it is preferable that the chip arrangement region having an area larger than the area of the semiconductor chip is set in a plan view as viewed from the normal direction of the surface of the support substrate.
According to this method, since the chip placement area in the support substrate has an area larger than the area of the semiconductor chip, inconvenience caused by the misalignment of the semiconductor chip during the step of placing the semiconductor chip is suppressed. it can. Thereby, the yield can be improved and the reliability of the semiconductor device can be improved. In addition, since the sealing structure is cut along the trench that divides the chip arrangement region, in the semiconductor device obtained after the singulation process, the back surface of the support substrate has an area larger than the area of the semiconductor chip in plan view. An exposed surface having Therefore, a semiconductor device having a structure that effectively dissipates heat generated in the semiconductor chip to the outside can be manufactured.

  In the step of preparing the support substrate, the support substrate including the same type of semiconductor material as the semiconductor chip may be prepared. According to this method, the thermal expansion coefficient of the support substrate is substantially equal to that of the semiconductor chip. Therefore, the bonding between the semiconductor chip and the support substrate can be stably maintained regardless of the temperature change. As a result, it is possible to manufacture a semiconductor device that has high durability against thermal cycles and thereby improved reliability. In addition, since the thermal coupling between the semiconductor chip and the support substrate can be stably maintained, the heat generated in the semiconductor chip can be favorably transmitted to the support substrate. This also provides a highly reliable semiconductor device.

  In the step of preparing the support substrate, an impurity-free silicon substrate is preferably prepared as the support substrate. According to this method, a support substrate having a high resistivity (for example, a resistivity higher than that of a semiconductor chip) is prepared. Such a support substrate can effectively suppress the inflow of current from the semiconductor chip. Thereby, the fluctuation | variation of the undesirable electrical characteristic in a semiconductor chip can be suppressed, and generation | occurrence | production of the heat | fever in a support substrate can be suppressed collectively. Moreover, since the impurity-free silicon substrate has good thermal conductivity (for example, about the same level as that of a semiconductor chip), heat generated in the semiconductor chip is quickly conducted, and efficiency is improved from the back surface (exposed surface) exposed to the outside. Dissipate. Thereby, the temperature rise of the semiconductor device can be effectively suppressed, and therefore a highly reliable semiconductor device can be provided. Further, according to this method, since silicon that is relatively easily available is used as the support substrate, the manufacturing cost can be reduced.

  The step of disposing the semiconductor chip comprises joining the back surface of the semiconductor chip opposite to the element formation surface and the front surface of the support substrate with a metal film, thereby attaching the semiconductor chip to the support substrate. It is preferable to include a step of fixing to the chip arrangement region. According to this method, the semiconductor chip is fixed to the support substrate by the metal film. Thereby, since it can suppress that a semiconductor chip peels from a support substrate, it can control effectively that a semiconductor chip shifts after a semiconductor chip arrangement process. As a result, the yield can be effectively improved and the reliability of the semiconductor device can be further improved.

  Moreover, since the thermal conductivity of the metal film is high, the thermal conduction between the semiconductor chip and the support substrate is good. Therefore, the heat generated in the semiconductor chip can be satisfactorily transmitted to the support substrate. Further, even when there is a difference in the coefficient of thermal expansion between the semiconductor chip and the support substrate, the difference in thermal expansion / shrinkage between them can be absorbed by the ductility of the metal film. Therefore, the bonding between the semiconductor chip and the support substrate is highly durable against thermal cycling. Accordingly, since the mechanical coupling and the thermal coupling between the semiconductor chip and the support substrate can be maintained, a semiconductor device with improved reliability can be manufactured.

The metal film preferably contains solder or a metal adhesive. According to this method, the semiconductor chip can be satisfactorily fixed to the support substrate. Thereby, it can suppress effectively that a semiconductor chip peels from a support substrate.
The electrode exposure step may also serve as a step of forming the electrode as an external terminal located in a region surrounded by a side surface of the semiconductor chip in a plan view as viewed from the normal direction of the element formation surface. Good. According to this method, since the step of exposing the electrode also serves as the step of forming the external terminal, the Fan-in type semiconductor device in which the external terminal is located in a region surrounded by the side surface of the semiconductor chip in plan view Can be manufactured.

  In the method, after the electrode exposure step, prior to the individualization step, the side surface of the semiconductor chip is electrically connected to the electrode and viewed from the normal direction of the element formation surface. A step of forming a rewiring that crosses the outside of the region surrounded by the side surface of the semiconductor chip, and an external terminal at least partially located outside the region surrounded by the side surface of the semiconductor chip in the plan view. And a forming step.

  According to this method, since the resin is formed so as to cover the side surface of the semiconductor chip, a region on the resin outside the semiconductor chip can be used as a region for forming a rewiring in a plan view. Therefore, the region where the external terminal electrically connected to the rewiring is formed is not limited to the region directly above the element formation surface of the semiconductor chip. Accordingly, a Fan-Out type semiconductor device in which external terminals are formed in a region outside the semiconductor chip can be provided.

In the singulation step, a cutting groove having a bottom in the trench is formed by digging a part of the sealing structure along the trench from the element forming surface side with a width narrower than the width of the trench. The step of forming the sealing structure and the step of grinding the back surface of the support substrate opposite to the front surface until the cutting groove is exposed may be included.
According to this method, it is possible to manufacture a semiconductor device in which the entire element formation surface of the semiconductor chip, the entire side surface of the semiconductor chip, and the entire side surface of the support substrate are covered with the resin. Thereby, the semiconductor device which can protect a semiconductor chip and a support substrate favorably with resin can be provided.

  The singulation step includes digging down a part of the sealing structure along the trench from the element formation surface side with a width narrower than the width of the trench, and thereby the element formation surface of the semiconductor chip and the element Forming a cutting groove in the sealing structure having a bottom portion located at a depth between the bottom portion of the trench, and the supporting substrate until the cutting groove is exposed and all of the supporting substrate is removed. And a step of grinding a back surface opposite to the front surface.

  According to this method, it is possible to provide a semiconductor device having a structure in which the back surface of the semiconductor chip forms an exposed surface exposed from the resin to the outside. This semiconductor device can dissipate the heat generated in the semiconductor chip to the outside from the back surface. Thereby, since the temperature rise in a semiconductor device can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. As a result, it is possible to provide a semiconductor device having excellent heat dissipation and excellent reliability. Further, since the resin covering the element formation surface and the side surface of the semiconductor chip can also serve as a package, the semiconductor device can be reduced in size. Furthermore, the entire region of the element formation surface of the semiconductor chip and the entire side surface of the semiconductor chip are covered with resin. Thereby, the semiconductor device which can protect a semiconductor chip favorably with resin can be provided.

FIG. 1 is a perspective view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 4 is a partially enlarged cross-sectional view of the configuration of FIG. FIG. 5 is a process diagram showing an example of a manufacturing method of the semiconductor device shown in FIG. FIG. 6 is a plan view of a support substrate used in the method for manufacturing the semiconductor device shown in FIG. FIG. 7 is an enlarged plan view of a region surrounded by a broken line shown in FIG. FIG. 8 is a cross-sectional view of the support member shown in FIG. FIG. 9 is a cross-sectional view showing the next step of FIG. FIG. 10 is a plan view of a semiconductor wafer used in the method for manufacturing the semiconductor device shown in FIG. FIG. 11 is an enlarged plan view of a region surrounded by a broken line shown in FIG. 12 is a cross-sectional view of the semiconductor wafer shown in FIG. FIG. 13 is a cross-sectional view showing the next step of FIG. FIG. 14 is a cross-sectional view showing the next step of FIG. FIG. 15 is a cross-sectional view showing a step subsequent to FIG. FIG. 16 is a cross-sectional view showing the next step of FIG. FIG. 17 is a cross-sectional view showing the next step of FIG. 18 is a cross-sectional view showing the next step of FIG. FIG. 19 is a cross-sectional view showing the next step of FIG. FIG. 20 is a cross-sectional view showing the next step of FIG. FIG. 21 is a bottom view of a semiconductor device according to the second embodiment of the present invention. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. FIG. 23 is a partial enlarged cross-sectional view of the configuration of FIG. FIG. 24 is a process diagram showing an example of a manufacturing method of the semiconductor device shown in FIG. FIG. 25 is a process diagram showing an example of a rewiring structure forming process shown in FIG. 26 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 27 is a cross-sectional view showing a step subsequent to FIG. FIG. 28 is a cross-sectional view showing a step subsequent to FIG. FIG. 29 is a cross-sectional view showing a step subsequent to FIG. FIG. 30 is a cross-sectional view showing the next step of FIG. FIG. 31 is a sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 32 is a bottom view of the semiconductor device according to the fourth embodiment of the present invention. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. FIG. 34 is a cross-sectional view of a semiconductor device according to a modification. FIG. 35 is a cross-sectional view showing an example of a method of manufacturing the semiconductor device shown in FIG. FIG. 36 is a cross-sectional view showing a step subsequent to FIG. FIG. 37 is a cross-sectional view of a semiconductor device according to another modification. FIG. 38 is a cross-sectional view of a semiconductor device according to still another modification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a perspective view of a semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device 1 shown in FIG.
The semiconductor device 1 includes a sealing structure 4 in which a substrate 2 including a semiconductor element is sealed with a sealing resin 3. The sealing structure 4 has a substantially rectangular parallelepiped shape. The sealing structure 4 includes a front surface 5, a back surface 6, and four side surfaces 7 that connect the front surface 5 and the back surface 6. The sealing resin 3 also serves as a package for sealing the substrate 2.

In this embodiment, the substrate 2 is formed in a substantially rectangular shape in plan view when viewed from the normal direction of the surface 5. As will be described later, the substrate 2 has a front surface 8, a back surface 9 located on the opposite side of the front surface 8, and four side surfaces 10 connecting the front surface 8 and the back surface 9.
The sealing resin 3 covers the front surface 8 and the side surface 10 of the substrate 2 so as to surround the back surface 9 of the substrate 2. Thereby, the back surface 9 of the substrate 2 forms an exposed surface 11 having a substantially rectangular shape in plan view exposed from the sealing resin 3 to the outside. A surface 5 of the sealing structure 4 is formed by the exposed surface 11 of the substrate 2 and the sealing resin 3. On the other hand, the back surface 6 and the side surface 7 of the sealing structure 4 are formed by the sealing resin 3.

An index 12 indicating the mounting direction is formed on the surface 5 of the sealing structure 4. More specifically, the index 12 is formed at the corner of the exposed surface 11 of the substrate 2. In this embodiment, the index 12 is a mark formed on the exposed surface 11. The index 12 may be a recess that is recessed from the exposed surface 11 toward the back surface 6 side of the sealing structure 4.
As shown in FIG. 2, a plurality (four in this embodiment) of external terminals 13 are formed on the back surface 6 of the sealing structure 4 so as to be exposed from the sealing resin 3. The plurality of external terminals 13 are arranged with a space between each other, and each is formed in a substantially rectangular shape. The plurality of external terminals 13 are arranged at intervals from the side surface 7 of the sealing structure 4 inward. The plurality of external terminals 13 are connected to wiring provided on the mounting board by, for example, solder.

FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 4 is a partially enlarged cross-sectional view of the configuration of FIG.
The substrate 2 includes a semiconductor chip 20 and a support substrate 21 that supports the semiconductor chip 20. The semiconductor chip 20 has, for example, a substantially rectangular parallelepiped shape. The semiconductor chip 20 has a surface 22 on which a semiconductor element is formed, a back surface 23 located on the opposite side of the surface 22, and four side surfaces 24 that connect the surface 22 and the back surface 23. The surface 22 of the semiconductor chip 20 corresponds to the surface 8 of the substrate 2. Hereinafter, the surface 22 of the semiconductor chip 20 (the surface 8 of the substrate 2) is referred to as an “element formation surface 22”. The side surface 24 of the semiconductor chip 20 forms a part of the side surface 10 of the substrate 2. The semiconductor chip 20 includes silicon. The area of the element formation surface 22 of the semiconductor chip 20 may be, for example, 0.2 mm ² or more and 10 mm ² or less. The thickness T1 of the semiconductor chip 20 may be, for example, 0.01 mm or more and 1 mm or less (more specifically, 0.05 mm or more and 0.775 mm or less).

  The semiconductor element includes, for example, various semiconductor elements formed using a semiconductor. As an example, the semiconductor element may include a transistor, a diode, or the like. The semiconductor element is a part of an integrated circuit such as SSI (Small Scale Integration), LSI (Large Scale Integration), MSI (Medium Scale Integration), VLSI (Very Large Scale Integration) or ULSI (Ultra-Very Large Scale Integration). It may be formed. Further, the semiconductor element may form a part of a voltage control element such as LDO (Low Drop Out) or a part of an amplification element such as an OP amplifier.

  The support substrate 21 has, for example, a substantially rectangular parallelepiped shape. The support substrate 21 is bonded to the back surface 23 of the semiconductor chip 20 to support the semiconductor chip 20, the back surface 26 located on the opposite side of the front surface 25, and the four side surfaces 27 connecting the front surface 25 and the back surface 26. And have. The back surface 26 of the support substrate 21 corresponds to the back surface 9 of the substrate 2. That is, the back surface 26 of the support substrate 21 forms the exposed surface 11 exposed from the sealing resin 3 to the outside. The side surface 27 of the support substrate 21 forms a part of the side surface 10 of the substrate 2.

The exposed surface 11 of the support substrate 21 has an area larger than the area of the element formation surface 22 of the semiconductor chip 20 in a plan view (hereinafter simply referred to as “plan view”) viewed from the normal direction of the element formation surface 22. doing. Area of the exposed surface 11 of the supporting substrate 21, for example 0.2 mm ² or more 15 mm ² or less (more specifically, 0.21 mm ² or more 10.9 mm ² or less) may be used. The thickness T2 of the support substrate 21 may be, for example, not less than 0.01 mm and not more than 1 mm (more specifically, not less than 0.05 mm and not more than 0.775 mm). The thickness T2 of the support substrate 21 may be larger or smaller than the thickness T1 of the semiconductor chip 20. Furthermore, the thickness T2 of the support substrate 21 may be substantially the same as the thickness T1 of the semiconductor chip 20.

The support substrate 21 may contain the same type of semiconductor material as the semiconductor chip 20. In this embodiment, an example will be described in which the support substrate 21 is an impurity-free silicon substrate containing silicon to which no impurity is added.
The support substrate 21 is a substrate having a thermal conductivity substantially equal to the thermal conductivity of the semiconductor chip 20 instead of the impurity-free silicon substrate, or a thermal conductivity higher than the thermal conductivity of the semiconductor chip 20. It may be a substrate. Examples of the substrate having a thermal conductivity higher than that of the semiconductor chip 20 include an alumina (aluminum oxide) substrate, a ceramic substrate, an alumina ceramic substrate, a copper substrate, and an aluminum substrate.

Further, the support substrate 21 may be a substrate having a resistivity higher than that of the semiconductor chip 20 instead of the impurity-free silicon substrate. Examples of the substrate having a resistivity higher than that of the semiconductor chip 20 include an alumina (aluminum oxide) substrate, a ceramic substrate, an alumina ceramic substrate, and a glass substrate.
The substrate 2 further includes a metal film 28 that fixes the semiconductor chip 20 and the support substrate 21. The metal film 28 is interposed between the semiconductor chip 20 and the support substrate 21, and fixes the semiconductor chip 20 on the support substrate 21. The metal film 28 may contain solder or a metal adhesive.

  For example, the solder may be an alloy containing at least two selected from the group consisting of tin, lead, phosphorus, silver, copper, nickel, germanium, bismuth, indium, zinc, aluminum, antimony, and cobalt. The solder may be, for example, an alloy containing tin and lead, an alloy containing tin and phosphorus, or an alloy containing tin and antimony. On the other hand, the metal adhesive may be, for example, a paste containing silver, gold, platinum, or copper.

  As shown in FIG. 4, a wiring film 29 electrically connected to the semiconductor element is formed on the element formation surface 22 of the semiconductor chip 20. The wiring film 29 may be an aluminum film, for example. In this embodiment, an example is shown in which the wiring film 29 is formed as the lowermost layer wiring in contact with the element formation surface 22. For example, when a multilayer wiring structure is formed on the element formation surface 22 of the semiconductor chip 20, the wiring film 29 may be formed as the uppermost layer wiring exposed from the outermost surface of the multilayer wiring structure. In this case, the multilayer wiring structure electrically connects a plurality of insulating layers formed on the element formation surface 22, a plurality of wiring layers interposed between the plurality of insulating layers, and a wiring layer disposed above and below the insulating layer. May be connected via via electrode.

  An insulating film 30 is formed so as to cover the entire area of the element formation surface 22 of the semiconductor chip 20. As shown in FIG. 4, the insulating film 30 has a laminated structure including a passivation film 31 and a resin film 32. The passivation film 31 may be a nitride film, for example. Resin film 32 may be, for example, a polyimide film. A pad opening 34 is formed in the insulating film 30 to expose a part of the wiring film 29 as an electrode pad 33. On the element formation surface 22, an electrode 35 that is electrically connected to the wiring film 29 and forms the external terminal 13 is formed.

  More specifically, the electrode 35 is formed in a region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. The electrode 35 has a stacked structure including a first electrode layer 36 and a second electrode layer 37. As shown in FIG. 4, the first electrode layer 36 is embedded in the pad opening 34. The first electrode layer 36 may include a copper film, a gold film, or a nickel film. On the other hand, the second electrode layer 37 is formed on the first electrode layer 36 so as to be electrically connected to the first electrode layer 36. The second electrode layer 37 may be formed as a post electrode including a copper film, for example.

  Sealing resin 3 is formed so as to cover substrate 2 (semiconductor chip 20 and support substrate 21). More specifically, the sealing resin 3 covers the first portion 38 that covers the entire area of the element formation surface 22 (insulating film 30) of the semiconductor chip 20 and the entire area of the side surface 24 of the semiconductor chip 20, and supports the support substrate. The second portion 39 formed on the surface 25 of the substrate 21 and the third portion 40 that covers the entire side surface 27 of the support substrate 21 are integrally provided.

  The first portion 38 of the sealing resin 3 covers the entire region of the insulating film 30 so that the electrode 35 (second electrode layer 37) is exposed. The first portion 38 of the sealing resin 3 is formed so that the surface of the electrode 35 (second electrode layer 37) is flush with the back surface 6 of the sealing structure 4. Thereby, a portion of the second electrode layer 37 exposed from the first portion 38 of the sealing resin 3 is formed as the external terminal 13.

The back surface 6 of the sealing structure 4 is formed flat by the first portion 38 and the second portion 39 of the sealing resin 3. The side surface 7 of the sealing structure 4 is formed flat by the second portion 39 and the third portion 40 of the sealing resin 3. The surface 5 of the sealing structure 4 is formed flat by the third portion 40 of the sealing resin 3 and the exposed surface 11 of the support substrate 21.
The thickness T3 of the second portion 39 of the sealing resin 3 in the normal direction of the side surface 24 of the semiconductor chip 20 is the thickness T4 of the third portion 40 of the sealing resin 3 in the normal direction of the side surface 27 of the support substrate 21. Bigger than. The thickness T3 of the second portion 39 of the sealing resin 3 may be, for example, 0.01 mm to 1 mm (more specifically, 0.05 mm to 0.5 mm). The thickness T4 of the third portion 40 of the sealing resin 3 may be, for example, 0.01 mm or more and 1 mm or less (more specifically, 0.05 mm or more and 0.5 mm or less).

  According to the configuration of this embodiment, the back surface 9 of the substrate 2 forms the exposed surface 11 exposed to the outside from the sealing resin 3. Therefore, the heat generated in the substrate 2, particularly the semiconductor element, can be dissipated to the outside from the back surface 9 of the substrate 2. Thereby, since the temperature rise in the semiconductor device 1 can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. As a result, it is possible to provide the semiconductor device 1 having excellent heat dissipation and excellent reliability accordingly.

More specifically, the substrate 2 includes a semiconductor chip 20 and a support substrate 21 that supports the semiconductor chip 20. The heat generated in the semiconductor chip 20 can be dissipated to the outside from the back surface 26 (exposed surface 11) of the support substrate 21. Thereby, since the temperature rise in the semiconductor device 1 can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying temperature rise can be suppressed.
Further, since the semiconductor chip 20 is supported by the support substrate 21 from the back surface 23 side and the side surface 24 is covered with the sealing resin 3, it is not exposed to the outside from the sealing resin 3. Thereby, since the influence from the outside with respect to the semiconductor chip 20 can be reduced, the electrical characteristic of the semiconductor chip 20 can be kept favorable. As a result, it is possible to provide the semiconductor device 1 having excellent heat dissipation and excellent reliability accordingly.

  The back surface 26 of the support substrate 21 that forms the exposed surface 11 has an area larger than the area of the element formation surface 22 of the semiconductor chip 20 in plan view. Thereby, the heat generated in the substrate 2 (semiconductor chip 20) can be effectively dissipated to the outside. As a result, since the temperature rise in the semiconductor device 1 can be effectively suppressed, the reliability of the semiconductor device 1 can be further improved.

  The support substrate 21 includes the same kind of semiconductor material as that of the semiconductor chip 20. More specifically, the semiconductor chip 20 includes silicon, and the support substrate 21 includes impurity-free silicon. Thereby, since the thermal expansion coefficients of the semiconductor chip 20 and the support substrate 21 can be made substantially equal, the bonding between the semiconductor chip 20 and the support substrate 21 can be stably maintained regardless of the temperature change. Therefore, it is possible to provide the semiconductor device 1 having high durability against thermal cycles and high reliability accordingly. In addition, since the thermal coupling between the semiconductor chip 20 and the support substrate 21 can be stably maintained, the heat generated in the semiconductor chip 20 can be transferred to the support substrate 21 satisfactorily. Can be improved.

  Furthermore, according to this configuration, the support substrate 21 has a higher resistivity than the semiconductor chip 20. Such a support substrate 21 can effectively suppress the inflow of current from the semiconductor chip 20. Thereby, the fluctuation | variation of the undesired electrical characteristic in the semiconductor chip 20 can be suppressed, and generation | occurrence | production of the heat | fever in the support substrate 21 can be suppressed collectively. In addition, since the impurity-free silicon substrate has good thermal conductivity (for example, about the same as that of the semiconductor chip 20), the heat generated in the semiconductor chip 20 is quickly conducted and exposed to the outside 26 (exposed surface). Efficiently dissipates from 11). Thereby, the temperature rise of the semiconductor device 1 can be effectively suppressed, and therefore the highly reliable semiconductor device 1 can be provided.

  The substrate 2 includes a metal film 28 interposed between the semiconductor chip 20 and the support substrate 21. Thereby, the semiconductor chip 20 can be satisfactorily fixed on the support substrate 21 via the solder or the metal adhesive as the metal film 28. Thereby, it can suppress effectively that the semiconductor chip 20 peels from the support substrate 21. FIG. Further, since the thermal conductivity of the metal film 28 is high, the thermal conduction between the semiconductor chip 20 and the support substrate 21 is good. Therefore, the heat generated in the semiconductor chip 20 can be transmitted to the support substrate 21 satisfactorily.

  Further, even when there is a difference in thermal expansion coefficient between the semiconductor chip 20 and the support substrate 21, the difference in thermal expansion / contraction between them can be absorbed by the ductility of the metal film 28. Therefore, the bonding between the semiconductor chip 20 and the support substrate 21 has high durability against thermal cycling. Accordingly, since the mechanical coupling and the thermal coupling between the semiconductor chip 20 and the support substrate 21 can be maintained, the reliability of the semiconductor device 1 can be improved.

In addition, the electrode 35 (second electrode layer 37) forms the external terminal 13 in a region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. Thereby, the Fan-in type semiconductor device 1 in which the external terminal 13 is located in a region surrounded by the side surface 24 of the semiconductor chip 20 in plan view can be provided.
The sealing resin 3 includes a first portion 38 that covers the entire area of the element forming surface 22 (insulating film 30) of the semiconductor chip 20, a second portion 39 that covers the entire area of the side surface 24 of the semiconductor chip 20, and a support substrate. 21 has a third portion 40 that covers the entire region of the side surface 27. Thereby, since the semiconductor chip 20 and the support substrate 21 can be protected by the sealing resin 3, the reliability of the semiconductor device 1 can be improved. In addition, since the sealing resin 3 also serves as a package for sealing the substrate 2, the semiconductor device 1 can be downsized.

FIG. 5 is a process diagram showing an example of a manufacturing method of the semiconductor device 1 shown in FIG. FIG. 6 is a plan view of a support substrate 21 used in the method for manufacturing the semiconductor device 1 shown in FIG. FIG. 7 is an enlarged plan view of a region D1 surrounded by a broken line shown in FIG. FIG. 8 is a cross-sectional view of the support member shown in FIG. FIG. 9 is a cross-sectional view showing the next step of FIG.
To manufacture the semiconductor device 1, first, as shown in FIGS. 6 to 8, a support substrate 50 is prepared (step S <b> 1: support substrate preparation). At this time, a support substrate 21 including the same type of semiconductor material as the semiconductor chip 20 may be prepared. In this embodiment, a semiconductor wafer to which no impurity is added is prepared as the support substrate 50. Hereinafter, the support substrate 50 is referred to as an “impurity-free semiconductor wafer 50”. The surface 51 of the impurity-free semiconductor wafer 50 corresponds to the surface 25 of the support substrate 21, and the back surface 52 of the impurity-free semiconductor wafer 50 corresponds to the back surface 26 (exposed surface 11) of the support substrate 21. .

  As shown in FIG. 7, on one surface of the impurity-free semiconductor wafer 50, a plurality of chip arrangement regions 53 in which a plurality of semiconductor chips 20 are arranged in a later step are set (two points in FIG. 7). (See chain line). The chip arrangement region 53 is set to an area larger than the area of the element formation surface 22 of the semiconductor chip 20 in a plan view viewed from the normal direction of the surface 51 of the impurity-free semiconductor wafer 50. In this embodiment, the plurality of chip arrangement regions 53 are set in a matrix at intervals from each other along the row direction and the column direction orthogonal to the row direction. A boundary region 54 is set between adjacent chip placement regions 53. The boundary region 54 is a belt-like region having a substantially constant width, and extends in two orthogonal directions and is formed in a lattice shape.

  Next, as shown in FIG. 9, a trench 55 that matches the boundary region 54 (see FIG. 7) is formed in the impurity-free semiconductor wafer 50 (step S2: trench formation). More specifically, first, a thermal oxide film 56 is formed on the surface 51 of the impurity-free semiconductor wafer 50 by, eg, thermal oxidation. Next, a resist mask (not shown) having an opening matching the boundary region 54 (see FIG. 7) is formed. Etching through the resist mask removes unnecessary portions of the thermal oxide film 56, and an opening 56 a that matches the boundary region 54 (see FIG. 7) is formed in the thermal oxide film 56. Thereafter, the resist mask is removed. Next, the surface is removed from the surface 51 of the impurity-free semiconductor wafer 50 to a predetermined depth by etching (for example, plasma etching) using the thermal oxide film 56 as a mask. As a result, trenches 55 that partition the chip placement region 53 are formed. Thereafter, the thermal oxide film 56 is removed.

FIG. 10 is a plan view of a semiconductor wafer 60 used in the method for manufacturing the semiconductor device 1 shown in FIG. FIG. 11 is an enlarged plan view of a region D2 surrounded by a broken line shown in FIG. FIG. 12 is a cross-sectional view of the semiconductor wafer 60 shown in FIG. 13-20 is sectional drawing which shows the process after FIG.
While the impurity-free semiconductor wafer 50 is prepared, the semiconductor chip 20 disposed on the impurity-free semiconductor wafer 50 is prepared. More specifically, as shown in FIGS. 10 to 12, first, a semiconductor wafer 60 is prepared (step S3: preparation of semiconductor wafer). The front surface 61 of the semiconductor wafer 60 corresponds to the element forming surface 22 of the semiconductor chip 20, and the back surface 62 of the semiconductor wafer 60 corresponds to the back surface 23 of the semiconductor chip 20.

  As shown in FIG. 11, a plurality of chip regions 63 corresponding to the plurality of semiconductor chips 20 are set on the surface 61 of the semiconductor wafer 60. The plurality of chip regions 63 are set in a matrix at intervals from each other along the row direction and the column direction orthogonal to the row direction. In each chip region 63, a semiconductor element is formed. A boundary region 64 through which a cutting line passes is set between adjacent chip regions 63. The boundary region 64 is a belt-like region having a substantially constant width and is formed in a lattice shape extending in two orthogonal directions.

  Next, a wiring film 29 (see FIG. 4) electrically connected to the semiconductor element is formed on the surface 61 of the semiconductor wafer 60 (step S4: wiring film formation). More specifically, an aluminum film is formed on element formation surface 22 by sputtering, for example. Next, the aluminum film is patterned by, for example, photolithography and etching to form the wiring film 29.

  Next, as shown in FIG. 13, the insulating film 30 is formed (Step S5: Insulating film formation). More specifically, first, a passivation film 31 (see FIG. 4) is formed so as to cover the wiring film 29 (see FIG. 4). Next, on the passivation film 31, for example, a resin film 32 (see FIG. 4) such as photosensitive polyimide is applied. The resin film 32 is developed after being exposed with a pattern corresponding to the pad opening 34. Thereafter, heat treatment for curing the resin film 32 is performed as necessary. Next, unnecessary portions of the passivation film 31 are removed by etching using the resin film 32 as a mask. Thereby, the insulating film 30 having the pad opening 34 exposing a part of the wiring film 29 as the electrode pad 33 is formed.

  Next, a plurality of electrodes 35 are formed in each chip region 63 (step S6: electrode formation). More specifically, the first electrode layer 36 is formed to fill the pad opening 34 and cover the insulating film 30 by, for example, sputtering. The first electrode layer 36 may be a nickel film, for example. Next, unnecessary portions of the first electrode layer 36 formed on the insulating film 30 are removed by etch back. As a result, the first electrode layer 36 is embedded in the pad opening 34.

Next, a resist mask (not shown) that selectively has an opening exposing the first electrode layer 36 is formed on the insulating film 30. Next, a copper film is formed in the opening by electroless plating or electrolytic plating. Thereafter, the resist mask is removed. Thereby, the electrode 35 including the first electrode layer and the second electrode layer 37 formed on the first electrode layer 36 is formed.
Next, a support tape 65 having an adhesive surface is attached to the front surface 61 or the back surface 62 of the semiconductor wafer 60, and the semiconductor wafer 60 is fixed to the support tape 65. In this embodiment, an example in which a support tape 65 is attached to the back surface 62 of the semiconductor wafer 60 is shown.

  Next, as shown in FIG. 14, the semiconductor wafer 60 is separated into semiconductor chips 20 (step S7: individualized into semiconductor chips). More specifically, in a state where the semiconductor wafer 60 is fixed to the support tape 65, along the boundary region 64 (see FIG. 11) set between the chip regions 63, the front surface 61 to the back surface 62 of the semiconductor wafer 60. The semiconductor wafer 60 is cut toward the surface. The semiconductor wafer 60 may be cut by a dicing blade or may be cut by etching. As a result, the semiconductor wafer 60 is separated into a plurality of semiconductor chips 20.

  Next, as shown in FIG. 15, a plurality of semiconductor chips 20 are arranged on the surface 51 of the impurity-free semiconductor wafer 50 (step S8: fixing the semiconductor chips to the support member). More specifically, the metal film 28 containing solder or a metal adhesive is formed on the chip arrangement region 53 (see also FIG. 7) of the impurity-free semiconductor wafer 50. Next, the semiconductor chip 20 is placed on the metal film 28 with the back surface 23 of the semiconductor chip 20 facing the chip placement region 53 of the impurity-free semiconductor wafer 50. Thereafter, the metal film 28 is heated, and the semiconductor chip 20 is fixed to the chip placement region 53 of the impurity-free semiconductor wafer 50.

  Next, as shown in FIG. 16, in a state where the plurality of semiconductor chips 20 are fixed to the impurity-free semiconductor wafer 50, the plurality of semiconductor chips 20 are collectively packed with the sealing resin 3 by, for example, coating or molding with epoxy resin. (Step S9: formation of a sealing structure). At this time, the sealing resin 3 fills the trench 55, covers the entire side surface 24 of the semiconductor chip 20 and the entire element formation surface 22, and covers the entire surface 51 of the impurity-free semiconductor wafer 50. It is formed. Thereafter, the sealing resin 3 is heated and the sealing resin 3 is cured. Thereby, the sealing structure 66 in which the plurality of semiconductor chips 20 are collectively sealed with the sealing resin 3 is formed.

  Next, as shown in FIG. 17, the sealing resin 3 that covers the element formation surface 22 of the semiconductor chip 20 is formed on the electrode 35 (second electrode) by, for example, CMP (Chemical Mechanical Polishing). Grinding is performed until the layer 37) is exposed (step S10: sealing resin grinding). As a result, the surface of the second electrode layer 37 is exposed from the sealing resin 3 and the external terminals 13 are formed.

  Next, as shown in FIG. 18, a support tape 67 having an adhesive surface is attached to the back surface of the sealing structure 66 (the back surface 52 of the impurity-free semiconductor wafer 50), and the sealing structure 66 is supported by the support tape 67. Fixed to. Next, in a state where the sealing structure 66 is fixed to the support tape 67, a cutting groove 68 along the trench 55 is formed by, for example, half-cut dicing (step S11: cutting groove formation). In half-cut dicing, a part of the sealing structure 66 is ground with a width narrower than the width of the trench 55 from the front surface side to the back surface side of the sealing structure 66 by, for example, a dicing saw. As a result, a cut groove 68 having a bottom portion located in the trench 55 is formed across the side surface 24 of the semiconductor chip 20 and the surface 51 of the impurity-free semiconductor wafer 50. Instead of half-cut dicing, the cut groove 68 may be formed by removing a part of the sealing structure 66 by etching (for example, dry etching).

Next, an electrical test is performed on the plurality of semiconductor chips 20 in a state where the sealing structure 66 is fixed to the support tape 67 (step S12: electrical test). In the electrical test, a measurement probe 69 is pressed against the electrode 35 exposed from the sealing resin 3. Thereby, the electrical characteristics of the semiconductor chip 20 are inspected. Thereafter, the support tape 67 is removed.
Next, as shown in FIG. 19, a support tape 70 having an adhesive surface is attached to the surface of the sealing structure 66, and the sealing structure 66 is fixed to the support tape 70 (step S13: backside grinding, Separation of sealing structure). Next, the back surface 52 of the impurity-free semiconductor wafer 50 is ground by CMP, for example. Grinding of the back surface 52 of the impurity-free semiconductor wafer 50 is performed until the cutting groove 68 is exposed. As a result, as shown in FIG. 20, the sealing structure 66 is cut along the cutting groove 68 (trench 55), and the semiconductor chip 20 is separated into the sealing structure 4 sealed with the sealing resin 3. It is separated. The semiconductor device 1 is manufactured through the above steps.

  According to the above method, the back surface 23 of the semiconductor chip 20 is supported by the impurity-free semiconductor wafer 50 in the step S8, and the element formation surface 22 and the side surface 24 are sealed in the step S9. Since it is covered with the resin 3, it is not exposed to the outside from the sealing resin 3. Thereby, since the influence from the outside with respect to the semiconductor chip 20 is reduced, the electrical characteristic of the semiconductor chip 20 can be kept favorable. On the other hand, since the singulation process is performed in a state where the back surface 52 of the impurity-free semiconductor wafer 50 is exposed to the outside from the sealing resin 3, in the sealing structure 4, the back surface 26 (no impurity added) of the support substrate 21. The back surface 52) of the semiconductor wafer 50 becomes the exposed surface 11 exposed from the sealing resin 3 to the outside.

  Thereby, the heat generated in the semiconductor chip 20 is dissipated from the exposed surface 11 of the support substrate 21 to the outside, so that the temperature increase in the semiconductor device 1 can be suppressed. Variation can be suppressed. As a result, it is possible to manufacture the semiconductor device 1 having excellent heat dissipation and correspondingly high reliability. Furthermore, since the sealing resin 3 that covers the element formation surface 22 and the side surface 24 of the semiconductor chip 20 and the side surface 27 of the support substrate 21 can also serve as a package, the semiconductor device 1 can be downsized. Furthermore, the semiconductor device 1 in which the entire area of the element formation surface 22 of the semiconductor chip 20, the entire area of the side surface 24 of the semiconductor chip 20, and the entire area of the side surface 27 of the support substrate 21 are covered with the sealing resin 3 can be manufactured. Thereby, the semiconductor device 1 which can protect the semiconductor chip 20 and the support substrate 21 favorably by the sealing resin 3 can be provided.

  Further, according to this method, the impurity-free semiconductor wafer 50 in which the chip arrangement region 53 having a larger area than the semiconductor chip 20 in plan view is set (see FIG. 7). Thereby, in the process of disposing the semiconductor chip 20 in step S8, inconvenience caused by the positional deviation of the semiconductor chip 20 can be suppressed. As a result, the yield can be improved and the reliability of the semiconductor device 1 can be improved.

  Further, according to this method, the sealing structure 66 is cut along the trench 55 that partitions the chip placement region 53. Thereby, in the sealing structure 4 (that is, the semiconductor device 1) after the singulation process of step S13, the support having the exposed surface 11 having an area larger than the area of the element forming surface 22 of the semiconductor chip 20 in plan view. A substrate 21 is formed (see FIG. 20). Therefore, the semiconductor device 1 that can effectively dissipate the heat generated in the semiconductor chip 20 to the outside can be provided.

  Further, according to this method, the impurity-free semiconductor wafer 50 containing the same kind of semiconductor material as that of the semiconductor chip 20 is prepared. Thereby, the thermal expansion coefficient of the impurity-free semiconductor wafer 50 becomes substantially equal to that of the semiconductor chip 20. Therefore, the junction between the semiconductor chip 20 and the impurity-free semiconductor wafer 50 can be stably maintained regardless of the temperature change. As a result, it is possible to manufacture the semiconductor device 1 having high durability against thermal cycles and thereby improving reliability. In addition, since the thermal coupling between the semiconductor chip 20 and the impurity-free semiconductor wafer 50 can be stably maintained, the heat generated in the semiconductor chip 20 can be transferred to the impurity-free semiconductor wafer 50 satisfactorily. Also by this, the highly reliable semiconductor device 1 can be provided.

  Furthermore, according to this method, an impurity-free semiconductor wafer 50 having a higher resistivity than the semiconductor chip 20 is prepared. The support substrate 21 obtained by such an impurity-free semiconductor wafer 50 can effectively suppress the inflow of current from the semiconductor chip 20. Thereby, the fluctuation | variation of the undesired electrical characteristic in the semiconductor chip 20 can be suppressed, and generation | occurrence | production of the heat | fever in the support substrate 21 can be suppressed collectively. In addition, since the support substrate 21 has good thermal conductivity (for example, about the same as the semiconductor chip 20), the heat generated in the semiconductor chip 20 is quickly conducted and the back surface 26 exposed to the outside (exposed surface 11). Efficiently dissipate from. Thereby, the temperature rise of the semiconductor device 1 can be effectively suppressed, and therefore the highly reliable semiconductor device 1 can be provided. Furthermore, according to this method, since silicon that is relatively easily available is used as the impurity-free semiconductor wafer 50, the manufacturing cost can be reduced.

  Further, according to this method, the semiconductor chip 20 is satisfactorily fixed to the impurity-free semiconductor wafer 50 by solder or a metal adhesive as the metal film 28. Thereby, since it can suppress effectively that the semiconductor chip 20 peels from the impurity-free semiconductor wafer 50, the position shift of the semiconductor chip 20 after the arrangement | positioning process of the semiconductor chip 20 of step S8 can be suppressed effectively. As a result, the yield can be effectively improved and the reliability of the semiconductor device 1 can be further improved.

  Further, since the thermal conductivity of the metal film 28 is high, the thermal conduction between the semiconductor chip 20 and the impurity-free semiconductor wafer 50 is good. Therefore, the heat generated in the semiconductor chip 20 can be satisfactorily transmitted to the impurity-free semiconductor wafer 50. Even when there is a difference in the thermal expansion coefficient between the semiconductor chip 20 and the impurity-free semiconductor wafer 50, the difference in thermal expansion / contraction between them can be absorbed by the ductility of the metal film 28. Therefore, the bonding between the semiconductor chip 20 and the impurity-free semiconductor wafer 50 has high durability against thermal cycling. Accordingly, since the mechanical coupling and the thermal coupling between the semiconductor chip 20 and the impurity-free semiconductor wafer 50 can be maintained, the semiconductor device 1 with improved reliability can be manufactured.

Further, according to this method, the sealing resin grinding step of Step S10 also serves as the step of forming the external terminals 13. Thereby, a Fan-in type semiconductor device in which the external terminal 13 is located in a region surrounded by the side surface 24 of the semiconductor chip 20 in plan view can be manufactured.
Second Embodiment
FIG. 21 is a bottom view of a semiconductor device 81 according to the second embodiment of the present invention. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. FIG. 23 is a partial enlarged cross-sectional view of the configuration of FIG. 21 to 23, parts corresponding to those shown in FIGS. 1 to 20 are denoted by the same reference numerals, and description thereof is omitted.

The semiconductor device 81 further includes a rewiring structure 82 formed on the back surface 6 of the sealing structure 4. In this embodiment, the sealing resin 3 for sealing the substrate 2 and the rewiring structure 82 also serve as a package.
The rewiring structure 82 is electrically connected to the electrode 35 and the rewiring 83 formed on the first portion 38 of the sealing resin 3 and the first of the sealing resin 3 so as to cover the rewiring 83. A back-side insulating film 84 formed on the portion 38 and an external terminal 86 electrically connected to the rewiring 83 via the post electrode 85 are included.

  The rewiring 83 extends on the first portion 38 of the sealing resin 3 in a plan view (hereinafter, simply referred to as “plan view”) viewed from the normal direction of the element formation surface 22, and the side surface 24 of the semiconductor chip 20 is extended. It is formed so as to cross and reach the second portion 39 of the sealing resin 3. As shown in FIG. 23, the rewiring 83 is surrounded by the one end 87 located in the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view and by the side surface 24 of the semiconductor chip 20 in plan view. It has the other end part 88 located on the 2nd part 39 of the sealing resin 3 outside the area | region. One end 87 of the rewiring 83 is electrically connected to the electrode 35. On the other hand, the other end portion 88 of the rewiring 83 faces the surface 25 of the support substrate 21 with the second portion 39 of the sealing resin 3 interposed therebetween. In this embodiment, an example is shown in which the other end portion 88 of the rewiring 83 is located in a region between the side surface 24 of the semiconductor chip 20 and the side surface 27 of the support substrate 21 in plan view. The other end 88 of the rewiring 83 may be formed so as to further cross the side surface 27 of the support substrate 21 in plan view. The rewiring 83 may be a copper wiring, for example.

  The back-side insulating film 84 is formed on the back surface 6 of the sealing structure 4, that is, on the first portion 38 and the second portion 39 of the sealing resin 3 so as to cover the rewiring 83. The back side insulating film 84 is formed in a substantially square shape that matches the back side 6 of the sealing structure 4. The back-side insulating film 84 may be an insulating film such as a nitride film or a resin film such as polyimide. A pad opening 90 for exposing a part of the other end 88 of the rewiring 83 as an electrode pad 89 is formed in the back surface side insulating film 84. A post electrode 85 is embedded in the pad opening 90.

  The post electrode 85 has a laminated structure including a UBM film (under bump metal film) 91 and an electrode film 92 formed on the UBM film 91. The UBM film 91 has a front surface and a back surface formed along the inner surface of the pad opening 90. The UBM film 91 is electrically connected to the rewiring 83 (electrode pad 89) in the pad opening 90. The UBM film 91 may include, for example, a titanium film, a copper film, or a laminated film in which a titanium film and a copper film are laminated in this order. The electrode film 92 is embedded in a concave space formed by the UBM film 91 entering the pad opening 90. The electrode film 92 is electrically connected to the rewiring 83 (electrode pad 89) through the UBM film 91. The electrode film 92 may include, for example, a copper film, a gold film, or an aluminum film. In this embodiment, the electrode film 92 is a copper film. A plurality (ten in this embodiment) of external terminals 86 are formed on the back-side insulating film 84 so as to be electrically connected to the post electrode 85.

  As shown in FIG. 21, the plurality of external terminals 86 are arranged at intervals from each other, and are formed in a substantially rectangular shape. The plurality of external terminals 86 are formed along the side surface 7 of the sealing structure 4. The plurality of external terminals 86 are formed at intervals from the side surface 7 of the sealing structure 4 inward. The plurality of external terminals 86 are preferably located at least partially outside the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. As shown in FIG. 23, in the present embodiment, the plurality of external terminals 86 have an outer region 93 located outside the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. The outer region 93 of the external terminal 86 faces the surface 25 of the support substrate 21 with the second portion 39 of the sealing resin 3 interposed therebetween. Further, the outer region 93 of the external terminal 86 may be at least partially located outside the region surrounded by the side surface 27 of the support substrate 21 in plan view. The external terminals 86 may all be located outside the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. The external terminal 86 may be, for example, a laminated film having a nickel film, a palladium film formed on the nickel film, and a gold film formed on the palladium film.

  Even with the configuration of this embodiment, the same effects as those of the semiconductor device 1 described above can be obtained. In addition, according to the configuration of this embodiment, the sealing resin 3 is formed so as to cover the side surface 10 of the substrate 2. More specifically, the second portion 39 of the sealing resin 3 is formed so as to cover the side surface 24 of the semiconductor chip 20. Thereby, the region on the second portion 39 of the sealing resin 3 outside the semiconductor chip 20 in a plan view can be used as a region for forming the rewiring 83. Therefore, the region where the external terminal 86 electrically connected to the rewiring 83 is formed is not limited to the region directly above the element formation surface 22 of the semiconductor chip 20 (substrate 2). As a result, a Fan-Out type semiconductor device 81 in which a large number of external terminals 86 are formed in a region outside the element formation surface 22 of the semiconductor chip 20 (substrate 2) can be provided.

FIG. 24 is a process diagram showing an example of a manufacturing method of the semiconductor device 81 shown in FIG. FIG. 25 is a process diagram showing an example of a process of forming the rewiring structure 82 shown in FIG. 26-30 is sectional drawing which shows an example of the manufacturing method of the semiconductor device 81 shown in FIG.
The manufacturing method of the semiconductor device 81 is different from the manufacturing method of the semiconductor device 1 described above, as shown in FIGS. 24 and 25, after the sealing resin grinding process in step S10, the cutting groove forming process in step S11. Prior to this, the process includes the step of forming the rewiring structure 82 in step S101. Since the other steps are the same as those in the method for manufacturing the semiconductor device 1 described above, only the main steps will be described in this embodiment.

In order to manufacture the semiconductor device 81, first, as shown in FIG. 26, a sealing structure 66 in which the electrode 35 exposed from the sealing resin 3 is formed is prepared through the sealing resin grinding step of step S10. .
Next, as shown in FIG. 27, the rewiring 83 is formed (step S102: rewiring formation). More specifically, a copper film is first formed on the surface of the sealing structure 66 by sputtering, for example. Next, for example, by photolithography and etching, the copper film is patterned to form a rewiring 83 electrically connected to the electrode 35.

  Next, a nitride film is laminated on the surface of the sealing structure 66 by, for example, the CVD method to form the back surface side insulating film 84 (step S103: back surface side insulating film formation). Next, a resist mask (not shown) having an opening selectively in a region where the electrode pad 89 (see FIG. 23) is to be formed is formed on the back-side insulating film 84 (step S104: pad opening formation). By etching through the resist mask, a pad opening 90 (see FIG. 23) is formed in the back-side insulating film 84 to expose a part of the rewiring 83 as the electrode pad 89. After the pad opening 90 is formed, the resist mask is removed.

Next, the UBM film 91 and the electrode film 92 are sequentially formed in the pad opening 90 by, for example, electrolytic plating or electroless plating (step S105: post electrode formation). Thereby, the post electrode 85 electrically connected to the rewiring 83 is formed.
Next, as shown in FIG. 28, a nickel film, a palladium film, and a gold film are sequentially formed on the back-side insulating film 84 by, for example, electroless plating or electrolytic plating (step S106: external terminal). Formation). Next, the laminated film including the nickel film, the palladium film, and the gold film is patterned by, for example, photolithography and etching. Thereby, the external terminal 86 is formed.

  Next, for example, photosensitive polyimide 94 is applied so as to cover the back-side insulating film 84 (step S107: cut groove formation). The photosensitive polyimide 94 is developed after being exposed so that a groove 95 along the trench 55 is formed in a plan view seen from the normal direction of the surface of the sealing structure 66. The groove 95 formed in the photosensitive polyimide 94 has an opening width narrower than the opening width of the trench 55 in a plan view viewed from the normal direction of the surface of the sealing structure 66. Located in the area. Thereafter, heat treatment for curing the photosensitive polyimide 94 is performed as necessary. Next, unnecessary portions of the back-side insulating film 84 are removed by etching using the photosensitive polyimide 94 as a mask. As a result, a cut groove 96 that matches the groove 95 formed in the photosensitive polyimide 94 is formed in the back-side insulating film 84, and at the same time, the rewiring structure 82 is formed. Thereafter, the photosensitive polyimide 94 is removed.

  Next, as shown in FIG. 29, the support tape 67 is attached to the back surface of the sealing structure 66 (the back surface 52 of the impurity-free semiconductor wafer 50), and the sealing structure 66 is fixed to the support tape 67. (Step S11: Cut groove formation). Next, in a state where the sealing structure 66 is fixed to the support tape 67, a cut groove 68 communicating with the cut groove 96 along the trench 55 is formed by, for example, half-cut dicing.

Next, an electrical test is performed on the plurality of semiconductor chips 20 in a state where the sealing structure 66 is fixed to the support tape 67 (step S12: electrical test). In the electrical test, the measurement probe 69 is pressed against the external terminal 86. Thereby, the electrical characteristics of the semiconductor chip 20 are inspected. Thereafter, the support tape 67 is removed.
Next, as shown in FIG. 30, a support tape 70 having an adhesive surface is attached to the surface of the sealing structure 66, and the sealing structure 66 is fixed to the support tape 70 (step S13: sealing structure). Individualization). Next, the back surface 52 of the impurity-free semiconductor wafer 50 is ground by CMP, for example. The back surface 52 of the impurity-free semiconductor wafer 50 is ground until the cutting groove 68 is exposed. Thereby, the sealing structure 66 is cut along the cutting groove 96 and the cutting groove 68, and the semiconductor chip 20 is singulated into the sealing structure 4 sealed with the sealing resin 3. Through the above steps, the semiconductor device 81 including the sealing structure 4 and the rewiring structure 82 is manufactured.
<Third Embodiment>
FIG. 31 is a sectional view of a semiconductor device 101 according to the third embodiment of the present invention. In FIG. 31, parts corresponding to those shown in FIGS. 1 to 30 are given the same reference numerals, and description thereof will be omitted.

The semiconductor device 101 is different from the above-described semiconductor device 81 in that the rewiring structure 82 includes an external terminal 86 directly connected to the rewiring 83 in the pad opening 90 formed in the back-side insulating film 84. That is, in the semiconductor device 101, the post electrode 85 is not formed. Other configurations of the semiconductor device 101 are the same as those of the semiconductor device 81 described above.
With the above configuration, the same effect as that of the semiconductor device 81 described above can be obtained.
<Fourth embodiment>
FIG. 32 is a bottom view of the semiconductor device 102 according to the fourth embodiment of the present invention. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. 32 and 33, parts corresponding to those shown in FIGS. 1 to 30 are denoted by the same reference numerals, and description thereof is omitted.

The semiconductor device 102 is different from the semiconductor device 81 described above in that the rewiring structure 82 includes a plurality of (11 in this embodiment) solder balls 103 as external terminals instead of the external terminals 86. The plurality of solder balls 103 are formed on the first portion 38 of the sealing resin 3 (on the back surface 6 of the sealing structure 4) so as to be electrically connected to the post electrode 85.
The plurality of solder balls 103 are arranged with a space between each other, and each has a substantially hemispherical shape. The plurality of solder balls 103 are formed at intervals from the side surface 7 of the sealing structure 4 inward. More specifically, the plurality of solder balls 103 are formed in a plurality of side surface side solder balls 104 formed along the side surface 7 of the sealing structure 4 and a region inside the side surface side solder balls 104. One inner solder ball 105. The plurality of solder balls 103 may include a plurality of inner solder balls 105 or may not include the inner solder balls 105.

  It is preferable that at least a part of the plurality of side surface side solder balls 104 is located outside the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. As shown in FIG. 33, this embodiment shows an example in which a plurality of side surface side solder balls 104 are located outside the region surrounded by the side surface 24 of the semiconductor chip 20 in plan view. The plurality of side surface side solder balls 104 are opposed to the surface 25 of the support substrate 21 with the second portion 39 of the sealing resin 3 interposed therebetween. Further, at least a part of the plurality of side surface side solder balls 104 may be located outside the region surrounded by the side surface 27 of the support substrate 21 in plan view.

Each of the plurality of solder balls 103 is, for example, an alloy containing at least two or more selected from the group consisting of tin, lead, phosphorus, silver, copper, nickel, germanium, bismuth, indium, zinc, aluminum, antimony, and cobalt. It may be. The plurality of solder balls 103 may be, for example, a SnAgCu alloy containing tin, silver, and copper.
Such a semiconductor device 102 can be formed by executing a process of forming the solder ball 103 instead of the process of forming the external terminal 86 (see FIG. 25) in step S106 described above. The step of forming the solder balls 103 may be a step of printing a plurality of solder balls 103 on the sealing structure 66 at a time so as to be electrically connected to the post electrodes 85, for example.

With the above configuration, the same effect as that of the semiconductor device 81 described above can be obtained.
Although a plurality of embodiments of the present invention have been described above, the present invention can be implemented in other forms.
For example, in each of the above-described embodiments, the example in which the substrate 2 includes the semiconductor chip 20 and the support substrate 21 has been described. However, as illustrated in FIG. 34, the semiconductor device 111 in which the substrate 2 is the semiconductor chip 20 is formed. Also good. The semiconductor chip 20 has an element forming surface 22, a back surface 23 positioned on the opposite side of the element forming surface 22, and four side surfaces 24 connecting the element forming surface 22 and the back surface 23. The element forming surface 22 and the side surface 24 of the semiconductor chip 20 are covered with a sealing resin. A back surface 23 of the semiconductor chip 20 is formed as an exposed surface 11 exposed to the outside from the sealing resin 3.

  In this case, for example, as shown in FIG. 35, in the back surface grinding process of step S13 (see also FIG. 5 and FIG. 24), the impurity-free semiconductor wafer 50 of the semiconductor chip 50 is exposed so that the back surface 23 of the semiconductor chip 20 is exposed. All and the metal film 28 may be removed. As a result, as shown in FIG. 36, the semiconductor device 111 in which the substrate 2 is the semiconductor chip 20 is manufactured. In this case, it is not necessary to form the cut groove 68 having the bottom in the trench 55 in the cut groove forming step of Step S11 (see also FIG. 5 and FIG. 24). For example, in the step of forming a cut groove in step S11 (see also FIGS. 5 and 24), the cut groove 68 having a bottom portion located at a depth between the element formation surface 22 of the semiconductor chip 20 and the bottom portion of the trench 55. May be formed.

  34, since the back surface 23 of the semiconductor chip 20 forms the exposed surface 11 exposed to the outside from the sealing resin 3, heat generated in the semiconductor chip 20 can be dissipated to the outside. it can. Thereby, since the temperature rise in the semiconductor device 111 can be suppressed, the fluctuation | variation of the electrical property of the semiconductor element accompanying a temperature rise can be suppressed. As a result, it is possible to provide the semiconductor device 111 having excellent heat dissipation and excellent reliability accordingly. In addition, since the sealing resin 3 that covers the element formation surface 22 and the side surface 24 of the semiconductor chip 20 can also serve as a package, the semiconductor device 111 can be downsized. In FIG. 34, the semiconductor device 111 is shown as a modified example of the semiconductor device 1 according to the first embodiment described above, but of course, the same configuration is applied to the semiconductor devices 81, 101, and 102 according to other embodiments. Can be adopted.

  In each of the above-described embodiments, examples of the semiconductor devices 1, 81, 101, and 102 in which one substrate 2 (one semiconductor chip 20 and one support substrate 21) is sealed with the sealing resin 3 have been described. However, as shown in FIG. 37, a semiconductor device 112 in which a plurality of (two or more) substrates 2 are sealed with a sealing resin 3 may be formed. Furthermore, as shown in FIG. 38, a plurality of (two or more) support substrates 21 are shared by one support substrate 21, whereby a plurality of (two or more) support substrates 21 are formed on one common support substrate 21. The semiconductor device 113 in which the semiconductor chip 20 is disposed may be formed. In FIGS. 37 and 38, semiconductor devices 112 and 113 are shown as modified examples of the semiconductor device 81 according to the second embodiment described above. However, of course, the semiconductor devices 1, 101 and 102 according to other embodiments are used. Can adopt the same configuration.

In each of the above-described embodiments, the example in which the electrical test in step S12 is performed after the cutting groove forming process in step S11 has been described. However, the order may be changed (see also FIGS. 5 and 24). .
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Board | substrate 3 Sealing resin 4 Sealing structure 8 The surface of a board | substrate 9 The back surface of a board | substrate 10 The side surface 11 of a board | substrate Exposed surface 13 The semiconductor terminal 21 The support substrate 22 The surface (element formation surface) of a semiconductor chip
23 Back surface of semiconductor chip 24 Side surface of semiconductor chip 28 Metal film 35 Electrode 50 Impurity-free semiconductor wafer (support substrate)
51 Front surface of impurity-free semiconductor wafer 52 Back surface 53 of impurity-free semiconductor wafer 53 Chip placement region 55 Trench 66 Sealing structure 68 Cutting groove 81 Semiconductor device 83 Rewiring 86 External terminal 96 Cutting groove 101 Semiconductor device 102 Semiconductor device 111 Semiconductor device 112 Semiconductor Device 113 Semiconductor Device

Claims (22)

A substrate having an element formation surface on which a semiconductor element is formed, a back surface located on the opposite side of the element formation surface, and a side surface connecting the element formation surface and the back surface;
An electrode formed on the element formation surface so as to be electrically connected to the semiconductor element;
And a resin that covers the element formation surface and the side surface of the substrate so as to expose the electrode and exposes the back surface.   The semiconductor device according to claim 1, wherein the back surface has an area larger than an area of the element formation surface.   3. The semiconductor device according to claim 1, wherein the electrode forms an external terminal in a region surrounded by a peripheral edge of the element formation surface in a plan view as viewed from the normal direction of the element formation surface. . A rewiring electrically connected to the electrode and reaching outside the region surrounded by the periphery of the element formation surface in a plan view as viewed from the normal direction of the element formation surface;
3. The semiconductor according to claim 1, further comprising an external terminal electrically connected to the redistribution and at least partially located outside a region surrounded by a periphery of the element formation surface in the plan view. apparatus. The substrate is
The first surface as the element forming surface, the first back surface located on the opposite side of the element forming surface, the first surface and the first back surface are connected, and a part of the side surface of the substrate is formed. A semiconductor chip having a first side surface;
A second surface which is bonded to the first back surface of the semiconductor chip and supports the semiconductor chip; a second back surface which is located on the opposite side of the second surface and forms the back surface of the substrate; and the second surface 5. The semiconductor device according to claim 1, further comprising: a support substrate having a second side surface that connects the first back surface to the second back surface and forms a part of the side surface of the substrate.   The semiconductor device according to claim 5, wherein the support substrate has an area larger than an area of the semiconductor chip in a plan view as viewed from a normal direction of the element formation surface.   The semiconductor device according to claim 5, wherein the support substrate includes the same type of semiconductor material as the semiconductor chip.   The semiconductor device according to claim 7, wherein the support substrate is an impurity-free silicon substrate.   The semiconductor device according to claim 5, wherein the substrate further includes a metal film interposed between the semiconductor chip and the support substrate and bonding the semiconductor chip to the support substrate.   The semiconductor device according to claim 9, wherein the metal film includes solder or a metal adhesive.   The semiconductor device according to claim 5, wherein the resin covers the entire area of the first side surface of the semiconductor chip and the entire area of the second side surface of the support substrate.   The substrate is a semiconductor chip, the element formation surface is a first main surface of the semiconductor chip, and the back surface is a second main surface opposite to the first main surface of the semiconductor chip. 2. The semiconductor device according to 1. A step of preparing a plurality of semiconductor chips having an element formation surface on which a semiconductor element is formed, and electrodes formed on the element formation surface;
Preparing a support substrate in which a plurality of chip placement areas in which the semiconductor chips are placed are set;
Forming a trench on the surface side of the support substrate so as to partition the chip placement region set on the surface of the support substrate;
Placing each of the plurality of semiconductor chips in the plurality of chip placement regions on the support substrate;
A sealing structure that forms a sealing structure in which the plurality of semiconductor chips are sealed with the resin by covering the support substrate with a resin so as to fill the trench and cover the plurality of semiconductor chips. Forming process;
An electrode exposure step of exposing the electrode formed on the semiconductor chip from the sealing structure;
A method for manufacturing a semiconductor device, comprising: a step of dividing the semiconductor chip into a plurality of semiconductor devices each sealed with the resin by cutting the sealing structure along the trench .   The step of preparing the support substrate, the chip placement region having an area larger than the area of the semiconductor chip in a plan view as viewed from the normal direction of the surface of the support substrate is set. Semiconductor device manufacturing method.   15. The method for manufacturing a semiconductor device according to claim 13, wherein in the step of preparing the support substrate, the support substrate including a semiconductor material of the same type as the semiconductor chip is prepared.   The method for manufacturing a semiconductor device according to claim 15, wherein in the step of preparing the support substrate, an impurity-free silicon substrate is prepared as the support substrate.   The step of disposing the semiconductor chip comprises joining the back surface of the semiconductor chip opposite to the element formation surface and the front surface of the support substrate with a metal film, thereby attaching the semiconductor chip to the support substrate. The manufacturing method of the semiconductor device as described in any one of Claims 13-16 including the process fixed to a chip | tip arrangement | positioning area | region.   The method of manufacturing a semiconductor device according to claim 17, wherein the metal film includes solder or a metal adhesive.   The electrode exposing step also serves as a step of forming the electrode as an external terminal located in a region surrounded by the side surface of the semiconductor chip in a plan view seen from the normal direction of the element forming surface. The manufacturing method of the semiconductor device as described in any one of Claims 13-18. After the electrode exposure step, prior to the singulation step, the semiconductor is electrically connected to the electrode and crosses the side surface of the semiconductor chip in a plan view as viewed from the normal direction of the element formation surface. Forming a rewiring that extends outside the area surrounded by the side of the chip;
19. The semiconductor device according to claim 13, further comprising: forming an external terminal at least a part of which is located outside a region surrounded by a side surface of the semiconductor chip in the plan view. Production method. The singulation process includes
A part of the sealing structure along the trench is dug from the element forming surface side with a width narrower than the width of the trench, thereby forming a cutting groove having a bottom in the trench in the sealing structure. Process,
The method of manufacturing a semiconductor device according to claim 13, further comprising a step of grinding a back surface opposite to the front surface of the support substrate until the cutting groove is exposed. The singulation process includes
A part of the sealing structure is dug down along the trench from the element formation surface side with a width narrower than the width of the trench, so that the gap between the element formation surface of the semiconductor chip and the bottom of the trench is reduced. Forming a cutting groove in the sealing structure having a bottom located at a depth;
Grinding the back surface opposite to the front surface of the support substrate until the cut grooves are exposed and all of the support substrate is removed. The manufacturing method of the semiconductor device of description.

Images