JP2016131316A - Slave for communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a slave for communication capable of smoothing variations that occur in a bus due to a current consumed by the slave itself.SOLUTION: A smoothing current output circuit 9 which generates a current with phase opposite to that of a dynamic consumption current detected by a current monitoring unit 8 is provided between a sense resistor 7 and the current monitoring unit 8, and a transmission circuit 5, which transmits a signal to a master 2 by driving a bus 3 with current. The smoothing current output circuit 9 is capable of smoothing variations that occur in the bus 3 due to a current consumed by the master 1 itself, so that the master 2 can receive a signal transmitted by a slave 1 without being affected by such variations.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication slave that operates by being supplied with power from a master via a pair of buses and that drives the current of the bus to transmit a signal to the master.

  The master and slave are connected by a pair of buses, and the slave is supplied with operating power from the master, and the communication method in which the slave drives the bus to send a signal to the master has the following problems: is there. Current fluctuation occurs in the bus when the slave transmits a signal to the master. However, current fluctuations based on the current consumed by the slave itself, noise, and the like are also superimposed on the bus, and if such current fluctuation components increase, the master may not be able to receive signals correctly.

  For example, in Patent Document 1, in a communication system that transmits and receives communication signals between a plurality of communication devices 1 and 2 connected to a communication line 3, the communication device 1 outputs communication data to be converted into communication signals. Control unit 11, communication unit 12 that generates a communication signal based on communication data output from control unit 11 and outputs the communication signal to communication line 3, and current consumption consumed when communication unit 12 generates a communication signal A configuration including a current output unit 15 that outputs a compensation current I3 having a phase opposite to that of I2 is disclosed.

JP 2008-306337 A

  However, the current output unit 15 of Patent Document 1 only targets “consumption current I2 consumed when the communication unit 12 generates a communication signal”. Therefore, the current fluctuation cannot be compensated for the current consumed during the period in which the communication device 1 does not generate the communication signal, the noise generated suddenly, and the like.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a communication slave capable of smoothing fluctuations generated on a bus due to current consumed by itself.

  According to the communication slave according to claim 1, consumption between the consumption current detection means for detecting its own dynamic consumption current and the transmission means for driving the bus to send a signal to the master. Smoothing means for generating a current having a phase opposite to the dynamic current consumption detected by the current detection means is provided. If comprised in this way, the fluctuation | variation which generate | occur | produces on a bus | bath by the electric current which self consumes by the smoothing means can be smoothed. Therefore, the master can receive the signal transmitted by the slave without being affected by the fluctuation.

  According to the communication slave of claim 2, the control circuit includes a transmission buffer for storing data of a signal transmitted via the transmission unit, and the reception unit detects its own current by detecting the current flowing through the bus. Receives a signal transmitted by a communication slave connected to the downstream side. When the control circuit receives the signal transmitted by the downstream communication slave via the receiving means, the control circuit temporarily stores the received signal data in the transmission buffer. Then, the reception signal is transmitted to the upstream side of the reception signal by the transmission means.

  With this configuration, when the communication slave connected downstream transmits a signal to the master, the signal data is received by the upstream communication slave and stored in the transmission buffer. Further, fluctuations in current consumption generated on the bus when a communication slave connected to the downstream side transmits a signal to the master are smoothed by the smoothing means of the upstream communication slave. The signal data stored in the transmission buffer is transmitted to the upstream side of the communication slave by the communication slave.

  That is, even in a network configuration in which a plurality of communication slaves are connected to the bus in multiple stages, current fluctuations on the bus that occur when each communication slave transmits a signal to the master are smoothed by the upstream communication slave. The signal data is sequentially transmitted to the master via the upstream communication slave. Therefore, the master can accurately receive the signal transmitted by each communication slave without being affected by the current fluctuation on the bus due to the current consumed dynamically by each communication slave other than the communication process.

The figure which is 1st Embodiment and shows the structure of the communication system which consists of a master and a slave The figure which shows the specific structural example of a current monitor part and a current smoothing circuit. The figure which is 2nd Embodiment and shows the structure of the communication system which consists of a master and several slaves The figure which shows the specific structural example of an electric current detection part. Flowchart showing data write processing to transmission buffer by control circuit Diagram showing an example of data transmission between the master and slave when performing synchronous communication The figure which is 3rd Embodiment and shows the example of data transmission between the master in the case of performing asynchronous communication Diagram showing an example of data transmission when performing full-duplex communication between master and slave The figure which is 4th Embodiment and shows the structure of the communication system which consists of a master and several slaves The figure which is 5th Embodiment and shows the structure of the communication system which consists of a master and several slaves The figure which is 6th Embodiment and shows the structure of the communication system which consists of a master and a slave

(First embodiment)
As shown in FIG. 1, the slave 1 (communication slave) and the master 2 of this embodiment are connected via a bus 3H (high potential side bus and power line) and 3L (low potential side bus and ground line). Has been. The slave 1 operates by being supplied with power from the master 2 via the bus 3. The transmission buffer 4 stores data that the slave 1 transmits to the master 2. The transmission data is, for example, A / D converted signals from sensors provided along with the slave 1.

  The transmission circuit 5 is connected between the buses 3H and 3L on the master 2 side (upstream side) in the slave 1. When the data stored in the transmission buffer 4 is serially input, the transmission circuit 5 (transmission means) indicated by a current source symbol drives the bus 3 in accordance with the value of each data bit, thereby driving the master 2. Send a signal to Similarly, a slave consumption current 6 indicated by a current source symbol indicates an equivalent circuit of a dynamic current consumed when the slave 1 operates.

  The sense resistor 7 (consumption current detection means, resistance element) is inserted in the bus 3H, and the current monitor unit 8 (consumption current detection means) monitors the current flowing through the bus 3H based on the terminal voltage of the sense resistor 7. The current includes the slave consumption current 6. A smoothing current output circuit 9 (smoothing means) indicated by a current source symbol is connected between the buses 3H and 3L on the downstream side of the transmission circuit 5. The smoothing current output circuit 9 generates a current signal having a phase opposite to the current detected by the current monitor unit 8 and outputs the current signal between the buses 3H and 3L.

  As shown in FIG. 2, the current monitor unit 8 includes an operational amplifier 11 and N-channel MOSFETs 12 and 13. The non-inverting input terminal and the inverting input terminal of the operational amplifier 11 are connected to the terminals of the sense resistor 7 via the resistance elements 14 and 15, respectively. The drain of the FET 12 is connected to the non-inverting input terminal of the operational amplifier 11, and the source is connected to the drain and gate of the FET 13. The source of the FET 13 is connected to a bus 3L indicated by a ground symbol. The gate of the FET 12 is connected to the output terminal of the operational amplifier 11.

  The smoothing current output circuit 9 includes N-channel MOSFETs 16 and 17 constituting a mirror pair. The drain of the FET 16 is connected to the power source via the current source 18 and is also connected to its own gate. The sources of the FETs 16 and 17 are connected to the ground, and the drain of the FET 17 is connected to the bus 3H. The N-channel MOSFET 19 is connected in parallel to the FET 16, and the gate of the FET 19 is connected to the gate of the FET 13. That is, the FETs 13 and 19 also constitute a mirror pair.

  Next, the operation of this embodiment will be described. The operational amplifier 11 of the current monitor unit 8 controls the gate potential of the FET 12 so that the potential of the non-inverting input terminal is equal to the potential of the inverting input terminal. Therefore, the current flowing through the series circuit of the FETs 12 and 13 is proportional to the voltage generated at both ends of the sense resistor 7 according to the current I flowing through the bus 3H. The current flowing through the series circuit becomes a current in phase with the current I at a current ratio of 1 / n, for example. The current I / n is mirrored by the FET 19, but when the current flowing through the FET 19 increases, the current flowing through the FET 16 decreases accordingly. Since the current is mirrored by n times by the FET 17, the waveform of the current flowing through the FET 17 is reversed from the waveform of the current I as a result.

  That is, even if a current fluctuation due to the slave consumption current 6 occurs in the bus 3, the fluctuation is smoothed by the action of the smoothing current output circuit 9, and the master 2 is not affected by the fluctuation. The transmission circuit 5 is connected to the upstream side of the smoothing current output circuit 9. Therefore, only the current fluctuation generated when the slave 1 transmits a signal by the transmission circuit 5 is transmitted to the master 2.

As described above, according to the present embodiment, in the slave 1, the current between the sense resistor 7 and the current monitor unit 8 and the transmission circuit 5 for driving the bus 3 to transmit a signal to the master 2. A smoothing current output circuit 9 is provided that generates a current having a phase opposite to the dynamic current consumption detected by the monitor unit 8. With this configuration, the smoothing current output circuit 9 can smooth the fluctuation generated on the bus 3 by the current consumed by the slave 1 itself, so that the master 2 is not affected by the fluctuation, and the slave 2 The signal transmitted by 1 can be received.
Moreover, since the current monitor unit 8 monitors the current flowing through the bus 3H based on the terminal voltage of the sense resistor 7 inserted into the bus 3H, the current consumption of the slave 1 can be detected with a simple configuration.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 3, the slave 21 according to the second embodiment is obtained by adding a control circuit 22 and a current detection unit 23 (reception unit) to the slave 1 according to the first embodiment. A plurality of slaves 21 (1 to 3) are connected to the bus 3. The current detection unit 23 is arranged so that the control circuit 22 detects a signal transmitted to the master 1 by the slave 21 connected downstream from itself. Therefore, the current detection unit 23 refers to the terminal voltage of the sense resistor 7 (reception means) as in the current monitor unit 8.

  As shown in FIG. 4, the current detection unit 23 includes an operational amplifier 24, an N-channel MOSFET 25, and a comparator 26. The non-inverting input terminal and the inverting input terminal of the operational amplifier 24 are connected to the respective terminals of the sense resistor 7 via resistance elements 27 and 28, respectively. The drain of the FET 25 is connected to the non-inverting input terminal of the operational amplifier 27, and the source is connected to the ground (bus 3L) via the resistance element 29. The gate of the FET 25 is connected to the output terminal of the operational amplifier 24.

  The source of the FET 25 is connected to the non-inverting input terminal of the comparator 26, and a reference voltage ref is given to the inverting input terminal of the comparator 26. In the current detection unit 23, similarly to the current monitoring unit 8, the operational amplifier 24 controls the gate of the FET 25 based on the voltage generated at both ends of the sense resistor 7 according to the current I flowing through the bus 3H. Thereby, for example, a drain current having the same phase as the current I flows in the FET 25 at a current ratio of 1 / n, and the terminal voltage of the resistance element 29 becomes a level corresponding to the value of the drain current.

  The comparator 26 compares the terminal voltage of the resistance element 29 with the reference voltage ref, generates a rectangular wave signal, and outputs it to the control circuit 22. Thereby, the control circuit 22 can detect the signal which the slave 21 connected to the downstream of itself transmitted to the master. The control circuit 22 is composed of a CPU (microcomputer) and writes transmission data to the transmission buffer 4.

  Next, the operation of the second embodiment will be described. As shown in FIG. 5, the control circuit 22 first determines whether or not a change in the current of the bus 3 due to the other slave 21 transmitting a signal to the master 2 is detected (S1). If the current change is not detected (NO), data (for example, a sensor signal) transmitted from the slave 21 to the master 2 is read (S5), and the read data is written in the transmission buffer 4 (S3). Thereafter, the writing is completed (S4). On the other hand, when a current change in the bus 3 is detected in step S1 (YES), the control circuit 22 reads data of a signal transmitted by another slave via the current detection unit 23 (S2). Then, the read data is written into the transmission buffer 4 (S3).

  For example, as shown in FIG. 6, when the master 2 outputs a synchronization signal on the bus 3, the slaves 21 that have received the synchronization signal start transmission all at once (the data stored in the transmission buffer 4 at that time). The transmission circuit 5 performs transmission accordingly). When the master 2 transmits a signal to the slave 21, the bus 3 is voltage driven. In this case, the slave 21 is provided with a comparator or the like (receiving means) that captures a voltage change of the bus 3 in order to receive the transmission data of the master 2. As a result, transmission from the master 2 to the slave 21 and transmission from the slave 21 to the master 2 can be performed simultaneously (full-duplex communication).

  When each of the slaves 21 (1 to 3) receives the synchronization signal, each of the slaves 21 (1 to 3) simultaneously transmits Slave1 data, Slave2 data, and Slave3 data. The slave 21 (1) located at the most upstream receives the Slave 2 data transmitted from the slave 21 (2) and writes it in the transmission buffer 4 in parallel with transmitting the Slave 1 data to the master 2. Then, when the transmission of the Slave1 data is completed, the Slave2 data is subsequently transmitted to the master 2.

  Similarly, Slave3 data transmitted by the slave 21 (3) is received by the slave 21 (2) and written to the transmission buffer 4 in parallel with the slave 21 (2) transmitting Slave2 data. Further, the Slave3 data is received by the slave 21 (1). When the slave 21 (1) completes the transmission of the Slave2 data, the Slave3 data is subsequently transmitted to the master 2. Note that the Slave 1 to 3 data includes ID information for determining each transmission source.

  That is, also in the slaves 21 (2) and 21 (3), the dynamic current fluctuation due to the slave consumption current 6 is smoothed by the smoothing current output circuit 9 that each has, so that each upstream side Only the current fluctuation accompanying data transmission is transmitted to the slaves 21 (1) and 21 (2). The data transmitted by the downstream slave 21 is once received by the upstream slave 21 and further transferred to the upstream slave 21. Eventually, the slave 21 (1) located at the most upstream transmits the data of all the slaves 21 directly to the master 2.

  As described above, according to the second embodiment, the control circuit 22 refers to the current consumption of the bus 3H via the current detection unit 23 and receives a signal transmitted by the slave 21 connected to the downstream side of the control circuit 22. Then, the received signal data is temporarily stored in the transmission buffer 4. Then, the reception signal data is transmitted to its upstream side by the transmission circuit 5.

That is, even in a network configuration in which a plurality of slaves 21 (1 to 3) are connected to the bus 3 in multiple stages, current fluctuations on the bus 3 that occur when each slave 21 transmits a signal to the master 2 are upstream of the slaves 21. The signal data is sequentially transmitted to the master 2 via the upstream slave 21. Therefore, there is no transmission data collision in the bus 3. Further, since the S / N ratio is improved, the maximum value of the signal current amplitude can be set small, and the power consumption can be reduced. Therefore, the master 2 can accurately receive the data transmitted by each slave 21 without being affected by fluctuations in current on the bus 3 due to the current dynamically consumed by each slave 21 except for communication processing.
Further, when the control circuit 22 receives the synchronization signal transmitted from the master 2 via the bus 3, the control circuit 22 transmits the data stored in the transmission buffer 4 via the transmission circuit 5, so that the master 2 takes the lead. Compatible with synchronous communication.

(Third embodiment)
As shown in FIG. 7, the third embodiment shows a case where the master 2 does not transmit a synchronization signal and each slave 21 (1-3) communicates asynchronously. In case (A) in the figure, transmission starts in the order of slave 21 (1), slave 21 (3), and slave 21 (2). When the slave 21 (1) receives the Slave 2 data while transmitting the Slave 1 data to the master 2, the slave 21 (1) writes the Slave 2 data in the transmission buffer 4. Then, after the transmission of Slave1 data is completed, transmission of Slave2 data to the master 2 is started.

  In addition, since the slave 21 (2) receives the Slave3 data before starting transmission of the Slave2 data, the slave 21 (2) writes the Slave3 data in the transmission buffer 4. When Slave2 data to be transmitted is generated during the writing, the transmission of Slave2 data is started, and when the transmission is completed, the transmission of Slave3 data is started. When the slaves 21 (1 to 3) start transmission at the same time as in the case (B), the transmission pattern is the same as that in FIG. 6 of the second embodiment.

FIG. 8 shows an example of full-duplex communication in which the slave 21 performs asynchronous communication and the master 2 voltage-drives the bus 3 to transmit data to the slave 21 in parallel.
As described above, according to the third embodiment, the control circuit 22 stores the data if it does not receive the signal transmitted by the slave 21 on the downstream side while storing the data transmitted by itself in the transmission buffer 4. Immediately after that, transmission is performed via the transmission circuit 5. Then, when a signal transmitted by the downstream slave 21 is received while the data to be transmitted is stored in the transmission buffer 4, the data of the received signal is stored in the transmission buffer 4 following the transmission data of itself. Then send. This can cope with the case where each slave 21 performs asynchronous communication.

(Fourth embodiment)
As shown in FIG. 9, in the slave 31 of the fourth embodiment, another sense resistor 32 (receiving means, resistance element) is arranged on the bus 3H in addition to the sense resistor 7. The current monitor unit 8 refers to the terminal voltage of the sense resistor 7, and the current detection unit 23 refers to the terminal voltage of the sense resistor 32.

  The signal at point A shown in the figure is a current fluctuation on the bus 3 generated by the downstream slave 31 (2) transmitting the signal, and the current fluctuation is captured by the sense resistor 32 and the current detector 23. It is done. At point B upstream of point A, current fluctuations according to the consumption current 6 of the slave 31 (1) are superimposed on the current fluctuations, but these current fluctuations are captured by the sense resistor 7 and smoothed. Smoothing is performed by the current output circuit 9. Therefore, current fluctuation does not occur at the point C upstream of the smoothing current output circuit 9.

  And since the control circuit 22 transmits a signal by the transmission circuit 5 according to the data received through the current detection unit 23, only the current fluctuation according to the transmission signal is detected at the point D upstream of the point C. Appears and the current fluctuation is received by the master 2. If comprised in this way, when the slave 31 receives the data which the downstream slave 31 transmitted via the sense resistor 32 and the current detection part 23, it will not receive to the influence of an own consumption current fluctuation | variation. Therefore, the S / N ratio can be further improved.

(Fifth embodiment)
As shown in FIG. 10, the slave 41 of the fifth embodiment shows a case where the transmission buffer 4 in the slave 31 is specifically composed of a FIFO (First In First Out) 4A and a parallel / serial converter 4B. . That is, the data written in the FIFO 4A by the control circuit 22 is read out first from the previously written data and transferred to the parallel / serial converter 4B. The parallel / serial conversion unit 4B converts the written parallel data into serial data and outputs the serial data to the transmission circuit 5.

(Sixth embodiment)
As shown in FIG. 11, the slave 51 according to the sixth embodiment has a current sensor 52 (consumption current detection means) arranged on the bus 3 </ b> H instead of the sense resistor 7. Also when comprised in this way, the effect similar to 1st Embodiment is acquired.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The number of slaves may be two or four or more.
In the fourth embodiment, the sense resistor 32 may be replaced with a current sensor as in the sixth embodiment.

  In the drawings, 1 is a slave (communication slave), 2 is a master, 3H and 3L are buses (high potential side bus, low potential side bus), 4 is a transmission buffer, 5 is a transmission circuit (transmission means), and 6 is a slave. Consumption current, 7 is a sense resistor (consumption current detection means, resistance element), 8 is a current monitor unit (consumption current detection means), and 9 is a smoothing current output circuit (smoothing means).

Claims (7)

In a communication slave (1, 21, 31, 41, 51) connected to a master (2) by a pair of high potential side and low potential side buses (3H, 3L) and operating with power supplied from the master. ,
Current consumption detecting means (7, 8, 52) for detecting its own dynamic current consumption (6);
A transmission means (5) disposed on the master side, for driving the bus in current and transmitting a signal to the master;
A smoothing unit (9) disposed between the consumption current detection unit and the transmission unit and configured to generate a current having a phase opposite to the dynamic consumption current detected by the consumption current detection unit; A slave for communication. A control circuit (22) for controlling communication with the master;
Receiving means (7, 23) for receiving a signal transmitted by a communication slave connected to the downstream side thereof by detecting a current flowing through the bus;
A transmission buffer (4) for storing data of a signal transmitted by the control circuit via the transmission means;
The consumption current detection means detects the consumption current,
When the control circuit receives a signal transmitted by the downstream communication slave via the receiving means, the control circuit temporarily stores the received signal data in the transmission buffer, and then transmits the received signal via the transmitting means. The communication slave according to claim 1, wherein the communication slave transmits to the upstream side of the communication slave. If the control circuit does not receive the signal transmitted by the downstream communication slave while storing the data to be transmitted in the transmission buffer, the control circuit transmits the data immediately after the data is stored,
When a signal transmitted by a downstream communication slave is received while data to be transmitted is stored in the transmission buffer, data of the received signal is stored in the transmission buffer following its transmission data. 3. The communication slave according to claim 2, wherein transmission is performed via said transmission means.   3. The communication according to claim 2, wherein the control circuit transmits the data stored in the transmission buffer via the transmission unit when receiving a synchronization signal transmitted by the master via the bus. For slave.   The communication slave according to any one of claims 1 to 4, wherein the consumption current detection means includes a resistance element (7) inserted into the bus.   6. The communication slave according to claim 5, wherein the receiving means includes a resistance element (7, 32) inserted into the bus.   The communication slave according to claim 6, further comprising a resistance element (7) constituting the consumption current detection means and a resistance element (32) constituting the reception means, respectively.

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