JP2009118315A - Communication system, transmitting device, receiving device, communication apparatus, semiconductor device, and communication scheme - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication system and the like which attains cost reduction and communication stabilization and is capable of being applied to an asynchronous system, in digital serial communication using a pulsewidth modulation system. <P>SOLUTION: A communication system includes a transmitting side for transmitting a pulsewidth-modulated digital signal and a receiving side which comprises a software counter function and acquires a corresponding count value between a rising edge and a falling edge of the digital signal as a pulsewidth of the digital signal. When starting communication with the receiving side, the transmitting side transmits a first digital signal having a pulsewidth corresponding to "0" and a second digital signal corresponding to "1" and the receiving side acquires a count value corresponding to the pulsewidth of the first digital signal as a first discrimination count value, acquires a count value corresponding to the pulsewidth of the second digital signal as a second discrimination count value, and discriminates "0" and "1" of the digital signal corresponding to data based on the first and second discrimination count values. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

 The present invention relates to a communication system, a transmission device, a reception device, a communication device, a semiconductor device, and a communication method.

As one of digital serial communication systems, a pulse width modulation system that expresses digital signals of “1” and “0” by the length of the pulse width is known. For example, in Patent Document 1 below, in a communication device that performs digital serial communication using the pulse width modulation method as described above, communication failure due to reception delay of transmission data or differences in system clocks between communication devices is prevented. In order to achieve this purpose, after transmitting the transmission data on the transmission line from the transmission means, the transmission data on the transmission line is received, and the transmission timing in bit units detected from the received transmission data is set. A technique for determining the pulse width for each bit of transmission data to be transmitted on the transmission line and the transmission timing of the next bit is disclosed.
JP-A-5-211511

The communication device disclosed in Patent Document 1 has the following problems.
(1) A signal source of a clock signal used for a counter for measuring the length of the pulse width is necessary, and the cost becomes high.
(2) In the pulse width detection circuit, a count value corresponding to a pulse width of “0” and a count value corresponding to a pulse width of “1” are preset as count values for determining “0” and “1”. Therefore, when the operation of the clock signal source changes due to changes in the operating environment such as temperature and power supply voltage, the above-mentioned discrimination count value set in advance does not make sense, and communication Will collapse.
(3) Since the communication speed is determined depending on the frequency of the clock signal, it is difficult to support high-speed communication. On the other hand, in recent years, an asynchronous system (see, for example, Japanese Patent Application Laid-Open No. 2004-303195) that can achieve both high speed and low power consumption of the entire system has attracted attention. Since a clock signal (system clock) is not required, the communication device of Patent Document 1 cannot perform communication between asynchronous systems or between a synchronous system and an asynchronous system.

  The present invention has been made in view of such circumstances, and in digital serial communication using a pulse width modulation method, the cost is reduced and the operation environment such as temperature and power supply voltage is not affected. An object of the present invention is to provide a communication system, a transmission device, a reception device, a communication device, a semiconductor device, and a communication method that can perform communication and can be applied to an asynchronous system.

 In order to achieve the above object, a communication system according to the present invention comprises a transmission apparatus having a transmission control means for transmitting a pulse width modulated digital signal, and a software counter function, and a rising edge or a falling edge of the digital signal. A reception control means for starting counting in synchronization with one of the signals and grasping a count value obtained by ending the counting in synchronization with the other of the rising edge or falling edge as the pulse width of the digital signal The transmission control means includes a first digital signal having a pulse width corresponding to “0” before transmission of a digital signal corresponding to data at the start of communication with the receiving device. , And a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal, The transmission control means acquires a count value corresponding to the pulse width of the first digital signal as a first determination count value, and sets a count value corresponding to the pulse width of the second digital signal to a second value. It is acquired as a discrimination count value, and “0” and “1” of a digital signal corresponding to the data received from the transmission device are discriminated based on the first and second discrimination count values. And

According to the communication system having such characteristics, the following effects can be obtained.
(1) Since the pulse width of a pulse width modulated digital signal is measured using a software counter, a clock signal source is unnecessary for both the transmission device and the reception device, and the system cost can be reduced.
(2) The first discrimination count value used to discriminate “0” “1” of the digital signal corresponding to the data received from the transmission device by the reception device (that is, the discrimination count value corresponding to “0”) And the second discriminating count value (that is, the discriminating count value corresponding to “1”) are obtained by a software counter that does not require a clock signal source. It is possible to prevent communication from failing due to a change.
(3) Since a clock signal (predetermined synchronization timing) is not required, communication between asynchronous systems or between a synchronous system and an asynchronous system is possible. In other words, by applying this communication system to an asynchronous system, in digital serial communication using a pulse width modulation method,
It is possible to realize high-speed communication and low power consumption independent of the frequency of the clock signal.

In the communication system according to the present invention, the reception control unit calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and the data It is preferable to discriminate between “0” and “1” of the digital signal corresponding to the data by comparing the threshold value with a count value corresponding to the pulse width of the digital signal corresponding to.
The count value corresponding to the pulse width of the digital signal obtained by the software counter may include a count error due to variations in the count start timing and the count end timing. In this case, simply using the first and second determination count values makes it difficult to accurately determine “0” or “1” of the digital signal corresponding to the data, and communication may fail. Therefore, as described above, the threshold value for discriminating between “0” and “1” calculated using the first and second discrimination count values and the count value corresponding to the pulse width of the digital signal are obtained. By comparing “0” and “1” of the digital signal by comparison, for example, it is possible to adopt a determination method of determining “0” below the threshold value, and determining “1” when larger than the threshold value. Even if the value includes a count error, it is possible to accurately determine “0” or “1”.

In the communication system according to the present invention, it is preferable that the reception control unit calculates an average value of the first determination count value and the second determination count value as the threshold value.
Thus, by setting the average value of the first determination count value and the second determination count value as the threshold value, both the first determination count value and the second determination count value are set. Therefore, even if the count value includes a large count error, it is possible to accurately determine “0” or “1”.

In the communication system according to the present invention, the receiving device detects a rising edge and a falling edge of a digital signal received from the transmitting device, and an interrupt signal indicating rising edge detection and an interrupt signal indicating falling edge detection. Edge detection means for outputting to the reception control means, the reception control means starts counting when an interrupt signal indicating the rising edge detection is input, and an interrupt signal indicating the falling edge detection. It is preferable that the count is terminated when is input.
As described above, when the interrupt control signal is input from the edge detection unit, the reception control unit adopts a configuration in which the count operation (measurement of the pulse width of the digital signal) is performed as an interrupt process so that no interrupt signal is input Since the reception control means can execute other processes in parallel during the period, the processing capability of the reception control means can be improved.

In the communication system according to the present invention, the first digital signal and the second digital signal at the start of communication are transmitted and received in response to a change in the operating environment, whereby the first digital signal corresponding to the operating environment is transmitted. It is preferable to obtain the first and second discrimination count values.
As a result, the first and second determination count values according to changes in the operating environment (for example, temperature, power supply voltage, etc.) can be acquired, and a threshold value for determining “0” or “1”. Can be dynamically changed in accordance with the operating environment, so that data communication failure due to a change in the operating environment can be prevented.

The transmission device according to the present invention further includes transmission control means for transmitting a pulse width modulated digital signal to the reception device, and the transmission control means is a digital signal corresponding to data at the start of communication with the reception device. Before transmission, a first digital signal having a pulse width corresponding to “0” and a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal are transmitted. It is characterized by that.
By using a transmission device having such characteristics, the above-described communication system can be configured.

The receiving device according to the present invention has a software counter function, starts counting in synchronization with one of the rising edge or falling edge of the digital signal received from the transmitting device, and the rising edge or falling edge. 6. A reception control means for grasping a count value obtained by ending the counting in synchronization with the other of the digital signal as a pulse width of the digital signal, wherein the reception control means receives the transmission device received from the transmission device according to claim 5. A count value corresponding to the pulse width of the first digital signal is acquired as a first determination count value, and a count value corresponding to the pulse width of the second digital signal is acquired as a second determination count value. And a digital signal corresponding to the data received from the transmitter based on the first and second discrimination count values. To determine the "0" and "1", characterized in that.
By using a receiving apparatus having such characteristics, the above-described communication system can be configured.

Further, in the receiving apparatus according to the present invention, the reception control means calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and the data It is preferable to discriminate between “0” and “1” of the digital signal corresponding to the data by comparing the threshold value with a count value corresponding to the pulse width of the digital signal corresponding to.
Thereby, even when the count value includes a count error, it is possible to accurately determine “0” or “1”.

In the receiving apparatus according to the present invention, it is preferable that the reception control means calculates an average value of the first determination count value and the second determination count value as the threshold value.
As a result, even when the count value includes a count error, it is possible to more accurately determine “0” or “1”.

Further, in the receiving apparatus according to the present invention, a rising edge and a falling edge of the digital signal received from the transmitting apparatus are detected, and an interrupt signal indicating a rising edge detection and an interrupt signal indicating a falling edge detection are received in the reception control means. When the interrupt control signal indicating the rising edge detection is input, the reception control unit starts the count, and the interrupt signal indicating the falling edge detection is input. It is preferable to end the counting.
Thereby, the processing capability in the reception control means can be improved.

 In addition, the communication device according to the present invention transmits a pulse width modulated digital signal to another communication device, and has a software counter function, and one of the rising edge or the falling edge of the digital signal received from the other communication device. Communication control means for starting counting in synchronization with and grasping the count value obtained by ending the counting in synchronization with the other of the rising edge or falling edge as the pulse width of the received digital signal The communication control means has a pulse width corresponding to “0” before transmission of a digital signal corresponding to data at the start of communication with the other communication device when the communication control means itself is a transmission side. The digital signal and a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal are transmitted and received by itself. In the case of the side, the count value corresponding to the pulse width of the received first digital signal is acquired as the first determination count value, and the count value corresponding to the pulse width of the second digital signal is set to the second value. And a digital signal “0” or “1” corresponding to the received data is determined based on the first and second determination count values.

Thus, by providing the functions of both the transmitting device and the receiving device described above in one communication device, bidirectional communication with other communication devices becomes possible. Of course, the following effects can be obtained.
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of a communication failure due to a change in the operating environment.
(3) Since it can be applied to an asynchronous system, it is possible to realize high-speed communication and low power consumption independent of the frequency of the clock signal.

Further, in the communication device according to the present invention, the communication control means calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and the data It is preferable to discriminate between “0” and “1” of the digital signal corresponding to the data by comparing the threshold value with a count value corresponding to the pulse width of the digital signal corresponding to.
Thereby, even when the count value includes a count error, it is possible to accurately determine “0” or “1”.

In the communication apparatus according to the present invention, it is preferable that the communication control unit calculates an average value of the first determination count value and the second determination count value as the threshold value.
As a result, even when the count value includes a count error, it is possible to more accurately determine “0” or “1”.

In the communication device according to the present invention, the rising edge and the falling edge of the digital signal received from the other communication device are detected, and the interrupt signal indicating the rising edge detection and the interrupt signal indicating the falling edge detection are detected in the communication. Edge detecting means for outputting to the control means, and the communication control means starts counting when an interrupt signal indicating the rising edge detection is input, and receives an interrupt signal indicating the falling edge detection. It is preferable to end the counting in the case of an error.
Thereby, the processing capability in the communication control means can be improved.

  The semiconductor device according to the present invention includes a transmission side circuit having a transmission control means for transmitting a pulse width modulated digital signal, and a software counter function, and is synchronized with one of a rising edge and a falling edge of the digital signal. A reception side circuit having reception control means for grasping as a pulse width of the digital signal a count value obtained by starting the count and ending the count in synchronization with the other of the rising edge or the falling edge The transmission control means includes a first digital signal having a pulse width corresponding to “0” and “1” before transmission of a digital signal corresponding to data at the start of communication with the receiving device. And a second digital signal having a pulse width different from that of the first digital signal, and the reception control means A count value corresponding to the pulse width of the first digital signal is acquired as a first determination count value, and a count value corresponding to the pulse width of the second digital signal is acquired as a second determination count value. Then, based on the first and second discrimination count values, “0” and “1” of the digital signal corresponding to the data received from the transmission device are discriminated.

According to the semiconductor device having such characteristics, the following effects can be obtained.
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of an internal operation failure (communication failure between the transmission side circuit and the reception side circuit) due to a change in the operating environment.
(3) Since an asynchronous system can be applied, it is possible to realize high-speed operation and low power consumption independent of the frequency of the clock signal.

 In addition, the semiconductor device according to the present invention transmits a pulse width modulated digital signal to another semiconductor device and has a software counter function, and one of the rising edge and the falling edge of the digital signal received from the other semiconductor device. Communication control means for starting counting in synchronization with and grasping the count value obtained by ending the counting in synchronization with the other of the rising edge or falling edge as the pulse width of the received digital signal The communication control means has a pulse width corresponding to “0” before transmission of a digital signal corresponding to data at the start of communication with the other semiconductor device when the communication control means itself is a transmission side. Transmitting a digital signal and a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal; When the body is the receiving side, the count value corresponding to the pulse width of the received first digital signal is acquired as the first discrimination count value, and the count value corresponding to the pulse width of the second digital signal Is obtained as the second discrimination count value, and “0” and “1” of the digital signal corresponding to the received data are discriminated based on the first and second discrimination count values. And

According to the semiconductor device having such characteristics, two-way communication between the semiconductor devices becomes possible. Of course, the following effects can be obtained.
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of a communication failure due to a change in the operating environment.
(3) Since it can be applied to an asynchronous system, it is possible to realize high-speed communication and low power consumption independent of the frequency of the clock signal.

  Further, the communication system according to the present invention comprises a transmitting side for transmitting a pulse width modulated digital signal, and a software counter function, and starts counting in synchronization with one of the rising edge or falling edge of the digital signal, A receiving side that acquires a count value obtained by ending the counting in synchronization with the other of the rising edge or the falling edge as a pulse width of the digital signal, and the transmitting side is connected to the receiving side. At the start of communication, before transmission of a digital signal corresponding to data, a first digital signal having a pulse width corresponding to “0” and a pulse width corresponding to “1” and different from the first digital signal The second digital signal having the first digital signal having a count value corresponding to a pulse width of the first digital signal. And a count value corresponding to the pulse width of the second digital signal is acquired as a second determination count value, and the transmission side is based on the first and second determination count values. The digital signal corresponding to the data received from “0” and “1” is discriminated.

According to the communication system having such characteristics, the following effects can be obtained.
(1) A clock signal source is unnecessary on both the transmission side and the reception side, and the system cost can be reduced.
(2) It is possible to prevent the occurrence of a communication failure due to a change in the operating environment.
(3) In digital serial communication using a pulse width modulation method, it is possible to realize high-speed communication and low power consumption that do not depend on the frequency of the clock signal.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a communication system, a transmission device, a reception device, a communication device, a semiconductor device, and a communication method according to the present invention will be described with reference to the drawings.
[Communication system, transmitter, receiver]
FIG. 1 is a configuration block diagram of a communication system in the present embodiment. As shown in FIG. 1, the communication system according to this embodiment includes a transmission device 10, a reception device 20, and a signal transmission path 30. The transmission device 10 includes a transmission side CPU (Central Processing Unit) 11 and a digital signal output circuit 12. The reception device 20 includes an edge detection circuit 21 and a reception side CPU 22. Note that the communication system in this embodiment employs digital serial communication using a pulse width modulation method as a communication method between the transmission device 10 and the reception device 20. In the present embodiment, the pulse width refers to a high level period of a digital signal.

  In the transmission apparatus 10, the transmission side CPU 11 (transmission control means) transmits the pulse width modulated digital signal to the reception apparatus 20 via the digital signal output circuit 12 and the signal transmission path 30. Further, the transmission side CPU 11 transmits a predetermined code signal (for example, “01”) before transmission of a digital signal corresponding to data at the start of communication with the receiving device 20. The code signal includes a first digital signal having a pulse width corresponding to “0” and a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal. Signal.

  The digital signal output circuit 12 transmits the pulse width modulated digital signal (including the code signal) output from the transmission side CPU 11 to the edge detection circuit 21 of the reception device 20 through the signal transmission path 30.

  In the receiving device 20, the edge detection circuit 21 (edge detection means) detects a rising edge and a falling edge of the digital signal received from the transmitting device 10, and generates an interrupt signal indicating the rising edge detection (hereinafter referred to as a count start interrupt signal). And an interrupt signal indicating falling edge detection (hereinafter referred to as a count end interrupt signal) is output to the receiving CPU 22.

  The reception side CPU 22 (reception control means) has a software counter function, starts counting in synchronization with the count start interrupt signal (that is, the rising edge of the digital signal received from the transmission device 10), and count end interrupt signal (that is, transmission). The count value obtained by ending the count in synchronization with the falling edge of the digital signal received from the device 10 is grasped as the pulse width of the digital signal received from the transmitting device 10. Further, the reception side CPU 22 acquires a count value corresponding to the pulse width of the first digital signal included in the code signal received from the transmission device 10 as the first determination count value, and the second digital signal. The count value corresponding to the pulse width of the second is acquired as the second determination count value, and a threshold value for determining “0” and “1” is calculated using the first and second determination count values. Then, the value is stored in the internal register in advance, and the count value corresponding to the pulse width of the digital signal corresponding to the data received from the transmission apparatus 10 is compared with the threshold value, thereby “0” of the digital signal corresponding to the data. "1" is discriminated.

Next, the operation (communication method) of the communication system in the present embodiment configured as described above will be described.
FIG. 2 is a timing chart showing a waveform of a digital signal (digital signal corresponding to a code signal and data) transmitted by the transmission side CPU 11 of the transmission apparatus 10 and an operation waveform of a software counter in the reception side CPU 22 of the reception apparatus 20. .

  As shown in FIG. 2, at the start of communication, the sending CPU 11 has a first digital signal having a pulse width corresponding to “0” and a pulse corresponding to “1” different from the first digital signal. The code signal “01” including the second digital signal having the width is transmitted to the receiving device 20. In the present embodiment, the pulse width corresponding to “1” is set to be larger than the pulse width corresponding to “0”.

  When detecting the rising edge of the first digital signal having a pulse width corresponding to “0” at time t1 in FIG. 2, the edge detection circuit 21 of the reception device 20 outputs a count start interrupt signal to the reception CPU 22. . At this time, the receiving CPU 22 starts a counting operation by the software counter function in synchronization with the count start interrupt signal. Specifically, the receiving side CPU 22 sets the count variable CNT, assigns a predetermined internal register for the count operation of the count variable CNT, and uses this register to “read” → “increment” → “ A series of processing called “light” is repeated. Such a counting operation by the software counter function is not performed in synchronization with the clock signal (that is, the clock signal source is unnecessary), and the operation speed thereof is a circuit such as a transistor constituting the receiving side CPU 22 including the register exclusively. Depends on device performance.

  Subsequently, at time t <b> 2, when the edge detection circuit 21 detects a falling edge of the first digital signal having a pulse width corresponding to “0”, it outputs a count end interrupt signal to the receiving CPU 22. At this time, the receiving CPU 22 finishes the counting operation by the software counter function in synchronization with the count end interrupt signal, and acquires the value of the count variable CNT (that is, the count value) as the first determination count value CNT0 (CNT0). Stored in the register for).

  Similarly, when the edge detection circuit 21 detects a rising edge of the second digital signal having a pulse width corresponding to “1” at time t 3, it outputs a count start interrupt signal to the receiving CPU 22. At this time, the receiving CPU 22 starts a counting operation by the software counter function in synchronization with the count start interrupt signal.

  At time t4, when the edge detection circuit 21 detects a falling edge of the second digital signal having a pulse width corresponding to “1”, it outputs a count end interrupt signal to the receiving CPU 22. At this time, the receiving CPU 22 finishes the count operation by the software counter function in synchronization with the count end interrupt signal, and acquires the value of the count variable CNT as the second determination count value CNT1 (stored in the register for CNT1). To do).

Here, the reception side CPU 22 discriminates between “0” and “1” of the digital signal transmitted from the transmission device 10 using the first discrimination count value CNT0 and the second discrimination count value CNT1. A threshold value CNTh for calculating the threshold value is calculated. In the present embodiment, the average value of the first determination count value CNT0 and the second determination count value CNT1 is calculated as the threshold value CNTh for determining “0” and “1”. That is, the threshold value CNTh is expressed by the following equation (1). For example, assuming that CNT0 = 10 and CNT1 = 20, the threshold value CNTh = 15. When the reception side CPU 22 calculates the threshold value CNTh for determining “0” or “1” in this way, it stores it in the threshold value register.
CNTh = (CNT0 + CNT1) / 2 (1)

  Subsequently, when a digital signal corresponding to data is transmitted from the transmission side CPU 11 after time t4 in FIG. 2 (after the code signal), the edge detection circuit 21 detects the digital signal corresponding to the data at time t5. A rising edge is detected and a count start interrupt signal is output to the receiving CPU 22. At this time, the receiving CPU 22 starts a counting operation by the software counter function in synchronization with the count start interrupt signal.

  At time t6, the edge detection circuit 21 detects the falling edge of the digital signal corresponding to the data and outputs a count end interrupt signal to the receiving CPU 22. At this time, the receiving side CPU 22 compares the value of the count variable CNT obtained by ending the counting operation by the software counter function in synchronization with the count end interrupt signal and the threshold value CNTh, thereby obtaining a digital signal corresponding to the data. “0” and “1” are discriminated. Specifically, “0” is determined when CNT ≦ CNTh, and “1” is determined when CNT> CNTh. For example, if the threshold value CNTh = 15 and the count value CNT = 19 between time t5 and t6 = 19, the receiving CPU 22 determines that “1” data has been received from the transmitting device 10.

  Similarly, for example, when the count value CNT = “21” between the times t <b> 7 and t <b> 8, the reception side CPU 22 determines that the data “1” has been received from the transmission device 10. Further, when the count value CNT = “8” between the times t <b> 9 and t <b> 10, the reception-side CPU 22 determines that “0” data has been received from the transmission device 10.

As described above, according to the communication system of the present embodiment,
(1) Since the pulse width of the pulse width-modulated digital signal is measured using a software counter, neither the transmission device 10 nor the reception device 20 requires a clock signal source, and the system cost can be reduced.
(2) Since the first discrimination count value CNT0 and the second discrimination count value CNT1 are obtained by a software counter that does not require a clock signal source, changes in the operating environment such as temperature and power supply voltage Thus, it is possible to prevent communication from failing.
Further, the count value CNT includes a count error by setting the average value of the first discrimination count value CNT0 and the second discrimination count value CNT1 to the threshold value CNTh for discrimination of “0” and “1”. Even in such a case, it is possible to accurately determine “0” or “1”.
(3) Since a clock signal (predetermined synchronization timing) is not required, communication between asynchronous systems or between a synchronous system and an asynchronous system is possible. In other words, by applying the communication system according to the present embodiment to an asynchronous system, it is possible to realize high-speed communication and low power consumption that do not depend on the frequency of the clock signal in digital serial communication using the pulse width modulation method. .

  In the above embodiment, the average value of the first discrimination count value CNT0 and the second discrimination count value CNT1 is set to the threshold value CNTh for discrimination of “0” and “1”. The threshold value CNTh may be obtained by other calculation methods. Further, when it is not necessary to consider the occurrence of a count error using a high-precision software counter, it is not always necessary to obtain the threshold value CNTh for determining “0” or “1”, and the digital signal corresponding to the data is counted. By checking whether the value CNT matches the first determination count value CNT0 or the second determination count value CNT1, the data “0” and “1” are determined. Also good.

  In the above-described embodiment, the description has been made assuming a system in which the high level period of the digital signal is a pulse width, but the present invention can also be applied to a system in which the low level period of the digital signal is a pulse width. In this case, the counting operation may be started in synchronization with the falling edge of the digital signal, and the counting operation may be ended in synchronization with the rising edge. Furthermore, although the above embodiment has been described assuming a system in which the pulse width corresponding to “1” is larger than the pulse width corresponding to “0”, the present invention can be applied to the opposite system.

Further, for example, the transmission device 10 is provided with means for grasping changes in the operating environment such as a temperature sensor and a power supply voltage measurement circuit, and the transmission-side CPU 11 monitors output signals from the temperature sensor and the power supply voltage measurement circuit. When the output signal changes, that is, when the operating environment changes, a new code signal may be transmitted to the receiving device 20 at the start of communication.
In this way, by transmitting and receiving the code signal (first digital signal corresponding to “0” and second digital signal corresponding to “1”) at the start of communication according to changes in the operating environment, The receiving device 20 can acquire the first and second determination count values according to the operating environment, and further dynamically changes the threshold value CNTh for determining “0” and “1” according to the operating environment. Therefore, it is possible to prevent data communication failure due to changes in the operating environment.

  In the above embodiment, the transmission side CPU 11 and the reception side CPU 22 may be configured with an asynchronous circuit that does not require a clock signal, or between CPUs configured with a synchronous circuit. Even if it is a combination, the same effect can be acquired.

〔Communication device〕
Next, an embodiment of a communication apparatus according to the present invention will be described. In the above embodiment, the case where one-way communication is performed from the transmission device 10 to the reception device 20 has been described. However, the communication device according to the present embodiment has a configuration capable of realizing not only one-way communication but also two-way communication. Is.

  FIG. 3 shows a block diagram of the configuration of the communication device 40 in the present embodiment. As shown in FIG. 3, the communication device 40 in this embodiment includes a communication control unit 41, a digital signal output circuit 42, and an edge detection circuit 43. The digital signal output circuit 42 has the same function as the digital signal output circuit 12 of the transmission device 10 described above, and the edge detection circuit 43 has the same function as the edge detection circuit 21 of the reception device 20. Therefore, detailed description thereof will be omitted.

  The communication control unit 41 (communication control means) has the functions of both the transmission side CPU 11 and the reception side CPU 22 described above. That is, the communication control unit 41 transmits a pulse width modulated digital signal to another communication device via the digital signal output circuit 42, and has a software counter function and outputs a count start interrupt output from the edge detection circuit 43. A count operation is started in synchronization with the signal, and a count value obtained by ending the count operation in synchronization with the count end interrupt signal is grasped as a pulse width of a digital signal received from another communication device.

In addition, when the communication control unit 41 is the transmission side, the first communication unit 41 has a pulse width corresponding to “0” before transmission of a digital signal corresponding to data at the start of communication with another communication device. A code signal including a digital signal and a second digital signal corresponding to “1” and having a pulse width different from that of the first digital signal is transmitted. Furthermore, when the communication control unit 41 is the receiving side, the communication control unit 41 sets the count value corresponding to the pulse width of the first digital signal included in the code signal received from another communication device as the first determination count value CNT0. At the same time, a count value corresponding to the pulse width of the second digital signal is acquired as the second discrimination count value CNT1, and “0” and “1” are used by using these first and second discrimination count values. ”Is calculated and stored in the internal register in advance, and the count value CNT corresponding to the pulse width of the digital signal corresponding to the data received from another communication device and the threshold value CNTh By comparing, “0” and “1” of the digital signal corresponding to the data are discriminated.
Since the operation of the communication device 40 is the same as that of the communication system described above, description thereof is omitted.

According to the communication device 40 having such a configuration, bidirectional communication with other communication devices is possible, and the following effects can be obtained as in the communication system described above.
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of a communication failure due to a change in the operating environment.
(3) Since it can be applied to an asynchronous system, it is possible to realize high-speed communication and low power consumption independent of the frequency of the clock signal.

[Semiconductor device]
Next, an embodiment of a semiconductor device according to the present invention will be described. In the following, a first embodiment in which the communication method according to the present invention is applied to data communication between circuits provided in a semiconductor device, and a second embodiment in which the communication method according to the present invention is applied to data communication between semiconductor devices. Embodiments will be described.

<First Embodiment>
FIG. 4 is a block diagram showing the configuration of the semiconductor device 50 according to the first embodiment. The semiconductor device 50 is, for example, an LSI (Large Scale Integration), and includes a transmission side circuit 60 and a reception side circuit 70 therein. The semiconductor device 50, which is an LSI, includes a large number of circuit blocks having various functions, but is omitted in FIG.

 The transmission side circuit 60 includes a transmission side CPU 61 and a digital signal output circuit 62. The reception side circuit 70 includes an edge detection circuit 71 and a reception side CPU 72. The transmission side CPU 61 and the digital signal output circuit 62 have the same functions as the transmission side CPU 11 and the digital signal output circuit 12 in the transmission device 10 described above, and the edge detection circuit 71 and the reception side CPU 72 are in the reception device 20 described above. The edge detection circuit 21 and the reception side CPU 22 have the same functions. Since the operation of the semiconductor device 50 is the same as that of the communication system described above, the description thereof is omitted.

According to the semiconductor device 50 having such a configuration,
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of an internal operation failure (communication failure between the transmission side circuit 60 and the reception side circuit 70) due to a change in the operating environment.
(3) Since an asynchronous system can be applied, it is possible to realize a semiconductor device with high speed operation and low power consumption that does not depend on the frequency of the clock signal.

Second Embodiment
FIG. 5 is a block diagram showing the configuration of the semiconductor device 80 according to the second embodiment. The semiconductor device 80 is, for example, an LSI (Large Scale Integration), and includes a communication control unit 81, a digital signal output circuit 82, and an edge detection circuit 83. The semiconductor device 80, which is an LSI, includes a large number of circuit blocks having various functions, but is omitted in FIG.

 The communication control unit 81, the digital signal output circuit 82, and the edge detection circuit 83 have the same functions as the communication control unit 41, the digital signal output circuit 42, and the edge detection circuit 43 in the communication device 40 described above. Since the operation of the semiconductor device 80 is the same as that of the communication device 40 described above, description thereof is omitted.

According to the semiconductor device 80 having such a configuration, bidirectional communication with other semiconductor devices is possible, and the following effects can be obtained as in the communication device 40 described above.
(1) A clock signal source is unnecessary, and the cost of the apparatus can be reduced.
(2) It is possible to prevent the occurrence of a communication failure due to a change in the operating environment.
(3) Since it can be applied to an asynchronous system, it is possible to realize high-speed communication and low power consumption independent of the frequency of the clock signal.

1 is a configuration block diagram of a communication system in an embodiment of the present invention. It is operation | movement explanatory drawing of the communication system in one Embodiment of this invention. 1 is a configuration block diagram of a communication device according to an embodiment of the present invention. It is the 1st explanatory view of the semiconductor device in one embodiment of the present invention. It is a 2nd explanatory view of a semiconductor device in one embodiment of the present invention.

Explanation of symbols

 DESCRIPTION OF SYMBOLS 10 ... Transmission apparatus, 11, 61 ... Transmission side CPU, 12, 42, 62, 82 ... Digital signal output circuit, 20 ... Reception apparatus, 21, 43, 71, 83 ... Edge detection circuit, 22, 72 ... Reception side CPU , 30 ... signal transmission path, 40 ... communication device, 41, 81 ... communication control unit, 50, 80 ... semiconductor device, 60 ... transmission side circuit, 70 ... reception side circuit

Claims (17)

A transmission apparatus having transmission control means for transmitting a pulse width modulated digital signal;
A count value obtained by having a software counter function, starting counting in synchronization with one of the rising edge or falling edge of the digital signal, and ending the counting in synchronization with the other of the rising edge or falling edge Comprising a reception control means for grasping as a pulse width of the digital signal,
The transmission control means corresponds to a first digital signal having a pulse width corresponding to “0” and “1” before transmission of a digital signal corresponding to data at the start of communication with the receiving apparatus. Transmitting a second digital signal having a pulse width different from that of the first digital signal;
The reception control means obtains a count value corresponding to the pulse width of the first digital signal as a first determination count value, and sets a count value corresponding to the pulse width of the second digital signal to a second value. And determining the digital signal “0” or “1” corresponding to the data received from the transmitting device based on the first and second determination count values.
A communication system characterized by the above.   The reception control means calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and according to the pulse width of the digital signal corresponding to the data The communication system according to claim 1, wherein “0” or “1” of the digital signal corresponding to the data is determined by comparing the counted value with the threshold value.   3. The communication system according to claim 2, wherein the reception control unit calculates an average value of the first determination count value and the second determination count value as the threshold value. The receiving device is:
Edge detection means for detecting a rising edge and a falling edge of a digital signal received from the transmission device, and outputting an interrupt signal indicating rising edge detection and an interrupt signal indicating falling edge detection to the reception control means;
The reception control means starts the counting when an interrupt signal indicating the rising edge detection is input, and ends the counting when the interrupt signal indicating the falling edge detection is input. The communication system according to any one of claims 1 to 3.  By transmitting and receiving the first digital signal and the second digital signal at the start of communication according to a change in the operating environment, the first and second determination count values corresponding to the operating environment are obtained. The communication system according to claim 1, wherein the communication system is acquired. Transmission control means for transmitting a pulse width modulated digital signal to a receiving device;
The transmission control means corresponds to a first digital signal having a pulse width corresponding to “0” and a corresponding to “1” before transmission of a digital signal corresponding to data at the start of communication with the receiving device. Transmitting a second digital signal having a different pulse width from the first digital signal;
A transmission apparatus characterized by the above. A software counter function is provided, and starts counting in synchronization with one of a rising edge or a falling edge of a digital signal received from the transmission device according to claim 6 and synchronized with the other of the rising edge or the falling edge. Receiving control means for grasping a count value obtained by ending the count as a pulse width of the digital signal;
The reception control means acquires a count value corresponding to a pulse width of the first digital signal received from the transmission device according to claim 6 as a first determination count value, and A count value corresponding to the pulse width is acquired as a second discrimination count value, and “0” of the digital signal corresponding to the data received from the transmission device is obtained based on the first and second discrimination count values. "" 1 "is discriminated,
A receiving apparatus.  The reception control means calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and according to the pulse width of the digital signal corresponding to the data 8. The receiving apparatus according to claim 7, wherein “0” and “1” of the digital signal corresponding to the data are discriminated by comparing the counted value with the threshold value.  9. The receiving apparatus according to claim 8, wherein the reception control unit calculates an average value of the first determination count value and the second determination count value as the threshold value. Edge detection means for detecting a rising edge and a falling edge of a digital signal received from the transmission device, and outputting an interrupt signal indicating rising edge detection and an interrupt signal indicating falling edge detection to the reception control means;
The reception control means starts the counting when an interrupt signal indicating the rising edge detection is input, and ends the counting when the interrupt signal indicating the falling edge detection is input. The receiving device according to any one of claims 7 to 9. The pulse width modulated digital signal is transmitted to another communication device, and has a software counter function, and starts counting in synchronization with one of the rising edge or falling edge of the digital signal received from the other communication device, Communication control means for grasping the count value obtained by ending the count in synchronization with the other of the rising edge or the falling edge as the pulse width of the received digital signal;
The communication control means includes
When the device itself is the transmission side, the first digital signal having a pulse width corresponding to “0” and “1” before transmission of the digital signal corresponding to the data at the start of communication with the other communication device. And transmitting a second digital signal having a pulse width different from that of the first digital signal,
When the receiver itself is the receiving side, the count value corresponding to the pulse width of the received first digital signal is acquired as the first determination count value, and the count value corresponding to the pulse width of the second digital signal Is determined as a second determination count value, and “0” and “1” of the digital signal corresponding to the received data are determined based on the first and second determination count values.
A communication device.  The communication control means calculates a threshold value for discriminating between “0” and “1” using the first and second discrimination count values, and according to the pulse width of the digital signal corresponding to the data 12. The communication apparatus according to claim 11, wherein “0” and “1” of the digital signal corresponding to the data are discriminated by comparing the counted value with the threshold value.   13. The communication apparatus according to claim 12, wherein the communication control unit calculates an average value of the first determination count value and the second determination count value as the threshold value. Edge detecting means for detecting a rising edge and a falling edge of a digital signal received from the other communication device and outputting an interrupt signal indicating rising edge detection and an interrupt signal indicating falling edge detection to the communication control means; And
The communication control means starts the counting when an interrupt signal indicating the rising edge detection is input, and ends the counting when the interrupt signal indicating the falling edge detection is input. The communication apparatus according to any one of claims 11 to 13. A transmission side circuit having a transmission control means for transmitting a pulse width modulated digital signal;
A count value obtained by having a software counter function, starting counting in synchronization with one of the rising edge or falling edge of the digital signal, and ending the counting in synchronization with the other of the rising edge or falling edge A receiving side circuit having a receiving control means for grasping as a pulse width of the digital signal,
The transmission control means corresponds to a first digital signal having a pulse width corresponding to “0” and “1” before transmission of a digital signal corresponding to data at the start of communication with the receiving apparatus. Transmitting a second digital signal having a pulse width different from that of the first digital signal;
The reception control means obtains a count value corresponding to the pulse width of the first digital signal as a first determination count value, and sets a count value corresponding to the pulse width of the second digital signal to a second value. And determining the digital signal “0” or “1” corresponding to the data received from the transmitting device based on the first and second determination count values.
A semiconductor device. The pulse width modulated digital signal is transmitted to another semiconductor device, and has a software counter function, and starts counting in synchronization with either the rising edge or the falling edge of the digital signal received from the other semiconductor device, Communication control means for grasping the count value obtained by ending the count in synchronization with the other of the rising edge or the falling edge as the pulse width of the received digital signal;
The communication control means includes
When the device itself is the transmission side, the first digital signal having a pulse width corresponding to “0” and “1” before transmission of the digital signal corresponding to the data at the start of communication with the other semiconductor device. And transmitting a second digital signal having a pulse width different from that of the first digital signal,
When the receiver itself is the receiving side, the count value corresponding to the pulse width of the received first digital signal is acquired as the first determination count value, and the count value corresponding to the pulse width of the second digital signal Is determined as a second determination count value, and “0” and “1” of the digital signal corresponding to the received data are determined based on the first and second determination count values.
A semiconductor device. A transmitter for transmitting a pulse width modulated digital signal;
A count value obtained by having a software counter function, starting counting in synchronization with one of the rising edge or falling edge of the digital signal, and ending the counting in synchronization with the other of the rising edge or falling edge A receiving side for obtaining the pulse width of the digital signal,
The transmission side corresponds to a first digital signal having a pulse width corresponding to “0” and a corresponding to “1” before transmission of a digital signal corresponding to data at the start of communication with the reception side. Transmitting a second digital signal having a different pulse width from the first digital signal;
The receiving side obtains a count value corresponding to the pulse width of the first digital signal as a first determination count value, and sets a count value corresponding to the pulse width of the second digital signal to a second value. Obtained as a discrimination count value, and based on the first and second discrimination count values, discriminates “0” “1” of the digital signal corresponding to the data received from the transmission side;
A communication method characterized by this.

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