JP2007259094A - Serial communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable reduction of both a communication time when transferring data and a transfer error occurrence frequency, by making it possible to properly adjust a baud rate according to a transmission data size, without transmitting/receiving a special command, and to reduce an initialization processing time by making unnecessary a series of operation for determining the baud rate. <P>SOLUTION: A start mark ST in the transfer data of a start-stop synchronization method is set to be a 2-bit alternating data. A detector 22 obtains a pulse width PW by measuring between a rise and a fall edge of the ST, a generator 23 generates a CK2 corresponding to the baud rate from the PW, and a reception controller 24 fetches the data from the CK2. A calculation setter 26 obtains an optimal baud rate corresponding to the size of a processing result data D4 in a data, and a generator 27 generates a CK3 corresponding to the optimal baud rate. A transmission controller 28 fetches D4 using CK3, and transmits the above ST with added stop mark thereafter. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a serial communication apparatus capable of automatically adjusting a baud rate when serial communication is performed in an asynchronous manner.

Conventionally, when performing serial communication between a plurality of communication devices, there are, for example, a configuration in which each communication device performs communication at a predetermined baud rate (communication speed), a configuration in which a transmission side matches a baud rate with a reception side, and the like.
For example, in a system that communicates between a master device and a plurality of slave devices, in the former configuration, all of the master device and each slave device communicate at a predetermined baud rate. In the latter configuration, the master device sequentially asks the slave device at a plurality of baud rates, and the baud rate at which the response is made is used as the baud rate of the system. In other words, the slave device can receive correctly when making an inquiry at the same baud rate as its own device. In this case, a response to the master device is possible, and the baud rate is determined by the response from the slave device. It has become.

As this type of conventional serial communication device, for example, there are those described in Patent Documents 1 and 2. In any of these, by transmitting a special AT command from the transmitting side to the receiving side, the receiving side grasps the baud rate and receives the next data at the grasped baud rate.
JP 2000-278356 A Japanese Patent Laid-Open No. 10-294772

  However, the conventional serial communication device has the following problems. In a configuration in which each communication device performs communication at a predetermined baud rate, communication is not possible unless the baud rate is fixed. When the baud rate is fixed, it is impossible to adjust the baud rate according to the transmission data size, and when the transmission data size increases, the communication time becomes longer. Furthermore, the fixed baud rate is a high-speed communication rate. The frequency of occurrence of transfer errors increases.

Next, in a configuration in which the transmission side matches the baud rate with the reception side, a series of operations are required on the transmission / reception side to determine the baud rate, so that initialization processing takes time.
In Patent Documents 1 and 2 described above, a special AT command is transmitted and received to grasp the baud rate, so that an extra configuration for that is required.
The present invention has been made in view of such problems, and enables communication time during data transfer by appropriately adjusting the baud rate according to the transmission data size without transmitting / receiving special commands. And a serial communication device that can reduce the frequency of occurrence of transfer errors and can reduce the initialization processing time by eliminating the need for a series of operations for determining the baud rate. It is aimed.

  To achieve the above object, a serial communication apparatus according to claim 1 of the present invention performs serial communication in an asynchronous manner using transmission / reception data formatted in the order of a start mark portion, a data portion, and a stop mark portion. In a serial communication device, pulse width detection means for measuring a pulse width by measuring a falling edge and a rising edge of the alternating data in received data in which the start mark portion is 2-bit alternating data, and using the pulse width A reception clock generation means for generating a reception clock signal having a frequency corresponding to the communication speed obtained in this manner, a reception control means for obtaining the data part by taking reception data by the reception clock signal, and the reception control means. Detects the data size that is the processing result of the data part, and serializes this size data A calculation means for obtaining an optimum communication speed for transmission, a transmission clock generation means for generating a transmission clock signal having a frequency corresponding to the optimum communication speed, and taking in the data as the processing result by the transmission clock signal. And a transmission control means for adding a start mark portion of the alternating data structure of 2 bits before data and adding a stop mark portion after the data and transmitting to the communication partner.

  According to this configuration, it is possible to optimally adjust the communication speed according to the transmission data size without transmitting / receiving a special AT command as in the prior art. As a result, the communication time during data transfer can be shortened and the frequency of occurrence of transfer errors can be reduced. Furthermore, since the received data is received by measuring the pulse width of the received data and generating a reception clock signal having a frequency corresponding to the communication speed, a series of operations for determining the baud rate becomes unnecessary, thereby Such initialization processing time can be shortened.

The serial communication device according to claim 2 of the present invention is characterized in that, in claim 1, the transmission control means uses the start mark portion as alternating data exceeding 2 bits.
According to this configuration, the accuracy of measuring the pulse width by the pulse width detecting means can be further increased, and accordingly, the communication speed of the received data can be obtained with high accuracy.

  As described above, according to the present invention, the communication time during data transfer can be shortened by making it possible to appropriately adjust the baud rate according to the transmission data size without transmitting / receiving special commands. At the same time, the frequency of occurrence of transfer errors can be reduced, and further, a series of operations for determining the baud rate is unnecessary, and the initialization processing time can be shortened.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a communication system in which a serial communication device according to an embodiment of the present invention is applied to a master device and a plurality of slave devices.
The communication system shown in FIG. 1 is configured by connecting a master device 11 and first to nth slave devices 12-1 to 12-n via a serial communication line 13.
There are serial communication lines 13 for half-duplex and full-duplex communication. Here, it is assumed that the serial communication line 13 is a full-duplex line composed of two lines for transmission data and reception data.

  Each of the master device 11 and each of the slave devices 12-1 to 12-n includes a serial communication device 20 shown in FIG. The serial communication device 20 includes a reception buffer 21, a pulse width detection unit (pulse width detection unit) 22, a reception clock generation unit (reception clock generation unit) 23, a reception control unit (reception control unit) 24, and data processing. A unit 25, a division ratio calculation setting unit (calculation unit) 26, a transmission clock generation unit (transmission clock generation unit) 27, and a transmission control unit (transmission control unit) 28 are configured. The reception control unit 24 includes a start mark removal unit 24a, a data unit 24b, and a stop mark removal unit 24c, and the transmission control unit 28 includes a start mark addition unit 28a, a data unit 28b, and a stop mark addition unit 28c.

Data (received data) D1 from the communication partner side received via the serial communication line 13 by the serial communication device 20 and data (transmission data) D2 transmitted from the serial communication device 20 to the communication partner side are: The format configuration shown in FIG. In some cases, the received data D1 and the transmitted data D2 are expressed as serial transfer data to distinguish them.
That is, the serial transfer data is usually the same as the signal format used when serial communication is performed in an asynchronous manner, and represents the start mark portion ST indicating the start of transfer, the data portion DA, and the end of transfer. Stop mark portions SP are arranged in this order.

  This feature is that the start mark portion ST has two bits of “0” and “1”. As will be described later, this is a pattern configuration for detecting the falling edge e1 and the rising edge e2 from the start mark portion ST and measuring the pulse width PW. This 2-bit pattern is the minimum pattern, and when it is necessary to further improve the accuracy, the repetition of “0” and “1” may be lengthened. The start mark portion ST having this characteristic configuration is added by a transmission control unit 28 described later.

  The reception buffer 21 uses a first-in first-out (FiFo) memory, has a buffer size necessary for detecting the start mark portion ST of the reception data D1 and measuring the pulse width PW, and has a basic clock signal. The received data D1 is sequentially buffered by CK1. However, the buffer size is the length of the start mark ST at the slowest baud rate used during communication.

However, the frequency of the basic clock signal CK1 is preferably about several hundred times the fastest baud rate among the baud rates used during communication in consideration of communication stability.
The pulse width detection unit 22 takes in the reception data D1 by the basic clock signal CK1, and measures the pulse width PW of the start mark portion ST included in the reception data D1 as follows. The falling edge e1 and the rising edge e2 are extracted, and the pulse width PW is obtained by measuring the interval between the edges e1 and e2 with a counter or the like, and this is output to the reception clock generator 23. That is, in order to extract the falling edge e1 and the rising edge e2 and obtain the pulse width PW, the start mark portion ST has a 2-bit configuration of “0” and “1”.

  The reception clock generator 23 divides the basic clock signal CK1 using the pulse width PW to generate the reception clock signal CK2 as follows. In asynchronous communication, the 1-bit data width is X times the baud rate, but the pulse width PW is divided by the magnification X of the baud rate of the 1-bit data width (PW / X). As a result, N is used as the denominator. 1 / N is the division ratio 1 / N. Then, the basic clock signal CK1 is divided by the division ratio 1 / N, and this is output to the reception control unit 24 as the reception clock signal CK2.

For example, if the pulse width PW is “112”, since the 1-bit data width is 16 times the baud rate in asynchronous communication, 112/16 = 7, and 1/7 of the division ratio is obtained. Therefore, the basic clock signal CK1 is divided by 1/7, and the reception clock signal CK2 is obtained by this division.
However, when the basic clock signal CK1 is 20 MHz, the frequency division ratio 1 / N is as shown in the following (1) to (5).

(1) When the baud rate of the received data D1 is 5 Kbps, the pulse width PW of the start mark portion ST is 20M / 5K = 4000, so 4000/16 = 250, and the division ratio is 1/250.
(2) When the baud rate of the received data D1 is 10 Kbps, the pulse width PW of the start mark portion ST is 20M / 10K = 2000, so 2000/16 = 125, and the division ratio is 1/125.

(3) When the baud rate of the reception data D1 is 20 Kbps, the pulse width PW of the start mark portion ST is 20M / 20K = 1000, so 1000/16 = 62 and the frequency division ratio is 1/62.
(4) When the baud rate of the reception data D1 is 40 Kbps, the pulse width PW of the start mark portion ST is 20M / 40K = 500, so 500/16 = 31, and the division ratio is 1/31.

(5) When the baud rate of the received data D1 is 80 Kbps, the pulse width PW of the start mark portion ST is 20M / 80K = 250, so 250/16 = 15, and the division ratio is 1/15.
The reception control unit 24 takes in the reception data D1 from the reception buffer 21 by the reception clock signal CK2, removes the start mark part ST by the start mark removal unit 24a, removes the stop mark part SP by the stop mark removal unit 24c, and The data part DA is input to the data processing part 25 as the input data D3 by the data part 24b.

The data processing unit 25 takes in the input data D3, performs predetermined processing, and outputs the data of the processing result to the frequency division calculation setting unit 26 and the transmission control unit 28 as output data D4.
The division ratio calculation setting unit 26 holds the output data D4, obtains the optimum baud rate for transmitting the data of the held data size to the communication partner via the serial communication line 13, and further, the basic clock signal CK1. The frequency division ratio 1 / M for dividing the data to the frequency at which the data is transmitted at the optimum baud rate is obtained, set and output to the transmission clock generation unit 27.

The transmission clock generation unit 27 divides the basic clock signal CK1 by the division ratio 1 / M, and outputs this to the transmission control unit 28 as the transmission clock signal CK3.
The transmission control unit 28 captures the output data D4 in the data unit 28b by the transmission clock signal CK3, adds the start mark unit ST to the captured data unit DA (= D4) by the start mark appending unit 28a, and adds the stop mark. The stop mark part SP is added by the part 28c, and this is transmitted as transmission data D2 to the communication partner via the serial communication line 13.

  A serial communication operation between the master device 11 to which the serial communication device 20 having such a configuration is applied and each of the slave devices 12-1 to 12-n will be described with reference to a flowchart shown in FIG. However, the operation between the master device 11 and the first slave device 12-1 will be described. Further, it is assumed that the frequency of the basic clock signal CK1 of the first slave device 12-1 is 20 MHz.

In step S1, it is assumed that the data D1 is transmitted from the master device 11 to the first slave device 12-1 via the serial communication line 13 at a baud rate of 20 Kbps.
In step S2, the data D1 from the master device 11 is sequentially fetched by the basic clock signal CK1 and buffered in the reception buffer 21 of the first slave device 12-1.

  In step S3, simultaneously with the buffering operation, the pulse width detector 22 receives the reception data D1 by the basic clock signal CK1, and the falling edge e1 and the rising edge e2 of the start mark portion ST of the reception data D1 are detected. The pulse width PW = “1000” is obtained by extracting and measuring the interval between the edges e1 and e2 with a counter. This pulse width “1000” is output to the reception clock generator 23.

In step S4, the reception clock generation unit 23 divides the pulse width “1000” by the baud rate magnification “16” of the 1-bit data width, and the result “62” is the division ratio 1/62. , The 20 MHz basic clock signal CK1 is frequency-divided and output to the reception control unit 24 as the reception clock signal CK2.
In step S5, the reception control unit 24 takes in the reception data D1 from the reception buffer 21 by the reception clock signal CK2, removes the start mark part ST by the start mark removal part 24a, and stops the mark part by the stop mark removal part 24c. The SP is removed, and after this removal, the data part DA is output from the data part 24b to the data processing part 25 as input data D3.

In step S6, after the input data D3 is taken in by the data processing unit 25, a predetermined process is performed, and the data of the processing result is output as the output data D4 to the division ratio calculation setting unit 26 and the transmission control unit 28. Is output.
In step S 7, the output data D 4 is held in the division ratio calculation setting unit 26, and the baud rate optimal for transmitting the data having the held data size to the master device 11 as the communication partner via the serial communication line 13. (For example, 10 KHz) is required. Further, a division ratio “1/125” for dividing the 20 MHz basic clock signal CK1 to a frequency for transmitting data at the optimum baud rate of 10 KHz is obtained, and this is set and output to the transmission clock generation unit 27. .

In step S8, the transmission clock generator 27 divides the basic clock signal CK1 by the frequency division ratio “1/125”, and outputs this to the transmission controller 28 as the transmission clock signal CK3.
In step S9, the transmission control unit 28 takes the output data D4 into the data unit 28b by the transmission clock signal CK3, and the start mark adding unit 28a adds the start mark unit ST to the fetched data unit DA (= D4). Then, the stop mark adding portion 28c adds the stop mark portion SP, which is transmitted as transmission data D2 to the master device 11 through the serial communication line 13 at a baud rate of 10 Kbps.

  In this way, by using the serial communication device 20 of the present embodiment for the master device 11 and the slave devices 12-1 to 12-n, transmission data can be transmitted without transmitting / receiving special AT commands as in the prior art. The baud rate can be adjusted optimally according to the size. As a result, the communication time during data transfer can be shortened and the frequency of occurrence of transfer errors can be reduced. Further, since the reception clock signal CK2 having a frequency corresponding to the baud rate is generated by measuring the pulse width PW of the reception data and the data reception is performed, a series of operations for determining the baud rate becomes unnecessary, thereby It is possible to shorten the initialization processing time.

1 is a block diagram showing a configuration of a communication system in which a serial communication device according to an embodiment of the present invention is applied to a master device and a plurality of slave devices. It is a block diagram which shows the structure of the said serial communication apparatus. It is a format block diagram of the data transmitted / received by the said serial communication apparatus. It is a flowchart for demonstrating the serial communication operation | movement between the master apparatus with which the said serial communication apparatus was applied, and each slave apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Master apparatus 12-1 to 12-n Slave apparatus 13 Serial communication line 20 Serial communication apparatus 21 Reception buffer 22 Pulse width detection part 23 Reception clock generation part 24 Reception control part 24a Start mark removal part 24b Data part 24c Stop mark removal part 25 data processing unit 26 division ratio calculation setting unit 27 transmission clock generation unit 28 transmission control unit 28a start mark addition unit 28b data unit 28c stop mark addition unit D1 reception data D2 transmission data D3 input data D4 output data CK1 basic clock signal CK2 Receive clock signal CK3 Transmit clock signal PW Pulse width 1 / N, 1 / M Divide ratio X 1-bit data width baud rate multiplier

Claims (2)

In a serial communication device that performs serial communication in an asynchronous manner using data for transmission / reception formatted in the order of a start mark portion, a data portion, and a stop mark portion,
Pulse width detection means for measuring a pulse width by measuring a falling edge and a rising edge of the alternating data in the reception data in which the start mark portion is 2-bit alternating data;
A reception clock generating means for generating a reception clock signal having a frequency corresponding to a communication speed obtained using the pulse width;
A reception control means for obtaining the data part by receiving the reception data by the reception clock signal;
Calculating means for detecting the size of the data which is the processing result of the data part obtained by the reception control means, and obtaining an optimum communication speed for serial transmission of data of this size;
Transmission clock generation means for generating a transmission clock signal having a frequency corresponding to the optimum communication speed;
Transmission control means for fetching data as a result of the processing by the transmission clock signal, adding a start mark portion of the two-bit alternating data structure before the data, and adding a stop mark portion after the data and transmitting it to the communication partner And a serial communication device comprising:   2. The serial communication apparatus according to claim 1, wherein the transmission control means uses the start mark portion as alternating data having more than 2 bits.

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