JP2016127779A - Power supply system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply system capable of controlling partial charge of a power loss among a plurality of switching elements that form a power converter.SOLUTION: A power converter 50 includes a reactor L1 and switching elements S1-S4 configured to alternately form a first current path for storing energy in the reactor L1 and a second current path for emitting energy in the reactor L1 between a DC power source B1 and power lines PL and GL in response to a control signal from a control device 40. The switching elements S1-S4 include switching elements S3 and S4 which are electrically connected in series and configured to be commonly turned on and turned off in accordance with the control signal, thereby forming and cutting off the first current path. The control device 40 generates the control signal in such a manner that a time difference is provided in turn-on timing or turn-off timing between the switching elements S3 and S4.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power supply system, and more particularly to a power supply system for performing DC power conversion between a DC power supply and a load.

  As a power supply system for executing DC power conversion between a DC power supply and a load, for example, JP 2012-70514 A (Patent Document 1) and JP 2013-13234 A (Patent Document 2) include: A power supply system that supplies power to a load using a power converter connected between two DC power supplies and a load is described. In Patent Document 1 and Patent Document 2, the power converter is configured to perform DC power conversion in a state where two DC power sources are connected in series by switching switching patterns of a plurality of switching elements, and a series connection mode. An operation mode (parallel connection mode) in which DC power conversion is performed in a state where two DC power supplies are connected in parallel can be switched.

JP 2012-70514 A JP2013-13234A

  In the power converters described in Patent Documents 1 and 2, an operation mode in which DC power conversion is performed using only one of the two DC power sources can be selected according to the operating state of the DC power source and / or the load. In an operation mode in which only one of the two DC power supplies is used, on / off of the plurality of switching elements is controlled in accordance with a control pulse signal based on a duty ratio for controlling the output of the one DC power supply. Specifically, a pair of two switching elements that are electrically connected in series and constitute the upper arm of the step-up chopper circuit are on / off controlled in accordance with a control pulse signal and electrically connected in series, A pair of two switching elements constituting the lower arm of the step-up chopper circuit is commonly turned on / off according to the control pulse signal.

  At this time, power loss occurs in the upper and lower arms of the step-up chopper circuit during the switching operation of the pair of two switching elements that are controlled on and off in common. When the switching speeds between the two switching elements are equal to each other, the two switching elements are turned on and off at the same timing, so that the power loss is equally shared between the two switching elements. Therefore, compared with the power converter which comprises each arm with a single switching element, the power loss per element can be substantially halved.

  On the other hand, when the switching speeds are different between the two switching elements, the two switching elements cannot be turned on / off at the same time, so that the power loss generated in the two switching elements is biased. If the switching loss is biased, heat generation tends to occur intensively in one of the switching elements, so that the heat generation is biased, making it difficult to improve the output of the power converter.

  However, the magnitude of the switching speed fluctuates due to manufacturing variations of the switching elements, and therefore, it is determined by the event as to which switching element the switching loss is biased. Therefore, since it is difficult to control the sharing of power loss between the two switching elements, there is a problem that it is difficult to suppress the above-described bias of heat generation.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a power supply system capable of controlling the sharing of power loss among a plurality of switching elements constituting a power converter. Is to provide.

  In one aspect of the present invention, a power supply system for controlling a DC voltage between a first power line on a high voltage side and a second power line on a low voltage side includes a DC power supply, a DC power supply, and first and second power supplies. The power converter for performing direct-current power conversion between these power lines and a control device for controlling direct-current power conversion in the power converter are provided. In response to the control signal from the reactor and the control device, the power converter includes a first current path for storing energy in the reactor between the DC power source and the first and second power lines, and the reactor. A plurality of switching elements configured to alternately form second current paths for releasing energy. The plurality of switching elements are electrically connected in series and are turned on and off in common according to a control signal, thereby forming and blocking the first current path, the first and second switching elements including. The control device generates a control signal so as to provide a time difference between the turn-on timings or the turn-on timings of the first and second switching elements.

  Preferably, in the control device, the turn-on timing of the first switching element is earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element is earlier than the turn-off timing of the first switching element. So that the turn-on timing of the first mode for generating the control signal and the second switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element. Has a second mode for generating a control signal such that the control signal is later than the turn-off timing of the second switching element. The control device executes the first mode and the second mode in a time division manner.

  Preferably, the control device executes the first mode and the second mode in a time-sharing manner so that the time for executing the first mode and the time for executing the second mode are equal to each other. .

  In another aspect of the present invention, a power supply system for controlling a DC voltage between a first power line on a high voltage side and a second power line on a low voltage side includes a first DC power supply and a second DC power supply. A power converter, a power converter for executing DC power conversion in parallel between the first and second DC power supplies and the first and second power lines, and for controlling DC power conversion in the power converter A control device is provided. The power converter is electrically connected between the first switching element electrically connected between the first power line and the first node, and between the second node and the first node. A second switching element, a third switching element electrically connected between the second node and the third node electrically connected to the negative terminal of the second DC power supply, A fourth switching element electrically connected between the negative terminal of the DC power source and the third node, and the first DC power source in series between the second node and the second power line. A first reactor that is electrically connected and a second reactor that is electrically connected in series with the second DC power source are included between the first node and the third notebook. According to the control signal from the control device, the third and fourth switching elements are turned on in common, and the first and second switching elements are turned off in common to store energy in the first reactor. The first and second switching elements are commonly turned off and the first and second switching elements are commonly turned on in accordance with the control signal. A second current path is formed for releasing the stored energy of one reactor. The control device generates a control signal so as to provide a time difference in turn-on timing or turn-on timing of the third and fourth switching elements and to provide a time difference in turn-on timing or turn-off timing of the first and second switching elements. .

  Preferably, in the control device, the turn-on timing of the second switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element is greater than the turn-off timing of the second switching element. The turn-on timing of the third switching element is earlier than the turn-on timing of the fourth switching element, and the turn-off timing of the fourth switching element is later than the turn-off timing of the third switching element. As described above, the first mode for generating the control signal and the turn-on timing of the first switching element are earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element. Is delayed from the turn-off timing of the first switching element, the turn-on timing of the fourth switching element is earlier than the turn-on timing of the third switching element, and the turn-off timing of the third switching element is A second mode for generating the control signal so as to be later than the turn-off timing of the fourth switching element. The control device executes the first mode and the second mode in a time division manner.

  Preferably, the control device sets a dead time, which is a period for simultaneously blocking the first and second current paths, to the control signal when switching between the first current path and the second current path. To do. In each of the first and second modes, the control device sets a time difference so as not to exceed the dead time.

  Preferably, the control device executes the first mode and the second mode in a time-sharing manner so that the time for executing the first mode and the time for executing the second mode are equal to each other. .

  Preferably, according to a control signal from the control device, the second and third switching elements are turned on in common, and the first and fourth switching elements are turned off in common, whereby energy is supplied to the second reactor. While the third current path for accumulation is formed, according to the control signal, the second and third switching elements are turned off in common, and the first and fourth switching elements are turned on in common As a result, a fourth current path for discharging the stored energy of the second reactor is formed. The control device generates a control signal so as to provide a time difference in turn-on timing or turn-on timing of the second and third switching elements and to provide a time difference in turn-on timing or turn-off timing of the first and fourth switching elements. .

  Preferably, in the control device, the turn-on timing of the fourth switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element is the turn-off timing of the fourth switching element. The turn-on timing of the second switching element is earlier than the turn-on timing of the third switching element, and the turn-off timing of the third switching element is greater than the turn-off timing of the second switching element. So that the turn-on timing of the third mode for generating the control signal and the first switching element is earlier than the turn-on timing of the fourth switching element, and the turn-off timing of the fourth switching element. Is delayed from the turn-off timing of the first switching element, the turn-on timing of the third switching element is earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element. Has a fourth mode for generating the control signal so as to be later than the turn-off timing of the third switching element. The control device executes the third mode and the fourth mode in a time division manner.

  Preferably, the control device sets a dead time, which is a period for simultaneously blocking the third and fourth current paths, for the control signal when switching between the third current path and the fourth current path. To do. In each of the third and fourth modes, the control device sets a time difference so as not to exceed the dead time.

  Preferably, the control device executes the third mode and the fourth mode in a time division manner so that the time for executing the third mode and the time for executing the fourth mode are equal to each other. .

  According to the present invention, it is possible to provide a power supply system capable of controlling the sharing of power loss among a plurality of switching elements constituting a power converter.

It is a circuit diagram which shows the structural example of the power supply system according to embodiment of this invention. It is a circuit diagram explaining the DC power conversion with respect to the 1st DC power supply in the single mode by a 1st DC power supply. It is a wave form diagram for demonstrating the example of control operation of the single mode by a 1st DC power supply. It is a graph for demonstrating the setting of the control signal in the single mode by a 1st DC power supply. It is a circuit diagram explaining the DC power conversion with respect to the 2nd DC power supply in the single mode by a 2nd DC power supply. It is a wave form diagram for demonstrating the example of control operation of the single mode by a 2nd DC power supply. It is a graph for demonstrating the setting of the control signal in the single mode by a 2nd DC power supply. It is a wave form diagram which shows the example of control operation of the single mode by a 1st DC power supply. It is a wave form diagram of the switching element in the control operation example shown in FIG. It is a circuit diagram explaining the circuit operation | movement in the turn-off period of a switching element. It is a wave form diagram when a switching element is turned off. It is a wave form diagram for explaining an example of control operation in the 1st mode. It is a wave form chart for explaining an example of control operation in the 2nd mode. 6 is a chart summarizing the relationship between control operations and switching losses in first and second modes. It is a wave form chart for explaining an example of control operation in the 3rd mode. It is a wave form chart for explaining an example of control operation in the 4th mode. 6 is a chart summarizing the relationship between control operations and switching losses in third and fourth modes.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, a plurality of embodiments will be described. However, it is planned from the beginning of the application to appropriately combine the configurations described in the embodiments. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

(Circuit configuration)
FIG. 1 is a circuit diagram showing a configuration example of a power supply system according to an embodiment of the present invention. The power supply system 5 according to the first embodiment has the same circuit configuration as that of the power supply system disclosed in Patent Document 1.

  Referring to FIG. 1, power supply system 5 includes a DC power supply B <b> 1, a DC power supply B <b> 2, a load 30, a control device 40, and a power converter 50.

  In the present embodiment, DC power supplies B1 and B2 are constituted by power storage devices such as secondary batteries and electric double layer capacitors. For example, DC power supply B1 is comprised with secondary batteries, such as a lithium ion secondary battery and a nickel metal hydride battery. The DC power source B2 is constituted by a DC voltage source element having excellent output characteristics such as an electric double layer capacitor and a lithium ion capacitor. The DC power supply B1 and the DC power supply B2 correspond to “first DC power supply” and “second DC power supply”, respectively.

  Note that the DC power supplies B1 and B2 can be configured by the same type of power storage device. Further, the capacities of the DC power supplies B1 and B2 are not particularly limited, and each of the DC power supplies B1 and B2 may be configured with an equivalent capacity, and the capacity of one DC power supply may be the same as that of the other DC power supply. It may be larger than the capacity.

  The power converter 50 is configured to control a DC voltage VH (hereinafter also referred to as an output voltage VH) between the high voltage side power line PL and the low voltage side power line GL. The power line GL is typically constituted by a ground wiring.

  The load 30 operates in response to the output voltage VH of the power converter 50. Voltage command value VH * of output voltage VH is set to a voltage suitable for the operation of load 30. Voltage command value VH * may be variably set according to the state of load 30. Furthermore, the load 30 may be configured to be able to generate charging power for the DC power sources B1 and / or B2 by regenerative power generation or the like.

  Power converter 50 includes power semiconductor switching elements S1 to S4 and reactors L1 and L2. In the present embodiment, an IGBT (Insulated Gate Bipolar Transistor), a power MOS (Metal Oxide Semiconductor) transistor, a power bipolar transistor, or the like is used as a power semiconductor switching element (hereinafter also simply referred to as “switching element”). be able to. Anti-parallel diodes D1 to D4 are arranged for switching elements S1 to S4. The switching elements S1 to S4 can be turned on and off in response to control signals SG1 to SG4 from the control device 40.

  Switching element S1 is electrically connected between power line PL and node N1. Reactor L2 and DC power supply B2 are electrically connected in series between nodes N1 and N3. For example, reactor L2 is electrically connected between node N1 and the positive terminal of DC power supply B2, and the negative terminal of DC power supply B2 is electrically connected to node N3. Even if the connection order of the reactor L2 and the DC power supply B2 is changed, an electrically equivalent circuit configuration is formed.

  Switching element S2 is electrically connected between nodes N1 and N2. Reactor L1 and DC power supply B1 are electrically connected in series between node N2 and power line GL. For example, reactor L1 is electrically connected between the positive terminal of DC power supply B1 and node N1, and the negative terminal of DC power supply B1 is electrically connected to power line GL. Even if the connection order of the reactor L1 and the DC power supply B1 is changed, an electrically equivalent circuit configuration is formed.

  Switching element S3 is electrically connected between nodes N2 and N3. Switching element S4 is electrically connected between node N3 and power line GL. Power line GL is electrically connected to load 30 and the negative terminal of DC power supply B1.

  In the configuration example of FIG. 1, the switching element S1 corresponds to a “first switching element”, the switching element S2 corresponds to a “second switching element”, and the switching element S3 corresponds to a “third switching element”. The switching element S4 corresponds to a “fourth switching element”. Reactor L1 corresponds to “first reactor”, and reactor L2 corresponds to “second reactor”.

  As can be understood from FIG. 1, the power converter 50 has a boost chopper circuit corresponding to each of the DC power supply B1 and the DC power supply B2. That is, for DC power supply B1, a current bidirectional first step-up chopper circuit is configured with switching elements S1 and S2 as upper arms and switching elements S3 and S4 as lower arms. Similarly, for the DC power source B2, a current bidirectional second step-up chopper circuit is configured with the switching elements S1 and S4 as upper arms and the switching elements S2 and S3 as lower arms.

  Then, a current path formed between the DC power supply B1 and the power lines PL and GL by the first boost chopper circuit and a DC path between the DC power supply B2 and the power lines PL and GL are formed by the second boost chopper circuit. Switching elements S1 to S4 are included in both of the current paths.

  The control device 40 is configured by, for example, an electronic control unit (ECU) having a CPU (Central Processing Unit) and a memory (not shown). The control device 40 is configured to perform arithmetic processing using the detection values of each sensor based on the map and program stored in the memory. Alternatively, at least a part of the control device 40 may be configured to execute predetermined numerical / logical operation processing by hardware such as an electronic circuit.

  The control device 40 generates control signals SG1 to SG4 for controlling on / off of the switching elements S1 to S4 in order to control the output voltage VH.

  Although not shown in FIG. 1, the voltage (denoted as V [1]) and current (denoted as I [1]) of the DC power supply B1, and the voltage (V [2] of the DC power supply B2). And a detector (voltage sensor, current sensor) for output voltage VH and current (denoted as I [2]) and output voltage VH. The outputs of these detectors are provided to the controller 40.

(Power converter operation mode)
Similar to the power converters described in Patent Documents 1 and 2, the power converter 50 is different in the mode of DC power conversion (DC / DC conversion) between the DC power supplies B1 and B2 and the power lines PL and GL. It has a plurality of operation modes. These operation modes are selectively applied by switching the on / off control mode of the switching elements S1 to S4.

  The plurality of operation modes of power converter 50 include a “parallel boost mode” in which DC / DC conversion is performed in parallel between DC power supplies B1 and B1 and power lines PL and GL, and DC power supplies B1 and B1 connected in series. A “series boost mode” in which DC / DC conversion is performed between B2 and power lines PL and GL is included. The parallel boost mode corresponds to the “parallel connection mode” in Patent Document 1, and the series boost mode corresponds to the “series connection mode” in Patent Document 1.

  The plurality of operation modes of the power converter 50 further include “single mode using the DC power supply B1” that performs DC / DC conversion between the power lines PL and GL using only the DC power supply B1 and only the DC power supply B2. "Single mode by DC power supply B2" that performs DC / DC conversion between power lines PL and GL is included. In the single mode using the DC power supply B1, the DC power supply B2 maintains the state disconnected from the power line PL as long as the output voltage VH is controlled to be higher than the voltage V [2] of the DC power supply B2. Is done. Similarly, in the single mode by the DC power supply B2, the DC power supply B1 is kept disconnected from the power line PL as long as the output voltage VH is controlled to be higher than the voltage V [1] of the DC power supply B1. Not used.

  In the present embodiment, control operations in the single mode by DC power supply B1 and the single mode by DC power supply B2 will be described.

(Circuit operation in single mode with DC power supply B1)
Next, the boosting operation in the single mode by the DC power supply B1 will be described with reference to FIGS.

  FIG. 2 shows DC / DC conversion (step-up operation) for the DC power supply B1 in the single mode by the DC power supply B1.

  Referring to FIG. 2A, a current path 120 for storing energy in reactor L1 is formed by turning on a pair of switching elements S3 and S4 and turning off a pair of switching elements S1 and S2. . As a result, a state in which the lower arm of the boost chopper circuit is turned on is formed.

  On the other hand, referring to FIG. 2 (b), the pair of switching elements S3 and S4 is turned off, and the pair of switching elements S1 and S2 is turned on, whereby the stored energy of reactor L1 is supplied to DC power supply B1. A current path 121 for outputting with energy is formed. Thereby, a state is formed in which the upper arm of the boost chopper circuit is turned on.

  While the pair of switching elements S3 and S4 is turned on, the first period in which at least one of the switching elements S1 and S2 is turned off and the pair of switching elements S1 and S2 are turned on, while the switching element S3 , S4 are alternately turned off and the second period in which the current path 120 in FIG. 2 (a) and the current path 121 in FIG. 2 (b) are alternately formed. As a result, a boost chopper circuit having a pair of switching elements S1 and S2 equivalently as an upper arm and a pair of switching elements S3 and S4 equivalently as a lower arm is configured for the DC power supply B1.

  In such DC / DC conversion, the relationship expressed by the following equation (1) is established between the voltage V [1] of the DC power supply B1 and the output voltage VH of the power line PL. In the expression (1), the duty ratio during a period when the pair of switching elements S3 and S4 is turned on is Da.

VH = 1 / (1-Da) · V [1] (1)
In the single mode by the DC power supply B1, the switching elements S1 to S4 are controlled according to the control pulse signal SDa based on the duty ratio Da for controlling the output of the DC power supply B1.

  FIG. 3 shows a waveform diagram for explaining an example of the control operation in the single mode by the DC power supply B1. Referring to FIG. 3, control pulse signal SDa is generated by pulse width modulation (PWM) control based on a comparison between duty ratio Da and periodic carrier wave 25. Generally, a triangular wave or a sawtooth wave is used for the carrier wave 25. The period of the carrier wave 25 corresponds to the switching frequency of each switching element, and the amplitude of the carrier wave 25 is set to a voltage corresponding to Da = 1.0.

  When the voltage indicating the duty ratio Da is higher than the voltage of the carrier wave 25, the control pulse signal SDa is set to a logic high level (hereinafter referred to as H level) while being lower than the voltage of the carrier wave 25. It is set to a logic low level (hereinafter referred to as L level). The ratio of the H level period to the cycle (H level period + L level period) of the control pulse signal SDa, that is, the duty ratio of the control pulse signal SDa is equal to Da.

  Control pulse signal / SDa is an inverted signal of control pulse signal SDa. As the duty ratio Da increases, the H level period of the control pulse signal SDa increases. On the other hand, when the duty ratio Da decreases, the L level period of the control pulse signal SDa increases.

  Control pulse signal SDa corresponds to a signal for controlling on / off of the lower arms (switching elements S3, S4) of the boost chopper circuit shown in FIG. On the other hand, control pulse signal / SDa corresponds to a signal for controlling on / off of the upper arms (switching elements S1, S2) of the boost chopper circuit shown in FIG.

  FIG. 4 is a chart for explaining the setting of control signals in the single mode by the DC power supply B1. As shown in FIG. 4, control signals SG1 to SG4 are set based on control pulse signal SDa (/ SDa).

  Switching elements S1 and S2 form the upper arm of the boost chopper circuit of FIG. Therefore, control signal SG1 for controlling on / off of switching element S1 and control signal SG2 for controlling on / off of switching element S2 are generated based on control pulse signal / SDa.

  Switching elements S3 and S4 form the lower arm of the boost chopper circuit of FIG. Therefore, control signal SG3 for controlling on / off of switching element S3 and control signal SG4 for controlling on / off of switching element S4 are generated based on control pulse signal SDa.

  As described above, in the single mode using the DC power supply B1, the switching elements S3 and S4 are turned on / off in response to the control signals SG3 and SG4, thereby forming the current path 120 (FIG. 2A). A state and an off state that interrupts the current path 120 are selectively formed. On the other hand, the switching elements S1 and S2 are turned on / off in response to the control signals SG1 and SG2 to thereby turn on the current path 121 (FIG. 2B) and turn off the current path 121. And selectively forming.

  The current path 120 in FIG. 2A corresponds to the “first current path”, and the current path 121 in FIG. 2B corresponds to the “second current path”. The switching elements S3 and S4 correspond to “first switching element” and “second switching element” configured to form and block the first current path (current path 120), respectively. As shown in FIG. 3, by generating control signals SG1 to SG4 so that the pair of switching elements S3 and S4 and the pair of switching elements S1 and S2 are turned on and off in a complementary manner, current path 120 (first 1 current path) and current path 121 (second current path) are alternately formed.

(Circuit operation in single mode with DC power supply B2)
FIG. 5 shows DC / DC conversion (step-up operation) for the DC power supply B2 in the single mode by the DC power supply B2.

  Referring to FIG. 5A, by turning on the pair of switching elements S2 and S3 and turning off the pair of switching elements S1 and S4, a current path 130 for storing energy in reactor L2 is formed. . As a result, a state in which the lower arm of the boost chopper circuit is turned on is formed.

  On the other hand, referring to FIG. 5 (b), by turning off the pair of switching elements S2 and S3 and turning on the pair of switching elements S1 and S4, the stored energy of reactor L2 is supplied to DC power supply B2. A current path 131 is formed for output with energy. Thereby, a state is formed in which the upper arm of the boost chopper circuit is turned on.

  While the pair of switching elements S2 and S3 is turned on, the first period when at least one of the switching elements S1 and S4 is turned off, and the pair of switching elements S1 and S4 is turned on, while the switching element S2 , S3 and the second period in which at least one of them is off are alternately repeated, whereby the current path 130 in FIG. 5A and the current path 131 in FIG. 5B are alternately formed. As a result, a step-up chopper circuit having a pair of switching elements S1 and S4 equivalently as an upper arm and a pair of switching elements S2 and S3 equivalently as a lower arm is configured for the DC power supply B2.

  In such DC / DC conversion, the relationship expressed by the following equation (2) is established between the voltage V [2] of the DC power supply B2 and the output voltage VH of the power line PL. In the equation (2), Db is a duty ratio during a period in which the pair of switching elements S2 and S3 is turned on.

VH = 1 / (1-Db) · V [2] (2)
In the single mode using DC power supply B2, switching elements S1 to S4 are controlled in accordance with control pulse signal SDb based on duty ratio Db for controlling the output of DC power supply B2.

  FIG. 6 shows a waveform diagram for explaining an example of the control operation in the single mode by the DC power supply B2. Referring to FIG. 6, control pulse signal SDb is generated by PWM control based on a comparison between duty ratio Db and periodic carrier wave 25, similarly to control pulse signal SDa (FIG. 3). The period of the carrier wave 25 corresponds to the switching frequency of each switching element, and the amplitude of the carrier wave 25 is set to a voltage corresponding to Db = 1.0.

  Control pulse signal SDb is set to H level when the voltage indicating duty ratio Db is higher than the voltage of carrier wave 25, and is set to L level when the voltage is lower than the voltage of carrier wave 25. The ratio of the H level period to the cycle (H level period + L level period) of the control pulse signal SDb, that is, the duty ratio of the control pulse signal SDb is equal to Db.

  Control pulse signal / SDb is an inverted signal of control pulse signal SDb. As the duty ratio Db increases, the H level period of the control pulse signal SDb increases. On the contrary, when the duty ratio Db decreases, the L level period of the control pulse signal SDb increases.

  Control pulse signal SDb corresponds to a signal for controlling on / off of the lower arms (switching elements S2, S3) of the boost chopper circuit shown in FIG. On the other hand, control pulse signal / SDb corresponds to a signal for controlling on / off of the upper arms (switching elements S1, S4) of the boost chopper circuit shown in FIG.

  FIG. 7 is a table for explaining setting of control signals in the single mode by the DC power supply B2. As shown in FIG. 7, control signals SG1 to SG4 are set based on control pulse signal SDb (/ SDb).

  Switching elements S1 and S4 form the upper arm of the boost chopper circuit of FIG. Therefore, control signal SG1 for controlling on / off of switching element S1 and control signal SG4 for controlling on / off of switching element S4 are generated based on control pulse signal / SDb.

  Switching elements S2 and S3 form the lower arm of the boost chopper circuit of FIG. Therefore, control signal SG2 for controlling on / off of switching element S2 and control signal SG3 for controlling on / off of switching element S3 are generated based on control pulse signal SDb.

  As described above, in the single mode using the DC power supply B2, the switching elements S2 and S3 are turned on and off in response to the control signals SG2 and SG3, respectively, thereby forming the current path 130 (FIG. 5A). A state and an off state that interrupts the current path 130 are selectively formed. On the other hand, the switching elements S1 and S4 are turned on and off in response to the control signals SG1 and SG4, thereby turning on the current path 131 (FIG. 5B) and turning off the current path 131. And selectively forming.

  5A corresponds to the “first current path (or third current path)”, and the current path 131 in FIG. 5B corresponds to the “second current path (or first current path). 4 current path) ”. The switching elements S2 and S3 correspond to “first switching element” and “second switching element” configured to form and block the first current path (current path 130), respectively. As shown in FIG. 6, by generating control signals SG1 to SG4 so as to complementarily turn on and off the pair of switching elements S2 and S3 and the pair of switching elements S1 and S4, current path 130 (first 1 current path) and current path 131 (second current path) are alternately formed.

(Basic control operation in single mode with DC power supply B1)
As described above, when power converter 50 according to the present embodiment is operated in a single mode by DC power supply B1 or a single mode by DC power supply B2, two switching elements that are electrically connected in series are connected. DC / DC conversion is performed between the DC power source and the power lines PL and GL with the pair equivalently as the upper arm or the lower arm of the boost chopper circuit.

FIG. 8 is a waveform diagram showing an example of a single mode control operation by the DC power supply B1.
Referring to FIG. 8, control signals SG1 to SG4 are set based on control pulse signal SDa (/ SDa) in accordance with the chart shown in FIG. By turning on and off switching elements S1 to S4 based on control signals SG1 to SG4, reactor current IL1 flowing through reactor L1 and reactor current IL2 flowing through reactor L2 are controlled as shown in FIG. Reactor current IL1 corresponds to current I [1] of DC power supply B1, and reactor current IL2 corresponds to current I [2] of DC power supply B2.

  In FIG. 8, switching elements S3 and S4 constituting the lower arm of the step-up chopper circuit are commonly turned on / off in accordance with control signals SG3 and SG4 generated based on control pulse signal SDa. Similarly, switching elements S1 and S2 constituting the upper arm of the step-up chopper circuit are commonly on / off controlled in accordance with control signals SG1 and SG2 generated based on control pulse signal / SDa. That is, since control signals SG1 and SG2 and control signals SG3 and SG4 are set at complementary levels, switching elements S1 and S2 (upper arm) and switching elements S3 and S4 (lower arm) are complementary. On and off.

  In such a boost chopper circuit control, normally, when switching on / off between the upper and lower arms so as not to cause a short-circuit path between the power lines PL and GL, both are turned off, so-called dead time. A period is provided.

  As shown in FIG. 8, the dead time Td is such that the control signals SG1 and SG2, the control signals SG3 and SG4, and the pair of switching elements S1 and S2 and the pair of switching elements S3 and S4 are not turned on at the same time. Both are provided to be set to the L level. Therefore, in the dead time period, both switching elements S1 and S3 and switching elements S3 and S4 (that is, switching elements S1 to S4) are turned off. That is, the dead time Td corresponds to a period for simultaneously blocking the current paths 120 and 121 when the current path 120 (FIG. 2A) and the current path 121 (FIG. 2B) are switched.

  Hereinafter, as a representative example of the control operation in the single mode by the DC power supply B1, control when the DC power supply B1 is in the power running state will be described.

  Until time T1 in FIG. 8, switching elements S3 and S4 are turned off, so that the lower arm of the step-up chopper circuit is turned off. For this reason, reactor current IL1 falls.

  At time T1, switching elements S1 and S2 are turned off, so that the upper arm is turned off. At this time, since the switching elements S3 and S4 are turned off, the lower arm of the step-up chopper circuit is turned off. For this reason, reactor current IL1 continues to fall.

  At the time T2 when the dead time Td has elapsed from the time T1, the switching elements S3 and S4 are turned on so that the upper arm is turned on, so that the reactor current IL1 starts to rise.

  When switching elements S3 and S4 are turned off at time T3, the lower arm is turned off, and reactor current IL1 starts to fall again. As a result, the state before time T1 described above is reproduced.

  Note that during execution of the single mode by the DC power supply B1, the current path to the DC power supply B2 is not formed, so that the reactor current IL2 = 0 is maintained.

  FIG. 9 shows a waveform diagram of the switching element when the switching elements S3 and S4 are controlled to be turned on and off in common.

  Referring to FIG. 9, when control signals SG3 and SG4 rise from the L level to the H level, turn-on operations of switching elements S3 and S4 are started. By forming the current path 120 (FIG. 2A), the current I (S3) of the switching element S3 and the current I (S4) of the switching element S4 start to rise, and the voltage V (S3 of the switching element S3) ) And the voltage V (S4) of the switching element S4 starts to fall.

  Next, when the control signals SG3 and SG4 fall from the H level to the L level, the turn-off operation of the switching elements S3 and S4 is started. When current path 120 is interrupted, currents I (S3) and I (S4) begin to decrease, and voltages V (S3) and V (S4) begin to increase. Since switching elements S3 and S4 are connected in series to current path 120, currents I (S3) and I (S4) have the same waveform.

  During an actual switching operation, the current and voltage of the switching element change according to a constant rate corresponding to the changing speed of the gate potential of the switching element. The constant rate corresponds to the switching speed of the switching element, and is also referred to as “switching speed”.

  As shown in FIG. 9, in the period from the start of the turn-on operation until the switching element is completely turned on (hereinafter also referred to as a turn-on period ton), the power corresponding to the product of the voltage and current of the switching element Loss occurs. Similarly, in a period from when the turn-off operation is started until the switching element is completely turned off (hereinafter also referred to as a turn-off period toff), power loss corresponding to the product of the voltage and current of the switching element occurs. The power loss during the switching operation is also referred to as “switching loss”. The switching loss includes a “turn-on loss” that is a switching loss during a turn-on operation and a “turn-off loss” that is a switching loss during a turn-off operation. The turn-on loss and the turn-off loss depend on the switching speed of the switching element.

  As understood from FIG. 9, when switching elements S3 and S4 are turned on / off in common, when the switching speed of switching element S3 is equal to the switching speed of switching element S4, turn-on period ton and turn-off period toff At each time point, the voltage V (S3) and the voltage V (S4) have the same magnitude. In other words, the voltage applied to the lower arm of the boost chopper circuit during the turn-on period ton and the turn-off period toff is equally shared by the switching element S3 and the switching element S4.

  FIG. 10 shows the circuit operation during the turn-off period of the switching elements S3 and S4. Referring to FIG. 10, when the turn-off operation of switching elements S3 and S4 is started from the state where the lower arm of the boost chopper circuit is turned on with respect to DC power supply B1, that is, the switching elements S3 and S4 are turned on. The current path in the power converter 50 changes from the state of FIG. 10 (a) to the state of FIG. 10 (b). When the switching elements S3 and S4 are completely turned off, the current path finally becomes the state shown in FIG. 10B, so that the switching elements S3 and S4 constituting the lower arm have a total voltage equal to the output voltage VH. Will be applied.

  Here, as described above, when the switching speeds of the switching elements S3 and S4 are equal, the voltage applied to the lower arm of the step-up chopper circuit in the turn-off period toff is equal to 1/2 in the switching elements S3 and S4. Will be shared. Therefore, the turn-off loss generated in the switching element S3 is equal to the turn-off loss generated in the switching element S4. That is, the turn-off loss generated in the lower arm of the step-up chopper circuit is equally shared by the switching element S3 and the switching element S4 by 1/2.

  Thus, if the switching speeds of the switching elements S3 and S4 constituting the lower arm of the step-up chopper circuit are equal, compared with the conventional power converter in which the lower arm is constituted by a single switching element, Turn-off loss can be halved. As a result, since heat generation per element can be suppressed, the output of the power converter 50 can be improved.

  However, when the switching speed of the switching element S3 and the switching speed of the switching element S4 are different, the output between the switching element S3 and the switching element S4 depends on the magnitude of the switching speed between the two as described below. The ratio of sharing the voltage VH is different.

  FIG. 11 shows a waveform diagram when switching elements S3 and S4 are turned off when the switching speed of switching element S3 is faster than the switching speed of switching element S4.

  Referring to FIG. 11, when control signals SG3 and SG4 fall from the H level to the L level, turn-off operation of switching elements S3 and S4 is started. In the operation example of FIG. 11, since the switching element S3 has a higher switching speed than the switching element S4, the switching element S3 is completely turned off at an earlier timing than the switching element S4.

  When the switching element S3 is turned off, the current path in FIG. 10A is interrupted, so that the state changes to the state in FIG. 10B, and the output voltage VH is applied to the lower arm of the boost chopper circuit. Is done. At this time, since the switching element S4 is not completely turned off, the switching element S3 takes over most of the output voltage VH. For example, as shown in FIG. 11, when the switching element S4 has not yet started the turn-off operation at the timing when the current path is cut off, the switching element S3 takes charge of all of the output voltage VH.

  As described above, when the switching elements S3 and S4 are turned off, the switching element having the higher switching speed of the switching elements S3 and S4 shares the output voltage VH as compared with the switching element having the lower switching speed. Becomes larger. Therefore, it is understood that the switching element with the higher switching speed has a larger turn-off loss than the switching element with the lower switching speed.

  Furthermore, even when the switching elements S3 and S4 are turned on, it is understood that the ratio of sharing the output voltage VH varies depending on the magnitude of the switching speed of both as in FIG.

  That is, when the switching speed of the switching element S3 is higher than the switching speed of the switching element S4, the switching elements S3, S4 are started after the turn-on operation of the switching elements S3, S4 is started according to the rise of the control signals SG3, SG4. It is completely turned on at an earlier timing than the switching element S4. At this time, since the switching element S4 is not completely turned on, the current path is in the state shown in FIG. 10B, and the output voltage VH is applied to the lower arm of the boost chopper circuit. The switching element S4 takes charge of all or most of the output voltage VH.

  As described above, when the switching elements S3 and S4 are turned on, the switching element having the slower switching speed among the switching elements S3 and S4 shares the output voltage VH as compared with the switching element having the higher switching speed. Becomes larger. Therefore, it is understood that the switching element with the slower switching speed has a larger turn-on loss than the switching element with the higher switching speed.

  On the other hand, when the DC power supply B1 is in the regenerative state, the switching loss of the switching elements S1 and S2 is biased due to the switching speed of the switching elements S1 and S2 constituting the upper arm of the boost chopper circuit. .

  Specifically, when the switching elements S1 and S2 are turned on, the switching element having the slower switching speed among the switching elements S1 and S2 shares the output voltage VH as compared with the switching element having the higher switching speed. The proportion increases. Therefore, a switching element with a slower switching speed has a larger turn-on loss than a switching element with a faster switching speed.

  In addition, when switching elements S1 and S2 are turned off, the switching element with the higher switching speed among switching elements S1 and S2 has a higher ratio of sharing the output voltage VH than the switching element with the lower switching speed. Become. Therefore, the switching element with the higher switching speed has a larger turn-off loss than the switching element with the lower switching speed.

  As described above, in the single mode using the DC power supply B1, when the DC power supply B1 is in the power running state, if the switching speeds of the switching elements S3 and S4 constituting the lower arm of the boost chopper circuit are equal to each other, Since S4 equally shares the switching loss, the switching loss per element can be suppressed. Further, when the DC power supply B1 is in the regenerative state, the switching elements S1 and S2 share the switching loss evenly if the switching speeds of the switching elements S1 and S2 constituting the upper arm of the boost chopper circuit are equal to each other. In addition, switching loss per element can be suppressed.

  However, as described above, if the switching speed is different between the switching elements S3 and S4 constituting the lower arm, the switching loss of the switching elements S3 and S4 is biased in the power running state of the DC power supply B1. Similarly, if the switching speed is different between the switching elements S1 and S2 constituting the upper arm, the switching loss of the switching elements S1 and S2 is biased in the regenerative state of the DC power supply B1.

  As described above, when a switching loss is biased in a pair of two switching elements that are electrically connected in series and are commonly controlled to be turned on / off, heat is likely to be concentrated in one switching element of the pair. . As a result, since the heat generation in the pair of switching elements is biased, it is difficult to improve the output of the power converter 50. In particular, when one switching element shares all of the output voltage VH at turn-on or turn-off, the switching element has a switching loss of the same level as when each of the upper and lower arms is configured by a single switching element. May occur.

  Note that the magnitude of the switching speed fluctuates due to manufacturing variations of the switching elements, and therefore, which switching element the switching loss is biased to depends on the situation. Therefore, the heat resistance design of each of the two switching elements constituting the pair must be guaranteed to the same extent as the heat resistance design of the switching element when the lower arm is configured by a single switching element.

  Here, if the switching speed can be made uniform between two paired switching elements, it is possible to suppress the bias of the heat generation of the switching elements described above. However, in practice, it is not always easy to achieve the same switching speed between the two switching elements in consideration of the manufacturing cost.

  Therefore, in power converter 50 according to the present embodiment, switching elements that generate switching loss are intentionally controlled when two pairs of switching elements are turned on or turned off. Using this control, switching loss (that is, heat generation) is distributed and generated between two paired switching elements.

(Control operation for switching loss dispersion in single mode by DC power supply B1)
Hereinafter, as a representative example, a control operation for switching loss dispersion in the single mode by the DC power supply B1 will be described.

  In power supply system 5 according to the present embodiment, control device 40 has a time difference in turn-on or turn-off timing between one switching element of the pair of two switching elements and the other switching element. Controls on / off of two switching elements. By intentionally shifting the turn-on or turn-off timing between the two switching elements, the switching element that generates the switching loss can be controlled. This makes it possible to intentionally generate the switching loss bias as described above in the pair of two switching elements.

  Specifically, in the single mode using DC power supply B1, control device 40 provides a time difference between the turn-on timing and the turn-off timing for the pair of switching elements S1 and S2 constituting the upper arm of the boost chopper circuit. Further, a time difference is provided between the turn-on timing and the turn-off timing for the pair of switching elements S3 and S4 constituting the lower arm.

  Furthermore, the control device 40 includes two control modes (first mode and second mode) in which switching elements that generate switching loss are different, and executes these two control modes in a time-sharing manner. As a result, switching losses are distributed between the two switching elements.

  Hereinafter, specific control operations in the two control modes included in the control device 40 will be described. Furthermore, time-division control for switching and executing these two control modes will be described.

(Control operation in the first mode)
FIG. 12 is a waveform diagram for explaining an example of the control operation in the first mode.

  Referring to FIG. 12, in the first mode, the turn-on timing of switching element S2 is earlier than the turn-on timing of switching element S1, and the turn-off timing of switching element S1 is greater than the turn-off timing of switching element S2. Control signals SG1 and SG2 are generated so as to be delayed.

  Specifically, control device 40 provides a time difference corresponding to dead time Td at each of the rising timings of control signals SG1 and SG2 and the falling timings of control signals SG1 and SG2. As shown in FIG. 12, the control device 40 removes the dead time Td provided at the rising timing of the control signal SG2, thereby setting the rising timing of the control signal SG2 to be higher than the rising timing of the control signal SG1. Make it faster by Td. The control device 40 also adds the dead time Td to the falling timing of the control signal SG1, thereby delaying the falling timing of the control signal SG1 by the dead time Td from the falling timing of the control signal SG2.

  Thereby, the turn-on timing of the switching element S2 is earlier than the turn-on timing of the switching element S1 by the dead time Td, and the turn-off timing of the switching element S1 is later than the turn-off timing of the switching element S2.

  Further, the control device 40 has a switching element S3 having a turn-on timing earlier than that of the switching element S4 with respect to the pair of switching elements S3 and S4 constituting the lower arm of the boost chopper circuit. Control signals SG3 and SG4 are generated so that the turn-off timing of S4 is later than the turn-off timing of switching element S3.

  Specifically, control device 40 provides a time difference corresponding to dead time Td at each of the rising timings of control signals SG3 and SG4 and the falling timings of control signals SG3 and SG4. As shown in FIG. 12, the control device 40 removes the dead time Td provided at the rising timing of the control signal SG3, thereby setting the rising timing of the control signal SG3 to be more dead time than the rising timing of the control signal SG4. Make it faster by Td. The control device 40 also adds the dead time Td to the falling timing of the control signal SG4, thereby delaying the falling timing of the control signal SG4 by the dead time Td from the falling timing of the control signal SG3.

  Accordingly, the turn-on timing of the switching element S3 is earlier than the turn-on timing of the switching element S4 by the dead time Td, and the turn-off timing of the switching element S4 is later than the turn-off timing of the switching element S3 by the dead time Td.

  As described above, even when the turn-on timing and the turn-off timing are shifted between the switching elements S1 and S2, the period during which both the switching elements S1 and S2 are in the on state, that is, the current path 121 (FIG. 2) is formed. This period guarantees an H level period of the control pulse signal / SDa based on the duty ratio Da. Similarly, even if the turn-on timing and the turn-off timing are shifted between the switching elements S3 and S4, the period during which both the switching elements S3 and S4 are in the on state, that is, the period during which the current path 120 (FIG. 2) is formed is The H level period of the control pulse signal SDa based on the duty ratio Da is guaranteed. Therefore, as shown in FIG. 12, the waveform of reactor current IL1 is the same as the waveform of reactor current IL in FIG.

  On the other hand, in reactor current IL2, a minute fluctuation from IL2 = 0 appears in a period corresponding to dead time Td. Specifically, during the period from time T1 to T2, reactor current IL2 fluctuates slightly to the positive side. This is because the current path is temporarily formed between the DC power supply B2 and the power lines PL and GL by turning on the switching element S1 during the dead time period. Further, in the period from time T3 to T4, reactor current IL2 fluctuates slightly to the negative side. This is because the current path is temporarily formed between the DC power supply B2 and the power lines PL and GL by turning on the switching element S2 during the dead time period.

  The time difference between the turn-on timing and the turn-off timing between the two switching elements is preferably set so as not to exceed the dead time Td. This is because when the time difference exceeds the dead time Td, the current paths 130 and 131 (FIGS. 5A and 5B) to the DC power source B2 may be formed during the excess time. .

  Thus, in the first mode, in each of the pair of switching elements S1 and S2 and the pair of switching elements S3 and S4, the turn-on and turn-off timings are shifted between the two switching elements as described above. A phenomenon that is substantially the same as when the switching speed between two paired switching elements is different may occur. That is, in the first mode, the above-described switching loss bias can be intentionally generated.

  Specifically, when the DC power supply B1 is in a power running state, it is possible to control a switching element that generates a switching loss for the pair of switching elements S3 and S4 that constitute the lower arm of the boost chopper circuit. When the switching elements S3 and S4 are turned on, the switching element S4 having the later turn-on timing among the switching elements S3 and S4 is responsible for all of the output voltage VH. Therefore, turn-on loss occurs in the switching element S4. Further, when the switching elements S3 and S4 are turned off, the switching element S3 having the earlier turn-off timing among the switching elements S3 and S4 is responsible for all of the output voltage VH. Therefore, a turn-off loss occurs in the switching element S3.

  On the other hand, when the DC power supply B1 is in the regenerative state, it is possible to control a switching element that generates a switching loss for the pair of switching elements S1 and S2 constituting the upper arm of the boost chopper circuit. When the switching elements S1 and S2 are turned on, the switching element S1 with the later turn-on timing of the switching elements S1 and S2 is responsible for all of the output voltage VH. Therefore, a turn-on loss occurs in the switching element S1. Further, when the switching elements S1 and S2 are turned off, the switching element S2 having the earlier turn-off timing among the switching elements S1 and S2 is responsible for all of the output voltage VH. Therefore, a turn-off loss occurs in the switching element S2.

(Control operation in the second mode)
FIG. 13 is a waveform diagram for explaining an example of the control operation in the second mode.

  Referring to FIG. 13, in the second mode, control device 40 determines the turn-on timing of switching element S <b> 1 for switching element S <b> 1 for the pair of switching elements S <b> 1 and S <b> 2 constituting the upper arm of the boost chopper circuit. The control signals SG1 and SG2 are generated so that the turn-on timing is earlier and the turn-off timing of the switching element S2 is later than the turn-off timing of the switching element S1.

  Specifically, as shown in FIG. 13, the control device 40 removes the dead time Td provided at the rising timing of the control signal SG1, thereby changing the rising timing of the control signal SG1 to the rising edge of the control signal SG2. The dead time is Td earlier than the timing. The control device 40 also adds the dead time Td to the falling timing of the control signal SG2, thereby delaying the falling timing of the control signal SG2 by the dead time Td from the falling timing of the control signal SG1.

  Accordingly, the turn-on timing of the switching element S1 is earlier than the turn-on timing of the switching element S2 by the dead time Td, and the turn-off timing of the switching element S2 is later than the turn-off timing of the switching element S1 by the dead time Td.

  Further, the control device 40 has the switching element S4 turn-on timing earlier than the switching element S3 turn-on timing for the pair of switching elements S3 and S4 constituting the lower arm of the boost chopper circuit. Control signals SG3 and SG4 are generated so that the turn-off timing of S3 is later than the turn-off timing of switching element S4.

  Specifically, as shown in FIG. 13, the control device 40 removes the dead time Td provided at the rising timing of the control signal SG4, thereby changing the rising timing of the control signal SG4 to the rising edge of the control signal SG3. The dead time is Td earlier than the timing. The control device 40 also adds the dead time Td to the falling timing of the control signal SG3, thereby delaying the falling timing of the control signal SG3 by the dead time Td from the falling timing of the control signal SG4.

  Thereby, the turn-on timing of the switching element S4 is earlier than the turn-on timing of the switching element S3 by the dead time Td, and the turn-off timing of the switching element S3 is later than the turn-off timing of the switching element S4 by the dead time Td.

  In the second mode, similarly to the first mode described above, the waveform of reactor current IL1 is the same as the waveform of reactor current IL in FIG. Further, in reactor current IL2, a minute fluctuation from IL2 = 0 appears in a period corresponding to dead time Td.

  As described above, even in the second mode, in each of the pair of switching elements S1 and S2 and the pair of switching elements S3 and S4, the turn-on and turn-off timings are shifted between the two switching elements. Since a phenomenon that is substantially the same as that in the case where the switching speeds between the two switching elements are different can occur, it is possible to intentionally generate a bias in switching loss.

  Here, comparing the waveform diagram of FIG. 12 with the waveform diagram of FIG. 13, the second mode is opposite to the first mode in setting the time difference between the turn-on timing and the turn-off timing. . With such a configuration, it is understood that the switching element in which the switching loss occurs is switched between the two switching elements in the first mode and the second mode.

  Specifically, in the second mode, when the DC power supply B1 is in a powering state, when the switching elements S3 and S4 are turned on, the switching element S3 having the later turn-on timing of the switching elements S3 and S4 loses the turn-on loss. Occurs. Further, when the switching elements S3 and S4 are turned off, a turn-off loss occurs in the switching element S4 having the earlier turn-off timing among the switching elements S3 and S4.

  On the other hand, when the DC power supply B1 is in a regenerative state, a turn-on loss occurs in the switching element S2 with the later turn-on timing of the switching elements S1 and S2 when the switching elements S1 and S2 are turned on. Further, when the switching elements S1 and S2 are turned off, a turn-off loss occurs in the switching element S1 with the earlier turn-off timing of the switching elements S1 and S2.

(Time division control in the first and second modes)
FIG. 14 summarizes the relationship between the control operation and the switching loss in the first and second modes.

  As understood from FIG. 14, when the DC power supply B1 is in the power running state, the switching element and the turn-off loss that generate the turn-on loss between the switching elements S3 and S4 in the first mode and the second mode. Each of the switching elements that generate is replaced.

  On the other hand, when the DC power supply B1 is in the regenerative state, the switching element that generates the turn-on loss and the switching element that generates the turn-off loss are switched between the switching elements S1 and S2 in the first mode and the second mode. ing.

  The control device 40 executes the first mode and the second mode in a time division manner. Thereby, in the pair of two switching elements, the switching elements in which the switching loss occurs are switched in a time division manner.

  As described above, when two pairs of switching elements are controlled to be turned on and off in common, the switching elements that generate switching losses are fixed in accordance with the magnitude of the switching speed. On the other hand, according to the time division control according to the present embodiment, since the switching elements in which the switching loss is generated can be replaced in a time division manner, the bias of the switching loss can be suppressed.

  Here, in the time division control according to the present embodiment, the ratio between the time for executing the first mode and the time for executing the second mode is adjusted between the two switching elements forming a pair. The ratio of sharing the switching loss can be controlled.

  For example, the control device 40 executes the first mode and the second mode in time division so that the time for executing the first mode and the time for executing the second mode are equal to each other. be able to. According to this, control is performed so that the switching loss that occurs in one switching element during execution of the first mode is equal to the switching loss that occurs in the other switching element during execution of the second mode. be able to. Therefore, the above-described ideal operation state in which the switching speeds are equal between the two switching elements can be realized by time division control. That is, the switching loss per element can be halved as compared with a conventional power converter in which each of the upper and lower arms is constituted by a single switching element. As a result, since heat generation per element can be suppressed, the output of the power converter 50 can be improved.

  Alternatively, the control device 40 executes the first mode and the second mode in a time division manner so that the time for executing the first mode and the time for executing the second mode are different. You can also According to this, it is possible to intentionally increase the switching loss of one switching element selected from the two switching elements, while intentionally reducing the switching element of the other switching element. In this way, by adjusting the sharing ratio of the switching loss, different heat resistant designs can be applied between the two switching elements. It should be noted that the same operation and effect can be obtained even in a configuration in which only the first mode is executed without executing the first mode and the second mode in time division, or only the second mode is executed. Can do.

(Control operation for switching loss dispersion in single mode by DC power supply B2)
12 to 14, the control operation in the single mode by the DC power supply B1 has been described. However, the same control for switching loss dispersion can be executed in the control operation in the single mode by the DC power supply B2.

  Specifically, in the single mode with DC power supply B2, control device 40 provides a time difference between the turn-on timing and the turn-off timing for the pair of switching elements S1 and S4 that constitute the upper arm of the boost chopper circuit. Further, a time difference is provided between the turn-on timing and the turn-off timing for the pair of switching elements S2 and S3 constituting the lower arm.

  Furthermore, the control device 40 includes two control modes (third mode and fourth mode) in which switching elements that generate switching losses are different, and executes these two control modes in a time-sharing manner. As a result, switching losses are distributed between the two switching elements.

(Third mode)
FIG. 15 is a waveform diagram for explaining an example of the control operation in the third mode.

  Referring to FIG. 15, in the third mode, the turn-on timing of switching element S1 is earlier than the turn-on timing of switching element S4 for the pair of switching elements S1 and S4 constituting the upper arm of the boost chopper circuit. And the control signals SG1 and SG4 are generated so that the turn-off timing of the switching element S4 is later than the turn-off timing of the switching element S1. Specifically, control device 40 provides a time difference corresponding to dead time Td at each of the rising timings of control signals SG1 and SG4 and the falling timings of control signals SG1 and SG4.

  Further, the control device 40 has a switching element S3 having a turn-on timing earlier than that of the switching element S2 with respect to the pair of switching elements S2 and S3 constituting the lower arm of the boost chopper circuit. Control signals SG2 and SG3 are generated such that the turn-off timing of S2 is later than the turn-off timing of switching element S3. Specifically, control device 40 provides a time difference corresponding to dead time Td at each of the rising timings of control signals SG2 and SG3 and the falling timings of control signals SG2 and SG3.

  In this way, in each of the pair of switching elements S1 and S4 and the pair of switching elements S2 and S3, the two switching elements forming the pair described above are shifted by shifting the turn-on and turn-off timing between the two switching elements. A phenomenon that is substantially the same as when the switching speed between elements is different may occur. Thereby, the bias of switching loss can be generated intentionally.

  Specifically, when the DC power supply B2 is in a power running state, it is possible to control a switching element that generates a switching loss with respect to the pair of switching elements S2 and S3 constituting the lower arm of the boost chopper circuit. When the switching elements S2 and S3 are turned on, a turn-on loss occurs in the switching element S2 with the later turn-on timing of the switching elements S2 and S3. Further, when the switching elements S2 and S3 are turned off, a turn-off loss occurs in the switching element S3 having the earlier turn-off timing of the switching elements S2 and S3.

  On the other hand, when the DC power supply B2 is in the regenerative state, it is possible to control a switching element that generates a switching loss for the pair of switching elements S1 and S4 constituting the upper arm of the boost chopper circuit. When the switching elements S1 and S4 are turned on, a turn-on loss occurs in the switching element S4 with the later turn-on timing of the switching elements S1 and S4. Further, when the switching elements S1 and S4 are turned off, a turn-off loss occurs in the switching element S1 with the earlier turn-off timing of the switching elements S1 and S4.

(Control operation in the fourth mode)
FIG. 16 is a waveform diagram for explaining an example of the control operation in the fourth mode.

  Referring to FIG. 16, in the fourth mode, control device 40 determines the turn-on timing of switching element S4 for switching element S1 for the pair of switching elements S1 and S4 constituting the upper arm of the boost chopper circuit. The control signals SG1 and SG4 are generated so that the turn-on timing is earlier and the turn-off timing of the switching element S1 is later than the turn-off timing of the switching element S4.

  Further, the control device 40 has a switching element S2 having a turn-on timing earlier than that of the switching element S3 with respect to the pair of switching elements S2 and S3 constituting the lower arm of the step-up chopper circuit. Control signals SG2 and SG3 are generated such that the turn-off timing of S3 is later than the turn-off timing of switching element S2.

  Comparing the waveform diagram of FIG. 15 with the waveform diagram of FIG. 16, the fourth mode is opposite to the third mode in setting the time difference between the turn-on timing and the turn-off timing. Therefore, in the third mode and the fourth mode, it is understood that the switching element in which the switching loss occurs is switched between the two switching elements.

  Specifically, in the fourth mode, when the DC power source B2 is in a power running state, when the switching elements S2 and S3 are turned on, the switching element S3 having the later turn-on timing is switched to the turn-on loss. Occurs. Further, when the switching elements S2 and S3 are turned off, a turn-off loss occurs in the switching element S2 with the earlier turn-off timing of the switching elements S2 and S3.

  On the other hand, when the DC power supply B2 is in the regenerative state, a turn-on loss occurs in the switching element S1 with the later turn-on timing of the switching elements S1 and S4 when the switching elements S1 and S4 are turned on. Further, when the switching elements S1 and S4 are turned off, a turn-off loss occurs in the switching element S4 having the earlier turn-off timing among the switching elements S1 and S4.

(Time-division control in the third and fourth modes)
FIG. 17 summarizes the relationship between the control operation and the switching loss in the third and fourth modes.

  As understood from FIG. 17, when the DC power supply B2 is in the power running state, the switching element and the turn-off loss that generate the turn-on loss between the switching elements S2 and S3 in the third mode and the fourth mode. Each of the switching elements that generate is replaced.

  On the other hand, when the DC power supply B2 is in the regenerative state, the switching element that generates the turn-on loss and the switching element that generates the turn-off loss are switched between the switching elements S1 and S4 in the third mode and the fourth mode. ing.

  The control device 40 executes the third mode and the fourth mode in a time division manner. Thereby, in the pair of two switching elements, the switching elements in which the switching loss occurs are switched in a time division manner.

  Here, even in the single mode using the DC power supply B2, two switching operations forming a pair are performed by adjusting the ratio of the time for executing the third mode and the time for executing the fourth mode in the time-sharing control. It is possible to control the proportion of the switching loss between the elements. For example, the control device 40 executes the third mode and the fourth mode in a time-sharing manner so that the time for executing the third mode and the time for executing the fourth mode are equal to each other. be able to. According to this, the switching loss generated in one switching element during execution of the third mode and the switching loss generated in the other switching element during execution of the fourth mode are controlled to be equal in magnitude. Can do. Thereby, compared with the conventional power converter which comprises each of an upper and lower arm with a single switching element, the switching loss per element can be halved.

  Alternatively, the control device 40 executes the third mode and the fourth mode in a time-sharing manner so that the time for executing the third mode and the time for executing the fourth mode have different lengths. You can also According to this, it is possible to intentionally increase the switching loss of one switching element selected from the two switching elements, while intentionally reducing the switching element of the other switching element. In this way, by adjusting the sharing ratio of the switching loss, different heat resistant designs can be applied between the two switching elements. The same effect can be obtained even when the third mode and the fourth mode are not executed in a time-sharing manner, and only the third mode is executed or only the fourth mode is executed. it can.

  In the present embodiment, the configuration of the power converter 50 has been described by illustrating the connection relationship between the switching elements S1 to S4 and the reactors L1 and L2. However, the components of the power converter 50 are included in these elements. It is not meant to be limited. That is, in the present embodiment, the description that the components are “electrically connected” means that there are other circuit elements and connector terminals between the two elements, and the above-described components are connected via the other circuit elements. This includes ensuring electrical connection between the components.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  5 power system, 50 power converter, 30 load, 40 control device, 111-118 current path, 250 carrier wave, B1, B2 DC power supply, L1, L2 reactor, N1, N2 node, S1-S5 power semiconductor switching element , SDa (/ SDa), SDb (/ SDb) control pulse signal, SG1 to SG4 control signal, VH output voltage, VH * voltage command value.

Claims (11)

A power supply system for controlling a DC voltage between a first power line on a high voltage side and a second power line on a low voltage side,
DC power supply,
A power converter for performing direct current power conversion between the direct current power source and the first and second power lines;
A controller for controlling the DC power conversion in the power converter,
The power converter is
Reactor,
In response to a control signal from the control device, a first current path for storing energy in the reactor and the energy of the reactor are discharged between the DC power supply and the first and second power lines. A plurality of switching elements configured to alternately form second current paths for
The plurality of switching elements are electrically connected in series, and are configured to perform the first current path and the second current path by turning on and off in common according to the control signal. Switching elements
The said control apparatus is a power supply system which produces | generates the said control signal so that a time difference may be provided in the turn-on timing or turn-on timing of the said 1st and said 2nd switching element. The controller is
The turn-on timing of the first switching element is earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element is later than the turn-off timing of the first switching element. A first mode for generating the control signal,
The turn-on timing of the second switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element is later than the turn-off timing of the second switching element. A second mode for generating the control signal,
The power supply system according to claim 1, wherein the first mode and the second mode are executed in a time division manner.   The control device time-divides the first mode and the second mode so that the time for executing the first mode and the time for executing the second mode are equal to each other. The power supply system according to claim 2, wherein the power supply system is executed. A power supply system for controlling a DC voltage between a first power line on a high voltage side and a second power line on a low voltage side,
A first DC power supply;
A second DC power source;
A power converter for performing DC power conversion in parallel between the first and second DC power supplies and the first and second power lines;
A control device for controlling the DC power conversion in the power converter;
The power converter is
A first switching element electrically connected between the first power line and a first node;
A second switching element electrically connected between a second node and the first node;
A third node electrically connected to the negative terminal of the second DC power source and a third switching element electrically connected between the second node;
A fourth switching element electrically connected between the negative terminal of the first DC power supply and the third node;
A first reactor electrically connected in series with the first DC power source between the second node and the second power line;
A second reactor electrically connected in series with the second DC power source between the first node and the third notebook;
According to a control signal from the control device, the third and fourth switching elements are turned on in common, and the first and second switching elements are turned off in common, whereby energy is supplied to the first reactor. Is formed, while the third and fourth switching elements are turned off in common according to the control signal, and the first and second switching elements are shared. Is turned on, a second current path is formed to release the stored energy of the first reactor,
The control device is configured to provide a time difference in turn-on timing or turn-on timing of the third and fourth switching elements, and to provide a time difference in turn-on timing or turn-off timing of the first and second switching elements. A power system that generates signals. The controller is
The turn-on timing of the second switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element is later than the turn-off timing of the second switching element. And the turn-on timing of the third switching element is earlier than the turn-on timing of the fourth switching element, and the turn-off timing of the fourth switching element is earlier than the turn-off timing of the third switching element. A first mode for generating the control signal to be slow;
The turn-on timing of the first switching element is earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element is later than the turn-off timing of the first switching element. And the turn-on timing of the fourth switching element is earlier than the turn-on timing of the third switching element, and the turn-off timing of the third switching element is earlier than the turn-off timing of the fourth switching element. A second mode for generating the control signal to be slow,
The power supply system according to claim 4, wherein the first mode and the second mode are executed in a time division manner. The control device sets a dead time, which is a period for simultaneously blocking the first and second current paths, to the control signal when switching between the first current path and the second current path. Set
The power supply system according to claim 5, wherein in each of the first and second modes, the control device sets the time difference so as not to exceed the dead time.   The control device time-divides the first mode and the second mode so that the time for executing the first mode and the time for executing the second mode are equal to each other. The power supply system according to claim 5 or 6, wherein the power supply system is executed. According to a control signal from the control device, the second and third switching elements are turned on in common, and the first and fourth switching elements are turned off in common, whereby energy is supplied to the second reactor. Is formed, while the second and third switching elements are turned off in common according to the control signal, and the first and fourth switching elements are shared. Is turned on to form a fourth current path for discharging the stored energy of the second reactor,
The control device is configured to provide a time difference in turn-on timing or turn-on timing of the second and third switching elements, and to provide a time difference in turn-on timing or turn-off timing of the first and fourth switching elements. The power supply system of claim 4, wherein the power supply system generates a signal. The controller is
The turn-on timing of the fourth switching element is earlier than the turn-on timing of the first switching element, and the turn-off timing of the first switching element is later than the turn-off timing of the fourth switching element. And the turn-on timing of the second switching element is earlier than the turn-on timing of the third switching element, and the turn-off timing of the third switching element is the turn-off timing of the second switching element. A third mode for generating the control signal to be slower than
The turn-on timing of the first switching element is earlier than the turn-on timing of the fourth switching element, and the turn-off timing of the fourth switching element is later than the turn-off timing of the first switching element. And the turn-on timing of the third switching element is earlier than the turn-on timing of the second switching element, and the turn-off timing of the second switching element is the turn-off timing of the third switching element. A fourth mode for generating the control signal so as to be slower than
The power supply system according to claim 8, wherein the third mode and the fourth mode are executed in a time-sharing manner. The control device sets a dead time, which is a period for simultaneously blocking the third and fourth current paths, to the control signal when switching the third current path and the fourth current path. Set
The power supply system according to claim 9, wherein in each of the third and fourth modes, the control device sets the time difference so as not to exceed the dead time.   The control device time-divides the third mode and the fourth mode so that the time for executing the third mode is equal to the time for executing the fourth mode. The power supply system according to claim 9 or 10, which is executed.

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