JP2016122810A - Substrate for semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a semiconductor device that enables an internal terminal face having a semiconductor element mounted thereon and an internal terminal portion electrically connected to the semiconductor element to be uniform in height, and enables omission of a step of forming an opening portion through which only an external terminal portion is exposed, thereby reducing the number of steps in a semiconductor device manufacturing process and enabling manufacturing of a resin sealed type semiconductor device having high reliability, and a manufacturing method for the substrate.SOLUTION: A first noble metal plating layer 11 serving as an internal terminal is formed at a predetermined site on a metal plate 1. A metal plating layer 12 is formed on the first noble metal plating layer so as to have the same shape as the first noble metal plating layer. A permanent resist 16 is formed on the metal plate and the metal plating layer so that a predetermined site of the metal plating layer is opened. A second noble metal plating layer 14 serving as an external terminal is formed on the metal plating layer located at the opening portion of the permanent resist.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device substrate and a method for manufacturing the same.

2. Description of the Related Art Conventionally, a substrate for a semiconductor device is used, for example, in a surface mount type sealing resin type semiconductor device having an ELP (Etched Leadless Package) structure, and has internal terminals and external terminals on a metal plate as a substrate. In addition, there is a type in which the wiring part is formed by metal plating.
As such a type of semiconductor device substrate, for example, the following Patent Document 1 describes a semiconductor substrate.

  In the substrate for a semiconductor device described in Patent Document 1, an external terminal surface having an external terminal portion is formed on a metal plate from the metal plate side, an intermediate layer is formed in the same shape thereon, and an internal terminal is further formed thereon. A semiconductor device substrate in which internal terminal surfaces having portions are formed in the same shape is disclosed. This substrate for a semiconductor device is formed so that the inner terminal surface having an inner terminal portion electrically connected to the semiconductor element is the uppermost surface, and the height from the metal plate to the uppermost surface is almost the same as the whole It is the structure formed in height.

  In the semiconductor device substrate described in Patent Document 1, when manufacturing a semiconductor device, the external terminal surface is in contact with the surface on the metal plate side, and the internal terminal surface is exposed on the surface opposite to the metal plate Used in. Specifically, a semiconductor element is mounted on the internal terminal surface side of the substrate for a semiconductor device, the electrode of the semiconductor element and the internal terminal portion are connected, sealed with resin, and after sealing with resin, the metal plate is dissolved by etching, etc. The external connection surface having the external terminal portion is exposed on the back surface of the resin sealed by removing. Thereafter, a resin that covers the entire exposed external connection surface is formed, and an opening that exposes only the external terminal portion is formed.

  However, when the external terminal surface is formed from the metal plate side and the internal terminal surface is formed on the uppermost layer by plating, in actual production, variations in the plating thickness occur. For example, when the plating thickness is about 30 μm, Since a height difference of about 7 μm occurs, when a semiconductor element is mounted and electrically connected to the internal terminal portion, the semiconductor element may be mounted in a tilted state, or conduction failure may occur in the electrical connection. There is a need to form a resin that covers the entire external connection surface and to form an opening through which only the external terminal portion is exposed.

JP 2009-164594 A

  As described above, in the substrate for a semiconductor device described in Patent Document 1, the height of the internal terminal surface on which the semiconductor element is mounted on the uppermost layer and the height of the internal terminal portion that is electrically connected to the semiconductor element are different due to variations in production. In this case, the present invention eventually causes poor conduction due to connection failure such as tilting or bonding of the mounted semiconductor element. Therefore, the present invention provides an internal terminal surface on which the semiconductor element is mounted and an internal terminal that is electrically connected to the semiconductor element. Reduces the number of processes when manufacturing semiconductor devices by making a semiconductor element substrate where the height of the part can be made uniform and by further eliminating the step of forming the opening where only the external terminal part is exposed Then, it aims at providing the board | substrate for semiconductor devices which can manufacture a highly reliable resin-sealed semiconductor device, and its manufacturing method.

  In order to achieve the above object, in a semiconductor device substrate according to the present invention, a first noble metal plating layer serving as an internal terminal is formed at a predetermined portion on a metal plate, and the first noble metal plating layer is formed on the first noble metal plating layer. A metal plating layer having the same shape as the first noble metal plating layer is formed, and a permanent resist having a predetermined portion opened in the metal plating layer is formed on the metal plate and the metal plating layer. A second noble metal plating layer serving as an external terminal is formed on the metal plating layer located in the opening of the resist.

  In the semiconductor device substrate of the present invention, a second metal plating layer having the same shape as the second noble metal plating layer is formed between the metal plating layer and the second noble metal plating layer. It is preferable.

  In the substrate for a semiconductor device of the present invention, as the first noble metal plating layer, the Au plating layer, the Pd plating layer, the metal plating layer, and the second metal plating layer in this order from the metal plate side. It is preferable that a Ni plating layer, a Pd plating layer as the second noble metal plating layer, and an Au plating layer are formed.

  In the semiconductor device substrate of the present invention, the permanent resist is formed with an opening for exposing the upper surface of the second noble metal plating layer, and the upper surface of the second noble metal plating layer is It is preferable to be located below the upper surface of the permanent resist.

  In the method of manufacturing a semiconductor device substrate according to the present invention, a resist mask having an opening of a pattern A is formed on a metal plate, a first noble metal plating layer is formed in the opening of the pattern A, and the first A metal plating layer having the same shape as the first noble metal plating layer is formed on one noble metal plating layer, the resist mask is peeled off, and then an opening of a pattern B where a part of the metal plating layer is exposed is formed. A second resist mask made of a permanent resist is formed, and a second noble metal plating layer or a second metal plating layer and the second noble metal plating layer are formed in the opening of the pattern B. .

  According to the present invention, there is provided a substrate for a semiconductor element in which the height of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion electrically connected to the semiconductor element can be made uniform, thereby reducing the number of processes when manufacturing the semiconductor device. Thus, there can be obtained a semiconductor device substrate and a method for manufacturing the same which can manufacture a highly reliable resin-encapsulated semiconductor device capable of improving productivity.

1A and 1B are diagrams illustrating a configuration of a substrate for a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view viewed from an external terminal side, and FIG. It is explanatory drawing which shows the manufacturing process of the board | substrate for semiconductor devices shown in FIG. FIG. 3 is a plan view showing a change in the state of a semiconductor device substrate in the manufacturing process of FIG. 2. It is explanatory drawing which shows an example of the manufacturing process of the resin sealing type semiconductor device using the board | substrate for semiconductor devices of 1st Embodiment manufactured through the manufacturing process shown in FIG. It is explanatory drawing which shows the manufacturing process of the conventional board | substrate for semiconductor devices concerning a comparative example. It is a top view which shows the change of the state of the board | substrate for semiconductor devices in the manufacturing process of FIG. It is explanatory drawing which shows an example of the manufacturing process of the resin sealing type | mold semiconductor device using the board | substrate for semiconductor devices of the comparative example manufactured through the manufacturing process shown in FIG.

Prior to the description of the embodiment, the function and effect of the present invention will be described.
The substrate for a semiconductor device of the present invention is a substrate for a semiconductor device on which a semiconductor element is mounted after removing the metal plate, and a first noble metal plating layer serving as an internal terminal from the metal plate side is formed on a predetermined portion on the metal plate A permanent resist in which a metal plating layer having the same shape as the first noble metal plating layer is formed on the first noble metal plating layer, and a predetermined portion of the metal plating layer is opened on the metal plate and the metal plating layer. Further, a second noble metal plating layer serving as an external terminal is formed on the metal plating layer located in the opening of the permanent resist.

  As in the semiconductor device substrate of the present invention, the resin provided in the semiconductor device manufacturing process in the conventional semiconductor device substrate is provided in advance as a permanent resist on the semiconductor device substrate, and internal terminals and wirings are formed in the openings of the permanent resist. Unlike the conventional semiconductor device substrate, in the process of manufacturing a semiconductor device, external terminals having different thicknesses from the portion are provided in advance, the internal terminals and wiring portions are sealed with a permanent resist, and only the external terminals are exposed. There is no need to provide an insulating layer having an opening on the connection surface with the external member, and the number of steps in manufacturing the semiconductor device is reduced and productivity is improved.

This point will be described in detail.
The applicant of the present application has come up with the idea that, after trial and error, the electrical connection surfaces of the internal terminals and external terminals in the semiconductor device substrate used when manufacturing the semiconductor device are reversed from those of the conventional semiconductor device substrate. did.
That is, in the conventional semiconductor device substrate, when manufacturing a semiconductor device, the external terminal surface is used with the metal plate side surface exposed, and the internal terminal surface is used with the surface opposite to the metal plate exposed. It is configured.
On the other hand, in the semiconductor device substrate of the present invention, when the semiconductor device is manufactured, the external terminal surface is the surface opposite to the metal plate, and the internal terminal surface is the surface exposed on the metal plate side. Based on the idea to be used, the plating layer constituting the external terminal is configured to be higher from the metal plate than the plating layer constituting the internal terminal and the wiring portion. For this purpose, a permanent resist having a predetermined portion opened in the metal plating layer is formed on the metal plate and the metal plating layer serving as the internal terminal, and further, the external is formed on the metal plating layer located at the opening of the permanent resist. A second noble metal plating layer to be a terminal is formed.

For example, when the metal plate in the substrate for a semiconductor device of the present invention is removed by dissolution or the like by etching, the surface of the first noble metal plating layer serving as the internal terminal on the side from which the metal plate is removed is the metal plate after the metal plate is removed. It is exposed in a state where there is no step following the surface (with a height difference of 1 μm or less). This metal plate is a general rolled material used for lead frames and the like.
Here, as in a semiconductor device using a conventional substrate for a semiconductor device, a semiconductor element is mounted on the first noble metal plating layer, but the surface of the first noble metal plating layer is exposed without a step. As a result, the entire connection surface is flat, so that the connection is stable.
In this case, the external terminal needs to expose the surface opposite to the metal plate side. Therefore, the present applicant, after applying noble metal plating and metal plating on the parts to be the internal terminal, the external terminal and the wiring part on the metal plate, further becomes an external terminal, unlike the conventional semiconductor device substrate. A metal plate and a metal plating layer serving as an internal terminal in order to form an external terminal having a height difference from the internal terminal and wiring part by further applying noble metal plating (or metal plating and noble metal plating) to only the part. A book in which a permanent resist having a predetermined portion opened in the metal plating layer is formed on the metal plating layer, and a second noble metal plating layer serving as an external terminal is formed on the metal plating layer located in the opening of the permanent resist. The inventors have come up with the semiconductor device substrate of the invention.

  Like the substrate for a semiconductor device of the present invention, if the external terminal, the internal terminal and the wiring part are provided with a height difference, only the internal terminal and the wiring part are sealed with a permanent resist, and only the external terminal is exposed, Unlike a conventional substrate for a semiconductor device, there is no need to form an opening in a connection surface with an external member in the manufacturing process of the semiconductor device, and accordingly, the number of steps is reduced and productivity is improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First Embodiment FIGS. 1A and 1B are views showing a configuration of a semiconductor device substrate according to a first embodiment of the present invention. FIG. 1A is a partial plan view seen from the external terminal side, and FIG. It is A sectional drawing. FIG. 2 is an explanatory view showing a manufacturing process of the semiconductor device substrate shown in FIG. FIG. 3 is a plan view showing a change in the state of the semiconductor device substrate in the manufacturing process of FIG.

As shown in FIG. 1B, the substrate for a semiconductor device according to the first embodiment is formed with a first noble metal plating layer 11 serving as an internal terminal at a predetermined portion on the metal plate 1, and the first noble metal plating layer. A metal plating layer 12 having the same shape as that of the first noble metal plating layer 11 is formed on the metal plate 1, and a permanent resist 16 having a predetermined portion in the metal plating layer 11 opened on the metal plate 1 and the metal plating layer 11. A second metal plating layer 13 is formed on the metal plating layer 11 formed and positioned in the opening of the permanent resist 16, and has the same shape as the second metal plating layer 13 on the second metal plating layer 13. A second noble metal plating layer 14 is formed as an external terminal.
The metal plate 1 is made of, for example, a copper plate.
The first noble metal plating layer 11 includes, for example, an Au plating layer 11a and a Pd plating layer 11b, which are sequentially formed from the metal plate 1 side.
The metal plating layer 12 and the second metal plating layer 13 are composed of, for example, a Ni plating layer.
The second noble metal plating layer 14 is composed of, for example, a Pd plating layer 14a and an Au plating layer 14b that are sequentially formed from the metal plate 1 side.
The height H2 of the surface of the second noble metal plating layer 14 (ie, the surface of the Au plating layer 14b) from the surface of the metal plate 1 is the height of the surface of the metal plating layer 12 from the surface of the metal plate 1. It is higher than H1.

The substrate for a semiconductor device according to the first embodiment configured as described above can be manufactured, for example, as follows. Note that description of pre-processing and post-processing including chemical solution cleaning and water cleaning performed in each manufacturing process is omitted for the sake of convenience.
First, as shown in FIG. 2 (a), a dry film resist for a resist mask is laminated on both surfaces of a metal plate to be a substrate. At this time, the plating layer is not formed on the metal plate as shown in FIG.
Next, as shown in FIG. 2 (b), for the dry film resist on the front side, there is a pattern (here referred to as pattern A) that forms base portions of internal terminals, wiring portions, and external terminals at predetermined positions. Using the formed glass mask, the front side is exposed and developed, and for the dry film resist on the back side, the back side is exposed and developed using a glass mask that irradiates the entire surface. Then, as shown in FIG. 2 (c), a resist mask of pattern A is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface. Exposure and development are performed by a conventionally known method. For example, by irradiating ultraviolet rays in a state covered with a glass mask, reducing the solubility of the dry film resist portion irradiated with the ultraviolet rays that passed through the glass mask with respect to the developer, and removing other portions, A resist mask is formed. Although a negative dry film resist is used here as a resist, a negative liquid resist may be used for forming a resist mask. Furthermore, by using a positive dry film resist or a liquid resist, the solubility of the resist portion irradiated with ultraviolet rays that has passed through the glass mask is increased in the developing solution, and the resist mask is removed by removing the portion. You may make it form. Furthermore, a solder resist may be used as the resist for forming the resist mask.
Next, the first noble metal plating layer 11 is plated on the portion of the metal plate exposed from the resist mask, for example, by Au plating so as to have a predetermined thickness in the order of the Au plating layer 11a and the Pd plating layer 11b, Pd plating is performed respectively.
Next, Ni plating is performed on the Pd plating layer 11b as the metal plating layer 12, for example, so that the Ni plating layer is formed in the same shape as the noble metal plating layer. FIG. 2 (d) shows the state at this time.

Next, the resist masks on both sides are peeled off. FIG. 3 (b) is a diagram showing a plating layer of pattern A applied to the semiconductor device substrate at this time, and FIG. 3 (c) is an enlarged view of a part of the region enclosed by a rectangle in FIG. 3 (b). FIG. Then, as shown in FIG. 2 (e), a film type permanent resist is laminated on the front surface side where the plating layer is formed, and a dry film resist similar to that used in FIG. 2 (a) is laminated on the back surface side. .
Next, as shown in FIG. 2 (f), there is a pattern (here referred to as pattern B) for forming a plating layer that is a part of the previously formed Ni plating layer and overlaps with a portion to be an external terminal. The formed glass mask is used to expose and develop the front side, and the back side resist film is exposed and developed using a glass mask that irradiates the entire surface. Then, as shown in FIG. 2G, a resist mask (permanent resist 16 shown in FIG. 1) made of a permanent resist of pattern B is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface.
Next, Ni plating is performed so that, for example, a Ni plating layer is formed as the second metal plating layer 13 on the surface of the Ni plating constituting the metal plating layer 12 exposed from the resist mask.
Next, on the surface of the Ni plating layer which is the second metal plating layer 13, as the second noble metal plating layer 14, for example, a Pd plating layer 14a and an Au plating layer 14b are respectively in a predetermined thickness in order. Pd plating and Au plating are performed respectively. FIG. 2 (h) shows the state at this time. In addition, without providing the second metal plating layer 13, as the second noble metal plating layer 14, for example, Pd plating, Au, and Au plating layers 14a and Au plating layers 14b are respectively formed in a predetermined thickness in this order. Plating may be performed respectively. FIG. 2 (i) shows the state at this time.
Next, as shown in FIG. 2 (j), the resist mask on the back surface is peeled off to complete the semiconductor device substrate of this embodiment. FIG. 3 (d) is a diagram showing a plating layer of the pattern B applied to the semiconductor device substrate at this time, and FIG. 3 (e) is an enlarged view of a part of the region enclosed by a rectangle in FIG. 3 (d). FIG. In FIGS. 3E and 3D, the permanent resist 16 is omitted for convenience.

A semiconductor device using the semiconductor device substrate of the first embodiment manufactured as described above is manufactured as follows. 4 is an explanatory view showing an example of a manufacturing process of a resin-encapsulated semiconductor device using the semiconductor device substrate of the first embodiment manufactured through the manufacturing process shown in FIG.
First, the metal plate of the semiconductor device substrate shown in FIG. 4A is etched, and the metal plate is removed by dissolution or the like. As a result, the surfaces of the internal terminal, the wiring portion, and the external terminal are exposed flush with the permanent resist surface. FIG. 4B shows the state at this time.
Next, the semiconductor element is mounted on the internal terminal surface side that appears when the metal plate is removed, and the electrode of the semiconductor element is connected to the internal terminal exposed flush with the permanent resist surface. In this case, in the flip chip method, as shown in FIG. 4C, the electrode of the semiconductor element and the internal terminal are connected. In the wire system, as shown in FIG. 4D, the electrodes of the semiconductor elements and the internal terminals are connected by wires. The surface of the internal terminal exposed through the semiconductor device manufacturing process shown in FIGS. 4A and 4B using the semiconductor device substrate of the first embodiment is flush with the permanent resist surface. The semiconductor element can be mounted in a stable state. Here, for convenience, description of die bonding for fixing the semiconductor element is omitted.
Next, as shown in FIG. 4E, the surface on which the semiconductor element is mounted is sealed with resin. Thereby, the semiconductor device is completed. 4A to 4E show the semiconductor device substrate without changing the vertical direction.

  The completed semiconductor device is mounted on an external member with its orientation in the vertical direction reversed from that shown in FIG. In this case, since only the external terminal is exposed from the permanent resist, it can be easily connected to the connection terminal provided on the external member. FIG. 4 (f) shows the state at this time.

Comparative Example Next, a configuration of a conventional semiconductor device substrate will be described as a comparative example of the semiconductor device substrate of the present embodiment. FIG. 5 is an explanatory view showing a manufacturing process of a conventional substrate for a semiconductor device according to a comparative example. FIG. 6 is a plan view showing a change in the state of the semiconductor device substrate in the manufacturing process of FIG.

  As shown in FIG. 5D, the semiconductor device substrate of the comparative example is formed such that the surfaces of the internal terminals, wiring portions, and external terminals formed on the metal plate are substantially the same height from the surface of the metal plate. ing.

The substrate for a semiconductor device of the comparative example configured as described above is manufactured, for example, as follows.
As shown in FIGS. 5 (a) to 5 (d), a resist mask dry film resist is laminated on both surfaces of a metal plate serving as a semiconductor device substrate, and exposure is performed using glass masks on the front and back sides. The pattern A and development of the resist mask on the entire surface by development, and the plating on the metal plate exposed from the resist mask, the semiconductor of the first embodiment shown in FIGS. 2 (a) to 2 (d) This is substantially the same as the manufacturing process of the device substrate.
The substrate for the semiconductor device of the comparative example is completed by removing the resist masks on both sides from the state of FIG. 5D, and is the first in that it does not go through the steps shown in FIGS. 2E to 2I. This is different from the manufacturing process of the semiconductor device substrate of one embodiment.

The assembly of the semiconductor device using the semiconductor device substrate of the comparative example manufactured as described above is performed as follows. FIG. 7 is an explanatory view showing a manufacturing process of a resin-encapsulated semiconductor device using a semiconductor device substrate of a comparative example manufactured through the manufacturing process shown in FIG.
First, a semiconductor element is mounted on the side of the metal plate of the substrate for a semiconductor device shown in FIGS. 7 (a) and 7 (b) on the side where the plating layer serving as the internal terminal, wiring portion, and external terminal protrudes, and the electrode of the semiconductor element is mounted. Connect to the internal terminal. In this case, in the flip chip method, as shown in FIG. 7A, the electrode of the semiconductor element and the internal terminal are connected. In the wire system, as shown in FIG. 7B, the electrodes of the semiconductor elements and the internal terminals are connected by wires. In addition, since the surface which mounts a semiconductor element has a height difference from the dispersion | variation in the thickness formed by plating, it is difficult to mount in the stable state. Therefore, an adhesive layer using a film or paste adhesive material is provided in the gap between the metal plate on which the semiconductor element is mounted and the semiconductor element, and when the semiconductor element is mounted, the semiconductor element and a part of the internal terminal are in contact with each other. Then, the semiconductor element is fixed to the metal plate through the adhesive layer so that the semiconductor element does not tilt.
Next, as shown in FIG. 7C, the surface on which the semiconductor element is mounted is sealed with resin.
Next, the metal plate of the semiconductor device substrate is etched to dissolve and remove the metal plate. Thereby, the surface of the internal terminal, the wiring part, and the external terminal is exposed from the resin surface on the back side of the semiconductor device. FIG. 7D shows the state at this time.
Next, as shown in FIG. 7E, the back side of the semiconductor device is covered with resin, and an opening is processed in the resin so that a part of the surface of the external terminal is exposed, thereby forming an external insulating layer. Thereby, the semiconductor device is completed.

The external insulating layer is formed as follows.
For example, as shown in FIG. 7G, a liquid solder resist for a resist mask is applied to the side where the surfaces of the internal terminals, wiring portions, and external terminals are flush with the resin surface shown in FIG. Then, heating is performed at a temperature slightly below the glass transition point to perform pre-curing (pre-curing) (FIG. 7 (h)).
Next, as shown in FIG. 7 (i), the precured solder resist is exposed and developed using a glass mask in which a pattern for forming an opening is formed in a portion to be an external terminal. Then, as shown in FIG. 7 (j), a resist mask having a pattern for forming an opening at a portion to be an external terminal is formed. Thereafter, in order to obtain the final strength of the resist mask, post-curing is further performed (FIG. 7 (k)).
Thereby, the semiconductor device shown in FIG. 7E is completed.

  The completed semiconductor device is mounted on an external member. In this case, the external terminal is exposed inside the opening surface of the resist mask. Therefore, the solder ball is embedded in the opening to be electrically connected to the terminal of the external member. FIG. 7 (l) shows the state at this time.

Comparison of Semiconductor Device of First Embodiment and Comparative Example As described above, in the semiconductor device substrate of the comparative example, the thicknesses of the plating layers constituting the external terminal, the internal terminal, and the wiring portion are formed substantially the same. In the subsequent manufacturing process of the semiconductor device, it is necessary to form an insulating layer for embedding the plating layer, and to process an opening for connecting to the external terminal in the insulating layer. As a result, the production delays and the productivity deteriorates.
On the other hand, according to the semiconductor device substrate of the first embodiment, the external terminal is provided with a height difference between the internal terminal and the wiring portion, and only the internal terminal and the wiring portion are sealed with a permanent resist or the like. Unlike the semiconductor device substrate of the comparative example, it is not necessary to provide an insulating layer having an opening on the connection surface with the external member in the manufacturing process of the semiconductor device. Reduces productivity. Furthermore, according to the semiconductor device substrate of the first embodiment, it can be shipped as a wiring member from which the metal plate is removed. By doing so, an etching step for removing the metal plate at the time of manufacturing the semiconductor device becomes unnecessary, and the productivity is further improved.

Further, in the semiconductor device substrate of the comparative example, the height of the upper surface of the plurality of internal terminals is formed by a plating layer having a variation having a height difference of several μm (for example, 3 to 7 μm). When the electrical connection is made with the internal terminal portion, the semiconductor element is mounted in an inclined state, or conduction failure occurs in the electrical connection.
On the other hand, according to the substrate for a semiconductor device of the first embodiment, in the subsequent manufacturing process of the semiconductor device, the height of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion that is electrically connected to the semiconductor element are Since it becomes uniform, the reliability of electrical connection between the semiconductor element and the internal terminal portion is improved.

EXAMPLES Next, examples of the substrate for a semiconductor device and the manufacturing method thereof according to the present invention will be described.
In each step, pre-processing and post-processing including chemical cleaning, water cleaning and the like are performed.
First, a copper material having a thickness of 0.15 mm, which is also used as a lead frame material, was prepared as a metal plate.
In the resist mask forming step, a dry film resist (AQ-2558, manufactured by Asahi Kasei Co., Ltd.) having a thickness of 25 μm was laminated on both surfaces of the metal plate (see FIG. 2A).
Next, using a glass mask having a pattern A for forming a plating at a predetermined position on the surface side, the dry film resist on the surface side is exposed and developed, and a resist in which a portion for forming the plating is opened A mask was formed (see FIGS. 2B and 2C). For the dry film resist on the back side, a resist mask covering the entire back side of the metal plate was formed. This exposure / development was the same as in the conventional method, and the pattern A was exposed to the dry film resist by bringing an exposure glass mask into close contact with the dry film resist and irradiated with ultraviolet rays, and developed with sodium carbonate.
In the next plating step, after performing general plating pretreatment on the metal plate exposed from the formed resist mask, Au becomes 0.003 μm or more, Pd becomes 0.01 μm or more, and Ni becomes 6 μm or more in order. (See FIG. 2 (d)).
Next, the resist masks on both sides are peeled off, a film type permanent resist (manufactured by Hitachi Chemical Co., Ltd .: KI-1000T4F) is laminated on the surface side on which the plating layer is first formed, and the dry film resist similar to the above is laminated on the back side. (See FIG. 2 (e)). At this time, it is necessary to select the thickness of the permanent resist according to the thickness of the second metal plating layer to be formed. In this embodiment, however, the second metal plating layer is formed to have a thickness of 15 to 40 μm. A permanent resist having a thickness of 50 μm was used. A resist having a thickness of 25 μm was used on the back side.
Then, a resist mask is formed by performing exposure and development using a glass mask in which a pattern B for forming a plating layer is formed on a part of the plating layer previously formed and overlapped with a portion to be an external terminal. (See FIG. 2 (f) and FIG. 2 (g)). In addition, the resist mask which covers the whole was formed in the back surface side like the last resist mask formation process.
In the next plating step, the Ni plating surface exposed from the formed resist mask is plated in such a manner that Pd is 0.01 μm or more and Au is 0.003 μm or more, and Ni is 15 μm or more in order. A substrate with two types of plating, Pd of 0.01 μm or more and Au of 0.003 μm or more, was made (see FIG. 2 (h) and FIG. 2 (i)), then Then, the resist mask on the back surface of each substrate was removed to produce two types of semiconductor device substrates (see FIG. 2 (j)).
The metal plate (copper material) of the completed semiconductor device substrate is removed by etching (see FIG. 4 (b)), and the semiconductor element is placed on the surface that is in contact with the metal plate using the plating layer fixed with permanent resist as the wiring. Mounted and electrically connected to the internal terminal (see Fig. 4 (c)), and sealed with resin, the surface of the external terminal is almost flush with the surface of the permanent resist (see Fig. 4 (e)). In a state where the surface of the permanent resist is concave (as shown in FIG. 4 (g), a solder ball is embedded in the opening so that it can be electrically connected to the connection terminal of the external member). Two types of semiconductor devices were obtained.

Although the embodiments and examples of the semiconductor device substrate of the present invention have been described above, the semiconductor device substrate of the present invention is not limited to the configurations of the above embodiments and examples.
For example, in the semiconductor device substrate of the first embodiment, Au and Pd are used for the first noble metal plating layer, Ni is used for the metal plating layer, Ni is used for the second metal plating layer, and Pd and Au are used for the second noble metal plating layer. The combination of the plating used for forming the first noble metal plating layer, the metal plating layer (or the metal plating layer and the second metal plating layer), and the second noble metal plating layer in the substrate for a semiconductor device of the present invention is used. However, the present invention is not limited to this, and as a modification, a first noble metal plating layer, a metal plating layer (or a metal plating layer and a second metal plating layer) plated as shown in Table 1 below, You may comprise the board | substrate for semiconductor devices of this invention combining a 2nd noble metal plating layer. In Table 1, it is shown that plating is performed in order from the top of each column in each modification.
Table 1 Plating combinations that make up semiconductor device substrates

  The substrate for a semiconductor device of the present invention is useful in a field where it is necessary to assemble a surface mount type sealing resin type semiconductor device.

1 metal plate 11 first noble metal plating layer 11a Au plating layer (first noble metal plating layer)
11b Pd plating layer (first noble metal plating layer)
12 Ni plating layer (metal plating layer)
13 Ni plating layer (second metal plating layer)
14 Second noble metal plating layer 14a Pd plating layer (second noble metal plating layer)
14b Au plating layer (second noble metal plating layer)
16 Permanent resist

Claims (6)

  A first noble metal plating layer serving as an internal terminal is formed at a predetermined portion on the metal plate, and a metal plating layer having the same shape as the first noble metal plating layer is formed on the first noble metal plating layer, A permanent resist having a predetermined portion opened in the metal plating layer is formed on the metal plate and the metal plating layer, and further serves as an external terminal on the metal plating layer located in the opening of the permanent resist. A semiconductor device substrate, wherein a second noble metal plating layer is formed. 2. The semiconductor according to claim 1, wherein a second metal plating layer having the same shape as the second noble metal plating layer is formed between the metal plating layer and the second noble metal plating layer. Device substrate.   In order from the metal plate side, as an Au plating layer as the first noble metal plating layer, a Pd plating layer, the Ni plating layer as the metal plating layer and the second metal plating layer, and the second noble metal plating layer The substrate for a semiconductor device according to claim 1, wherein a Pd plating layer and an Au plating layer are formed. The permanent resist is formed having an opening for exposing the upper surface of the second noble metal plating layer,
4. The semiconductor device substrate according to claim 1, wherein an upper surface of the second noble metal plating layer is positioned below an upper surface of the permanent resist. 5.   A resist mask having an opening of pattern A is formed on the metal plate, a first noble metal plating layer is formed in the opening of pattern A, and the first noble metal plating is formed on the first noble metal plating layer. Forming a metal plating layer with the same shape as the layer, peeling off the resist mask, and then forming a second resist mask made of a permanent resist having an opening of pattern B from which a part of the metal plating layer is exposed, A method for manufacturing a substrate for a semiconductor device, wherein the second noble metal plating layer or the second metal plating layer and the second noble metal plating layer are formed in the opening of the pattern B.   6. The method for manufacturing a substrate for a semiconductor device according to claim 5, wherein an upper surface of the second noble metal plating layer is positioned below an upper surface of the second resist mask.

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