JP2016122809A - Wiring member for semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring member for a semiconductor device that enables an internal terminal face having a semiconductor element mounted thereon and an internal terminal portion electrically connected to the semiconductor element to be uniform in height, and also enables etching removal of a metal plate and omission of a step of forming an opening portion through which only an external terminal portion is exposed in a semiconductor device manufacturing process, thereby reducing the number of steps in the semiconductor device manufacturing process and thus enabling manufacturing of a resin sealed type semiconductor device having high reliability, and a manufacturing method for the substrate.SOLUTION: A first noble metal plating layer 11 serving as an internal terminal is formed at a predetermined site on one surface 15a of a resin layer 15 while the lower surface thereof is exposed to constitute the same plane together with the one surface 15a of the resin layer. A metal plating layer 12 is formed on the first noble metal plating layer so as to have the same shape as the first noble metal plating layer. A second noble metal plating layer 14 partially serving as an external terminal is formed on the metal plating layer while the upper surface thereof is exposed from the other surface 15b of the resin layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring member for a semiconductor device and a method for manufacturing the same.

2. Description of the Related Art Conventionally, a substrate for a semiconductor device is used, for example, in a surface mount type sealing resin type semiconductor device having an ELP (Etched Leadless Package) structure, and has internal terminals and external terminals on a metal plate as a substrate. In addition, there is a type in which the wiring part is formed by metal plating.
As such a type of semiconductor device substrate, for example, the following Patent Document 1 describes a semiconductor substrate.

  In the substrate for a semiconductor device described in Patent Document 1, an external terminal surface having an external terminal portion is formed on a metal plate from the metal plate side, an intermediate layer is formed in the same shape thereon, and an internal terminal is further formed thereon. A semiconductor device substrate in which internal terminal surfaces having portions are formed in the same shape is disclosed. This substrate for a semiconductor device is formed so that the inner terminal surface having an inner terminal portion electrically connected to the semiconductor element is the uppermost surface, and the height from the metal plate to the uppermost surface is almost the same as the whole It is the structure formed in height.

  In the semiconductor device substrate described in Patent Document 1, when manufacturing a semiconductor device, the external terminal surface is in contact with the surface on the metal plate side, and the internal terminal surface is exposed on the surface opposite to the metal plate Used in. Specifically, a semiconductor element is mounted on the internal terminal surface side of the substrate for a semiconductor device, the electrode of the semiconductor element and the internal terminal portion are connected, sealed with resin, and after sealing with resin, the metal plate is dissolved by etching, etc. The external connection surface having the external terminal portion is exposed on the back surface of the resin sealed by removing. Thereafter, a resin that covers the entire exposed external connection surface is formed, and an opening that exposes only the external terminal portion is formed.

  However, when the external terminal surface is formed from the metal plate side and the internal terminal surface is formed on the uppermost layer by plating, the plating thickness varies in actual production. For example, when the plating thickness is about 30 μm, 3-7 μm Since there is a difference in level, there is a possibility that when mounting a semiconductor element and making an electrical connection with an internal terminal, the semiconductor element is mounted in a tilted state or a continuity failure occurs in the electrical connection. In addition, a process of forming a resin that covers the entire external connection surface and forming an opening from which only the external terminal portion is exposed is necessary.

JP 2009-164594 A

  As described above, in the substrate for a semiconductor device described in Patent Document 1, the height of the internal terminal surface on which the semiconductor element is mounted on the uppermost layer and the height of the internal terminal portion that is electrically connected to the semiconductor element are different due to variations in production. In this case, the present invention eventually causes poor conduction due to connection failure such as tilting or bonding of the mounted semiconductor element. Therefore, the present invention provides an internal terminal surface on which the semiconductor element is mounted and an internal terminal that is electrically connected to the semiconductor element. Wiring member for a semiconductor element capable of making the height of the part uniform, and further, the step of forming an opening through which only the external terminal part is exposed in the manufacturing process of the semiconductor device can be omitted. Therefore, a wiring member for a semiconductor device and a method for manufacturing the same that can manufacture a highly reliable resin-encapsulated semiconductor device by reducing the number of steps in manufacturing the semiconductor device It is intended to be subjected.

  In order to achieve the above object, a wiring member for a semiconductor device according to the present invention has a first noble metal plating layer serving as an internal terminal at a predetermined portion on one surface of a resin layer, and a lower surface of the first noble metal plating layer. A metal plating layer having the same shape as that of the first noble metal plating layer is formed on the first noble metal plating layer, and is partially formed on the metal plating layer. The second noble metal plating layer serving as an external terminal is formed with the upper surface exposed from the other surface of the resin layer.

  In the wiring member for a semiconductor device of the present invention, a second metal plating layer having the same shape as the second noble metal plating layer is formed between the metal plating layer and the second noble metal plating layer. It is preferable.

  In the wiring member for a semiconductor device of the present invention, in order from one surface side of the resin layer, an Au plating layer, a Pd plating layer, the metal plating layer, and the second noble metal plating layer as the first noble metal plating layer. It is preferable that a Ni plating layer as a metal plating layer, a Pd plating layer as the second noble metal plating layer, and an Au plating layer are formed.

  The method for manufacturing a wiring member for a semiconductor device according to the present invention includes forming a resist mask having an opening of a pattern A on a metal plate, forming a first noble metal plating layer in the opening of the pattern A, and An opening of a pattern B in which a part of the metal plating layer is exposed after a metal plating layer having the same shape as the first noble metal plating layer is formed on the first noble metal plating layer and the resist mask is removed. A second noble metal plating layer or a second metal plating layer and the second noble metal plating layer in the opening of the pattern B, and the second resist mask After peeling, a resin layer is formed on the metal plate and the metal plating layer so as to expose the upper surface of the second noble metal plating layer on a portion where the second noble metal plating layer is not formed. After forming the resin layer, it is characterized by removing the metal plate.

  According to the present invention, there is provided a wiring member for a semiconductor element in which the height of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion that is electrically connected to the semiconductor element can be made uniform, thereby reducing the number of processes when manufacturing the semiconductor device. Thus, there can be obtained a wiring member for a semiconductor device capable of improving the productivity and capable of manufacturing a highly reliable resin-encapsulated semiconductor device and a manufacturing method thereof.

2A and 2B are diagrams illustrating the configuration of the wiring member for a semiconductor device according to the first embodiment of the present invention, in which FIG. 1A is a plan view viewed from the external terminal side, and FIG. It is explanatory drawing which shows the manufacturing process of the wiring member for semiconductor devices shown in FIG. FIG. 3 is a plan view showing changes in the state of a semiconductor device wiring member in the manufacturing process of FIG. It is explanatory drawing which shows an example of the manufacturing process of the resin sealing type | mold semiconductor device using the wiring member for semiconductor devices of 1st Embodiment manufactured through the manufacturing process shown in FIG. It is explanatory drawing which shows the manufacturing process of the conventional board | substrate for semiconductor devices concerning a comparative example. It is a top view which shows the change of the state of the board | substrate for semiconductor devices in the manufacturing process of FIG. It is explanatory drawing which shows an example of the manufacturing process of the resin sealing type | mold semiconductor device using the board | substrate for semiconductor devices of the comparative example manufactured through the manufacturing process shown in FIG.

Prior to the description of the embodiment, the function and effect of the present invention will be described.
The wiring member for a semiconductor device according to the present invention is a wiring member for a semiconductor device on which a semiconductor element from which a metal plate has been removed is mounted, and a first noble metal plating layer serving as an internal terminal is formed at a predetermined portion on one surface of the resin layer. The lower surface is formed in a state where it is flush with one surface of the resin layer, a metal plating layer is formed on the first noble metal plating layer in the same shape as the first noble metal plating layer, and further the metal plating layer A second noble metal plating layer that partially serves as an external terminal is formed on the upper surface of the resin layer with the upper surface exposed from the other surface of the resin layer.

  As in the semiconductor device wiring member of the present invention, an external terminal having a thickness different from that of the internal terminal and the wiring portion is provided at a portion corresponding to the opening of the resin layer provided in the manufacturing process of the semiconductor device in the conventional semiconductor device substrate. Unlike the conventional semiconductor device substrate, the external member and the external member are provided in advance by sealing the internal terminals and the wiring portion with resin and exposing only the external terminals from the other surface of the resin layer. Therefore, it is not necessary to provide an insulating layer having an opening on the connection surface, and accordingly, the number of steps in manufacturing the semiconductor device is reduced and productivity is improved.

This point will be described in detail.
The applicant of the present application has come up with the idea that, after trial and error, the electrical connection surfaces of the internal terminals and external terminals in the semiconductor device substrate used when manufacturing the semiconductor device are reversed from those of the conventional semiconductor device substrate. did.
That is, in the conventional semiconductor device substrate, when manufacturing a semiconductor device, the external terminal surface is used with the metal plate side surface exposed, and the internal terminal surface is used with the surface opposite to the metal plate exposed. It is configured.
In contrast, in the semiconductor device wiring member of the present invention, when manufacturing a semiconductor device, the external terminal surface is the surface opposite to the metal plate used when manufacturing the semiconductor device substrate, and the internal terminal surface is the semiconductor device. Manufacturing a substrate for a semiconductor device with a plating layer that constitutes an external terminal rather than a plating layer that constitutes an internal terminal and a wiring part, based on the idea of using the surface on the metal plate side exposed when the substrate for manufacturing is exposed. It is configured to be higher than the metal plate used sometimes.

For example, when the metal plate used in manufacturing the wiring member for a semiconductor device of the present invention is removed by dissolution or the like by etching, the surface of the first noble metal plating layer that becomes the internal terminal on the side from which the metal plate is removed after the metal plate is removed. Is exposed in a state having no level difference (with a height difference of 1 μm or less) following the surface of the metal plate. This metal plate is a general rolled material used for lead frames and the like.
Here, as in a semiconductor device using a conventional substrate for a semiconductor device, a semiconductor element is mounted on the first noble metal plating layer, but the surface of the first noble metal plating layer is exposed without a step. As a result, the entire connection surface is flat, so that the connection is stable.
In this case, the external terminal needs to expose the surface opposite to the metal plate side. Therefore, the present applicant, after applying noble metal plating and metal plating on the parts to be the internal terminal, the external terminal and the wiring part on the metal plate, further becomes an external terminal, unlike the conventional semiconductor device substrate. By applying additional precious metal plating (or metal plating and precious metal plating) only on the part, external terminals having a height difference from the internal terminals and wiring portions are formed, and a second precious metal plating layer is formed. The present inventors have arrived at the wiring member for a semiconductor device of the present invention in which the resin layer is formed in a state in which the upper surface of the second noble metal plating layer is exposed on a portion that is not present, and the metal plate is removed by etching.

  Like the wiring member for a semiconductor device of the present invention, the external terminal, the internal terminal and the wiring part are provided with a height difference, and only the internal terminal and the wiring part are sealed with resin, and only the external terminal is exposed. If it is provided on the other surface of the resin layer, unlike the conventional semiconductor device substrate, it is necessary to remove the metal plate by etching or form an opening in the connection surface with the external member in the manufacturing process of the semiconductor device. Therefore, the number of processes is reduced correspondingly, and productivity is improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First Embodiment FIG. 1 is a diagram showing a configuration of a wiring member for a semiconductor device according to a first embodiment of the present invention, in which (a) is a partial plan view seen from the external terminal side, and (b) is A in (a). It is -A sectional drawing. FIG. 2 is an explanatory view showing a manufacturing process of the semiconductor device wiring member shown in FIG. FIG. 3 is a plan view showing a change in the state of the wiring member for a semiconductor device in the manufacturing process of FIG.

In the wiring member for a semiconductor device according to the first embodiment, as shown in FIG. 1B, the first noble metal plating layer 11 serving as an internal terminal is formed on the lower surface of the resin layer 15 at a predetermined portion on one surface 15a of the resin layer 15. A metal plating layer 12 is formed on the first noble metal plating layer 11 in the same shape as the first noble metal plating layer 11, and is exposed to the one surface 15 a of 15. A second metal plating layer 13 is partially formed on 12, and a second noble metal plating layer 14 having the same shape as the second metal plating layer 12 and serving as an external terminal is formed on the second metal plating layer 13. Is formed with the upper surface exposed from the other surface 15 b of the resin layer 15.
The first noble metal plating layer 11 includes, for example, an Au plating layer 11a and a Pd plating layer 11b, which are sequentially formed from the one surface 15a side of the resin layer 15.
The metal plating layer 12 and the second metal plating layer 13 are composed of, for example, a Ni plating layer.
The second noble metal plating layer 14 is composed of, for example, a Pd plating layer 14a and an Au plating layer 14b formed in this order from the one surface 15a side of the resin layer 15.
The height H2 of the surface of the second noble metal plating layer 14 (that is, the surface of the Au plating layer 14b) from the one surface 15a of the resin layer 15 is one of the resin layers 15 on the surface of the metal plating layer 12. It is higher than the height H1 from the surface 15a.

The wiring member for a semiconductor device according to the first embodiment configured as described above can be manufactured, for example, as follows. Note that description of pre-processing and post-processing including chemical solution cleaning and water cleaning performed in each manufacturing process is omitted for the sake of convenience.
First, as shown in FIG. 2 (a), a dry film resist for a resist mask is laminated on both surfaces of a metal plate to be a substrate. At this time, the plating layer is not formed on the metal plate as shown in FIG.
Next, as shown in FIG. 2 (b), for the dry film resist on the front side, there is a pattern (here referred to as pattern A) that forms base portions of internal terminals, wiring portions, and external terminals at predetermined positions. Using the formed glass mask, the front side is exposed and developed, and for the dry film resist on the back side, the back side is exposed and developed using a glass mask that irradiates the entire surface. Then, as shown in FIG. 2 (c), a resist mask of pattern A is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface. Exposure and development are performed by a conventionally known method. For example, by irradiating ultraviolet rays in a state covered with a glass mask, reducing the solubility of the dry film resist portion irradiated with the ultraviolet rays that passed through the glass mask with respect to the developer, and removing other portions, A resist mask is formed. Although a negative dry film resist is used here as a resist, a negative liquid resist may be used for forming a resist mask. Furthermore, by using a positive dry film resist or a liquid resist, the solubility of the resist portion irradiated with ultraviolet rays that has passed through the glass mask is increased in the developing solution, and the resist mask is removed by removing the portion. You may make it form. Furthermore, a solder resist may be used as the resist for forming the resist mask.
Next, the first noble metal plating layer 11 is plated on the portion of the metal plate exposed from the resist mask, for example, by Au plating so as to have a predetermined thickness in the order of the Au plating layer 11a and the Pd plating layer 11b, Pd plating is performed respectively.
Next, Ni plating is performed on the Pd plating layer 11b as the metal plating layer 12, for example, so that the Ni plating layer is formed in the same shape as the noble metal plating layer. FIG. 2 (d) shows the state at this time.

Next, the resist masks on both sides are peeled off. FIG. 3 (b) is a diagram showing a plating layer of pattern A applied to the semiconductor device substrate at this time, and FIG. 3 (c) is an enlarged view of a part of the region enclosed by a rectangle in FIG. 3 (b). FIG. Then, as shown in FIG. 2 (e), a dry film resist is laminated on both the peeled surfaces.
Next, as shown in FIG. 2 (f), there is a pattern (here referred to as pattern B) for forming a plating layer that is a part of the previously formed Ni plating layer and overlaps with a portion to be an external terminal. The formed glass mask is used to expose and develop the front side, and the back side resist film is exposed and developed using a glass mask that irradiates the entire surface. Then, as shown in FIG. 2 (g), a resist mask of pattern B is formed on the front surface, and a resist mask covering the entire surface is formed on the back surface.
Next, Ni plating is performed so that, for example, a Ni plating layer is formed as the second metal plating layer 13 on the surface of the Ni plating constituting the metal plating layer 12 exposed from the resist mask.
Next, on the surface of the Ni plating layer which is the second metal plating layer 13, as the second noble metal plating layer 14, for example, a Pd plating layer 14a and an Au plating layer 14b are respectively in a predetermined thickness in order. Pd plating and Au plating are performed respectively. FIG. 2 (h) shows the state at this time. In addition, without providing the second metal plating layer 13, as the second noble metal plating layer 14, for example, Pd plating, Au, and Au plating layers 14a and Au plating layers 14b are respectively formed in a predetermined thickness in this order. Plating may be performed respectively.
Next, as shown in FIG. 2 (i), the resist masks on both sides are removed. FIG. 3 (d) is a diagram showing a plating layer of the pattern B applied to the semiconductor device substrate at this time, and FIG. 3 (e) is an enlarged view of a part of the region enclosed by a rectangle in FIG. 3 (d). FIG.
Next, as shown in FIG. 2 (j), the surface of the noble metal plating layer 14 serving as the external terminal is exposed on the side where the plating layers corresponding to the internal terminal, the wiring portion, and the external terminal protrude on the metal plate. Then, other parts are sealed with resin. FIG. 2 (j) shows a metal plate provided with a noble metal plating layer 14 which is a second noble metal plating layer without providing the second metal plating layer 13 on the surface of the Ni plating constituting the metal plating layer 12. The state of resin sealing when used is shown. A metal plate in which a second metal plating layer 13 is provided on the surface of Ni plating constituting the metal plating layer 12, and a noble metal plating layer 14 which is a second noble metal plating layer is provided on the surface of the second metal plating layer 13. 2 is used, as shown in FIG. 2 (j ′), when the resin is sealed, the noble metal plating layer 14 protrudes from the surface of the resin. In the following description, for convenience, a metal plate provided with a noble metal plating layer 14 as a second noble metal plating layer without using the second metal plating layer 13 is used. In addition, when the metal plate which provided the noble metal plating layer 14 which is a 2nd noble metal plating layer without providing the 2nd metal plating layer 13 was used in the case of resin sealing, the terminal by plating of a terminal pattern The resin may wrap around the external terminal surface due to the unevenness of the height. In that case, the surface of the sealed resin is polished to expose the external terminal surface.
Next, etching is performed on the metal plate of the substrate for a semiconductor device, and the metal plate is removed by dissolution or the like. As shown in FIG. 2 (k), the surfaces of the internal terminals, wiring portions, and external terminals are faced from the resin surface. Expose to one. Thereby, the wiring member for a semiconductor device of this embodiment is completed.

Manufacturing of the semiconductor device using the wiring member for semiconductor device of the first embodiment manufactured as described above is performed as follows. FIG. 4 is an explanatory view showing an example of a manufacturing process of a resin-encapsulated semiconductor device using the semiconductor device wiring member of the first embodiment manufactured through the manufacturing process shown in FIG. In FIG. 4A, a predetermined portion is formed by providing a noble metal plating layer 14 as a second noble metal plating layer on the surface of Ni plating constituting the metal plating layer 12 without providing the second metal plating layer 13. A semiconductor device substrate in which resin sealing is performed and a metal plate is dissolved and removed is shown. A second metal plating layer 13 is provided on the surface of the Ni plating constituting the metal plating layer 12, and a noble metal plating layer 14 which is a second noble metal plating layer is provided on the surface of the second metal plating layer 13, thereby providing a predetermined portion. 4 is used, the noble metal plating layer 14 protrudes from the surface of the resin, as shown in FIG. 4 (a '). In the following description, for convenience, the second metal plating layer 13 is not provided, but the noble metal plating layer 14 as the second noble metal plating layer is provided, and a predetermined portion is sealed with resin, and the metal plate is dissolved and removed. A semiconductor device substrate is used.
First, a semiconductor element is mounted on the internal terminal surface side of the wiring member for a semiconductor device shown in FIG. 4A, and the electrode of the semiconductor element is connected to the internal terminal exposed flush with the resin surface. In this case, in the flip chip method, as shown in FIG. 4B, the electrode of the semiconductor element and the internal terminal are connected. In the wire system, as shown in FIG. 4C, the electrodes of the semiconductor elements and the internal terminals are connected by wires. Note that in the semiconductor device wiring member according to the first embodiment, since the exposed surface of the internal terminal is flush with the resin surface, the semiconductor element can be mounted in a stable state. Here, for convenience, description of die bonding for fixing the semiconductor element is omitted.
Next, as shown in FIG. 4D, the surface on which the semiconductor element is mounted is sealed with resin. Thereby, the semiconductor device is completed. 4A to 4D illustrate the semiconductor device wiring member without changing the vertical direction.

  The completed semiconductor device is mounted on an external member with its orientation in the vertical direction reversed from that shown in FIG. In this case, since only the external terminal is exposed from the resin, it can be easily connected to the connection terminal provided on the external member. FIG. 4 (e) shows the state at this time.

Comparative Example Next, a configuration of a conventional substrate for a semiconductor device will be described as a comparative example of the wiring member for a semiconductor device of the present embodiment. FIG. 5 is an explanatory view showing a manufacturing process of a conventional substrate for a semiconductor device according to a comparative example. FIG. 6 is a plan view showing a change in the state of the semiconductor device substrate in the manufacturing process of FIG.

  As shown in FIG. 5D, the semiconductor device substrate of the comparative example is formed such that the surfaces of the internal terminals, wiring portions, and external terminals formed on the metal plate are substantially the same height from the surface of the metal plate. ing.

The substrate for a semiconductor device of the comparative example configured as described above is manufactured, for example, as follows.
As shown in FIGS. 5 (a) to 5 (d), a resist mask dry film resist is laminated on both surfaces of a metal plate serving as a semiconductor device substrate, and exposure is performed using glass masks on the front and back sides. The pattern A and development of the resist mask on the entire surface by development, and the plating on the metal plate exposed from the resist mask, the semiconductor of the first embodiment shown in FIGS. 2 (a) to 2 (d) This is substantially the same as the manufacturing process of the device wiring member.
The substrate for a semiconductor device of the comparative example is completed by removing the resist masks on both sides from the state of FIG. 5D, and is the first in that the steps shown in FIGS. 2E to 2K are not performed. This is different from the manufacturing process of the semiconductor device wiring member according to the embodiment.

The assembly of the semiconductor device using the semiconductor device substrate of the comparative example manufactured as described above is performed as follows. FIG. 7 is an explanatory view showing a manufacturing process of a resin-encapsulated semiconductor device using a semiconductor device substrate of a comparative example manufactured through the manufacturing process shown in FIG.
First, a semiconductor element is mounted on the side of the metal plate of the substrate for a semiconductor device shown in FIGS. 7 (a) and 7 (b) on the side where the plating layer serving as the internal terminal, wiring portion, and external terminal protrudes, and the electrode of the semiconductor element is mounted. Connect to the internal terminal. In this case, in the flip chip method, as shown in FIG. 7A, the electrode of the semiconductor element and the internal terminal are connected. In the wire system, as shown in FIG. 7B, the electrodes of the semiconductor elements and the internal terminals are connected by wires. In addition, since the surface which mounts a semiconductor element has a height difference from the dispersion | variation in the thickness formed by plating, it is difficult to mount in the stable state. Therefore, an adhesive layer using a film or paste adhesive material is provided in the gap between the metal plate on which the semiconductor element is mounted and the semiconductor element, and when the semiconductor element is mounted, the semiconductor element and a part of the internal terminal are in contact with each other. Then, the semiconductor element is fixed to the metal plate through the adhesive layer so that the semiconductor element does not tilt.
Next, as shown in FIG. 7C, the surface on which the semiconductor element is mounted is sealed with resin.
Next, the metal plate of the semiconductor device substrate is etched to dissolve and remove the metal plate. Thereby, the surface of the internal terminal, the wiring part, and the external terminal is exposed from the resin surface on the back side of the semiconductor device. FIG. 7D shows the state at this time.
Next, as shown in FIG. 7E, the back side of the semiconductor device is covered with resin, and an opening is processed in the resin so that a part of the surface of the external terminal is exposed, thereby forming an external insulating layer. Thereby, the semiconductor device is completed.

The external insulating layer is formed as follows.
For example, as shown in FIG. 7G, a liquid solder resist for a resist mask is applied to the side where the surfaces of the internal terminals, wiring portions, and external terminals are flush with the resin surface shown in FIG. Then, heating is performed at a temperature slightly below the glass transition point to perform pre-curing (pre-curing) (FIG. 7 (h)).
Next, as shown in FIG. 7 (i), the precured solder resist is exposed and developed using a glass mask in which a pattern for forming an opening is formed in a portion to be an external terminal. Then, as shown in FIG. 7 (j), a resist mask having a pattern for forming an opening at a portion to be an external terminal is formed. Thereafter, in order to obtain the final strength of the resist mask, post-curing is further performed (FIG. 7 (k)).
Thereby, the semiconductor device shown in FIG. 7E is completed.

  The completed semiconductor device is mounted on an external member. In this case, the external terminal is exposed inside the opening surface of the resist mask. Therefore, the solder ball is embedded in the opening to be electrically connected to the terminal of the external member. FIG. 7 (l) shows the state at this time.

Comparison of Semiconductor Device of First Embodiment and Comparative Example As described above, in the semiconductor device substrate of the comparative example, the thicknesses of the plating layers constituting the external terminal, the internal terminal, and the wiring portion are formed substantially the same. In the subsequent manufacturing process of the semiconductor device, it is necessary to form an insulating layer for embedding the plating layer, and to process an opening for connecting to the external terminal in the insulating layer. As a result, the production delays and the productivity deteriorates.
On the other hand, according to the wiring member for a semiconductor device of the first embodiment, the height difference is provided between the external terminal, the internal terminal, and the wiring part, and only the internal terminal and the wiring part are sealed with resin, Since only the external terminals are exposed from the other surface, unlike the semiconductor device substrate of the comparative example, it is necessary to remove the metal plate by etching or process an opening in the connection surface with the external member in the semiconductor device manufacturing process. Therefore, the number of processes is reduced correspondingly, and the productivity is improved.

In addition, in the semiconductor device substrate of the comparative example, the height of the upper surfaces of the plurality of internal terminals is formed by a plating layer having a variation having a height difference of several μm, so that a semiconductor element is mounted and the internal terminal portion When electrical connection is made, the semiconductor element is mounted in an inclined state, or conduction failure occurs in electrical connection.
On the other hand, according to the wiring member for a semiconductor device of the first embodiment, in the subsequent manufacturing process of the semiconductor device, the height of the internal terminal surface on which the semiconductor element is mounted and the internal terminal portion that is electrically connected to the semiconductor element. Therefore, the reliability of electrical connection between the semiconductor element and the internal terminal portion is improved.

EXAMPLE Next, an example of a wiring member for a semiconductor device and a method for manufacturing the same according to the present invention will be described.
In each step, pre-processing and post-processing including chemical cleaning, water cleaning and the like are performed.
First, a copper material having a thickness of 0.15 mm, which is also used as a lead frame material, was prepared as a metal plate.
In the resist mask forming step, a dry film resist (AQ-2558, manufactured by Asahi Kasei Co., Ltd.) having a thickness of 25 μm was laminated on both surfaces of the metal plate (see FIG. 2A).
Next, using a glass mask having a pattern A for forming a plating at a predetermined position on the surface side, the dry film resist on the surface side is exposed and developed, and a resist in which a portion for forming the plating is opened A mask was formed (see FIGS. 2B and 2C). For the dry film resist on the back side, a resist mask covering the entire back side of the metal plate was formed. This exposure / development was the same as in the conventional method, and the pattern A was exposed to the dry film resist by bringing an exposure glass mask into close contact with the dry film resist and irradiated with ultraviolet rays, and developed with sodium carbonate.
In the next plating step, after performing general plating pretreatment on the metal plate exposed from the formed resist mask, Au becomes 0.003 μm or more, Pd becomes 0.01 μm or more, and Ni becomes 6 μm or more in order. (See FIG. 2 (d)).
Next, the resist masks on both sides were peeled off, and the same dry film resist was laminated on both sides (see FIG. 2 (e)). At this time, it is necessary to select the thickness of the resist according to the thickness of the second metal plating layer to be formed. In this embodiment, the surface of the second metal plating layer is formed so as to be 15 to 40 μm. A resist having a thickness of 50 μm was used only on the side, and a resist having a thickness of 25 μm was used on the back side.
Then, a resist mask is formed by performing exposure and development using a glass mask in which a pattern B for forming a plating layer is formed on a part of the plating layer previously formed and overlapped with a portion to be an external terminal. (See FIG. 2 (f) and FIG. 2 (g)). In addition, the resist mask which covers the whole was formed in the back surface side like the last resist mask formation process.
In the next plating step, plating is performed on the Ni plating surface exposed from the formed resist mask so that Ni is 40 μm or more, Pd is 0.01 μm or more, and Au is 0.003 μm or more (FIG. 2 (h Then, the resist masks on both sides were removed (see FIG. 2 (i)).
Next, the other part was sealed with resin so that the surface of the noble metal plating layer serving as the external terminal was exposed on the side where the plating layer corresponding to the internal terminal, wiring portion, and external terminal of the metal plate protruded ( (See FIG. 2 (j)).
Next, the metal plate (copper material) was removed by etching to produce a semiconductor device wiring member (see FIG. 2 (k)).
The finished plating layer fixed with resin of the wiring member for a semiconductor device is used as a wiring, and a semiconductor element is mounted on the surface side that is in contact with the metal plate to establish conduction with the internal terminal (see FIG. 4C). By sealing the element mounting portion with resin, a semiconductor device in which the surface of the external terminal was exposed from the resin surface was obtained (see FIG. 4E).

While the embodiments and examples of the semiconductor device wiring member of the present invention have been described above, the semiconductor device wiring members of the present invention are not limited to the configurations of the above embodiment and examples.
For example, in the wiring member for a semiconductor device of the first embodiment, Au and Pd are used for the first noble metal plating layer, Ni is used for the metal plating layer, Ni is used for the second metal plating layer, and Pd and Au are used for the second noble metal plating layer. Of the plating used for forming the first noble metal plating layer, the metal plating layer (or the metal plating layer and the second metal plating layer), and the second noble metal plating layer in the wiring member for a semiconductor device of the present invention. The combination is not limited to this. As a modification, the first noble metal plating layer and the metal plating layer (or the metal plating layer and the second metal plating layer) plated as shown in the following Table 1 are used. ), And the second noble metal plating layer may be combined to form the semiconductor device wiring member of the present invention. In Table 1, it is shown that plating is performed in order from the top of each column in each modification.
Table 1 Combinations of plating that constitute wiring members for semiconductor devices

  The wiring member for a semiconductor device of the present invention is useful in a field where it is necessary to assemble a surface mount type sealing resin type semiconductor device.

11 1st noble metal plating layer 11a Au plating layer (first noble metal plating layer)
11b Pd plating layer (first noble metal plating layer)
12 Ni plating layer (metal plating layer)
13 Ni plating layer (second metal plating layer)
14 Second noble metal plating layer 14a Pd plating layer (second noble metal plating layer)
14b Au plating layer (second noble metal plating layer)
15 Resin layer 15a One surface 15b The other surface

Claims (4)

  A first noble metal plating layer serving as an internal terminal is formed at a predetermined site on one surface of the resin layer with a lower surface exposed to be flush with one surface of the resin layer, and the first noble metal plating layer A metal plating layer having the same shape as the first noble metal plating layer is formed thereon, and a second noble metal plating layer partially serving as an external terminal is provided on the other surface of the resin layer. A wiring member for a semiconductor device, wherein the wiring member is exposed from a surface. 2. The semiconductor according to claim 1, wherein a second metal plating layer having the same shape as the second noble metal plating layer is formed between the metal plating layer and the second noble metal plating layer. Wiring member for equipment.   In order from one surface side of the resin layer, an Au plating layer as the first noble metal plating layer, a Pd plating layer, the Ni plating layer as the metal plating layer and the second metal plating layer, the second plating layer The wiring member for a semiconductor device according to claim 1, wherein a Pd plating layer and an Au plating layer are formed as noble metal plating layers.   A resist mask having an opening of pattern A is formed on the metal plate, a first noble metal plating layer is formed in the opening of pattern A, and the first noble metal plating is formed on the first noble metal plating layer. After forming a metal plating layer with the same shape as the layer and peeling off the resist mask, a second resist mask having an opening of pattern B from which a part of the metal plating layer is exposed is formed. After the second noble metal plating layer or the second metal plating layer and the second noble metal plating layer are formed in the opening, and the second resist mask is peeled off, the metal plate and the metal plating layer in the first Forming a resin layer so as to expose the upper surface of the second noble metal plating layer on a portion where the noble metal plating layer is not formed, and removing the metal plate after forming the resin layer. A method for manufacturing a wiring member for a semiconductor device according to symptoms.

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