JP2016111494A - Multiple input integration circuit, multiple input δς modulator, and a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an error of a multiple input integration circuit.SOLUTION: A multiple input integration circuit (1) according to the present invention, comprises: a first switching circuit (10) that sequentially selects and outputs n pieces of input signals; and an integration circuit (11) that integrates the n pieces of input signals into a separation part by synchronizing integral capacities (CFAp, CFAn, CFBp, and CFBn) arranged corresponding to each of the n pieces of input signals with selection of an input signal by a first switch circuit and connecting to an input and an output of a computing amplifier (AMP). When the integral capacities connecting to the input and the output of the computing amplifier is switched, the integration circuit connects the input and the output of the computing amplifier without passing through the integral capacities, and thereafter, connects the integral capacities corresponding to the input signal selected by the first switch circuit to the input and the output of computing amplifier.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a multi-input integrating circuit that integrates a plurality of input signals, a multi-input delta-sigma (ΔΣ) modulator using the multi-input integrating circuit, and an A / D converter using the multi-input ΔΣ modulator. About.

Conventionally, a multi-input integration circuit that integrates a plurality of input signals is used in a multi-input ΔΣ modulator and a multi-input ΔΣ analog / digital converter (hereinafter referred to as “ΔΣ A / D converter”). ing. Conventionally, as a multi-input integration circuit, an integration circuit having a configuration in which an operational amplifier (OP amplifier) and a plurality of integration capacitors are provided for each input signal is widely known.
However, a multi-input integrating circuit having a plurality of operational amplifiers has a problem that the circuit area, power consumption, and cost increase. As a multi-input integrating circuit that solves this problem, for example, a multi-input integrating circuit that includes one operational amplifier and a plurality of integrating capacitors and selectively holds the integration results of a plurality of input signals in the integrating capacitors is known. (See Patent Document 1).

JP 2003-234638 A

  However, in the multi-input integration circuit disclosed in Patent Document 1, when one input signal is integrated, the amount of charge accumulated in the integration capacitor changes depending on the amount of charge of the other integration capacitor, so that the integration The inventor of the present application has found that the error may increase. Details will be described below.

  FIG. 11 is a diagram showing a configuration of a multi-input ΔΣ A / D converter using a multi-input integration circuit studied by the inventors of the present application prior to the present application. The multi-input ΔΣ A / D converter 8 shown in the figure is an integration circuit 81 for integrating two input signals separately, and an input for selectively supplying charges corresponding to the two input signals to the integration circuit 81. A circuit 80 and subtracters 84 and 85 are provided. The multi-input ΔΣ A / D converter 8 is, for example, a fully differential ΔΣ A / D converter circuit. The input circuit 80 and the integration circuit 81 including the subtractors 84 and 85 include a positive side and a negative side of the input signal. Circuits corresponding to are provided respectively.

  The multi-input ΔΣ A / D converter 8 alternately integrates the two input signals Vin_A and Vin_B in a time division manner, thereby A / D converting the input signals Vin_A and Vin_B in parallel. Specifically, by controlling on / off of each switch in accordance with the timing chart shown in FIG. 12, a pulse train having a density proportional to the input signal Vin_A and a pulse train having a density proportional to the input signal Vin_B are time-divisionally digitally filtered. The A / D conversion result of the input signal Vin_A and the A / D conversion result of the input signal Vin_B are output from the digital filter 86.

  FIG. 13 is a diagram showing experimental results of the multi-input ΔΣ A / D converter shown in FIG. This figure shows the experimental results when the voltage of the input signal Vin_B is changed and the voltage of the input signal Vin_A is changed in the multi-input ΔΣ A / D converter 8 shown in FIG. In the figure, the horizontal axis represents the voltage of the input signal Vin_A, and the vertical axis represents the error between the input signal Vin_B and the input converted voltage of the A / D conversion result of the input signal Vin_B.

  According to the experimental results shown in FIG. 13, in the multi-input ΔΣ A / D converter 8, the error of the A / D conversion result of the input signal Vin_B increases as the voltage of the input signal Vin_A increases. That is, when two input signals Vin_A and Vin_B are alternately integrated in a time division manner and A / D conversion of each input signal is performed, the A / D conversion result of one input signal is the magnitude of the other input signal. It will fluctuate depending on. In this multi-input integration circuit, the amount of charge flowing into one integration capacitor (for example, CFBp) is transferred to the other integration capacitor (for example, CFAp) due to charge injection or clock feedthrough that occurs when each switch is switched. This is due to a change in accordance with the amount of accumulated charge.

For example, as shown in FIGS. 14A and 14B, when the switch element S2Bp is turned off from the state where the switch element S2Bp is turned on, immediately after the switch element S2Bp is turned off (the integration capacitor CPBp is changed to the operational amplifier AMP). The voltage Vop at the output terminal of the operational amplifier AMP (immediately after being cut off from the output terminal) depends on the integration voltage of the integration capacitor CFBp (the voltage across the integration capacitor CFBp) due to the influence of parasitic capacitance and the like. Thereafter, as shown in FIG. 14C, when the switching element S2Ap is turned on and the integration capacitor CPAp is connected to the operational amplifier AMP, unintended charges are injected into the integration capacitor CPAp due to the occurrence of charge injection or clock feedthrough. The At this time, the amount of charge injected into the integration capacitor CPAp varies depending on the magnitude immediately before the output voltage Vop of the operational amplifier AMP. For this reason, the error of the A / D conversion result of the input signal Vin_A changes depending on the magnitude immediately before the output voltage Vop of the operational amplifier AMP, that is, the voltage value of the input signal Vin_B immediately before.
As described above, in the multi-input integration circuit disclosed in Patent Document 1, since the integration error fluctuates, when the multi-input integration circuit is applied to an A / D converter, the A / D conversion accuracy may deteriorate. .

In view of the above, an object of the present invention is to reduce errors in a multi-input integrating circuit.
Another object of the present invention is to improve A / D conversion accuracy by an A / D converter.

  The multi-input integrating circuit (1, 3) according to the present invention includes a first switch circuit (10, 20) for sequentially selecting and outputting n (n is an integer of 2 or more) input signals and n inputs. Integration capacitors (CFA, CFB, CFAp, CFAn, CFBp, CFBn) provided for each signal are input and output between operational amplifiers (AMP, AMPS) in synchronization with the selection of the input signal by the first switch circuit. To the integration circuit (11, 21) for individually integrating the n input signals, and the integration circuit switches the integration capacitor connected between the input and output of the operational amplifier. After connecting between the input and output of the operational amplifier without interposing, the integration capacitor corresponding to the input signal selected by the first switch circuit is connected between the input and output of the operational amplifier.

  In the multi-input integrating circuit (1), the first switch circuit (10) has positive side and negative side output terminals (N1P, N1N), and sequentially selects n input signals, thereby positive side and negative side. The integration circuit includes a fully differential operational amplifier (AMP) and a positive electrode connected between the positive output terminal of the first switch circuit and the inverting input terminal of the operational amplifier. Side switched capacitor circuit (110), a negative side switched capacitor circuit (111) connected between the negative side output terminal of the first switch circuit and the non-inverting input terminal of the operational amplifier, and n inputs N positive-side integration capacitors (CFAp, CFBp) provided corresponding to the signals, n negative-side integration capacitors (CFAn, CFBn) provided corresponding to the n input signals, n positive side integral capacitors The positive-side integration capacitance corresponding to the selected input signal is selected in synchronization with the first switch circuit, and the positive-side integration capacitance selected is the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier. The second switch circuit (112) on the positive electrode side connected between the negative electrode side and the negative electrode side integration capacitor corresponding to the input signal selected among the n negative electrode side integration capacitors in synchronization with the first switch circuit. A second switch circuit (113) on the negative electrode side that selects and connects the selected negative-side integral capacitance between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier, and the inverting input terminal of the operational amplifier Switch element (S9p) connected between the non-inverting output terminal of the operational amplifier and a negative-side switch connected between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier Element (S n), and the second switch circuit on the positive electrode side and the second switch circuit on the negative electrode side switch the integration capacitor on the positive electrode side when the integral capacitor to be selected is switched. A dead time period (Td) that is not connected between the output terminal and that does not connect the negative-side integration capacitor between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier; The positive-side switch element and the positive-side switch element are connected to the positive-side integral capacitance between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier by the second switch circuit on the positive side. The second switch circuit may be turned off during a period in which the negative-side integration capacitor is connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier, and may be turned on during the dead time period. Yes.

  The multi-input ΔΣ modulator (2) according to the present invention receives a reference signal selected based on a feedback signal from the signal output from the integration circuit (1) and the positive output terminal of the first switch circuit. A subtractor (14) on the positive electrode side for subtracting, and a subtracter (15) on the negative electrode side for subtracting the reference signal selected based on the feedback signal from the signal output from the output terminal on the negative electrode side of the first switch circuit. A quantizer (12) that quantizes the difference voltage between the signal output from the non-inverting output terminal of the integrating circuit and the signal output from the inverting output terminal of the integrating circuit, and the signal output from the quantizer And a feedback circuit (13) for generating a feedback signal based on the above.

  An A / D converter (3) according to the present invention includes the multi-input ΔΣ modulator (2) and a digital filter (16) for inputting a signal output from the quantizer. .

  In the above description, the reference numerals with parentheses merely exemplify what are included in the concept of the constituent elements with the reference numerals in the drawings.

  As described above, according to the present invention, errors in the multi-input integration circuit can be reduced. Further, according to the present invention, the A / D conversion accuracy by the A / D converter can be improved.

1 is a diagram showing a configuration of a multi-input integrating circuit according to Embodiment 1 of the present invention. FIG. 2 is a timing chart showing the operation of each switch element in the multi-input integrating circuit according to the first embodiment. FIG. 3A is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit. FIG. 3B is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit. FIG. 3C is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit. FIG. 4 is a diagram illustrating a configuration of an A / D converter including a multi-input ΔΣ modulator to which the multi-input integration circuit according to the first embodiment is applied. FIG. 5 is a diagram illustrating a circuit simulation result of the A / D converter according to the first embodiment. FIG. 6 is a diagram illustrating a configuration of an A / D converter including a multi-input ΔΣ modulator to which another multi-input integration circuit according to the first embodiment is applied. FIG. 7 is a diagram showing a configuration of a multi-input integrating circuit according to Embodiment 2 of the present invention. FIG. 8 is a timing chart showing the operation of each switch element in the multi-input integrating circuit according to the second embodiment. FIG. 9 is a diagram illustrating a configuration of an A / D converter including a multi-input ΔΣ modulator to which the multi-input integration circuit according to the second embodiment is applied. FIG. 10 is a diagram illustrating a configuration of an A / D converter including a multi-input ΔΣ modulator to which another multi-input integration circuit according to the second embodiment is applied. FIG. 11 is a diagram showing a configuration of a multi-input ΔΣ A / D converter using a multi-input integration circuit studied by the inventors of the present application prior to the present application. FIG. 12 is a timing chart showing the operation of each switch element in the multi-input ΔΣ A / D converter shown in FIG. FIG. 13 is a diagram showing experimental results of the multi-input ΔΣ A / D converter shown in FIG. FIG. 14A is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit shown in FIG. FIG. 14B is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit shown in FIG. FIG. 14C is a diagram for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit shown in FIG. 11.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
<Fully differential multi-input integration circuit>
FIG. 1 is a diagram showing a configuration of a multi-input integrating circuit according to an embodiment of the present invention.
The multi-input integration circuit 1 shown in FIG. 1 is a fully differential switched capacitor type integration circuit that sequentially integrates n (n is an integer of 2 or more) input signals in time division and outputs them. The multi-input integration circuit 1 enables integration for each input signal by switching a plurality of integration capacitors connected to one operational amplifier in time division for each input signal. The multi-input integrating circuit 1 connects (for example, short-circuits) the input and output of the operational amplifier without switching through the integrating capacitor when switching the integrating capacitor, so that the charge injection or clock generated when each switch is switched. It has a function of suppressing fluctuations in the amount of charge flowing into the integration capacitor by feedthrough. Hereinafter, a specific configuration of the multi-input integration circuit 1 will be described.

  In the present specification, a case where two (n = 2) input signals Vin_A and Vin_B are input to the multi-input integration circuit according to the present invention and a multi-input ΔΣ modulator described later will be described as an example. The number (n) of input signals is not particularly limited.

  As shown in FIG. 1, the multi-input integration circuit 1 includes an input switch circuit 10, an integration circuit 11, and a control signal generation unit 17.

The input switch circuit 10 sequentially selects and outputs a plurality of input signals. Specifically, the input switch circuit 10 includes an input signal Vin_A supplied between the positive input terminal PIAp and the negative input terminal PIAn, and the positive input terminal PIBp and the negative input terminal PIBn. The input signal Vin_B supplied between them is sequentially selected and output.
More specifically, the input switch circuit 10 includes switch elements S1Bp, S1Ap, S1An, and S1Bn. Switch element S1Bp has one end connected to input terminal PIBp and the other end connected to node N1p. The switch element S1Ap has one end connected to the input terminal PIP_A and the other end connected to the node N1p. The switch element S1Bn has one end connected to the input terminal PIP_A and the other end connected to the node N1n. The switch element S1An has one end connected to the input terminal PIN_A and the other end connected to the node N1n.

  The switch elements S1Bp, S1Ap, S1An, and S1Bn are analog switches, for example, and have a circuit configuration in which, for example, a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel. In the present embodiment, it is assumed that other switch elements used in the multi-input integrating circuit according to the present invention and the multi-input ΔΣ modulator described later are also analog switches.

  The integration circuit 11 integrates the signal output from the input switch circuit 10. Specifically, the integrating circuit 11 includes an operational amplifier AMP, a positive switched capacitor circuit 110, a negative switched capacitor circuit 111, a plurality of integrating capacitors CFAp, CFAn, CFBp, and CFBn, and switching circuits 112 and 113. The operational amplifier AMP is a fully differential OP amplifier.

  The switched capacitor circuit 110 is connected between the positive output terminal (node N1p) of the input switch circuit 10 and the inverting input terminal of the operational amplifier AMP. Specifically, the switched capacitor circuit 110 includes an input capacitor CINp and switch elements S3p, S4p, and S5p. The input capacitor CINp has one end connected to the node N1p and the other end connected to the node N2p. Switch element S3p has one end connected to node N1p and the other end connected to a ground node. Switch element S4p has one end connected to node N2p and the other end connected to a ground node. The switch element S5p has one end connected to the node N2p and the other end connected to the inverting input terminal of the operational amplifier AMP.

  The switched capacitor circuit 111 is connected between the negative output terminal (node N1n) of the input switch circuit 10 and the non-inverting input terminal of the operational amplifier AMP. Specifically, the switched capacitor circuit 111 includes an input capacitor CINn and switch elements S3n, S4n, and S5n. The input capacitor CINn has one end connected to the node N1n and the other end connected to the node N2n. Switch element S3n has one end connected to node N1n and the other end connected to a ground node. Switch element S4n has one end connected to node N2n and the other end connected to a ground node. The switch element S5n has one end connected to the node N2n and the other end connected to the inverting input terminal of the operational amplifier AMP.

  The integration capacitors CFAp, CFAn, CFBp, and CFBn are provided corresponding to the respective input signals. For example, the integration capacitors CFAp and CFAn are capacitors used when integrating the input signal Vin_A, and the integration capacitors CFBp and CFBn are capacitors used when integrating the input signal Vin_B. One end of each of the integration capacitors CFAp and CFBp is commonly connected to the inverting input terminal of the operational amplifier AMP. One end of each of the integration capacitors CFAn and CFBn is commonly connected to the non-inverting input terminal of the operational amplifier AMP.

  The switch circuits 112 and 113 function as a capacitance switching circuit for switching the integration capacitance. Specifically, the switch circuit 112 selects an integration capacitor corresponding to the input signal selected by the input switch circuit 10 among the plurality of integration capacitors CFAp and CFBp in synchronization with the input switch circuit 10, and this selected integration capacitor Is connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier AMP. In addition, the switch circuit 113 selects an integration capacitor corresponding to the input signal selected by the input switch circuit 10 among the plurality of integration capacitors CFAn and CFBn, and calculates the selected integration capacitor. The amplifier AMP is connected between the non-inverting input terminal and the inverting output terminal.

  More specifically, the switch circuit 112 has one end connected to the other end of the integration capacitor CFAp, the other end connected to the non-inverting output terminal of the operational amplifier AMP, and one end connected to the other end of the integration capacitor CFBp. And a switch element S2Bp having the other end connected to the non-inverting output terminal of the operational amplifier AMP. The switch circuit 113 has one end connected to the other end of the integration capacitor CFAn, the other end connected to the inverting output terminal of the operational amplifier AMP, and one end connected to the other end of the integration capacitor CFBn. A switching element S2Bn having the other end connected to the inverting output terminal of the operational amplifier AMP.

  The switch elements S9p and S9n are elements for connecting the input / output terminals of the operational amplifier AMP without using an integration capacitor. Specifically, the switch element S9p has one end connected to the inverting input terminal of the operational amplifier AMP and the other end connected to the non-inverting output terminal of the operational amplifier AMP. The switch element S9n has one end connected to the non-inverting input terminal of the operational amplifier AMP and the other end connected to the inverting output terminal of the operational amplifier AMP.

The control signal generator (CGEN) 17 generates control signals Φ1 to Φ3, ΦA, ΦB, Φ1A, and Φ1B for controlling on / off of each switch element in the multi-input integrating circuit 1 respectively. The control signals [Phi] 1- [Phi] 3, [Phi] A, [Phi] B, [Phi] 1A, [Phi] 1B are digital signals that switch between a high level and a low level at regular intervals, for example.
Specifically, the control signal Φ1 is used for on / off control of the switch elements S4p and S4n. The control signal Φ2 is used for on / off control of the switch elements S3p, S3n, S5p, S5n. The control signal Φ3 is used for on / off control of the switch elements S9p, S9n. The control signal ΦA is used for on / off control of the switch elements S2Ap and S2An. The control signal ΦB is used for on / off control of the switch elements S2Bp and S2Bn. The control signal Φ1A is used for on / off control of the switch elements S1Ap and S1An. The control signal Φ1B is used for on / off control of the switch elements S1Bp and S1Bn.
In FIG. 1, reference numerals representing control signals for controlling on / off of the switch elements are shown in parentheses following the reference numerals representing the respective switch elements.

Next, the operation of the multi-input integration circuit 1 will be described.
FIG. 2 is a timing chart showing the operation of each switch element in the multi-input integrating circuit 1. In the figure, each switch element is described as being on when the control signals Φ1 to Φ3, ΦA, ΦB, Φ1A, and Φ1B are at a high level, and off when the control signals are at a low level.

In the multi-input integrating circuit 1, in each phase (periods TA and TB) corresponding to the input signals Vin_A and Vin_B, on / off of each switch element is controlled as shown in FIG. 2, thereby the input signals Vin_A and Vin_B. Is integrated in a time-sharing manner.
Specifically, in the period TA, the input signal Vin_A is integrated and the integration result of the input signal Vin_A is held. That is, in the period TA, the control signals Φ1, Φ1A, and ΦA become high level during the period from time t1 to t2, so that the switch elements S4p, S4n, S1Ap, S1An, S2Ap, and S2An are turned on and the control is performed. When the signals Φ2, Φ1B, ΦB, and Φ3 become low level, the switch elements S3p, S3n, S5p, S5n, S1Bp, S1Bn, S2Bp, S2Bn, S9p, and S9n are turned off. Thereafter, in the period from time t2 to t3, the control signals Φ2 and ΦA become high level, so that the switches S3p, S3n, S5p, S5n, S2Ap, and S2An are turned on, and the control signals Φ1, Φ1A, Φ1B, When ΦB and Φ3 become low level, the switch elements S4p, S4n, S1Ap, S1An, S1Bp, S1Bn, S2Bp, S2Bn, S9p, and S9n are turned off. As a result, in the period TA, the input signal (voltage) Vin_A is integrated, and the integration result is output from the output terminal OUT. The integration result of the input voltage is held in the capacitors CFAp and CFAn from the time when the switches S2Ap and S2An are turned off to the next time they are turned on.

  In the period TB, the input signal Vin_B is integrated and the integration result of the input signal Vin_B is held. That is, in the period TB, the control signals Φ1, Φ1B, and ΦB become high level during the period from the time t4 to the time t5, so that the switch elements S4p, S4n, S1Bp, S1Bn, S2Bp, and S2Bn are turned on. When the signals Φ2, Φ1A, ΦA, and Φ3 become low level, the switch elements S3p, S3n, S5p, S5n, S1Ap, S1An, S2Ap, S2An, S9p, and S9n are turned off. Thereafter, during a period from time t5 to t6, the control signals Φ2 and ΦB become high level, so that the switches S3p, S3n, S5p, S5n, S2Bp, and S2Bn are turned on, and the control signals Φ1, Φ1A, Φ1B, When ΦA and Φ3 become low level, the switch elements S4p, S4n, S1Ap, S1An, S1Bp, S1Bn, S2Ap, S2An, S9p, and S9n are turned off. As a result, in the period TB, the input signal (voltage) Vin_B is integrated, and the integration result is output from the output terminal OUT. Further, the integration result of the input voltage is held in the capacitors CFBp and CFBn from the time when the switches S2Bp and S2Bn are turned off until the next time they are turned on.

  As shown in FIG. 2, in the multi-input integration circuit 1, the period TA for integrating the input signal Vin_A and the period TB for integrating the input signal Vin_B are alternately repeated with a dead time period Td interposed therebetween. The dead time period Td is a period in which the input signal is not integrated, and specifically, a period in which no integration capacitor is connected between the input and output of the operational amplifier AMP. More specifically, as shown in FIG. 2, during the dead time period Td, the positive-side integration capacitors CFAp and CFBp are not connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier AMP, and the negative electrode This is a period in which the integration capacitors CFAn and CFBn on the side are not connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier AMP.

  In the dead time period Td, the control signal Φ3 becomes high level. As a result, the switch elements S9p and S9n are turned on, and the input / output terminals of the operational amplifier AMP are short-circuited. As a result, the output voltage of the operational amplifier AMP at the timing immediately before the integration capacitors CFAp, CFAn (CFBp, CFBn) are connected to the operational amplifier AMP, that is, the timing immediately before the switch elements S2Ap, S2An (S2Bp, S2Bn) are turned on. Can be reset, and fluctuations in the amount of charge flowing into the integration capacitor when the switch element is switched can be suppressed. This principle will be described in more detail with reference to FIGS. 3 to 3C.

3A to 3C are diagrams for explaining the operation at the time of switching of the integration capacitance in the multi-input integration circuit according to the first embodiment.
3A to 3C show only functional units necessary for explaining the operation at the time of switching of the integration capacitance, and other functional units in the multi-input integration circuit 1 are not shown. .
Here, the operation at the time of switching between the integral capacitors CFAp and CFBp will be described taking the switch elements S9p, S2Bp, S2Ap and the integral capacitors CFAp, CFBp connected to the inverting input terminal side of the operational amplifier AMP as an example. The operation at the time of switching of the integration capacitors CFAn and CFBn connected to the non-inverting input terminal side of the AMP is the same, and detailed description thereof is omitted.

  FIG. 3A shows the state of each switch element immediately after the switch S2Ap is turned off (for example, immediately after time t3 in FIG. 2). As shown in the figure, when the switch S2Ap is turned off with the switches S2Bp and S9p being turned off (for example, immediately after time t3 in FIG. 2), the inverting input terminal and the non-inverting output terminal of the operational amplifier AMP are both Open (open) state. Therefore, the voltage Vop at the non-inverting output terminal is a value that depends on the charge amount (voltage) of the integration capacitor CFAp connected immediately before, that is, the voltage of the input signal Vin_A.

Thereafter, as shown in FIG. 3B, when the switch S9p is turned on (for example, the dead time period Td from time t3 to t4 in FIG. 2), the inverting input terminal and the non-inverting output terminal of the operational amplifier AMP are short-circuited. The non-inverting input terminal and the inverting output terminal of the AMP are short-circuited. The fully differential operational amplifier AMP operates so that the intermediate voltage between the voltage at the non-inverting output terminal and the voltage at the inverting output terminal is constant (common feedback operation). As a result, the operational amplifier AMP outputs a constant voltage from the non-inverting output terminal (positive side) and the inverting input terminal (negative side) regardless of the charge amount of the integration capacitor CFAp connected immediately before. As a result, as shown in FIG. 3C, immediately after the switch S9p is turned off and the switch S2Bp is turned on (for example, immediately after time t4 in FIG. 2), the intention to the connected integration capacitor CFBp is caused by charge injection or clock feedthrough. The charge injection amount is not affected by the charge amount of the integration capacitor CFAp connected in the immediately preceding phase (for example, the period TA from time t1 to t3 in FIG. 2). .
As a result, the multi-input integration circuit 1 can perform an integration operation with less error.

<Fully differential multi-input ΔΣ A / D converter>
Next, an A / D converter including a multi-input ΔΣ modulator to which the multi-input integration circuit 1 is applied will be described as an application example of the multi-input integration circuit 1 according to the first embodiment.
FIG. 4 is a diagram illustrating a configuration of an A / D converter including a multi-input ΔΣ modulator to which the multi-input integration circuit 1 according to the first embodiment is applied.
The A / D converter 3 shown in the figure is a fully differential switched capacitor type ΔΣ A / D conversion circuit that performs A / D conversion of a plurality of input signals in a time division manner. The A / D converter 3 can be applied to instrumentation equipment such as a temperature regulator, a flow rate regulator, and a pressure regulator, for example.

The A / D converter 3 includes a ΔΣ modulator 2 that outputs a plurality of input signals by performing ΔΣ modulation processing in a time division manner, and a digital filter circuit (DFLTR) 16. The A / D converter 3 includes a ΔΣ modulator 2 and a digital filter circuit (DFLTR) 16 which are manufactured by, for example, a known CMOS (Complementary Metal Oxide Semiconductor) manufacturing process or BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) manufacturing process. It is realized as a one-chip semiconductor device formed on a semiconductor substrate.
In the present embodiment, as in the case of the multi-input integration circuit 1 described above, a case where two input signals Vin_A and Vin_B are A / D converted in a time division manner will be described as an example. In the A / D converter 3, the same components as those in the multi-input integrating circuit 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

The ΔΣ modulator 2 includes an input switch circuit 10, an integration circuit 11, a quantizer (CMP) 12, a feedback circuit (FBC) 13, subtraction circuits 14 and 15, and a control signal generation unit 17.
The input switch circuit 10 and the integrating circuit 11 implement the multi-input integrating circuit 1 described above.

  The subtracters 14 and 15 are circuits that subtract the reference signal selected based on the feedback signal from the signal output from the input switch circuit 10. Specifically, the positive side subtractor 14 includes switch elements S8p, S8Xp, a switch S7p, and a capacitor CPFp. One end of the capacitor CPFp is connected to the node N2p. The other end of the capacitor CPFp is connected to the reference signal + Vref via the switch S8p, to the reference signal −Vref via the switch S8Xp, and to the ground node via the switch S7p. The switch elements S8p and S8Xp are controlled to be turned on / off in synchronization with the control signal Φ1. For example, the switch elements S8p and S8Xp are controlled to be turned on / off based on signals V (L) * Φ1 and V (H) * Φ1 output from a feedback circuit 13 described later. For example, the switch element S8p is turned off when the output signal V of the quantizer 12 is at a high level (H), and the control signal Φ1 when the output signal V of the quantizer 12 is at a low level (L). ON / OFF is controlled in synchronization with The switch element S8n is turned off when the output signal V of the quantizer 12 is at a low level, and is synchronized with the control signal Φ1 when the output signal V of the quantizer 12 is at a high level (H). ON / OFF is controlled. The switch S7p is controlled to be turned on / off based on the control signal Φ2.

The negative side subtractor 15 includes switch elements S8n and S8Xn, a switch S7n, and a capacitor CPFn. One end of the capacitor CPFn is connected to the node N2n. The other end of the capacitor CPFn is connected to the reference signal + Vref via the switch S8n, to the reference signal −Vref via the switch S8Xn, and to the ground node via the switch S7n. The switch elements S8n and S8Xn are controlled to be turned on / off by signals V (H) * Φ1 and V (L) * Φ1 output from the feedback circuit 13, respectively. For example, the switch element S8n is turned off when the output signal V of the quantizer 12 is at a low level (L), and the control signal Φ1 when the output signal V of the quantizer 12 is at a high level (H). ON / OFF is controlled in synchronization with The switch element S8Xn is turned off when the output signal V of the quantizer 12 is at a high level, and turned on in synchronization with the control signal Φ1 when the output signal V of the quantizer 12 is at a low level. Off is controlled. The switch S7n is turned on / off based on the control signal Φ2.
By configuring the subtractors 14 and 15 as described above, the input signals Vin_A and Vin_B are subtracted by the subtracters 14 and 15, and the subtracted signals are integrated by the integration circuit 11.

  The quantizer 12 quantizes the difference voltage between the output Vop signal at the non-inverting output terminal and the output signal Von at the inverting output terminal of the operational amplifier AMP in the integrating circuit 11 and outputs a high level (H) or low level (L). An output signal V is generated. For example, the quantizer 12 is composed of a comparator, and determines whether or not the voltage difference between the output signal Vop and the output signal Von of the differential amplifier circuit AMP exceeds a threshold value. The output signal V is set to the high level, and when the threshold value is not exceeded, the output signal V is set to the low level. In the following description, the case where the output signal V is at a high level is denoted as V (H), and the case where the output signal V is at a low level is denoted as V (L).

The feedback circuit 13 generates feedback signals V (L) * Φ1 and V (H) * Φ1 based on the signal output from the quantizer 12. Specifically, the feedback circuit 13 includes, for example, two delay circuits (DFF) 131 and 132 connected in series and a logic circuit (LGC) 133. The delay circuits 131 and 132 are D flip-flop circuits that operate using the inverted signal of the control signal Φ2 as a clock, and delay the output signal V of the quantizer 12 in accordance with the timing of integrating the input signals Vin_A and Vin_B. To the logic circuit 133. The logic circuit 133 is at a low level when the output signal V of the quantizer 12 is at a high level, and when the output signal V is at a low level, feedback in which the high level and the low level are switched in synchronization with the control signal Φ1. A signal V (L) * Φ1 is generated. Further, the logic circuit 133 is at a low level when the output signal V of the quantizer 12 is at a low level, and when the output signal V is at a high level, the logic circuit 133 has a high level and a low level in synchronization with the control signal Φ1. The switching feedback signal V (H) * Φ1 is generated.
By configuring the feedback circuit 13 as described above, the nth integration result of the input signal Vin_A (or Vin_B) is fed back at the (n + 1) th integration of the input signal Vin_A (or Vin_B).

  According to the ΔΣ modulator 2 described above, the multi-input integration circuit 1 integrates the input signals Vin_A and Vin_B in a time-sharing manner, and inputs the integration results to the quantizer 12 to obtain the amplitude of the input signal Vin_A. A pulse train having a proportional density (output signal V) and a pulse train having a density proportional to the amplitude of the input signal Vin_B (output signal V) are output in a time division manner.

  The digital filter circuit 16 separately performs filter processing (for example, low-pass filter processing) on each pulse train corresponding to the input signals Vin_A and Vin_B output from the ΔΣ modulator 2, and A / D converts the processing result. The results are output as DO_A and DO_B, respectively.

FIG. 5 shows a circuit simulation result of the A / D converter according to the first embodiment.
In FIG. 5, the horizontal axis represents the voltage [V] of the input signal Vin_A, and the vertical axis represents the change amount [mV] of the voltage of the integration capacitor CFBp. In the same figure, as a transient analysis result of the A / D converter 3 by the circuit simulator (SPICE), the voltage of the input signal Vin_B input to the A / D converter 3 is fixed, and the voltage of the input signal Vin_A is changed. The characteristic of the fluctuation amount of the voltage (voltage at both ends) of the integration capacitor CFBp at this time is shown.

  In FIG. 5, reference numeral 400 represents the voltage variation characteristic of the integration capacitor CFBp in the A / D converter 3 using the multi-input integration circuit (with switch elements S9p and S9n) according to the first embodiment. . Reference numeral 401 denotes a ΔΣ-type A / D converter using a multi-input integrating circuit (without switch elements S9p and S9n) according to the above-described prior study example shown in FIG. 11 as a comparative example of the A / D converter 3. The characteristics of the voltage fluctuation amount of the integration capacitor CFBp in the D converter are shown.

  As understood from the circuit simulation result shown in FIG. 5, in the A / D converter (see FIG. 11) using the multi-input integration circuit according to the prior study example, as described above, the integration (A / The voltage fluctuation amount of the integration capacitor CFBp changes depending on the magnitude of the input signal Vin_A that has been D-converted. On the other hand, in the A / D converter 3 using the multi-input integration circuit 1 according to the first embodiment, when switching the integration capacitance, the output voltage of the operational amplifier AMP is short-circuited between the input and output of the operational amplifier AMP. Therefore, even if unintended charge injection to the integration capacitor CFBp occurs, the charge injection amount becomes substantially constant regardless of the input signal Vin_A integrated immediately before. Thereby, in the A / D converter 3 using the multi-input integration circuit 1 according to the first embodiment, the integration result of the input signal does not depend on the magnitude of other input signals.

  As described above, according to the multi-input integration circuit according to the first embodiment, when switching the integration capacitor, the input and output of the operational amplifier AMP are short-circuited to reset the output voltage of the operational amplifier AMP. Even if charge injection occurs, the amount of charge injection becomes substantially constant, and integration errors for each input signal can be reduced.

  Further, according to the fully differential switched capacitor type ΔΣ A / D converter to which the multi-input integration circuit according to the first embodiment is applied, as described above, the integration error for each input signal is reduced by the multi-input integration circuit. Therefore, the conversion accuracy of A / D conversion can be improved.

  In the multi-input integration circuit 1 according to the first embodiment, the switched capacitor type integration circuit 11 is used as the integration circuit. However, a CR type integration circuit can also be used. For example, as shown in FIG. 6, resistors R1p and R1n are provided instead of the switched capacitor circuits 110 and 111, a switch element S7p of the subtractor circuit 14 and a resistor RFp are provided instead of the capacitor CPFp, and a switch element S7n of the subtractor circuit 15 is provided. The A / D converter 3A may be provided with a resistor RFn instead of the capacitor CPFn. According to this, similarly to the A / D converter 3 of FIG. 4 described above, the integration error for each input signal can be reduced by the multi-input integration circuit, so that the conversion accuracy of the A / D conversion is improved. be able to.

<< Embodiment 2 >>
<Single-ended multi-input integration circuit>
The multi-input integration circuit according to the second embodiment is different from the multi-input integration circuit 1 according to the first embodiment having a fully differential integration circuit in that it has a single-ended integration circuit. Is the same as that of the multi-input integrating circuit 1 according to the first embodiment.
FIG. 7 shows the configuration of the multi-input integrating circuit according to the second embodiment. In the figure, the same components as those in the multi-input integrating circuit 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 7, the multi-input integration circuit 4 includes an input switch circuit 20, an integration circuit 21, and a control signal generation unit 17.
The input switch circuit 20 includes switch elements S1A and S1B. The switch element S1B has one end connected to the input terminal PIA and the other end connected to the node N1. Switch element S1A has one end connected to input terminal PIB and the other end connected to node N1.

  The integration circuit 21 integrates the signal output from the input switch circuit 20. Specifically, the integration circuit 21 includes an operational amplifier AMPS, a switched capacitor circuit 210, a plurality of integration capacitors CFA and CFB, a switch circuit 212, and a switch element S9. The operational amplifier AMPS is a single-ended OP amplifier. The non-inverting input terminal of the operational amplifier AMPS is connected to the ground node.

  The switched capacitor circuit 210 is connected between the output terminal (node N1) of the input switch circuit 20 and the inverting input terminal of the operational amplifier AMPS. Specifically, the switched capacitor circuit 210 includes an input capacitor CIN and switch elements S3, S4, and S5. The input capacitor CIN has one end connected to the node N1 and the other end connected to the node N2. Switch element S3 has one end connected to node N1 and the other end connected to a ground node. Switch element S4 has one end connected to node N2 and the other end connected to a ground node. The switch element S5 has one end connected to the node N2 and the other end connected to the inverting input terminal of the operational amplifier AMPS.

  The integration capacitors CFA and CFB are provided corresponding to the respective input signals. For example, the integration capacitor CFA is a capacitor used when integrating the input signal Vin_A, and the integration capacitor CFB is a capacitor used when integrating the input signal Vin_B. One end of each of the integration capacitors CFA and CFB is commonly connected to the inverting input terminal of the operational amplifier AMPS.

  The switch circuit 212 selects the integration capacitor corresponding to the input signal selected by the input switch circuit 20 among the plurality of integration capacitors CFA and CFB in synchronization with the input switch circuit 20 in the same manner as the switch circuits 112 and 113 described above. Then, the selected integration capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier AMPS. Specifically, the switch circuit 212 has one end connected to the other end of the integration capacitor CFA, the other end connected to the output terminal of the operational amplifier AMPS, and one end connected to the other end of the integration capacitor CFB. And a switching element S2B having the other end connected to the output terminal of the operational amplifier AMPS.

  The switch element S9 is an element for connecting the input / output terminals of the operational amplifier AMPS without going through the integration capacitor, similarly to the switch elements S9p and S9n described above. Specifically, the switch element S9 has one end connected to the inverting input terminal of the operational amplifier AMPS and the other end connected to the output terminal of the operational amplifier AMPS.

Next, the operation of the multi-input integration circuit 4 will be described.
FIG. 8 is a timing chart showing the operation of each switch element in the multi-input integrating circuit 4.
In the multi-input integrating circuit 4, as in the multi-input integrating circuit 1 according to the first embodiment, in each phase (period TA, TB) corresponding to the input signals Vin_A and Vin_B, as shown in FIG. By controlling on / off, the input signals Vin_A and Vin_B are integrated in a time-sharing manner.

  Specifically, in the period TA, the input signal Vin_A is integrated and the integration result of the input signal Vin_A is held. That is, in the period TA, the control signals Φ1, Φ1A, and ΦA become high level during the period from time t1 to t2, so that the switch elements S4, S1A, and S2A are turned on, and the control signals Φ2, Φ1B, ΦB , And Φ3 become low level, the switch elements S3, S5, S1B, S2B, and S9 are turned off. Thereafter, during the period from time t2 to t3, the control signals Φ2, and ΦA become high level, so that the switches S3, S5, and S2A are turned on, and the control signals Φ1, Φ1A, Φ1B, ΦB, and Φ3 are at low level. As a result, the switch elements S4, S1A, S2B, S1B, and S9 are turned off. As a result, in the period TA, the input signal (voltage) Vin_A is integrated, and the integration result is output as the output signal Vo. The integration result of the input voltage Vin_A is held in the capacitor CFA from when the switch S2A is turned off to when it is next turned on.

  In the period TB, the input signal Vin_B is integrated and the integration result of the input signal Vin_B is held. That is, in the period TB, the control signals Φ1, Φ1B, and ΦB become high level during the period from time t4 to t5, so that the switch elements S4, S1B, and S2B are turned on, and the control signals Φ2, Φ1A, ΦA , And Φ3 become low level, the switch elements S3, S5, S1A, S2A, and S9 are turned off. Thereafter, during the period from time t5 to t6, the control signals Φ2, and ΦB become high level, so that the switches S3, S5, and S2B are turned on, and the control signals Φ1, Φ1A, Φ1B, ΦA, and Φ3 are at low level. As a result, the switch elements S4, S1A, S1B, and S2A are turned off. As a result, in the period TB, the input signal (voltage) Vin_B is integrated, and the integration result is output as the output signal Vo. Further, the integration result of the input voltage Vin_B is held in the capacitor CFB from the time when the switch S2B is turned off until the time when the switch S2B is turned on.

As shown in FIG. 8, in the multi-input integrating circuit 2, as in the multi-input integrating circuit 1 according to the first embodiment, the period TA for integrating the input signal Vin_A and the period TB for integrating the input signal Vin_B are dead. Repeated alternately with the time period Td interposed therebetween. In the dead time period Td, when the control signal Φ3 becomes high level, the switch element S9 is turned on, and the input / output terminals of the operational amplifier AMPS are short-circuited. As a result, similarly to the multi-input integration circuit 1 according to the first embodiment, even if the charge flows into the integration capacitor due to charge injection or clock feedthrough when the switching elements S2A and S2B are switched, It is not affected by the charge amounts of the integration capacitors CFA and CFB connected in the immediately preceding phase (for example, the period TA from time t1 to t3 in FIG. 8).
As a result, the multi-input integration circuit 4 can perform an integration operation with less error.

<Single-ended multi-input ΔΣ A / D converter>
Next, as an application example of the multi-input integration circuit 4 according to the second embodiment, an A / D converter to which a multi-input ΔΣ modulator including the multi-input integration circuit 4 is applied will be described.
FIG. 9 is a diagram illustrating a configuration of an A / D converter to which a multi-input ΔΣ modulator including the multi-input integration circuit 4 according to the second embodiment is applied.
The A / D converter 6 shown in the figure is a single-ended switched capacitor type ΔΣ A / D conversion circuit that performs A / D conversion on a plurality of input signals in a time-sharing manner. The A / D converter 6 includes a delta-sigma modulator 5 that performs delta-sigma modulation processing on a plurality of input signals in a time-sharing manner, and a digital filter circuit (DFLTR) 16. In the A / D converter 6, like the A / D converter 3, the ΔΣ modulator 5 and the digital filter circuit 16 are formed on one semiconductor substrate by, for example, a known CMOS manufacturing process or BiCMOS manufacturing process. It is realized as a one-chip semiconductor device.
In the A / D converter 6, the same components as those in the A / D converter 3 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The ΔΣ modulator 5 includes an input switch circuit 20, an integration circuit 21, a quantizer (CMP) 22, a feedback circuit 13, a subtraction circuit 24, and a control signal generation unit 17.
The input switch circuit 20 and the integration circuit 21 implement the multi-input integration circuit 4 described above.

The subtracter 24 is a circuit that subtracts the reference signal selected based on the feedback signal from the signal output from the input switch circuit 20. The subtractor 24 includes switch elements S8 and S8X, a switch S7, and a capacitor CPF, similarly to the subtracters 14 and 15 described above. One end of the capacitor CPF is connected to the node N2. The other end of the capacitor CPF is connected to the reference signal + Vref via the switch S8, to the reference signal −Vref via the switch S8X, and to the ground node via the switch S7. The switch element S8X is turned off when the output signal V of the quantizer 22 is at a high level (H), and is synchronized with the control signal Φ1 when the output signal V of the quantizer 22 is at a low level (L). Thus, on / off is controlled. The switch element S8X is turned off when the output signal V of the quantizer 22 is at a low level, and is synchronized with the control signal Φ1 when the output signal V of the quantizer 22 is at a high level (H). ON / OFF is controlled. The switch S7 is controlled to be turned on / off based on the control signal Φ2.
By configuring the subtractor 24 as described above, the input signals Vin_A and Vin_B are subtracted by the subtractor 24, and the subtracted signal is integrated by the integration circuit 21.

  The quantizer 22 quantizes the output signal Vo of the operational amplifier AMPS in the integration circuit 21, and generates a high level (H) or low level (L) output signal V. For example, like the quantizer 12, the quantizer 22 is composed of a comparator, and determines whether or not the output signal Vo of the differential amplifier circuit AMPS exceeds a threshold, and exceeds the threshold. The output signal V is set to the high level at the same time, and when the threshold value is not exceeded, the output signal V is set to the low level.

  According to the ΔΣ modulator 5 described above, similarly to the ΔΣ modulator 2 according to the first embodiment, a pulse train having a density proportional to the amplitude of the input signal Vin_A (output signal V) and proportional to the amplitude of the input signal Vin_B. A pulse train of density (output signal V) is output from the quantizer 22 in a time division manner. By inputting these pulse trains to the digital filter circuit 16, an A / D conversion result DO_A of the input signal Vin_A and an A / D conversion result DO_B of the input signal Vin_B are generated.

  As described above, according to the multi-input integrating circuit according to the second embodiment, as in the multi-input integrating circuit 1 according to the first embodiment, when switching the integration capacitor, the input and output of the operational amplifier AMPS are short-circuited. Since the output voltage of the amplifier AMPS is reset, even if unintended charge injection to the integration capacitor occurs, the amount of charge injection becomes substantially constant, and the integration error for each input signal can be reduced.

  In addition, according to the single-ended switched capacitor type ΔΣ A / D converter to which the multi-input integration circuit according to the second embodiment is applied, an integration error for each input signal can be reduced by the multi-input integration circuit. Therefore, the conversion accuracy of A / D conversion can be improved.

  In the multi-input integrating circuit 4 according to the second embodiment, the switched capacitor type integrating circuit 21 is used as the integrating circuit, but a CR type integrating circuit may be used. For example, as shown in FIG. 10, an A / D converter 6A may be provided in which a resistor R1 is provided in place of the switched capacitor circuit 210 and a switch RF is provided in place of the switch element S7 and the capacitor CPF of the subtraction circuit 24. According to this, similarly to the A / D converter 6 of FIG. 10 described above, the integration error for each input signal can be reduced by the multi-input integration circuit, so that the conversion accuracy of the A / D conversion is improved. be able to.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the above-described embodiment, a multi-input integration circuit that integrates two input signals Vin_A and Vin_B in a time division manner is illustrated, but the present invention is not limited to this, and a multi-input integration that integrates three or more input signals in a time division manner. It may be a circuit. Also in this case, as in the above embodiment, the order in which the input signals are integrated, that is, the order in which the integration capacitors are connected between the input and output of the operational amplifier is not particularly limited, and the integration connected between the input and output of the operational amplifier is not limited. When switching the capacitance, a dead time period in which no integration capacitor is connected may be provided, and the input and output may be connected via a switch or the like during the dead time period.

  In the multi-input integration circuit according to the present invention, the arrangement of the integration capacitor and the switch element connected in series between the input and output of the operational amplifier may be switched. For example, in the multi-input integration circuit 1 shown in FIG. 1, the switch element S2Ap may be connected to the non-inverting input terminal side, and the integration capacitor CFAp may be connected to the output terminal side.

  In the above-described embodiment, the configuration in which the input and output of the operational amplifier are short-circuited by the switch element (S9p or the like) during the dead time period is illustrated, but other configurations may be used as long as the output voltage of the operational amplifier can be reset. . For example, a resistor may be inserted in series with a switch element (such as S9p) that is turned on during the dead time period.

  In addition, the control signal generation unit 17 may be formed inside the multi-input integration circuits 1 and 4 as in the above embodiment, or may be formed outside the multi-input integration circuits 1 and 4.

  In the above embodiment, the A / D converter including the multi-input integration circuit according to the present invention is formed on one semiconductor chip. However, a part of each component is formed on a separate semiconductor chip. It may be formed.

  DESCRIPTION OF SYMBOLS 1, 4 ... Multi-input integration circuit 2, 2, 2A, 5, 5A ... Multi-input delta-sigma modulator, 3, 6, 6A ... A / D converter, 10, 20 ... Input switch circuit, 11, 11A, 21, 21A ... Integral circuit, 110, 111, 210 ... Switched capacitor circuit, 112, 113, 212 ... Switch circuit 12, 22 ... Quantizer, 13 ... Feedback circuit, 14, 14A, 15, 15A, 24 ... Subtractor, 17 ... Control signal generator, AMP, AMPS ... operational amplifier, CFAp, CFAn, CFA, CFB ... integration capacitance, S1Ap, S1An, S2Ap, S2An, S1Bp, S1Bn, S2Bp, S2Bn, S3p, S3n to S9p, S9n, S1A, S2A , S1B, S2B, S3 to S9 ... switch elements, Vin_A, Vin_B ... input signals (analog signals), Vop, Von, Vo: operational amplifier output signal (output voltage), DO_A, DO_B: A / D conversion result (digital signal).

Claims (9)

a first switch circuit that sequentially selects and outputs n (n is an integer of 2 or more) input signals;
An integration capacitor provided corresponding to each of the n input signals is connected between the input and output of the operational amplifier in synchronization with the selection of the input signal by the first switch circuit. An integrating circuit for integrating the signals separately,
The integration circuit is selected by the first switch circuit after switching between the input and output of the operational amplifier without passing through the integration capacitor when switching the integration capacitor connected between the input and output of the operational amplifier. The multi-input integration circuit, wherein the integration capacitor corresponding to the input signal is connected between the input and output of the operational amplifier. The first switch circuit has positive and negative output terminals, sequentially selects the n input signals, and outputs from between the positive and negative output terminals,
The integration circuit includes:
A fully differential operational amplifier;
A positive switched capacitor circuit connected between a positive output terminal of the first switch circuit and an inverting input terminal of the operational amplifier;
A negative switched capacitor circuit connected between a negative output terminal of the first switch circuit and a non-inverting input terminal of the operational amplifier;
N positive-side integration capacitors provided corresponding to the n input signals;
N negative-side integration capacitors provided corresponding to the n input signals;
A positive side integration capacitor corresponding to the selected input signal is selected in synchronization with the first switch circuit among the n positive side integration capacitors, and the selected positive side integration capacitor is selected as the operational amplifier. A second switch circuit on the positive electrode side connected between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;
Of the n negative side integration capacitors, a negative side integration capacitor corresponding to the selected input signal is selected in synchronization with the first switch circuit, and the selected negative side integration capacitor is selected as the operational amplifier. A second switch circuit on the negative electrode side connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier;
A positive-side switch element connected between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;
A negative-side switch element connected between an inverting input terminal of the operational amplifier and a non-inverting output terminal of the operational amplifier,
The positive-side second switch circuit and the negative-side second switch circuit switch the positive-side integration capacitance between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier when switching the integration capacitance to be selected. And a dead time period in which the negative-side integration capacitor is not connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier,
In the positive switch element and the positive switch element, the positive-side second switching circuit causes the positive-side integral capacitance to be between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier. And is turned off during a period in which the negative-side integration capacitor is connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier by the negative-side second switch circuit, Multi-input integrator circuit that is turned on during the dead time period. The multi-input integration circuit according to claim 1,
The first switch circuit has positive and negative output terminals, sequentially selects the n input signals, and outputs from between the positive and negative output terminals,
The integration circuit includes:
A fully differential operational amplifier;
A positive-side resistor connected between a positive-side output terminal of the first switch circuit and an inverting input terminal of the operational amplifier;
A negative-side resistor connected between a negative-side output terminal of the first switch circuit and a non-inverting input terminal of the operational amplifier;
N positive-side integration capacitors provided corresponding to the n input signals;
N negative-side integration capacitors provided corresponding to the n input signals;
A positive side integration capacitor corresponding to the selected input signal is selected in synchronization with the first switch circuit among the n positive side integration capacitors, and the selected positive side integration capacitor is selected as the operational amplifier. A second switch circuit on the positive electrode side connected between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;
Of the n negative side integration capacitors, a negative side integration capacitor corresponding to the selected input signal is selected in synchronization with the first switch circuit, and the selected negative side integration capacitor is selected as the operational amplifier. A second switch circuit on the negative electrode side connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier;
A positive-side switch element connected between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;
A negative-side switch element connected between an inverting input terminal of the operational amplifier and a non-inverting output terminal of the operational amplifier,
The positive-side second switch circuit and the negative-side second switch circuit switch the positive-side integration capacitance between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier when switching the integration capacitance to be selected. And a dead time period in which the negative-side integration capacitor is not connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier,
In the positive switch element and the positive switch element, the positive-side second switching circuit causes the positive-side integral capacitance to be between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier. And is turned off during a period in which the negative-side integration capacitor is connected between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier by the negative-side second switch circuit, Multi-input integrator circuit that is turned on during the dead time period. A multi-input integrating circuit according to claim 2 or 3,
A positive-side subtractor that subtracts a reference signal selected based on a feedback signal from a signal output from a positive-side output terminal of the first switch circuit;
A negative-side subtractor that subtracts a reference signal selected based on the feedback signal from a signal output from a negative-side output terminal of the first switch circuit;
A quantizer that quantizes a difference voltage between a signal output from the non-inverting output terminal of the integrating circuit and a signal output from the inverting output terminal of the integrating circuit;
A multi-input ΔΣ modulator, comprising: a feedback circuit that generates the feedback signal based on a signal output from the quantizer. A multi-input ΔΣ modulator according to claim 4;
A digital filter for inputting a signal output from the quantizer;
An A / D converter characterized by comprising: The multi-input integration circuit according to claim 1,
The integration circuit includes:
An operational amplifier with a non-inverting input terminal connected to a fixed potential;
A switched capacitor circuit connected between an output terminal of the first switch circuit and an inverting input terminal of the operational amplifier;
N integration capacitors provided corresponding to the n input signals;
An integration capacitor corresponding to the selected input signal is selected from the n integration capacitors in synchronization with the first switch circuit, and the selected integration capacitor is selected between the inverting input terminal of the operational amplifier and the operational amplifier. A second switch circuit connected to the output terminal;
A switching element connected between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier,
The second switch circuit has a dead time period in which no integral capacitor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier when switching the integral capacitor to be selected.
The switch element is turned off during the period in which the integration capacitor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier by the second switch circuit, and is turned on during the dead time period. A characteristic multi-input integration circuit. The multi-input integration circuit according to claim 1,
The integration circuit includes:
An operational amplifier with a non-inverting input terminal connected to a fixed potential;
A resistor connected between an output terminal of the first switch circuit and an inverting input terminal of the operational amplifier;
N integration capacitors provided corresponding to the n input signals;
An integration capacitor corresponding to the selected input signal is selected from the n integration capacitors in synchronization with the first switch circuit, and the selected integration capacitor is selected between the inverting input terminal of the operational amplifier and the operational amplifier. A second switch circuit connected to the output terminal;
A switching element connected between an inverting input terminal of the operational amplifier and an output terminal of the operational amplifier,
The second switch circuit has a dead time period in which no integral capacitor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier when switching the integral capacitor to be selected.
The switch element is turned off during the period in which the integration capacitor is connected between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier by the second switch circuit, and is turned on during the dead time period. A characteristic multi-input integration circuit. A multi-input integrating circuit according to claim 6 or 7,
A subtractor for subtracting a reference signal selected based on a feedback signal from a signal output from the first switch circuit;
A quantizer that quantizes the signal output from the integrating circuit;
A multi-input ΔΣ modulator, comprising: a feedback circuit that generates the feedback signal based on a signal output from the quantizer. A multi-input ΔΣ modulator according to claim 8;
A digital filter for inputting a signal output from the quantizer;
An A / D converter characterized by comprising:

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