JP2016111301A - Wiring board and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress thinning of a pattern.SOLUTION: A manufacturing method of a wiring board includes: a step for forming a wiring layer 24 having a first pattern 26a and a second pattern 26b whose line width is narrower than that of the first pattern 26a on an insulating layer 10a; a step for sticking a metal 32 to the surface of the wiring layer 24 so that a concentration of the metal 32 whose standard potential is higher than that of a material of the wiring layer 24 on the surface of the wiring layer 24 in the first pattern 26a is lower than a concentration of the metal 32 on the surface of the wiring layer 24 in the second pattern 26b; and a step for roughening the surface of the wiring layer 24 after the step for sticking the metal 32.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a wiring board and a manufacturing method thereof, for example, a board whose surface of wiring is roughened and a manufacturing method thereof.

  A circuit board having wiring or a wiring board such as a package is used for electronic devices. It is known to roughen the wiring surface (for example, Patent Documents 1 and 2). It is known that a region having a relatively small unevenness and a region having a relatively large unevenness are formed on the surface of the wiring (for example, Patent Document 1).

JP 2008-252016 A JP 2011-14644 A

  Wirings having different line widths are formed on the wiring board. When the surface of a wiring having patterns with different line widths is roughened, the pattern of the wiring with a small line width becomes thin. In some cases, the pattern disappears.

  An object of the present wiring board and the manufacturing method thereof is to suppress the wiring pattern from becoming thin.

  Forming a wiring layer having a first pattern and a second pattern having a line width smaller than that of the first pattern on the insulating layer; and a material standard of the wiring layer on the surface of the wiring layer of the first pattern. After the step of attaching the metal to the surface of the wiring layer and the step of attaching the metal so that the concentration of the high potential metal is lower than the concentration of the metal on the surface of the wiring layer of the second pattern And a step of roughening the surface of the wiring layer.

  An insulating layer; and a wiring layer that is formed on the insulating layer and includes a first pattern and a second pattern having a line width smaller than a line width of the first pattern. The concentration of the metal having a higher standard potential than the material of the wiring layer on the surface of the wiring layer is lower than the concentration of the metal in the wiring layer of the second pattern, and the surface of the wiring layer of the first pattern is the surface of the wiring layer. A wiring board characterized by being rougher than the surface of the two wiring layers is used.

  According to the present wiring board and the manufacturing method thereof, it is possible to suppress the wiring pattern from becoming thin.

FIG. 1 is a cross-sectional view illustrating a semiconductor device in which the wiring board according to the first embodiment is used. FIG. 2 is an enlarged view of the wiring board according to the first comparative example. FIGS. 3A and 3B are cross-sectional views illustrating a method for manufacturing a wiring board according to Comparative Example 2. FIGS. 4A and 4B are cross-sectional views of the wirings of the patterns 26a and 26b, respectively. FIG. 5A to FIG. 5D are cross-sectional views (part 1) illustrating the method for manufacturing the wiring board according to the first embodiment. 6A to 6C are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the first embodiment. FIG. 7A and FIG. 7B are a plan view and a cross-sectional view showing patterns used in the experiment. FIG. 8A is a diagram showing the surface roughness of the surface of the wiring layer before and after the roughening treatment, and FIG. 8B is a diagram showing the palladium concentration and the surface roughness after the roughening treatment. FIG. 9 is a diagram showing the palladium concentration and surface roughness after the roughening treatment depending on the presence or absence of the underlayer during the roughening treatment.

  Embodiments will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view illustrating a semiconductor device in which the wiring board according to the first embodiment is used. As shown in FIG. 1, the wiring substrate 20 is used as an interposer that electrically connects the substrate 40 and the semiconductor chip 46, for example. A semiconductor chip 46 is mounted on the substrate 40 via the wiring substrate 20. The substrate 40 is an insulating substrate such as a resin substrate or a ceramic substrate. A land 42 is formed on the substrate 40. The land 42 is a metal layer such as a copper layer. The wiring board 20 is mounted on the land 42 via bumps 44. The bump 44 is, for example, a solder bump. A semiconductor chip 46 is mounted on the wiring board 20 via bumps 48. The bump 48 is, for example, a solder bump or a copper pillar. The semiconductor chip 46 is a chip on which, for example, an LSI (Large Scale Integrated Circuit) is formed.

  The wiring board 20 includes a plurality of insulating layers 10a and 10b. The insulating layers 10a and 10b are, for example, an epoxy resin layer or a polyimide resin layer. Wirings 12a and 12b are formed on the top surfaces of the insulating layer 10a and the insulating layer 10b, respectively. A wiring 12c is formed on the lower surface of the insulating layer 10a. The wirings 12a to 12c are metal layers such as a copper layer, for example. The wirings 12a and 12c include lands. A bump 44 is bonded to the land of the wiring 12c, and a bump 48 is bonded to the land of the wiring 12b. The through electrode 14a penetrates the insulating layer 10a and electrically connects the wirings 12a and 12c. The through electrode 14b penetrates the insulating layer 10b and electrically connects the wirings 12a and 12b.

  As shown in FIG. 1, the wiring board 20 can be used for rewiring to connect the board 40 and the semiconductor chip 46. Further, by using the wiring board 20 as an interposer for electrically connecting the semiconductor chips 46, a 2.5D integrated circuit can be realized. The wiring board 20 may be other than an interposer. As an example of the wiring board 20, an example in which the insulating layers 10 a and 10 b are two layers and the wirings 12 a to 12 c are three layers has been described, but the insulating layer and the wiring layer may be one or more each.

  FIG. 2 is an enlarged view of the wiring board according to the first comparative example. FIG. 2 is an enlarged view of the vicinity of the wiring 12a. As shown in FIG. 2, the wiring 12 a includes a base layer 22 formed on the insulating layer 10 a and a wiring layer 24 formed on the base layer 22. The wiring 12a includes a pattern 26a having a large line width and a pattern 26b having a small line width. Other configurations are the same as those in FIG. Adhesion at the interface 30 between the wiring layer 24 such as a copper layer and the insulating layer 10b is weak. In particular, in the pattern 26a having a large line width, the insulating layer 10b may be peeled off from the wiring 12a.

  FIGS. 3A and 3B are cross-sectional views illustrating a method for manufacturing a wiring board according to Comparative Example 2. FIGS. As shown in FIG. 3A, a wiring layer 24 including a pattern 26a having a large line width and a pattern 26b having a small line width is formed. As shown in FIG. 3B, the recess 28 is formed on the surface of the wiring layer 24 by etching the surface of the wiring layer 24. Thereby, the surface of the wiring layer 24 is roughened.

  4A and 4B are cross-sectional views of the wirings of the patterns 26a and 26b, respectively. As shown in FIG. 4A, the recesses 28 are formed on the surface of the wiring layer 24, thereby forming irregularities. Thereby, the adhesion between the wiring layer 24 and the insulating layer 10b is improved by the anchor effect. Therefore, it can suppress that the insulating layer 10b peels from the wiring layer 24. FIG.

  As shown in FIG. 4B, in the pattern 26b, when the line width of the wiring 12a cannot be ignored with respect to the recess 28 on the surface of the wiring layer 24, the line width of the wiring 12a becomes smaller. For example, with the high integration of LSI, it is required to reduce the line width of the wiring 12a of the wiring board 20. When the size of the concave portion 28 is about 1 μm, the influence of the concave portion 28 cannot be ignored if the line width of the wiring 12a is 3 μm or less.

  Further, the grain size of the wiring layer 24 having the pattern 26b having a small line width is smaller than that of the wiring layer 24 having the pattern 26a having a large line width. For this reason, at the time of roughening, the reaction potential of the wiring layer 24 of the pattern 26b increases, and the etching rate of the wiring layer 24 increases. For this reason, the concave portion 28 of the wiring layer 24 in the pattern 26b tends to be larger than the pattern 26a. For this reason, the pattern 26b may disappear as in the region 29 in FIG.

  In Example 1, as in Comparative Example 2, the line width of the pattern 26b is suppressed from being reduced.

  FIG. 5A to FIG. 6C are cross-sectional views illustrating a method for manufacturing a wiring board according to the first embodiment. An example in which the wiring 12a is formed using a semi-additive process method will be described. As shown in FIG. 5A, the base layer 22 is formed on the insulating layer 10a having the through electrodes 14a. The insulating layer 10a is, for example, an epoxy resin, and the thickness of the insulating layer 10a is, for example, several hundred nm to several tens of μm. The underlayer 22 is, for example, titanium, and the film thickness is, for example, several tens of nm. A seed layer such as a copper layer is formed on the base layer 22. The underlayer 22 is an adhesion layer between the wiring 12a and the insulating layer 10a. The underlayer 22 is formed using, for example, a sputtering method.

  As shown in FIG. 5B, a mask layer 50 having openings 52 a and 52 b is formed on the base layer 22. The mask layer 50 is, for example, a photoresist, and the thickness of the mask layer 50 is, for example, 1 μm to several tens of μm. The line width of the opening 52a is larger than the line width of the opening 52b. A wiring layer 24 is formed in the openings 52a and 52b using a plating method. The wiring layer 24 is a copper layer, for example, and the film thickness of the wiring layer 24 is, for example, several hundred nm to several tens of μm.

  As shown in FIG. 5C, the mask layer 50 is removed. As a result, the wiring layer 24 having the pattern 26 a having a large line width and the pattern 26 b having a small line width is formed on the base layer 22.

As shown in FIG. 5D, the metal 32 is deposited on the surface of the wiring layer 24 by immersing the wiring layer 24 in a solution containing metal ions. The metal 32 is an electrochemically noble metal than the material of the wiring layer 24. That is, the metal 32 is a metal having a higher standard potential than the material of the wiring layer 24. The metal 32 is deposited by a substitution reaction due to corrosion of the wiring layer 24. For example, when the wiring layer 24 is a copper layer and the metal 32 is paradigm, the reaction of the following reaction formula is performed.
Cu + Pd ²⁺ → Cu ²⁺ + Pd
Since the wiring layer 24 having a small line width is easily corroded, it is likely to be deposited on the metal 32. Therefore, more metal 32 is deposited on the surface of the wiring layer 24 of the pattern 26b than in the pattern 26a. As the solution containing metal ions, for example, an acidic solution containing metal ions can be used.

The standard potential of each metal is shown below.
Copper 0.340V
Mercury 0.796V
Silver 0.799V
Palladium 0.915V
Iridium 1.156V
Platinum 1.188V
Gold 1.52V
From the above, when the material of the wiring layer 24 is copper, the metal 32 is preferably at least one of mercury, silver, palladium, iridium, platinum and gold.

  As shown in FIG. 6A, the surface of the wiring layer 24 is roughened. For example, a solution containing sulfuric acid and hydrogen peroxide is used as the etchant for the wiring layer 24 for the roughening treatment. A metal 32 having a higher standard potential than the pattern 26a is deposited on the pattern 26b. For this reason, the potential of the wiring layer 24 of the pattern 26b is lower than that of the pattern 26a. Therefore, the wiring layer 24 of the pattern 26b is less likely to be etched than the pattern 26a. Thereby, the surface of the wiring layer 24 of the pattern 26a is roughened, but the surface of the wiring layer 24 of the pattern 26b is not roughened as much as the pattern 26a.

  As shown in FIG. 6B, the underlying layer 22 is removed using the wiring layer 24 as a mask. As a result, the wiring 12 a is formed from the base layer 22 and the wiring layer 24. As shown in FIG. 6C, an insulating layer 10b is formed on the insulating layer 10a so as to cover the wiring 12a. The material and film thickness of the insulating layer 10b are the same as those of the insulating layer 10a, for example. The insulating layer 10b is formed by attaching an insulating sheet, for example. A through electrode 14b penetrating the insulating layer 10b is formed. Since the surface of the wiring 12a of the pattern 26a is roughened, the adhesion between the wiring 12a and the insulating layer 10b is improved. By repeating FIG. 5A to FIG. 6B a plurality of times, a wiring substrate in which a plurality of insulating layers are laminated is formed.

  In FIG. 6A, the surface roughness of the wiring 12a and the metal concentration of the surface of the wiring 12a were measured. FIG. 7A and FIG. 7B are a plan view and a cross-sectional view showing patterns used in the experiment. As shown in FIG. 7A, the pattern 60 of the wiring layer 24 has a pad 64 and a wiring part 62. The wiring part 62 is formed between the pads 64. The length L of the wiring part 62 is about 1 mm, and the wiring width is W. The pad 64 is a circle having a diameter W0 of about 200 μm.

  As shown in FIG. 7B, five patterns having different wiring widths W are formed. The wiring widths W1 to W5 of the patterns 60a to 60e are 1 μm, 3 μm, 5 μm, 10 μm, and 100 μm, respectively.

  The manufacturing method of the patterns 60a to 60e is as follows. In FIG. 5A, a titanium layer having a thickness of 30 nm is formed as the base layer 22 on the insulating layer 10 that is a resin layer using a sputtering method. A copper seed layer having a thickness of 50 nm is formed on the underlayer 22.

  In FIG. 5B, a photoresist having a film thickness of 3 μm is formed as the mask layer 50. Patterning and exposure are performed, followed by development. Thereby, openings 52a and 52b corresponding to the patterns 60a to 60e are formed. The surface of the mask layer 50 is modified by oxygen ashing. A wiring layer 24, which is a copper layer having a film thickness of 1 μm, is formed using an electrolytic plating method using a sulfuric acid electrolytic plating solution.

  In FIG. 5C, the mask layer 50 is removed using N methylpyrrolidone. Thereafter, the copper seed layer is removed using a potassium hydrogen sulfate solution.

  In FIG. 5D, the wiring layer 24 was immersed in an aqueous palladium solution for about 10 minutes. The aqueous palladium solution contains palladium chloride, sodium hydrogen phosphate, and sodium dodecyl benzene sulfonate. The concentration of palladium in the palladium aqueous solution was 0.01 g / L, 0.1 g / L, 0.5 g / L, and 1.0 g / L. Sodium hydrogen phosphate was in the range of 5 g / L to 15 g / L. Sodium dodecyl benzene sulfonate was in the range of 0.1 g / L to 5 g / L.

  In FIG. 6A, the wiring layer 24 was immersed in the roughening treatment liquid for about 10 minutes. The roughening treatment liquid is Mec etch bond CZ manufactured by Mec. Thereafter, the surface roughness Ra of the surface of the wiring layer 24 was measured using an AFM (Atomic Force Microscope) method. Further, the palladium concentration on the surface of the wiring layer 24 was measured using an EDS (Energy Dispersive X-ray Spectroscopy) method.

  FIG. 8A is a diagram showing the surface roughness of the surface of the wiring layer before and after the roughening treatment, and FIG. 8B is a diagram showing the palladium concentration and the surface roughness after the roughening treatment. Before the roughening in FIG. 8A, the surface roughness immediately after FIG. 5C is shown. In FIG. 8B, “no Pd treatment after roughening” is an example in which the palladium aqueous solution treatment is not performed in FIG. 5D. As shown in FIG. 8A, before the roughening treatment, the surface roughness is 50 nm or less regardless of the wiring width W. After the roughening treatment without the palladium treatment, the surface roughness is 300 nm or more. The surface roughness increases as the wiring width W decreases. This is because the corrosion reaction is more likely to occur as the wiring width is smaller.

  The Pd concentration in FIG. 8B is the palladium concentration in the palladium aqueous solution. The amount of Pd is the palladium concentration on the surface of the wiring layer 24. As shown in FIG. 8B, when the wiring width W becomes small at any palladium concentration, the amount of Pd becomes large and the surface roughness becomes small. In particular, when the wiring width W is 3 μm or less, the amount of Pd increases. This is because the substitution reaction of copper on the surface of the wiring layer 24 with palladium is promoted when the wiring width is 3 μm or less. When the wiring width is 3 μm or less, the surface roughness becomes small. This is because when the wiring width is 3 μm or less, the amount of Pd increases, and the reaction potential during the roughening treatment increases. As the palladium concentration of the palladium aqueous solution decreases, the amount of Pd decreases. When the palladium concentration is 0.01 g / L, the amount of Pd with a wiring width W of 100 μm is very small. Thus, when the palladium concentration is reduced, it is possible to suppress the deposit of palladium on a pad or the like having a large wiring width W. On the other hand, when the palladium concentration of the palladium aqueous solution is 1.0 g / L, the amount of Pd on the surface of the wiring layer 24 increases even in a pattern with a large wiring width. As a result, the surface roughness of the wiring layer 24 is reduced even in a pattern having a large wiring width W.

  When the surface of the wiring layer 24 having a wiring width of 3 μm in the sample without Pd treatment after roughening in FIG. 8A was observed with a scanning electron microscope (SEM), large irregularities were observed. On the other hand, when the surface of the wiring layer 24 having a Pd concentration of 0.1 g / L in FIG. 8B having a wiring width of 3 μm was observed by SEM, no large unevenness was observed.

  Next, the roughening treatment and the palladium aqueous solution treatment were performed in a state where the patterns were not electrically connected to each other by the base layer 22. FIG. 9 is a diagram illustrating the palladium concentration and the surface roughness after the roughening treatment depending on the presence or absence of the base layer 22 during the roughening treatment. In FIG. 9, Ti removal is a sample that has been subjected to roughening treatment and palladium aqueous solution treatment in a state in which the titanium layer of the underlayer 22 between the patterns 60a to 60e has been removed. The Pd concentration of the aqueous palladium solution is 0.1 g / L. The presence of Ti is the same sample as the Pd concentration of 0.1 g / L in FIG.

  As shown in FIG. 9, even in the sample from which the titanium layer is removed, the Pd amount on the surface of the wiring layer 24 increases as the wiring width W decreases. However, it is not as pronounced as the sample with a titanium layer. Therefore, it is preferable that the patterns 60a to 60e are electrically connected when the roughening treatment and the palladium aqueous solution treatment are performed.

  According to the first embodiment, as shown in FIG. 5D, the wiring layer is formed such that the concentration of the metal 32 on the surface of the wiring layer 24 of the pattern 26a (first pattern) is lower than that of the pattern 26b (second pattern). A metal 32 is attached to the surface of 24. Thereafter, as shown in FIG. 6A, after the wiring layer 24 is exposed to a solution, the surface of the wiring layer 24 is roughened. Thereby, when the surface of the wiring layer 24 is roughened, the potential of the wiring layer 24 having the pattern 26b having a small line width becomes higher than that of the pattern 26b. Therefore, the surface of the wiring layer 24 of the pattern 26a having a large line width is roughened, and the adhesion between the insulating layer 10b and the wiring layer 24 is improved in FIG. On the other hand, the roughening of the wiring layer 24 of the pattern 26b having a small line width does not proceed, and the wiring layer 24 of the pattern 26b can be suppressed from becoming thin.

  In FIG. 5D, the wiring layers 24 of the patterns 26 a and 26 b are exposed to a solution containing the metal 32. Thereby, the density | concentration of the metal 32 of the surface of the pattern 26a can be made smaller than the pattern 26b. Therefore, in FIG. 6A, the surface of the wiring layer 24 of the pattern 26a can be made rougher than the surface of the wiring layer 24 of the pattern 26b. The method of varying the concentration of the metal 32 on the surfaces of the patterns 26 a and 26 b may be other than the method of immersing the wiring layer 24 in a solution containing the metal 32.

  As shown in FIG. 9, in the step of immersing the wiring layer 24 in the solution, the wiring layer 24 is preferably immersed in the solution in a state where the patterns 60a to 60e are electrically connected. The underlying layer 22 can be used as an electrical connection method.

  As shown in FIG. 8B, in order to increase the metal concentration difference on the surface of the wiring layer 24 between the patterns 26a and 26b, the line width of the pattern 26a is larger than 3 μm, and the line width of the pattern 26b is 3 μm or less. Is preferred. The line width of the pattern 26a is preferably 5 μm or more, and more preferably 10 μm or more. The line width of the pattern 26b is preferably 2 μm or less, and more preferably 1.5 μm or less.

  The metal concentration on the surface of the wiring layer 24 of the pattern 26a is preferably less than 10% by weight, and the metal concentration on the surface of the wiring layer 24 of the pattern 26b is preferably 10% by weight or more. Thereby, the difference in the surface roughness of the wiring layer 24 between the patterns 26a and 26b can be increased. The metal concentration on the surface of the wiring layer 24 of the pattern 26a is preferably 5% by weight or less, and more preferably 2% by weight or less. The metal concentration on the surface of the wiring layer 24 of the pattern 26b is preferably 20% by weight or more, and more preferably 30% by weight or more.

  It is preferable that the surface roughness of the surface of the wiring layer 24 of the pattern 26a is greater than 200 nm, and the surface roughness of the surface of the wiring layer 24 of the pattern 26b is 200 nm or less. The surface roughness of the surface of the wiring layer 24 of the pattern 26a is preferably 250 nm or more, and more preferably 300 nm or more. The surface roughness of the surface of the wiring layer 24 of the pattern 26b is preferably 150 nm or less, and more preferably 100 nm or less.

  In order to increase the metal concentration difference on the surface of the wiring layer 24 between the patterns 26a and 26b, the ion concentration of the metal 32 in the solution is preferably 0.5 g / L or less, more preferably 0.2 g / L or less. 0.1 g / L or less is more preferable.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1) Forming a wiring layer having a first pattern and a second pattern having a smaller line width than the first pattern on the insulating layer, and the wiring layer on the surface of the wiring layer of the first pattern Attaching the metal to the surface of the wiring layer such that the concentration of the metal having a higher standard potential than the material of the material is lower than the concentration of the metal on the surface of the wiring layer of the second pattern; And a step of roughening the surface of the wiring layer after the step of forming.
(Appendix 2) The step of attaching the metal to the surface of the wiring layer includes a step of exposing the wiring layer of the first pattern and the second pattern to a solution containing the metal. Wiring board manufacturing method.
(Supplementary note 3) The step of exposing the wiring layer to the solution includes a step of exposing the wiring layer to the solution in a state where the first pattern and the second pattern are electrically connected. 3. A method for producing a wiring board according to 2.
(Appendix 4) The step of roughening the surface of the wiring layer includes the step of roughening the surface of the wiring layer of the first pattern from the surface of the wiring layer of the second pattern. The method for manufacturing a wiring board according to any one of claims 1 to 3.
(Appendix 5) The material of the wiring layer is copper, and the metal is at least one of mercury, silver, palladium, iridium, platinum, and gold. The manufacturing method of the wiring board as described.
(Supplementary Note 6) The first pattern has a line width greater than 3 μm, the second pattern has a line width of 3 μm or less, and the step of attaching the metal to the surface of the wiring layer includes the wiring of the first pattern Additional steps 1 to 5 including a step of setting the concentration of the metal on the surface of the layer to less than 10% by weight and setting the concentration of the metal on the surface of the wiring layer of the second pattern to 10% by weight or more. The manufacturing method of the wiring board as described in any one.
(Additional remark 7) The line width of the said 1st pattern is larger than 3 micrometers, the line width of the said 2nd pattern is 3 micrometers or less, The process of roughening the surface of the said wiring layer is the process of the said wiring layer of the said 1st pattern. The wiring according to any one of appendices 1 to 6, further comprising a step of setting the surface roughness to be greater than 200 nm and setting the surface roughness of the surface of the wiring layer of the second pattern to 200 nm or less. A method for manufacturing a substrate.
(Additional remark 8) The manufacturing method of the wiring board of Additional remark 2 or 3 characterized by the metal ion concentration of the said solution being 0.5 g / L or less.
(Additional remark 9) The said wiring layer is a copper layer, The said metal is palladium, The manufacturing method of the wiring board as described in any one of additional marks 1-8 characterized by the above-mentioned.
(Additional remark 10) The said insulating layer is a resin layer, The manufacturing method of the wiring board as described in any one of additional remark 1 to 9 characterized by the above-mentioned.
(Supplementary Note 11) An insulating layer, and a wiring layer having a first pattern formed on the insulating layer and a second pattern having a line width smaller than the line width of the first pattern. The concentration of the metal having a standard potential higher than the material of the wiring layer on the surface of the wiring layer of one pattern is lower than the concentration of the metal of the wiring layer of the second pattern, and the concentration of the metal of the wiring layer of the first pattern The wiring board characterized in that the surface is rougher than the surface of the wiring layer of the second pattern.
(Supplementary Note 12) The line width of the first pattern is larger than 3 μm, the line width of the second pattern is 3 μm or less, and the concentration of the metal on the surface of the wiring layer of the first pattern is smaller than 10% by weight. The wiring board according to claim 11, wherein the concentration of the metal on the surface of the wiring layer of the second pattern is 10% by weight or more.
(Supplementary note 13) The line width of the first pattern is larger than 3 μm, the line width of the second pattern is 3 μm or less, the surface roughness of the surface of the wiring layer of the first pattern is larger than 200 nm, 13. The wiring board according to appendix 11 or 12, wherein the surface roughness of the surface of the two wiring layers is 200 nm or less.

10, 10a, 10b Insulating layer 12a-12c Wiring layer 14a, 14b Through electrode 20 Wiring substrate 22 Underlayer 24 Wiring layer 26a, 26b Pattern 28 Recess 32 Metal

Claims (9)

Forming a wiring layer having a first pattern and a second pattern having a smaller line width than the first pattern on the insulating layer;
In the wiring layer, the concentration of the metal having a higher standard potential than the material of the wiring layer on the surface of the wiring layer of the first pattern is lower than the concentration of the metal on the surface of the wiring layer of the second pattern. Attaching the metal to the surface;
After the step of attaching the metal, a step of roughening the surface of the wiring layer;
A method for manufacturing a wiring board, comprising:   2. The wiring board according to claim 1, wherein the step of attaching the metal to the surface of the wiring layer includes a step of exposing the wiring layer of the first pattern and the second pattern to a solution containing the metal. Manufacturing method.   3. The step of exposing the wiring layer to the solution includes a step of exposing the wiring layer to the solution in a state where the first pattern and the second pattern are electrically connected. A method for manufacturing a wiring board.   4. The step of roughening the surface of the wiring layer includes the step of roughening the surface of the wiring layer of the first pattern from the surface of the wiring layer of the second pattern. The manufacturing method of the wiring board as described in any one. The material of the wiring layer is copper,
5. The method of manufacturing a wiring board according to claim 1, wherein the metal is at least one of mercury, silver, palladium, iridium, platinum, and gold. The line width of the first pattern is larger than 3 μm, the line width of the second pattern is 3 μm or less,
The step of adhering the metal to the surface of the wiring layer includes reducing the concentration of the metal on the surface of the wiring layer of the first pattern to less than 10% by weight, and forming the metal on the surface of the wiring layer of the second pattern. 6. The method for manufacturing a wiring board according to claim 1, further comprising a step of setting the concentration to 10% by weight or more. The line width of the first pattern is larger than 3 μm, the line width of the second pattern is 3 μm or less,
In the step of roughening the surface of the wiring layer, the surface roughness of the surface of the wiring layer of the first pattern is larger than 200 nm, and the surface roughness of the surface of the wiring layer of the second pattern is 200 nm or less. The manufacturing method of the wiring board as described in any one of Claim 1 to 6 including the process to perform.   4. The method for manufacturing a wiring board according to claim 2, wherein the metal has an ion concentration of 0.5 g / L or less. An insulating layer;
A wiring layer formed on the insulating layer and having a first pattern and a second pattern having a line width smaller than the line width of the first pattern;
Comprising
The concentration of the metal having a higher standard potential than the material of the wiring layer on the surface of the wiring layer of the first pattern is lower than the concentration of the metal of the wiring layer of the second pattern,
The wiring board according to claim 1, wherein a surface of the wiring layer of the first pattern is rougher than a surface of the wiring layer of the second pattern.

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