JP2016101278A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine facilitating verification of validity of programs since a program for mounting amusement specifications and a program for preventing a fraudulent act are often mixedly disposed on a ROM.SOLUTION: When a program existing inside a first control area and accessed by a CPU, namely, a program implemented with amusement specifications, is disposed as a program existing inside a second control area and accessed by the CPU, namely, a program for preventing a fraudulent act, it is guaranteed that a processing result processed by the program implemented with amusement specifications and a processing result processed by the program for preventing a fraudulent act are not stored mixedly, and destruction of one of the processing results can be known easily even if the stored processing result is destroyed.SELECTED DRAWING: Figure 7

Description

  It relates to gaming machines.

  A spinning machine (slot machine) is a multi-row game machine in which a plurality of symbols are arranged on the outer periphery when a game start instruction device (start lever) is operated after a predetermined number of game medals have been inserted. The cylinder (reel) rotates, and as a result of stopping the rotation using a rotation stop device (stop button) for stopping the rotation, a combination of predetermined symbols (for example, “777” on the effective line) )), The game type is generally shifted to a special gaming state that is more profitable for the player than the normal gaming state {the gaming state in which the lottery probability of the winning combination is higher than in the normal state}. is there. Here, in the slot machine, there may be a case where an image for production for enhancing the fun of the game is displayed on a display such as a liquid crystal in a form synchronized with the rotation operation and the stop operation of the reel. In many cases, when a stop button or the like is operated, a game result is predicted and enjoyed while comparing a design displayed on the reel with an image for performance displayed on the display.

  In addition, the pachinko game machine has a symbol called “special symbol” variably displayed on the display section such as 7-segment when the game ball enters the start opening (start chucker). Is in a specific mode (for example, “7”), a special game state that is more profitable for the player than the normal game state {contents that a special winning opening (attacker) that is normally closed is opened under predetermined conditions] Is a type that shifts to the so-called “digipachi” (conventional “first-class gaming machine”). Here, in order to reduce the burden of display control of special symbols that are directly linked to the interests of the player, in addition to the aforementioned “special symbols”, it is referred to as “decorative symbols” for the purpose of enhancing the fun of the game. The symbol to be displayed may be variably displayed on a display such as a liquid crystal having a size larger than that of the display unit in a form synchronized with the variation of the special symbol. And when the change of the special symbol is started, the decorative symbol also starts to change accordingly. “777”). And many things are comprised so that a player can recognize clearly that transfer to a special game was decided because the decoration design stopped in the predetermined mode.

  Such a mechanism is common to many game machines of this type, but the program capacity for controlling the operation of the game machine is to prevent mixing of illegal programs (guaranteeing the validity of the program provided by the machine manufacturer). The upper limit of the capacity is strictly regulated from the viewpoint, and in addition to the program for implementing the gaming specification, the gaming machine is cheated (for example, for the slot of the game medium and the outlet) Many programs for preventing illegal acts are also implemented to protect against unauthorized access to obtain game media by unauthorized means.

JP2011-147675A

  However, at present, a program for implementing the game playability specification and a program for preventing fraud are often mixed on the ROM, and as a result, it is difficult to verify the legitimacy of these programs. There is a problem of becoming.

The gaming machine according to this aspect is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, The gaming machine is configured to be able to refer to information (for example, information held in a register in the CPUC 100) stored at the time when a call instruction is issued.

  According to the gaming machine according to the present aspect, there is an effect that it becomes easy to verify the validity of the program for implementing the gameability specification and the program for preventing fraud.

FIG. 1 is a perspective view of a rotating type gaming machine according to the present embodiment. FIG. 2 is a perspective view of a state in which the door of the spinning cylinder type gaming machine according to the present embodiment is opened. FIG. 3 is a perspective view of the inside of the medal slot in the spinning cylinder game machine according to the present embodiment. FIG. 4 is a front view and a top view of the medal payout device in the spinning cylinder type gaming machine according to the present embodiment. FIG. 5 is an overall electrical configuration diagram of the swivel type gaming machine according to the present embodiment. FIG. 6 is an electrical configuration diagram relating to the main control chip of the spinning cylinder gaming machine according to the present embodiment. FIG. 7 is a memory map configuration diagram of the main control chip in the rotating game machine according to the present embodiment. FIG. 8 is a main flowchart on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 9 is a flowchart of the setting change device control process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 10 is a flowchart of the game progress control process (first sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 11 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 12 is a flowchart of the game progress control process (third sheet) on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 13 is a flowchart of the non-recoverable error process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 14 is a flowchart of a medal insertion error detection process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 15 is a flowchart of the medal payout error detection process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 16 is a flowchart of the insertion / withdrawal error detection process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 17 is a flowchart of the timer interruption process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 18 is a flowchart of the medal insertion check process on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 19 is a flowchart of a medal payout check process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 20 is a flowchart of the input / withdrawal error check processing on the main control board side in the spinning cylinder type gaming machine according to the present embodiment. FIG. 21 is a flowchart of the power-off process on the main control board side in the spinning cylinder game machine according to the present embodiment. FIG. 22 is a main flowchart (first sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 23 is a main flowchart (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 24 is a flowchart of the game progress control process (second sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 25 is a flowchart of a medal insertion error detection process on the main control board side in the spinning-reel game machine according to the second embodiment. FIG. 26 is a flowchart of a medal payout error detection process on the main control board side in the spinning cylinder game machine according to the second embodiment. FIG. 27 is a flowchart of the insertion / withdrawal error detection process on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 28 is a flowchart of the game progress control process (third sheet) on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 29 is a flowchart of non-recoverable error processing on the main control board side in the spinning cylinder type gaming machine according to the second embodiment. FIG. 30 is a flowchart of timer interruption processing on the main control board side in the spinning-reel game machine according to the second embodiment. FIG. 31 is a flowchart of a power-off process on the main control board side in the spinning cylinder game machine according to the second embodiment.

  First, the meaning of each term in this specification will be described. “Random number” is a random number used in a lottery (lottery by an electronic computer) to determine some game content in a spinning-type game machine, and includes a pseudo-random number in addition to a random number in a narrow sense (for example, as a random number) Is a hard random number, and a soft random number as a pseudo-random number). For example, a so-called “basic random number” that affects the outcome of the game, specifically, a “winning random number” associated with the transition of a special game or a winning combination can be cited. “CPU” is synonymous with what is well known in the art, and is not limited to the architecture (CISC, RISC, number of bits, etc.) used, processing performance, or the like. “Power interruption (power interruption)” means that the power supply voltage supplied to the gaming machine falls below a certain level regardless of whether the power switch provided on the gaming machine is operated or not. This also includes shutting down the power supply due to unforeseen circumstances such as unit damage or power outages. “ROM” is synonymous with what is well known in the art, and physically retains information (for example, “1” for a device configuration that conducts when a current for reading data is applied, It will be “0” if the device configuration is not.) RAM is synonymous with what is well known in the art, and electrically holds information (for example, when a current for reading data is applied, “1” is stored if it is stored, and it is not stored. It is generally “0.” In general, backup power is supplied to some or all of the data stored in the RAM when the power is interrupted). The “game state” is, for example, a special game state in which a game medal can be easily acquired and advantageous to the player (so-called jackpot game, such as a bonus game, a type 1 BB, a type 2 BB, or the like) ), The re-game probability variation game state (RT state) in which the re-game win rate is higher (or lower) than the normal game state in which the re-game win rate is a predetermined value, and the winning combination is awarded For example, an AT (assist time) state in which the stop order of the reels can be notified, an ART (assist replay time) state in which the RT state and the AT state are combined, and the like. Further, even in the normal game state, there are a high-probability normal game state, a low-probability normal game state, and the like that have different lottery probabilities for transition to the RT state, AT state, and ART state. In addition, there is no problem even if the game states are combined {in addition, these game states and functions (for example, a lottery to shift to the AT state, an output of a notification instruction related to the stop order of reels, etc.) control the game progress. There is no problem even if all are mounted on the main control board side}.

  The following embodiment is based on the assumption of a revolving game machine (so-called slot machine), but is not limited to this, and other game machines (for example, pachinko game machines, sparrow balls, arrangements) It is also within the range when applied to a ball, etc., that is, with a microcomputer chip (chip equipped with a CPU, ROM, RAM) for controlling the progress of the game, and for operating a program on the microcomputer chip It is a technology that can be applied. Note that this embodiment is merely an example, the location and function of each means, the order of each step regarding various processes, the timing of flag on / off, the name of the means responsible for each step, etc. It is not limited to the following aspects. In addition, the above-described embodiments and modified examples should not be understood as being limited to being applied to specific items, and may be in any combination. For example, it should be understood that a modification example of an embodiment is a modification example of another embodiment, and even if one modification example and another modification example are described independently, there is the modification example. It should be understood that a combination of the modified example and another modified example is also described.

  Prior to the detailed description of the present invention, a simple configuration according to the present invention will be described.

  Among the swivel type gaming machines according to the present invention, a configuration in which the first RAM area (or register area) can be updated and referred to by the processing of the CPUC 100 based on the program code arranged in the second ROM area (this book) Embodiment) will be described in detail.

  Among the swivel type gaming machines according to the present invention, the second RAM area can be referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area, and is arranged in the second ROM area. A configuration in which the first RAM area can be referred to in the processing of the CPUC 100 based on the program code is described in detail in the second embodiment.

(This embodiment)
Here, before describing each component, the feature (outline) of the spinning-rotor type gaming machine P according to the present embodiment will be described. Hereinafter, each element will be described in detail with reference to the drawings.

  First, with reference to FIG. 1 (FIG. 2 for a part of the configuration), the basic structure on the front side of the rotary type gaming machine according to the present embodiment will be described. First of all, the swing type gaming machine P mainly includes a front door (also referred to as a front door), a back box (also referred to as a cabinet and a base body), a reel unit installed in the back box, a hopper device, a power supply unit, a main control. It is composed of a substrate M (a substrate on which the main control chip C is mounted). Hereinafter, these will be described in order.

  Next, the front door DU of the swing type gaming machine P includes a decorative lamp unit D150 and a medal tray D230. First, the decorative lamp unit D150 has a light-emitting source that emits light in accordance with the progress of the game of the rotary game machine P. Further, a door switch D80 capable of detecting the open / closed state of the front door DU is provided. Further, the front door DU is provided with a key hole D260, and a key (door key) that matches the shape of the key hole D260 is inserted into the key hole D260 {in addition, twisted in a predetermined direction (for example, clockwise)} The front door DU can be opened. Further, in the present embodiment, an error state (a door opening error, which will be described later) can be canceled by inserting the door key into the keyhole D260 {plus twisting in a predetermined direction (for example, counterclockwise)}. It is configured. Next, the medal tray D230 is a tray for game medals (or simply called medals) released from the discharge port D240.

  Next, the front door DU includes a mechanism for enabling visual recognition of the game state, a mechanism for enabling input of game media, a mechanism for operating the reel unit, and the like. Specifically, the reel window D160, the insertion number display lamp D210, the operation state display lamp D180, the special game state display apparatus D250, the payout number display apparatus D190, and the credit number display apparatus are provided as mechanisms for making the gaming state visible. D200 etc. are attached. Further, as a mechanism for enabling the insertion of game media and inputting the number of bets (the number of bets), a medal insertion slot D170, a bet button D220, and a mechanism for enabling the payout of the inserted game media are settled. Button D60 is attached. As a mechanism for operating the reel unit, a start lever D50 and a stop button D40 are attached. Hereinafter, each element will be described in detail.

<Mechanism to make game state visible>
Next, the reel window D160 is a transparent member formed of a synthetic resin or the like that constitutes a part of the front door DU, and is configured so that the reel unit installed in the gaming machine frame can be seen through the reel window D160. ing. In addition, the insertion number indicator lamp D210 is constituted by an LED, and is configured so that the same number of LEDs as the number of medals currently bet (to insert a game medal necessary for starting one game) are lit. Has been. Further, the operation state indicator lamp D180 is constituted by an LED, and is configured to be turned on / off according to the current operation state (medal acceptance / non-acceptance state, re-game winning state, game start wait state, etc.). The special game state display device D250 is configured by a 7-segment display, and is configured to display the total number of payouts paid out during the special game. In addition, it is good also as a structure which does not provide the special game state display apparatus D250, and when it is comprised in that way, it is comprised so that a player may be in special game by displaying so that the total of the said number of payouts may be displayed in production | presentation display apparatus S40. The total number of payouts paid out can be recognized, and a user-friendly gaming machine can be obtained. Further, the payout amount display device D190 is configured by a 7-segment display, and is configured to display the number of game medals currently being paid out. The credit amount display device D200 is configured by a 7-segment display, and is configured to display the total number of medals (credit number) stored in the gaming machine as medals held by the player.

<Mechanism to enable input of game media>
Next, the medal slot D170 is a slot for game medals, and the game medal inserted into the slot is guided to the inside of the gaming machine frame in a situation where medals can be received. In addition, an insertion acceptance sensor D10s, a first insertion sensor D20s, and a second insertion sensor D30s are provided in the gaming machine frame as sensors for detecting the insertion of medals. When it is determined that the guided game medal is normally inserted, the inserted medal is detected as a bet. Further, the bet button D220 is configured to be operable by the player, and configured to bet a stored medal (credit medal). Further, the settlement button D60 is configured to be operable by the player, and by this operation, the stored medal (credit medal) and / or the bet medal can be paid back to the player. ing. Note that the game medals paid out by operating the settlement button D60 are configured to be paid out to the discharge port D240.

<Mechanism for operating reel unit>
Next, the start lever D50 is configured to be operable by the player, and is configured to be able to start the operation of the reel unit by the operation. The stop button D40 includes a left stop button D41, a middle stop button D42, and a right stop button D43 that can be operated by the player. By operating the respective stop buttons, the operation of the reel unit can be stopped sequentially. It is configured.

  Next, the reel unit of the rotating type gaming machine P includes a reel M50 and a drive source (stepping motor or the like) of the reel M50. The reel M50 includes a left reel M51, a middle reel M52, and a right reel M53. Here, each reel part is formed of a synthetic resin or the like, and a plurality of symbols are drawn on the outer periphery (on the reel band) of the reel part. And based on operation of each stop button in the start lever D50 and the stop button D40, it is comprised so that rotation operation and stop operation | movement of each reel part are enabled. Although not shown, an LED (hereinafter also referred to as a reel backlight) is provided inside the left reel M51, the middle reel M52, and the right reel M53, and when the LED is lit, the reel portion It is configured so that the light transmitted through the outer periphery can be visually recognized as if the outer periphery of the reel portion is lit.

<Other mechanisms>
In addition, inside and outside the gaming machine frame of the swing type gaming machine P, as a mechanism for enhancing the interest of the game, an effect display device S40 for displaying effects such as a notice effect and a background effect, various lighting modes Are provided with an LED lamp S10 that can be turned on, a speaker S20 that can output sound, and an upper panel D130 and a lower panel D140 that are members formed of synthetic resin or the like.

  Next, FIG. 2 is a perspective view showing an internal configuration of the rotating game machine P with the front door DU opened. An effect display device S40 is attached to the upper part on the back side of the front door DU. A reel window D160 is provided substantially at the center of the front door DU, and a door substrate D described later is provided below the reel window D160. In addition, the door board D receives input signals such as the stop button D40, the start lever D50, and the settlement button D60 described above. A speaker S20 is provided below the door substrate D.

  Although details will be described later, an insertion acceptance sensor D10s serving as a path for game medals inserted from the medal insertion slot D170 is provided in the vicinity of the door substrate D, and below the insertion reception sensor D10s, A coin shooter D90 and the like for guiding a game medal to the discharge port D240 are provided. The insertion acceptance sensor D10s has a function of selecting game medals inserted from the medal insertion slot D170 mainly on the basis of dimensions, and accepting only game medals conforming to the standard dimensions. The selected medal (or other foreign matter) is returned to the discharge port D240 by the blocker D100. If the player inserts a game medal before operating the start lever D50 (in a state where the insertion of the game medal is valid), the game medal is selected by the insertion acceptance sensor D10s, and only those satisfying the standard are selected. A medal that does not satisfy the standard and is inserted into the hopper H40 is returned to the discharge port D240 through the coin shooter D90. On the other hand, when a game medal is inserted after the start lever D50 is operated (in a state where the insertion of the game medal is not valid), the inserted game medal passes through the coin shooter D90, and the discharge port D240. Returned to. In addition, a sensor for medal insertion, which will be described in detail later, is provided inside the insertion acceptance sensor D10s (the back of the flow path), and when a game medal that has been received satisfying the dimensional standard passes, the first insertion sensor D20s. The signal is detected by the second input sensor D30s and the signal is supplied to the main control board M to be described later.

  A main control board M, which will be described later, that controls the entire game is stored above the reel M50, and behind the reel M50, each reel (left reel M51, middle reel M52, right reel M53) is driven. For this purpose, a later-described rotor substrate K is stored. Further, on the left side of the reel M50, a sub-control board S (to be described later) that controls various effects performed using the effect display device S40 shown in FIG. 1, the LED lamp S10, the speaker S20, and the like is stored. . In addition, the main control board M has a setting key switch M20 used for executing a setting change device control process (to change settings), which will be described later, and a setting / reset that can execute setting value change, error cancellation, and the like. A setting door switch M10 for determining opening / closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30, and the like is connected. The setting key switch M20, the setting / reset button M30, and the setting door switch M10 are not shown, but they may be provided at appropriate positions on the main control board M (ie, the front door). If the DU is not opened, it may be in a position where it is difficult to access artificially).

  Below the reel M50, there are provided a hopper H40 for collecting inserted game medals and a medal payout device H for paying out game medals, and a power supply board for supplying power to the entire revolving game machine P E is stored. The game medals paid out from the medal payout device H pass through the coin shooter D90 and are paid out from the discharge port D240. Further, on the front surface of the power supply board E, there is also provided a power switch E10 for turning on the power of the swivel type gaming machine P.

  Next, FIG. 3 is a perspective view showing a path (selector) of game medals inserted into the medal insertion slot D170 inside the spinning cylinder type game machine. A game medal inserted into the medal slot D170 first passes through the slot acceptance sensor D10s. The insertion acceptance sensor D10s is a mechanical double sensor, and when the game medal passes, it turns on when the two protruding mechanisms are pressed, and the game medal can normally pass through the passage. Become. Also, with such a configuration, when a foreign object that is not a game medal (for example, one having a smaller diameter than the game medal) is inserted, the two protruding mechanisms are not pressed. Such medals cannot be maintained in the standing state, and therefore cannot pass through the passage (the medals fall down) and are paid back to the discharge port D240. In addition, the insertion acceptance sensor D10s is configured to be able to determine that there is an error even when the on-time continues for a predetermined time or longer (as a result, the blocker D100 can be turned off). .

  When a game medal normally passes through the blocker D100, it passes through the first insertion sensor D20s and the second insertion sensor D30s immediately after the passage. The throwing sensors (first throwing sensor D20s and second throwing sensor D30s) are composed of two sensors (adjacently arranged at an interval smaller than the standard diameter of the game medal), and each sensor is turned on. -Various errors (to be described later) are monitored by monitoring the OFF state (the order in which the combination of ON / OFF of the first input sensor D20s and the second input sensor D30s transitions) and the ON / OFF time. , Inserted medal retention error, inserted medal backflow error, etc.).

  Next, FIG. 4 is a front view and a perspective view of the medal payout device H in the spinning cylinder type gaming machine. The medal payout device H is operated with the checkout button in the state where credits (game medals stored electronically inside the gaming machine) or bets (medals inserted to start the game) exist. It is activated when a game medal is paid out by winning or winning. In operation, first, the hopper motor H80 is driven to rotate the disk H50 about the disk rotation axis H50a. The game medal in the medal payout device H flows down from the game medal outlet H60 toward the discharge port D240 by displacing the discharge urging means H70 by the rotation. The payout sensors (the first payout sensor H10s and the second payout sensor H20s) are composed of two sensors, and the ON / OFF status of each sensor (the ON / OFF state of the first payout sensor H10s and the second payout sensor H20s). The order of transition of the combination of off, etc.) and the on / off time are monitored to detect various errors (payout medal retention error, etc., which will be described later). More specifically, for example, when the game medal outlet H60 normally passes, the first payout sensor H10s = off and the second payout sensor H20s = off due to the displacement of the discharge biasing means H70. 1 payout sensor H10s = off / second payout sensor H20s = off → first payout sensor H10s = on / second payout sensor H20s = off → first payout sensor H10s = on / second payout sensor H20s = on → first payout Sensor H10s = on / second payout sensor H20s = off → first payout sensor H10s = off / second payout sensor H20s = off, so that when a movement contrary to this sensor state transition is detected It is possible to exemplify the configuration of an error.

  Next, referring to the block diagram of FIG. 5, an electrical schematic configuration of the rotating game machine P according to the present embodiment will be described. First, in the spinning-type game machine according to the present embodiment, a sub-control board S, a door board D, a spinning board K, a power board E, a relay board IN, centering on a main control board M that controls the progress of the game, A setting door switch M10, a setting key switch M20, a setting / reset button M30, and the like are connected to be able to exchange data. The solid line portion in the figure shows the movement related to the exchange of data, and the broken line portion in the figure shows the power supply route. The power supply route is not limited to this, and for example, power may be supplied from the power supply board E to the relay board IN and the door board D without going through the main control board.

  The main control board M is a board that governs the progress of the entire game performed in the rotating game machine P. A main control chip C is mounted on the main control board M, and a CPU C 100, a built-in ROM C 110, a built-in RAM C 120, and the like are mounted on the main control chip C so as to be able to exchange data with each other via a bus ( The illustration and details will be described later). The main control board M receives a signal indicating that the start lever D50 or the like has been operated from the door board D mounted on the front door DU, and receives the sub-control board S, the door board D, and the rotating board. By outputting a control command (or control signal) toward K or the like, the operation of these various substrates is controlled.

  Similarly to the main control board M described above, the sub control board SC is also mounted on the sub control board S. The sub control chip SC is provided with a CPU, ROM, RAM, etc. Are connected so as to be able to exchange data with each other. In addition, various LED lamps S10, a speaker S20, an effect display device S40, a rotating backlight S30, and the like are connected to the sub-control board S. Here, the spinning backlight S30 is a light that is provided inside each of the left reel M51, the middle reel M52, and the right reel M53, and illuminates the pattern drawn on the surface of the reel from the back side. The sub-control board S analyzes the control command received from the main control board M, and outputs various drive signals to the various LED lamps S10, the speaker S20, the effect display device S40, the rotary backlight S30, etc. The production of.

  On the door substrate D, the above-described insertion acceptance sensor D10s, first insertion sensor D20s, second insertion sensor D30s, stop button D40 for stopping the rotating reel M50, start for starting the rotation of the reel M50. A lever D50, a stored game medal (credit) and a game button D60 for paying out the inserted game medal and ending the game, various display panels D70 for displaying the game state (the above-mentioned input number display lamps) D210, operation state display lamp D180, special game state display device D250, payout number display device D190 is a collection of display devices such as credit number display device D200), door open / close determination, error cancellation, and setting value Door switch D80 for executing the change, game medals determined to be incompatible after being inserted (or other Blocker D100 or the like for refund things) the outlet D240 is connected. The door substrate D is connected to the main control substrate M described above so as to exchange data. For this reason, when a start lever D50, a stop button D40, a settlement button D60, etc. provided on the front door DU are operated, a signal related to the operation is supplied to the main control board M via the door board D. It has become. Further, a signal that the insertion acceptance sensor D10s detects the passage of the game medal is also supplied to the main control board M through the door board D.

  In addition, a rotating motor K10 for rotating the reel M50, a rotating sensor K20 for detecting the rotational position of the reel M50, and the like are connected to the rotating substrate K. The spinning board K can stop the reel M50 at the determined stop position by driving the spinning motor K10 while detecting the rotational position of the reel M50 by the spinning sensor K20. Yes. Further, in the spinning cylinder type gaming machine of the present embodiment, a so-called step motor (stepping motor) is used as the spinning cylinder motor K10. In the step motor, 504 steps are set as the number of steps for one rotation of the reel M50. Each reel (left reel M51, middle reel M52, right reel M53) has a predetermined number of symbols (for example, 21 symbols) with a substantially uniform size, and the number of steps corresponding to one symbol is set. 24 steps (= 21/504) are set. There is no problem even if the number of steps and the number of symbols per reel are changed.

  The medal payout device H is connected to the main control board M via the relay board IN, and pays out a predetermined number (for example, 10) of game medals based on a control signal from the main control board M. Perform the action The medal payout device H includes a first payout sensor H10s and a second payout sensor H20s for determining whether or not a medal has been paid out normally and measuring the number of game medals paid out, and a disk H50. A hopper motor H80 for rotation is connected.

  These various control boards and the power consumed by the boards are supplied from a power supply board E (a board for controlling the presence or absence of power supply by the power switch E10). In FIG. 5, the state in which electric power is supplied from the power supply board E is indicated by a dashed arrow. As shown in the figure, power is directly supplied from the power supply board E to the main control board M and the sub-control board S, and various boards (door board D, rotor board K, relay board IN) Electric power is supplied via the main control board M. A predetermined amount (for example, 100 V) of AC voltage is supplied to the power supply board E, and this electric power is converted into a DC voltage of a specified voltage and then supplied to each control board and board.

  In addition, the main control board M has a setting key switch M20 used for executing a setting change device control process (to change settings), which will be described later, and a setting / reset that can execute setting value change, error cancellation, and the like. A setting door switch M10 for determining opening / closing of a setting door (not shown) for protecting the button M30, the setting key switch M20, the setting / reset button M30, and the like is connected.

<Example of basic circuit configuration of main controller>
Next, a configuration example of the main control chip C of the main control board M will be described with reference to FIG.

  First, the main control chip C shown in FIG. 6 includes a CPU C100, built-in ROMC110 (first ROM area C111, second ROM area C112), built-in RAMC120 (first RAM area C121, second RAM area C122), external bus control circuit C190, parallel. In addition to the input port C130, address decoding circuit C150, timer circuit C170, counter circuit C180, reset control circuit C220, interrupt control circuit C160, clock circuit C210, random number generation circuit C140, verification block C230, specific information C240, arithmetic circuit C250 These are all connected to each other via an internal bus C200.

  Hereinafter, details of each of the above-described units will be described.

  First, the CPUC 100 executes various numerical calculations, information processing, control processing, and the like according to programs and data in the built-in ROMC 110 and the built-in RAMC 120. The built-in ROMC 110 stores control programs and various data. The built-in RAMC 120 temporarily stores data. Further, the built-in ROMC 110 and the built-in RAMC 120 hold addresses and data as a set, and uses are divided by address ranges. The main applications are a program area and a data area. Details of this point will be described later in the description of a memory map.

  The external bus control circuit C190 includes an IO request terminal (XIORQ terminal), a memory request terminal (XMREQ terminal), a read signal terminal (XRD terminal), a write signal terminal (XWR terminal), and a 16-bit width address output terminal (A0 terminal to A15 terminal) and data input / output terminals (D0 terminal to D7 terminal) which are input / output terminals having an 8-bit width. In the present embodiment, among these, the data input / output terminals (D0 terminal to D7 terminal) are used for data output to each drive circuit (for example, the rotating board K via the relay board IN) and each peripheral control circuit (for example, the terminal board). , Used for data input from various sensors and various operation members via the door substrate D). The data input / output destinations of the data input / output terminals (D0 terminal to D7 terminal) are the address signal output from the address output terminals (A0 terminal to A15 terminal) and the chip select signal output from the address decode circuit C150. Use to switch.

  The parallel input port C130 has four input terminals (P0 terminal to P3 terminal). As for these input terminals (P0 terminal to P3 terminal), for example, any one of the input terminals is connected to the start lever D50. It outputs to the random number generation circuit C140.

  The address decoding circuit C150 has a predetermined number (for example, 14) of output terminals (XCS0 terminal to XCS13 terminal). The output terminals (XCS0 terminal to XCS13 terminal) are connected to the peripheral control circuit outside the main control chip C, and are output from the data input / output terminals (D0 terminal to D7 terminal) of the external bus control circuit C190. It is used to output a chip select signal or the like for switching the data transmission destination.

  The timer circuit C170 is used for time measurement. The timer circuit C170 outputs a time-out signal to the counter circuit C180 when the set measurement time has passed. On the other hand, the counter circuit C180 is used for measuring the number of times of rising (or falling) of various signals. Signals measured by the counter circuit include a system clock of the main control chip C, a timeout signal from the timer circuit, a memory read / write signal, a memory request signal, an external input / output signal, an interrupt response signal, and the like. It can be measured.

  The reset control circuit C220 has two terminals, a system reset input terminal (XSRST terminal) and a reset output terminal (XRSTO terminal). This system reset input terminal (XSRST terminal) is connected to a voltage monitoring circuit (a circuit for monitoring voltage, not shown). When a system reset signal (for example, a signal at an L level for a predetermined time) is input from the system reset input terminal (XSRST terminal), the reset control circuit C220 sends this system reset signal to the internal circuit of the main control chip C. In addition to outputting, a reset signal (for example, a rising signal from L level to H level) is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the main control chip C. In this case, the main control chip C executes a process called system reset and initializes each circuit. An example of executing the system reset is when the power is turned on.

  In addition, the reset control circuit C220 includes a watchdog timer C222 and an out-of-designated area travel prohibition circuit C221. When the watchdog timer C222 times out, or when the CPU C100 refers to an address outside the predetermined range (runs outside the designated area), the reset control circuit C220 is connected to the circuit inside the main control chip C. Either system reset signal or user reset signal is output. Whether to output a system reset signal or a user reset signal depends on the setting of a program area (details will be described later) in the built-in ROMC 110. Further, a reset signal is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the main control chip C.

  The main control chip C can execute either the above-described system reset or a process called user reset depending on the setting.

  The traveling outside the designated area means that the program is operating unexpectedly. In this case, the CPUC 100 operates with a code that should not be handled as a program. Such a situation may be caused by some sort of fraud other than a so-called runaway state due to a program mistake. In this case, normal operation can be restored by any one of the system reset and user reset processes described above. Further, when the watchdog timer C222 times out, there are a case where the CPUC100 cannot perform the originally designed operation due to a runaway due to a program mistake or a voltage drop. Also in this case, it is configured to be able to return to normal operation by any one of the above system and user reset processes.

  The interrupt control circuit C160 generates an interrupt in order to appropriately execute a process according to a change in external input or internal state. This interrupt process includes, for example, a process executed when an external input (signal from a sensor) is received. In the present embodiment, timer interrupt processing executed in response to an interrupt request from the timer circuit is executed. The interrupt control circuit C160 includes an internal information register C161. The internal information register C161 includes an abnormality in the cycle of the external clock (count clock) that determines the random number update cycle in the random number generation circuit C140, and the update of the random number. In addition, information on the reset factor of the user reset that occurred immediately before is stored.

  The clock circuit C210 receives an external clock (24 MHz clock in this example) input from a crystal oscillator (not shown) via an external clock input terminal (EX terminal) with a predetermined frequency division ratio (for example, 1/2). The divided system clock (12 MHz clock in this example) is supplied to each circuit in the main control chip C. The system clock is output to a peripheral control circuit outside the main control chip C via a system clock output terminal (CLKO terminal).

  The random number generation circuit C140 uses the clock signal (count clock) for updating the random number, and holds the updated random number in the random number register when the random number latch signal is received. In this embodiment, an external clock signal input from a crystal oscillator via an external clock input terminal (RCK terminal) is divided by a predetermined frequency division ratio (for example, 1/2) and used as this count clock. However, the clock signal in the main control chip C can also be used, and in this case, a crystal oscillator is not necessary. The value held in the random number register can be read and used as a random number. Note that when a random number is read from the random number register, an allowable state in which the random number register is allowed to latch the next random number can be set.

  The verification block C230 executes a security check that is an authenticity check as to whether or not the main control chip C is a legitimate product that has passed the type approval. A signal related to the security check is transmitted via the SC terminal and the BRC terminal. It is configured to be able to transmit to or receive from the external terminal plate.

  The unique information C240 stores a unique identification number written when the main control chip C is manufactured, and the identification number cannot be rewritten. The arithmetic circuit C250 is a circuit that executes four arithmetic operations and logical operations.

<Memory map>
Next, an example of the memory map of the main control chip C shown in FIG. 6 will be described using FIG. The memory map shows an address space from “0000H” to “FFFFH”. Among these, the built-in ROMC 110 is assigned to the space from “0000H” to “27FFH”, and the register area built in each circuit in the main control chip C is assigned to the space from “2800H” to “28FFH”. The internal RAMC 120 is allocated to the space from “F000H” to “F2FFH”, and the XCS decode area (the given machine language is interpreted as an internal representation) in the space from “FDD0H” to “FDFBH”. (Decoding area) is allocated. By causing the CPUC 100 to execute an instruction to access these addresses, it is possible to execute access to the corresponding hardware.

  The built-in ROMC 110 has a first ROM area that is an area that mainly controls the progress of the game, and a second ROM area that is an area that mainly controls processing different from the normal progress of the game such as errors. The first ROM area is assigned to the space from “0000H” to “1FFFH”, and the second ROM area is assigned to the space from “2000H” to “27FFH”. Note that the first ROM area is configured to have a larger capacity than the second ROM area (in other words, the data capacity that exists in the first ROM area and is accessed by the CPUC 100 exists in the second ROM area, and the CPUC100 Configured to be larger than the data capacity accessed from

  The first ROM area stores a first control area in which program code (instruction code set for the CPUC 100) is stored, and program data used by the program (read by processing of the CPUC 100 based on the program code). First data area, an area for storing various identification information (company name, date of manufacture, model name, etc.), and various settings used when operating the main control chip C (operation of the random number generation circuit C140) A program management area in which settings, operation settings of the watchdog timer C222, etc.) are stored. In the figure, the memory map image in the first ROM area is illustrated, but the number of bytes in each area and the presence / absence of an unused area are merely examples.

  The second ROM area stores a second control area in which program codes (instruction code sets for the CPUC 100) are stored, and program data used by the program (read by processing of the CPUC 100 based on the program codes). The second control area is configured to have a capacity smaller than that of the first control area (in other words, the CPUC100 exists in the second control area. The program code capacity accessed from the first control area is smaller than the program code capacity accessed from the CPUC 100), and the second data area is configured to have a smaller capacity than the first data area. (In other words, it exists in the second data area and is accessed from the CPUC 100. Program data capacity is smaller than the program data capacity to be accessed from there to the first data area CPUC100).

  On the other hand, the built-in RAMC 120 is a first RAM area which is an area mainly storing information based on the progress of the game, and a second RAM area which is an area storing information mainly based on processing different from normal progress of the game such as an error related. And a stack area that is used when the program needs to store data internally, and a first RAM area is allocated to the space from “F000H” to “F1FFH”. The second RAM area is allocated to the space from “F200H” to “F2C9H”, and the stack area is allocated to the space from “F2CAH” to “F2FFH” (however, the number of bytes in each area is merely an example) ).

  The first RAM area has a first work area that is a work area for temporarily storing information related to the progress of the game, and the second RAM area temporarily stores information related to errors and the like. And a checksum area that is a work area for performing error detection of information temporarily stored in the first RAM area and the second RAM area. The first RAM area is configured to have a larger capacity than the second RAM area. In this embodiment, only the second RAM area is included in the checksum area (the first RAM area is not included), and the checksum area includes both the first RAM area and the second RAM area ( It is configured to manage a checksum (total of information temporarily stored in both sides). In this embodiment, as will be described later, when calculating the checksum, including the unused area, the calculation is not limited to this. The checksum may be calculated for the work area and the second work area. In addition, the method of performing error detection is not limited to the method of performing checksum check, and a method of performing other methods (for example, parity check) may be used. This is an area for storing information for error detection (for example, parity bits, etc.) required when using the technique.

  It should be noted that there is no problem even if the address of the area in which various kinds of identification information (company name, manufacturing date, model name, etc.) are stored is after the address of the built-in RAM. In addition, although there is no problem if the address that is an unused area is changed, it is preferable to provide an unused area between the first data area and the second control area. That is, in the case of the memory map configuration as shown in FIG. 7, the program code that exists in the first control area and is accessed from the CPUC 100, and the program code that exists in the second control area and is accessed from the CPUC 100 are: Since they are arranged apart from each other on the memory map (with discontinuous addresses) and an unused area is sandwiched between them, the location of both program codes on the program source code or dump list can be viewed visually. It can be clearly separated (the same can be said when an unused area is sandwiched between them).

  Here, the ROM mounted on the main control board M may be configured not to provide an unused area (an unfilled area) in order to prevent a program or the like modified by an illegal act from being written. It is preferable (for example, all unused areas are filled with zeros, and used areas are filled in young addresses and written). In addition, in order to prevent the first control area and the first data area from referring to data that is not normally referred to due to noise or fraudulent behavior, unused data (for example, in a gaming machine with different specifications) It is preferable not to provide data to be used or data used only for testing at the development stage. In addition, the first control area, the first data area, the second control area, the second data area, the first work area, and the second work area are arranged in a young address and used in the area (in the area). (For example, “0010H” to “0050H” in the first control area in the range of “0000H” to “0FA7H” are not used as unused areas). It is preferable to do. In this example, all the bits in the unused area are “0”, and any bit other than the unused area is “1” (not “0”). ing).

  Next, FIGS. 8 to 34 are flowcharts showing a flow of general processing performed by the main control board M in the present embodiment. First, in the flowchart showing the flow of these processes, when the CPUC 100 executes a process based on the program code and program data arranged in the first ROM area, or the processing result is stored in a register (register register) in the CPUC100. (Processing in the first ROM / RAM area) when the processing result is stored (updated) in the area) or the first RAM area, or the processing result is referred to in the processing of the CPUC 100 based on the program code arranged in the first ROM area. As indicated by a dotted line, it is described that the CPU C 100 executes the process “based on data in the first ROM / RAM area”. Further, in the flowchart showing the flow of these processes, when the CPUC 100 executes a process based on the program code and program data arranged in the second ROM area, or the process result is stored in a register (register register) in the CPUC100. (Processing in the second ROM / RAM area) when the processing result is stored (updated) in the area) or the second RAM area, or the processing result is referred to in the processing of the CPUC 100 based on the program code arranged in the second ROM area. As indicated by a dotted line, it is described that the CPU C 100 executes the process “based on data in the second ROM / RAM area”.

  The flowchart is mainly composed of processing steps (illustrated by rectangles), judgments (illustrated by diamonds), flow lines (arrows), terminals indicating start / end / return, etc. (illustrated by rounded rectangles). ing. Moreover, when the details are illustrated in another flowchart among the processing steps, those referring to the other flowchart are illustrated as a subroutine (illustrated by a rectangle in which the left and right lines are double lines). . Here, in the development stage of gaming machines, gaming machines with different specifications are also developed at the same time, but in this example, a subroutine ( (Subroutines that are not normally used) are not left behind, and processing related to unused subroutines that are not normally executed due to noise or fraudulent actions is prevented from being executed.

  And it is a case not following these movements. For example, when the second RAM area is updated or referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area, or conversely, the second ROM area When the first RAM area is updated or referred to in the processing of the CPUC 100 based on the program code arranged in (1), the update / reference destination is specified (or these) Even if it follows the movement, it may be noted as necessary for clarity). It should be noted that, when the processing movements in the embodiment described below are conceptually summarized, the following cases are obtained.

  <Operation 1> The program data arranged in the first ROM area (particularly the first data area) is processed by the CPUC 100 based on the program code arranged in the first ROM area (particularly the first control area). It is read or arranged in the second ROM area (particularly the second data area) by the processing of the CPUC 100 based on the program code arranged in the second ROM area (particularly the second control area). Program data is read out. However, depending on the processing of the CPUC 100 based on the program code arranged in the first ROM area (particularly, the first control area), the program data arranged in the second ROM area (particularly the second data area) is read. Depending on the processing of the CPUC 100 based on the program code arranged in the second ROM area (particularly the second control area), the program arranged in the first ROM area (particularly the first data area) Data is not read out.

  <Operation 2> The first RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and program data arranged in the first ROM area. Further, the second RAM area is updated and referred to by the processing of the CPUC 100 based on the program code and program data arranged in the second ROM area.

  <Operation 3> The processing of the CPUC 100 based on the program code arranged in the second ROM area can be executed by a calling instruction (for example, a CALL instruction called mnemonic) in the program code arranged in the first ROM area. The CPUC 100 based on the program code arranged in the first ROM area cannot be executed by a calling instruction (for example, a CALL instruction called mnemonic) in the program code arranged in the second ROM area. That is, the program code arranged in the first ROM area and the program code arranged in the second ROM area are in a master-slave relationship, and a call instruction in the program code arranged in the main first ROM area. Only when there is, the CPU C 100 can be executed based on the program code arranged in the secondary second ROM area.

  <Operation 4> When there is a call instruction in the program code arranged in the main first ROM area and the processing of the CPUC 100 based on the program code arranged in the subordinate second ROM area is executed, When the CPUC 100 executes the process based on the program code arranged in the slave second ROM area, information stored at the time when the call instruction is issued (for example, information in the register area) is referred to. Alternatively, after the processing of the CPUC 100 based on the program code arranged in the subordinate second ROM area is executed, the processing returns to the processing of the CPUC100 based on the program code arranged in the main first ROM area. When executing the processing of the CPUC 100 based on the program code arranged in the main first ROM area, information stored at the time of return (for example, information in the register area) is referred to.

  <Operation 5> In the above <Operation 4>, when the information in the register area is not referred to, <Operation 5-1> Processing result of the CPUC 100 based on the program code arranged in the main first ROM area Is stored in the first RAM area, and the processing result stored in the first RAM area can be referred to and updated when the CPUC 100 executes the process based on the program code arranged in the secondary ROM area. (Refer to the updated first RAM area when the process of the CPUC 100 is restored based on the program code arranged in the main first ROM area) <Operation 5-2> Main first ROM area The processing result of the CPUC 100 based on the program code arranged in is stored in the first RAM area, and the slave When executing the processing of the CPUC 100 based on the program code arranged in the second ROM area, the processing result stored in the first RAM area can be referred to and is arranged in the subordinate second ROM area. The processing result of the CPUC 100 based on the program code is stored in the second RAM area, and is stored in the second RAM area when the processing of the CPUC 100 based on the program code arranged in the main first ROM area is restored. It is possible to refer to the processing result that has been made available.

  Based on the above assumption (premise for explanation), a general flow of processing performed by the main control board M will be explained. <Operation 1> to <Operation 3> described above > Is an indispensable premise, while <Action 4> and <Action 5> are sorted by the implementation method of how the processing results in the CPUC 100 are inherited between program codes in a master-slave relationship. Since it is a premise that can be selected, even if only one of <Operation 4> and <Operation 5> is exemplified in the following processing flow, it can be replaced with the other. It supplements beforehand.

  First, FIG. 8 is a flowchart showing a flow of processing executed for the first time by the CPUC 100 of the main control board M after turning on the power of the rotating game machine P (or at the time of system reset or user reset). . In this case, generally, the program code is executed in order from the program code arranged at the address (that is, the first control area) of 0000H in the built-in ROMC 110. Note that, depending on the configuration of the main control chip C on the main control board M, the above-described security check is executed after turning on the power of the spinning machine P (or at the time of system reset or user reset). In some cases, it can be assumed that the program code for executing the security check is configured to be executed first, but even in such a configuration, the program code is arranged in the first control area shown in the present embodiment. (In addition, even if the initial address of the built-in ROMC 110 is not 0000H, it does not change to the overall configuration of the above-described memory map = each address.) Only deviate as appropriate). In the present embodiment, backup power is supplied to the built-in RAMC 120 so that data stored in the built-in RAMC 120 is retained even when the power is turned off.

<Processing in the first ROM / RAM area>
First, after turning on the power of the revolving game machine P in step 1000, the CPUC 100 sets a timer interrupt based on the data in the first ROM / RAM area in step 1002 (here, the type of timer interrupt) In the subsequent processing, when a timer interrupt is started, a flowchart related to timer interrupt processing described later is periodically executed). Next, in step 1004, the CPUC 100 executes the function setting of the main control chip C based on the data in the first ROM / RAM area. Next, in step 1006, the CPUC 100 calls a power-off recovery process for the second ROM area.

<Processing in the second ROM / RAM area>
Next, in step 1008, the CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the checksum area based on the data in the first ROM / RAM area. Next, in step 1010, the CPUC 100 checks the first RAM and the second RAM based on the data in the first ROM / RAM area (for example, the calculated checksum and the checksum data held in the checksum area). Based on the above, it is checked whether or not the data stored in the built-in RAMC 120 is correctly held by the power-off / power-off recovery), and the power-off recovery data is generated (the result of the check and the process at the time of power-off in step 1800) And is stored in the second RAM area). Next, in Step 1012, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to Step 1014.

<Processing in the first ROM / RAM area>
Next, in step 1014, the CPUC 100 confirms the switch states of the front door switch D80, the setting door switch M10, and the setting key switch M20 based on the data in the first ROM / RAM area. Next, in step 1016, the CPUC 100 refers to the data in the first ROM / RAM area and determines whether any of the door switch D80, the setting door switch M10, and the setting key switch M20 is OFF. In the case of Yes in Step 1016, in Step 1018, the CPUC 100 calls the non-setting change initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to Step 1022. On the other hand, in the case of No in step 1016, in step 1020, the CPUC 100 calls the setting change initialization process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1030.

<Processing in the second ROM / RAM area>
Next, in step 1022, the CPUC 100 turns on / off the power-off processing completion flag in the first RAM (turned on in step 1904) and the checksum state of all RAMs (based on the data in the second ROM / RAM area). With reference to the check result in step 1010), it is determined whether or not the power-off recovery data in the second RAM is normal. In the case of Yes in step 1022, in step 1026, the CPUC 100 sets a backup error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area. On the other hand, in the case of No in step 1022, in step 1028, based on the data in the second ROM / RAM area, the CPUC 100 sets the initialization range of the first RAM and the second RAM to the unused RAM range (shown in the box outside the figure). The unused area in the 1RAM area and the unused area in the second RAM area are determined and set (for example, set in the register area), and the process proceeds to step 1036.

  On the other hand, after the processing in step 1020, in step 1030, based on the data in the second ROM / RAM area, the CPUC 100 turns on / off the power-off processing completion flag in the first RAM (turned on in step 1904) and all of them. With reference to the checksum state of the RAM (check result in step 1010), it is determined whether or not the power-off recovery data in the second RAM is normal. In the case of Yes in step 1030, in step 1032 the CPUC 100 determines and sets the initialization range of the first RAM and the second RAM to all ranges except the set value in the RAM based on the data in the second ROM / RAM area. (For example, set in the register area), the process proceeds to step 1036. The set value is stored at the top address of the first RAM area. On the other hand, in the case of No in step 1030, in step 1034, based on the data in the second ROM / RAM area, the CPUC 100 determines and sets the initialization range of the first RAM and the second RAM to all the ranges of the RAM (for example, , Set in the register area), and go to Step 1036.

  Next, in step 1036, the CPUC 100 executes initialization of only the second RAM area within the determined initialization range based on the data in the second ROM / RAM area. Next, in step 1038, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1040.

<Processing in the first ROM / RAM area>
Next, in Step 1040, the CPUC 100 executes initialization of only the first RAM area within the initialization range determined in Step 1028, Step 1032 or Step 1034 based on the data in the first ROM / RAM area. Next, in step 1041, the CPUC 100 determines whether any of the front door switch D80, the setting door switch M10, and the setting key switch M20 is OFF based on the data in the first ROM / RAM area. In the case of Yes in Step 1041, in Step 1042, the CPUC 100 calls the setting value check process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to Step 1044. On the other hand, in the case of No in step 1041, in step 1100, the CPUC 100 executes a setting change device control process (also referred to as a setting change process), which will be described later, based on the data in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
Next, in step 1044, the CPUC 100 refers to the first RAM area based on the data in the second ROM / RAM area, and the data related to the set value in the first RAM area is within the normal range (in this example, 1 to 1). 6) It is determined whether or not. In the case of Yes in Step 1044, in Step 1046, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to Step 1050. On the other hand, in the case of No in step 1044, in step 1048, the CPUC 100 sets a setting value error display (for example, displayed on the payout number display device D190) based on the data in the second ROM / RAM area. (For example, set in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1050, the CPUC 100 restores the stack pointer based on the data related to the stack pointer saved in the power-off process (step 1902) based on the data in the first ROM / RAM area. Next, in step 1052, the CPUC 100 reads the input port based on the data in the first ROM / RAM area. Next, in step 1054, the CPUC 100 starts the timer interrupt set in step 1002 based on the data in the first ROM / RAM area. Next, in step 1056, the CPUC 100 turns off the power-off processing completion flag in the flag area in the first ROM / RAM area, and returns to the processing at the time of power-off according to the returned stack pointer.

  Although not shown, it is preferable that the initial value (value at the start of processing) of the temporary storage area (RAM area or the like) mounted on the main control board M is not a value at which a special game is executed. (In order to prevent a special game from being erroneously executed when a process for determining whether or not to execute a special game is executed due to noise or fraud immediately after the program processing is started). Although not shown, when a random number such as a winning random number is stored in the RAM area of the main control board M, a dedicated storage area is secured and the byte storing information on the random number is stored in the byte. It is preferable to configure to store only the information related to the random number (not to store other information such as various timer values) (when operating other data stored in the same 1 byte, due to noise etc. (To prevent the information related to random numbers from being rewritten).

<Processing in the first ROM / RAM area>
Next, FIG. 9 is a flowchart of the setting change device control process according to the subroutine of step 1100 in FIG. First, in step 1102, the CPUC 100 sets a stack pointer based on the data in the first ROM / RAM area (initialized with the start address of the process). Next, in step 1118, the CPUC 100 starts a timer interrupt based on the data in the first ROM / RAM area. Next, in step 1120, the CPUC 100 refers to the data in the first ROM / RAM area, and determines whether or not the set value in the first RAM area is within the normal range (1 to 6 in this example). . In the case of Yes in Step 1120, in Step 1122, the CPUC 100 sets a predetermined value (for example, 1 = value that is most disadvantageous for the player) as a setting value based on the data in the first ROM / RAM area, and Step 1124. Migrate to On the other hand, also in the case of No in step 1120, the process proceeds to step 1124. Next, in step 1124, based on the data in the first ROM / RAM area, the CPUC 100 displays on the error display LED (not shown) that the setting changing device is operating, and sets the setting display LED (not shown). The value is displayed and the process proceeds to step 1126.

  Next, in step 1126, the CPUC 100 determines whether or not the setting / reset button M30 has been switched from OFF to ON based on the data in the first ROM / RAM area. In the case of Yes in step 1126, in step 1128, the CPUC 100 adds 1 to the current set value based on the data in the first ROM / RAM area (if the added set value exceeds 6, the setting is made. The value becomes 1), and the process proceeds to Step 1130. In the case of No in step 1126, the process proceeds to step 1130. Next, in step 1130, the CPUC 100 determines whether or not the start lever D50 has been switched from OFF to ON based on the data in the first ROM / RAM area. In the case of Yes in step 1130, in step 1132, the CPUC 100 determines whether or not the setting key switch M20 has been switched from on to off based on the data in the first ROM / RAM area. If No in step 1132, the process in step 1132 is looped. On the other hand, in the case of Yes in step 1132, in step 1134, based on the data in the first ROM / RAM area, the CPUC 100 displays on the error display LED (not shown) that the operation of the setting change device has ended, and displays the setting display. The display of the set value of the LED (not shown) is erased, and the process proceeds to a game progress control process in step 1200. In the case of No in step 1130, the process proceeds to step 1126.

<Processing in the first ROM / RAM area>
Next, FIG. 10 is a flowchart of the game progress control process (first sheet) according to the subroutine of step 1200 in FIG. First, in step 1202, the CPUC 100 sets a stack pointer based on the data in the first ROM / RAM area (initialized with the start address of the process). Next, in step 1204, the CPUC 100 sets data in the first RAM area necessary for the game (for example, an upper limit number of bets, an effective line for winning, etc.) based on the data in the first ROM / RAM area. Next, in step 1206, the CPUC 100 sets a gaming state in the game (for example, during a normal game, during a big hit game, during a replay probability variation game, during an AT game, etc.) based on the data in the first ROM / RAM area. To do. Next, in step 1208, the CPUC 100 determines whether or not the medal payout device H is full of game medals based on the data in the first ROM / RAM area. Specifically, a subtank (not shown) for storing medals overflowing from the medal payout device H is provided, and a determination is made based on current conduction / non-conduction by a plurality of full detection sensors provided in the subtank (via the medal). If the current is conducted, it is determined to be full). If Yes in step 1208, the process proceeds to step 1218.

  On the other hand, in the case of No in step 1208, in step 1210, the CPUC 100 turns on the medal full error flag based on the data in the first ROM / RAM area (for example, turns on the medal full error flag area in the first RAM area). Update with a value equivalent to Next, in step 1212, the CPUC 100 displays an error number corresponding to the medal full error with a 7-segment LED (for example, a storage display LED or an acquired number LED) based on the data in the first ROM / RAM area. Next, in step 1214, the CPUC 100 refers to the data in the first ROM / RAM area to determine whether or not the medal full error has been canceled (for example, the current through the sub tank is non-conductive and the setting / reset button M30 is Whether or not it has been pressed). In the case of Yes in step 1214, in step 1216, the CPUC 100 turns off the medal full error flag based on the data in the first ROM / RAM area (for example, this corresponds to turning off the medal full error flag area in the first RAM area). Update with the value), and go to Step 1218. On the other hand, in the case of No in step 1214, the process proceeds to step 1212. Next, in step 1218, the CPUC 100 permits the medal insertion acceptance based on the data in the first ROM / RAM area (the insertion operation is automatically executed in the next game of the replay). The process proceeds to (the process of step 1220). Here, in Step 1218, the blocker D100 is turned on (process formed by the medal flow path). Specifically, when a re-game player is established in the previous game, the blocker D100 is turned on on the condition that the current storage number (credit) is less than a predetermined value (50 in this example). Run. In other words, when the current storage number (credit) is a predetermined value, the ON process of the blocker D100 is not executed. On the other hand, when the re-game combination is not established in the previous game, the blocker D100 is turned on uniformly. With this configuration, even when a re-game is established, if the number of stored credits (credits) has not reached a predetermined value, a game medal can be inserted. Replays that are difficult to understand as replays when you are staying in an RT state with a high game probability (replays that appear to be small roles: bell-bell-bell on the invalid line, or cherry on the left reel stops The player can play the game with a good rhythm (without a sense of incongruity) even when the symbol combination) is stopped.

<Processing in the first ROM / RAM area>
Next, FIG. 11 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in FIG. First, in step 1220, the CPUC 100 determines whether or not a game medal is bet and no credit exists based on the data in the first ROM / RAM area. In the case of Yes in step 1220, in step 1221 the CPUC 100 satisfies the setting display conditions based on the data in the first ROM / RAM area (for example, the door switch D80, the setting door switch M10, and the setting key switch M20 are It is determined whether or not the condition is satisfied if all are turned on. In the case of Yes in step 1221, in step 1222, the CPUC 100 sets the setting display LED (not shown, but the payout number display device D190, the credit number display device D200, the insertion number display light D210 based on the data in the first ROM / RAM area. The setting value may be displayed on the screen, and the process proceeds to step 1221. In the case of No in Step 1220 or Step 1221, in Step 1224, the CPUC 100 executes management related to game medal insertion and settlement based on the data in the first ROM / RAM area. Next, in step 1225, the CPUC 100 confirms the number of game medals that can be accepted based on the data in the first ROM / RAM area. Next, in step 1226, the CPUC 100 determines whether or not the blocker D100 is on based on the data in the first ROM / RAM area. In the case of Yes in step 1226, in step 1227, the CPUC 100 determines whether or not the first input sensor D20s or the second input sensor D30s is on based on the data in the first ROM / RAM area (first input). When the sensor D20s or the second insertion sensor D30s is turned on, it is determined that one game medal has been received). In the case of Yes in step 1227, in step 1228, the CPUC 100 calls the medal insertion error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1400.

<Processing in the second ROM / RAM area>
Next, in step 1400, the CPUC 100 executes medal insertion error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1229, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1230.

<Processing in the first ROM / RAM area>
Next, in step 1230, the CPUC 100 determines whether or not the first input sensor D20s and the second input sensor D30s are off based on the data in the first ROM / RAM area (the first input sensor D20s or the first input sensor D20s). When the first insertion sensor D20s and the second insertion sensor D30s are turned off after the second insertion sensor D30s is turned on, the received one game medal passes through the first insertion sensor D20s and the second insertion sensor D30s. judge). In the case of Yes in step 1230, in step 1231, the CPUC 100 determines that one normal game medal has been inserted based on the data in the first ROM / RAM area. Although not shown, after step 1231, the CPUC 100 determines that the credit is the upper limit (50 in this example) and the maximum bet (3 in this example) based on the data in the first ROM / RAM area. ) Is determined, and if the determination is Yes, the blocker D100 is controlled to be off (a state where no medal flow path is formed). In the case of No in step 1230, the process proceeds to step 1228, and in the case of No in step 1226 or step 1227, the process proceeds to step 1232.

  Next, in Step 1232, the CPUC 100 determines whether or not the settlement button D60 has been operated based on the data in the first ROM / RAM area. In the case of Yes in Step 1232, in Step 1233, the CPUC 100 determines whether or not there is a remaining number of credits or a betting game medal based on the data in the first ROM / RAM area. In the case of Yes in step 1233, in step 1234, the CPUC 100 turns on when a hopper drive flag (a flag in the first RAM area and the hopper motor H80 is driven) based on the data in the first ROM / RAM area. (Flag) is turned on, and one game medal is paid out. Next, in step 1236, the CPUC 100 refers to the data in the first ROM / RAM area and determines whether or not the first payout sensor H10s or the second payout sensor H20s is ON (the first payout sensor H10s or When the second payout sensor H20s is turned on, it is determined that a payout operation for one game medal is being performed). In the case of Yes in step 1236, in step 1238, the CPUC 100 calls a medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1450. Here, although not explicitly shown in the flowchart, only the remaining number of credits is to be settled when the previous game was a re-game player.

<Processing in the second ROM / RAM area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1240, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1247.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 1236, in step 1241, the CPUC 100 has passed a predetermined time (for example, 5 seconds) after driving the hopper (after the processing timing in step 1234) based on the data in the first ROM / RAM area. It is determined whether or not. Specifically, whether or not a situation in which it is determined that a medal has not been paid out has continued for a predetermined period of time despite transmission of a hopper drive signal to the hopper motor H80 (the hopper motor H80 is rotating). Determine whether or not. In the case of Yes in step 1241, in step 1242, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM / RAM area (for example, equivalent to turning on the medal empty error flag area in the first RAM area). Update with the value you want). Next, in step 1244, the CPUC 100 executes a medal empty error display based on the data in the first ROM / RAM area. Next, in step 1245, the CPUC 100 determines whether or not the medal empty error has been canceled based on the data in the first ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). If YES in step 1245, in step 1246, the CPUC 100 turns off the medal empty error flag in the flag area in the first ROM / RAM area (for example, turns off the medal empty error flag area in the first RAM area). Update to the corresponding value), and the process proceeds to step 1247. On the other hand, if No at step 1245, the process proceeds to step 1244.

<Processing in the first ROM / RAM area>
Next, in step 1247, the CPUC 100 determines whether or not the first payout sensor H10s and the second payout sensor H20s are off based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the first payout sensor H10s and the second payout sensor H20s are turned off after the two payout sensors H20s are turned on, it is determined that the payout operation of one game medal on which the payout operation has been performed is completed. In the case of Yes in step 1247, in step 1248, the CPUC 100 turns off the hopper driving flag based on the data in the first ROM / RAM area, and proceeds to step 1233. If step 1241 or step 1247 is No, the process proceeds to step 1236.

  On the other hand, in the case of No in step 1232 or step 1233, in step 1249, the CPUC 100 calls the second ROM area loading / dispensing error detection processing based on the data in the first ROM / RAM area, and proceeds to step 1500.

<Processing in the second ROM / RAM area>
Next, in step 1500, the CPUC 100 executes a loading / dispensing error detection process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1250, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1251.

<Processing in the first ROM / RAM area>
Next, in step 1251, the CPUC 100 determines that the start lever D50 is valid based on the data in the first ROM / RAM area (for example, a prescribed number of game medals for starting the game are inserted), and Then, it is determined whether or not the start lever D50 has been operated. In the case of Yes in step 1251, in step 1252, the CPUC 100 executes a process of obtaining a random number and turning off the blocker D100 based on data in the first ROM / RAM area, and then performing a setting value check process for the second ROM area. Call and go to step 1253.

<Processing in the second ROM / RAM area>
Next, in step 1253, the CPUC 100 determines whether or not the set value in the first RAM area is within the normal range (1 to 6 in this example) based on the data in the second ROM / RAM area. In the case of Yes in step 1253, in step 1254, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to the next process (process in step 1257). On the other hand, in the case of No in step 1253, in step 1256, the CPUC 100 sets a setting value error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 12 is a flowchart of the game progress control process (third sheet) according to the subroutine of step 1200 in FIG. First, in step 1257, the CPUC 100 starts an internal lottery (lottery for determining a winning combination in the game) based on the data in the first ROM / RAM area. Next, in step 1258, the CPUC 100 starts rotation of all reels (reel M50) based on the data in the first ROM / RAM area, and proceeds to step 1260. Next, in step 1260, the CPUC 100 makes a pull-in point creation request (request to determine the stop positions of the rotating left reel M51, middle reel M52, and right reel M53 based on the data in the first ROM / RAM area. It is determined whether or not there has been a request as appropriate depending on the stop order and the stop position of the other reels. In the case of Yes in Step 1260, in Step 1261, the CPUC 100 creates a pull-in point based on the data in the first ROM / RAM area, and proceeds to Step 1262. On the other hand, also in the case of No in step 1260, the process proceeds to step 1262. Next, in step 1262, the CPUC 100 executes a reel stop acceptability check based on the data in the first ROM / RAM area. Next, in step 1263, the CPUC 100 determines whether or not any stop button (left stop button D41, middle stop button D42, right stop button D43) has been operated based on the data in the first ROM / RAM area. To do. In the case of Yes in step 1263, in step 1264, the CPUC 100, based on the data in the first ROM / RAM area, corresponds to the operated stop button (for example, the left stop button D41 corresponds to the left reel M51). Is determined, and the process proceeds to step 1265. On the other hand, also in the case of No in step 1263, the process proceeds to step 1265. Next, in step 1265, the CPUC 100 executes an all reel stop check process based on the data in the first ROM / RAM area. Next, in step 1266, the CPUC 100 determines whether or not all the reels (the left reel M51, the middle reel M52, and the right reel M53) are stopped based on the data in the first ROM / RAM area. In the case of Yes in step 1266, in step 1267, the CPUC 100 calls the display determination check process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1268. If No in step 1266, the process proceeds to step 1260.

<Processing in the second ROM / RAM area>
Next, in step 1268, the CPUC 100 compares the symbol stop position data in the first RAM with the internal established combination stop position data based on the data in the second ROM / RAM area. Next, in step 1269, the CPUC 100 refers to the data in the second ROM / RAM area and determines whether or not the displayed symbol combination is normal (the winning combination determined by the internal lottery is determined). Is determined to be abnormal). In the case of Yes in step 1269, in step 1500, the CPUC 100 executes a loading / dispensing error detection process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1270, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1274. On the other hand, in the case of No in step 1269, in step 1272, the CPUC 100 sets a display determination error display based on the data in the second ROM / RAM area (for example, in the register area). Next, in step 1300, the CPUC 100 executes non-recoverable error processing, which will be described later, based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1274, the CPUC 100 executes a game medal payout process by winning based on the data in the first ROM / RAM area. Next, in step 1275, the CPUC 100 determines whether or not there has been a prize for paying out a game medal based on the data in the first ROM / RAM area {the game medal acquired by winning the prize is the maximum number of credits (this example) Then, when 50) is exceeded, game medals are paid out}. In the case of Yes in step 1275, in step 1276, based on the data in the first ROM / RAM area, the CPUC 100 turns on when the hopper driving flag (the flag in the first RAM area and the hopper motor H80 is being driven). (Flag) is turned on, and one game medal is paid out. Next, in step 1277, the CPUC 100 determines whether or not the first payout sensor H10s or the second payout sensor H20s is on based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the two payout sensor H20s is turned on, it is determined that a payout operation for one game medal is being performed). In the case of Yes in step 1277, in step 1278, the CPUC 100 calls a medal payout error detection process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1450.

<Processing in the second ROM / RAM area>
Next, in step 1450, the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1284, the CPUC 100 returns to the caller in the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1286.

<Processing in the first ROM / RAM area>
On the other hand, in the case of No in step 1277, in step 1279, based on the data in the first ROM / RAM area, the CPUC 100 has passed a predetermined time (for example, 5 seconds) after driving the hopper (after the processing timing of step 1276). It is determined whether or not. In the case of Yes in step 1279, in step 1280, the CPUC 100 turns on the medal empty error flag based on the data in the first ROM / RAM area (for example, equivalent to turning on the medal empty error flag area in the first RAM area). Update with the value you want). Next, in step 1281, the CPUC 100 executes a medal empty error display with a 7-segment LED based on the data in the first ROM / RAM area. Next, in step 1282, the CPUC 100 determines whether or not the medal empty error has been canceled based on the data in the first ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1282, in step 1283, the CPUC 100 turns off the medal empty error flag based on the data in the first ROM / RAM area (for example, this corresponds to turning off the medal empty error flag area in the first RAM area). Update with the value) and go to Step 1286. On the other hand, if No in step 1282, the process proceeds to step 1281.

<Processing in the first ROM / RAM area>
Next, in step 1286, the CPUC 100 determines whether or not the first payout sensor H10s and the second payout sensor H20s are off based on the data in the first ROM / RAM area (the first payout sensor H10s or the first payout sensor H10s). When the first payout sensor H10s and the second payout sensor H20s are turned off after the two payout sensors H20s are turned on, it is determined that the payout operation of one game medal on which the payout operation has been performed is completed. In the case of Yes in Step 1286, in Step 1288, the CPUC 100 turns off the hopper driving flag based on the data in the first ROM / RAM area, and proceeds to Step 1290. If No in step 1279 or step 1286, the process proceeds to step 1277. Next, in step 1290, the CPUC 100 determines whether or not the payout corresponding to the winning (the winning that becomes Yes in step 1275) is completed based on the data in the first ROM / RAM area. In the case of Yes in step 1290, in step 1292, the CPUC 100 executes game end processing (for example, clearing the number of bets, game state transition processing, etc.) based on the data in the first ROM / RAM area, and the next processing The process proceeds to (Step 1202). If No in step 1286, the process proceeds to step 1277. If No in step 1275, the process proceeds to step 1292.

<Processing in the first ROM / RAM area>
Next, FIG. 13 is a flowchart of non-recoverable error processing relating to the subroutine of step 1300 in FIG. 8 (and called in other flowcharts). First, in step 1302, the CPUC 100 prohibits an interrupt based on the data in the first ROM / RAM area (hereinafter, a flowchart relating to a timer interrupt process described later is not executed). Next, in step 1304, the CPUC 100 sets the output port address and the number of output ports based on the data in the first ROM / RAM area. Next, in step 1306, the CPUC 100 turns off the output port (0 to 6 in this example, display output to various LEDs and drive output to various motors) based on the data in the first ROM / RAM area. To. Next, in step 1308, the CPUC 100 sets the next port output address based on the data in the first ROM / RAM area (by repeating this, the display output to various LEDs and the drive output to various motors are sequentially stopped. ) Next, in step 1310, the CPUC 100 determines whether or not the output to each output port is completed based on the data in the first ROM / RAM area. In the case of Yes in step 1310, in step 1312, the CPUC 100 executes the set error display based on the data in the first ROM / RAM area (some error occurs when executing this process). If the power supply voltage is lowered, the reset signal is input and the process ends. (That is, since an infinite loop is entered, any operation that prompts a return is not accepted). In the case of No in step 1310, the process proceeds to step 1306. The processing from step 1306 to step 1310 is processing for clearing the output to the LED / motor (however, since the external output signal is not cleared, information about the error, game progress status at the time of the error, etc. are displayed on the hall computer side. It is possible to output to

<Processing in the second ROM / RAM area>
Next, FIG. 14 is a flowchart of medal insertion error detection processing according to the subroutine of step 1400 in FIG. First, in step 1402, the CPUC 100 sets the inserted medal backflow error flag (a flag turned on in step 1706, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1402, in step 1404, the CPUC 100 determines that the inserted medal backflow error (an error caused by the backflow of the inserted game medal is based on the data in the second ROM / RAM area. D20s off and the second throwing sensor D30s on → an error occurs when the first throwing sensor D20s is on and the second throwing sensor D30s is on). Next, the CPUC 100 determines whether or not the inserted medal error backflow error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1406, in step 1408, the CPUC 100 turns off the inserted medal backflow error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

  On the other hand, in the case of No in step 1402, in step 1410, based on the data in the second ROM / RAM area, the CPUC 100 is an inserted medal retention error flag (turned on in step 1710. In this embodiment, It is determined whether the flag in the 2RAM area is ON. In the case of Yes in step 1410, in step 1412, the CPUC 100 determines that the inserted medal retention error (the error caused by the inserted game medal remaining) based on the data in the second ROM / RAM area, for example, the first insertion sensor D20s on and the second input sensor D30s on is an error when the state continues for a predetermined time). Next, in step 1414, the CPUC 100 determines whether or not the inserted medal staying error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1414, in step 1416, the CPUC 100 turns off the inserted medal staying error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

  On the other hand, in the case of No in step 1410, in step 1418, the CPUC 100 is based on the data in the second ROM / RAM area, and is an insertion number error flag (a flag that is turned on in step 1716. In this embodiment, the second RAM It is determined whether or not the flag in the area is on. In the case of Yes in step 1418, in step 1420, the CPUC 100, based on the data in the second ROM / RAM area, causes an inserted number error (because the number of inserted game medals and the number of game medals successfully passed do not match). (For example, an error occurs when the number of game medals detected by the insertion acceptance sensor D10s and the number of game medals detected by the second insertion sensor D30s do not match or are outside a predetermined allowable range.) Execute the display. Next, in step 1422, the CPUC 100 determines whether or not the insertion number error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1422, in step 1424, the CPUC 100 turns off the insertion number error flag based on the data in the second ROM / RAM area, and proceeds to the next processing (processing in step 1229).

<Processing in the second ROM / RAM area>
Next, FIG. 15 is a flowchart of medal payout error detection processing according to the subroutine of step 1450 in FIGS. 11 and 12. First, in step 1452, the CPUC 100 sets a payout medal retention error flag (a flag turned on in step 1756, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1452, in step 1456, the CPUC 100 is based on the data in the second ROM / RAM area, and is a payout medal retention error (an error caused by the payout game medal remaining, for example, the first payout Display is performed when the sensor H10s is on and the second payout sensor H20s is on for a predetermined time. Next, in step 1458, the CPUC 100 determines whether or not the payout medal retention error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1458, in step 1460, the CPUC 100 turns off the payout medal retention error flag based on the data in the second ROM / RAM area, and proceeds to the next process (the process of step 1240 or step 1284).

<Processing in the second ROM / RAM area>
Next, FIG. 16 is a flowchart of the input / withdrawal error detection process according to the subroutine of step 1500 in FIGS. 11 and 12. First, in step 1502, the CPUC 100 turns on an abnormal insertion error flag (a flag that is turned on in step 1806, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. It is determined whether or not. In the case of Yes in step 1502, in step 1504, the CPUC 100 detects an abnormal insertion error (error due to detection of insertion of a game medal at a timing when a game medal should not be inserted) based on the data in the second ROM / RAM area. Execute the display. Next, in step 1506, the CPUC 100 determines whether or not the abnormal insertion error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1506, in step 1508, the CPUC 100 turns off the abnormal insertion error flag based on the data in the second ROM / RAM area, and proceeds to step 1510. In the case of No in step 1502, the process proceeds to step 1510.

  Next, in step 1510, the CPUC 100 sets an abnormal payout error flag (a flag that is turned on in step 1816, in the present embodiment, a flag in the second RAM area) based on the data in the second ROM / RAM area. Determine whether it is on. In the case of Yes in step 1510, in step 1514, the CPUC 100 detects an abnormal payout error (error due to detection of a game medal payout at a timing at which a game medal should not be paid out) based on the data in the second ROM / RAM area. ) Execute the display. Next, in step 1516, the CPUC 100 determines whether or not the abnormal payout error has been canceled based on the data in the second ROM / RAM area (for example, whether or not the set / reset button M30 has been pressed). In the case of Yes in step 1516, in step 1518, the CPUC 100 turns off the abnormal payout error flag based on the data in the second ROM / RAM area, and proceeds to the next process (the process of step 1250 or step 1270). Even in the case of No in step 1510, the process proceeds to the next process (the process in step 1250 or step 1270).

  Next, FIG. 17 is a flowchart of processing at the time of timer interruption according to the subroutine of step 1600 in the present embodiment. The processing of the subroutine is started when a timer interrupt is started in the processing of step 1054 or step 1118, and thereafter, a predetermined time (in this example, T is set, but a time of about 2 ms is set, for example) To be periodically executed.

<Processing in the first ROM / RAM area>
First, in step 1602, the CPUC 100 performs processing at the start of an interrupt (for example, saving of data held in a register in the CPUC100, input port check of a power-off detection signal, etc.) based on data in the first ROM / RAM area. ). Next, in step 1604, the CPUC 100 determines whether or not a power-off is currently detected (in the current interrupt process) based on the data in the first ROM / RAM area. In the case of No in step 1604, in step 1900, the CPUC 100 executes a power-off process, which will be described later, based on the data in the first ROM / RAM area. On the other hand, in the case of Yes in step 1604, in step 1606, the CPUC 100 starts timer measurement (update processing of various timers managed by software) based on the data in the first ROM / RAM area. Next, in step 1608, the CPUC 100 generates input port data based on the data in the first ROM / RAM area, and stores the data (updates the storage area of each input port data in the first RAM area). ). Here, the input port data includes the settlement button D60, the start lever D50, the stop button D40, the front door switch D80, the setting door switch M10, the setting key switch M20, the setting / reset button M30, the power-off detection signal, and the input acceptance sensor. D10s, the first input sensor D20s, the second input sensor D30s, the first payout sensor H10s, the second payout sensor H20s, and the like (that is, whether or not there is an operation on these operation members and the sensor detection state is information). , Sampled at interrupt interval T).

  Next, in step 1610, the CPUC 100 refers to the input port data in the first RAM area based on the data in the first ROM / RAM area, and sets the front door switch flag and the setting according to the sampling result of each input port data. Switch on / off of door switch flag and setting key switch flag (for example, turn on the front door switch flag when the switch state of the front door switch D80 is continuously on over a plurality of samplings) Thus, it can be detected that the front door DU is open without being affected by noise). Next, in step 1612, the CPUC 100 performs rotation drive control processing (reel M50 drive control) for all reels (left reel M51, middle reel M52, right reel M53) based on data in the first ROM / RAM area. This processing is executed. Next, in step 1614, the CPUC 100 outputs the output data to the output port based on the data in the first ROM / RAM area. Here, the output data is data for driving the reel M50, the blocker D100, and the like. In step 1616, the CPUC 100 calls an error check process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1700.

<Processing in the second ROM / RAM area>
Next, in step 1700, the CPUC 100 executes a medal insertion check process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1750, the CPUC 100 executes a medal payout check, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1800, the CPUC 100 executes an input / withdrawal error check process, which will be described later, based on the data in the second ROM / RAM area. Next, in step 1618, the CPUC 100 turns off all error flags based on the data in the second ROM / RAM area (inserted medal backflow flag, inserted number error flag, medal retention error flag, inserted abnormal error flag, payout error). It is determined whether the error flag, the payout medal retention error flag, the door switch flag, and the like are all off (however, in the present embodiment, the door switch flag is within the first RAM area). Since it is stored, it is determined with reference to the first RAM area). In the case of Yes in step 1618, in step 1620, based on the data in the second ROM / RAM area, the CPUC 100 issues an error non-detection command (a command to the sub-side indicating that no error has been detected). Set (for example, set in the register area), and go to Step 1624. On the other hand, in the case of No in step 1618, in step 1622, the CPUC 100 determines an error detection command (a command to the sub side and an error is detected) based on the data in the second ROM / RAM area. Is set (for example, in the register area), and the process proceeds to Step 1624. In step 1622, information related to an error (currently occurring error) corresponding to the error flag that is turned on is transmitted to the sub-side. The error not detected command may be set only when the error is released from the state where the error has occurred (only when it is determined that the flag is turned off). The information setting process may not be executed (S1620 may not be provided). Further, the error detection command may execute the set process only when an error occurs from a state where no error has occurred, or from the state where a first error (for example, a inserted medal retention error) has occurred. The set process may be executed when the type of error has changed, such as a second error (for example, a payout medal retention error). Next, in step 1624, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1626.

<Processing in the first ROM / RAM area>
Next, in step 1626, the CPUC 100 transmits a control command (sub-side command) based on the data in the first ROM / RAM area (for example, when it is set in the register area in step 1620 or step 1622). Will take over the set control command). Next, in step 1628, the CPUC 100 outputs an external signal (a signal for transmitting information from the spinning machine P to an external hall computer or the like) based on the data in the first ROM / RAM area. The information related to the error output by the external signal includes a door opening error, a closing abnormality error, a dispensing abnormality error, a setting door opening error (not shown), a closing reception sensor retention error (not shown), etc. Is output. The door opening error is configured to be an error when the front door DU is opened and the door switch flag is turned on, and the setting door opening error is set and the setting door switch flag is turned on. If the insertion acceptance sensor detects that a game medal has accumulated, an error will be generated. Next, in step 1630, the CPUC 100 outputs LED (7-segment LED lamp, etc.) output data (for example, a predetermined 7-segment LED among a plurality of 7-segment LED units) based on the data in the first ROM / RAM area. The unit is turned on and a predetermined segment of 7 segments is turned on) (so-called dynamic lighting). Next, in Step 1632, the CPUC 100 executes the LED lighting mode (for example, changing the LED lighting color) based on the data in the first ROM / RAM area. Note that step 1632 need not be executed. Next, in step 1634, the CPUC 100 executes a soft random number management process (such as an update process for random values managed by software) based on the data in the first ROM / RAM area. Next, in step 1636, the CPUC 100 calls a random number check process in the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1638.

<Processing in the second ROM / RAM area>
Next, in step 1638, the CPUC 100 obtains internal information register data based on the data in the second ROM / RAM area (in the internal information register, an area where an abnormality flag bit is set when an abnormality occurs in the random number generation circuit. Exist). Next, in step 1640, the CPUC 100 determines whether the frequency of the random number update clock is normal based on the data in the second ROM / RAM area (whether the abnormal flag bit indicating the frequency abnormality is not set). )). More specifically, the abnormality flag bit is set when the frequency of the random number update clock falls below a predetermined value. In the case of Yes in step 1640, in step 1642, the CPUC 100 determines whether the update state of the internal random number is normal based on the data in the second ROM / RAM area (the abnormal flag bit indicating the update state abnormality is set). Whether or not). In the case of Yes in step 1642, in step 1644, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area. On the other hand, in the case of No in step 1640 or step 1642, in step 1646, the CPUC 100 sets a built-in random number error display based on the data in the second ROM / RAM area (for example, sets an error number in the register area). To do). Next, in step 1300, the CPUC 100 executes the above-described non-recoverable error processing based on the data in the second ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, in step 1648, the CPUC 100 executes interrupt termination processing based on the data in the first ROM / RAM area, and proceeds to the next processing (processing in step 1602).

<Processing in the second ROM / RAM area>
Next, FIG. 18 is a flowchart of medal insertion check processing according to the subroutine of step 1700 in FIG. First, in step 1702, the CPUC 100 determines whether or not the first input sensor D20s is on (detected) based on the data in the second ROM / RAM area (however, the first input sensor). If the input port data itself of D20s is stored in the first RAM area, the determination is made with reference to the first RAM area). In the case of Yes in step 1702, in step 1704, the CPUC 100 detects the backflow of the inserted game medal by the first insertion sensor D20s and the second insertion sensor D30s based on the data in the second ROM / RAM area. (For example, the detection is made when the first input sensor D20s is turned off, the second input sensor D30s is turned on, the first input sensor D20s is turned on, and the second input sensor D30s is turned on. It is determined whether the series data itself is held in the second RAM area). In the case of Yes in step 1704, in step 1706, the CPUC 100 turns on the inserted medal backflow error flag based on the data in the second ROM / RAM area (for example, turns on the inserted medal backflow error flag area in the second RAM area). Update to the corresponding value), and the process proceeds to step 1708. On the other hand, also in the case of No in step 1704, the process proceeds to step 1708.

  Next, in step 1708, the CPUC 100 detects the stay of the inserted medal by the first insertion sensor D20s and the second insertion sensor D30s based on the data in the second ROM / RAM area (for example, the first insertion sensor D20s and the second insertion sensor D30s). It is detected when the input sensor D20s is on for a predetermined time or when the second input sensor D30s is on for a predetermined time, and the detection state data itself is held in the second RAM area. Is determined). If YES in step 1708, in step 1710, the CPUC 100 turns on the inserted medal staying error flag based on the data in the second ROM / RAM area (for example, turns on the inserted medal staying error flag area in the second RAM area). Update to the corresponding value), and the process proceeds to step 1712. On the other hand, also in the case of No in step 1708, the process proceeds to step 1712. Next, in step 1712, the CPUC 100 determines from the number of accepted medals (the number of accepted game medals received) to the number of normally passed games (the number of game medals considered to have been inserted normally) based on the data in the second ROM / RAM area. It is determined whether the value obtained by subtracting the number of sheets is not within a predetermined range (for example, 0 to 2 sheets). In the case of Yes in step 1712, in step 1716, the CPUC 100 turns on the insertion number error flag based on the data in the second ROM / RAM area (for example, corresponds to turning on the insertion number error flag area in the second RAM area). Update with the value) and proceed to the next process (the process of step 1750). Even in the case of No in step 1712, the processing shifts to the next processing (processing in step 1750). It is to be noted that an insertion number error monitoring period of a predetermined time (for example, 5 seconds) is provided, and the value obtained by subtracting the normal passing number from the received medal number during the monitoring period is within a predetermined range (for example, 0 to 2). It may be configured such that an error in the number of inserted sheets occurs when there is no more.

<Processing in the second ROM / RAM area>
Next, FIG. 19 is a flowchart of medal payout check processing according to the subroutine of step 1750 in FIG. First, in step 1752, the CPUC 100 determines whether or not the hopper drive flag is on (detected or not) based on the data in the second ROM / RAM area (however, the hopper drive flag itself is If it is stored in the first RAM area, it is determined by referring to the first RAM area). In the case of Yes in step 1752, in step 1754, the CPUC 100 detects the stay of the paid-out medals based on the data in the second ROM / RAM area (for example, the state where the first payout sensor H10s is on continues for a predetermined time). And when the second payout sensor H20s is on for a predetermined period of time, the detection state data itself is held in the second RAM area). judge. In the case of Yes in step 1754, in step 1756, the CPUC 100 turns on the payout medal staying error flag based on the data in the second ROM / RAM area (for example, turns on the payout medal staying error flag area in the second RAM area). Update with the corresponding value), and shift to the next processing (processing in step 1800). In addition, also when it is No in step 1752 or step 1754, it transfers to the next process (process of step 1800).

<Processing in the second ROM / RAM area>
Next, FIG. 20 is a flowchart of the input / withdrawal error check process according to the subroutine of step 1800 in FIG. First, in step 1802, the CPUC 100 determines whether or not the blocker D100 is off based on the data in the second ROM / RAM area (however, the output port data of the blocker D100 itself is stored in the first RAM area). If it is determined, the determination is made with reference to the first RAM area). In the case of Yes in step 1802, in step 1804, the CPUC 100 detects the abnormality of the insertion sensor based on the data in the second ROM / RAM area (the first insertion sensor D20s or the second insertion sensor D30s should not detect the game medal). It is determined whether or not there is detection at the timing. In the case of Yes in step 1804, in step 1806, the CPUC 100 turns on the abnormal injection error flag based on the data in the second ROM / RAM area (for example, it corresponds to turning on the abnormal injection error flag area in the second RAM area). Update with the value) and go to Step 1808. Note that if the answer is No in Step 1802 or Step 1804, the process proceeds to Step 1808.

  Next, in step 1808, the CPUC 100 determines whether or not the hopper drive flag is off based on the data in the second ROM / RAM area (however, the hopper drive flag itself is stored in the first RAM area). If so, the determination is made with reference to the first RAM area). In the case of Yes in step 1808, in step 1810, the CPUC 100 detects abnormality of the payout sensor based on the data in the second ROM / RAM area (the first payout sensor H10s or the second payout sensor H20s should not detect the game medal). It is determined whether or not there is detection at the timing. In the case of Yes in step 1810, in step 1812, the CPUC 100 turns on the abnormal payout error flag based on the data in the second ROM / RAM area (for example, it corresponds to turning on the abnormal payout error flag area in the second RAM area). Update with the value) and proceed to the next process (the process of step 1618). Note that if the answer is No in step 1808 or step 181, the process proceeds to the next process (process in step 1618).

<Processing in the first ROM / RAM area>
Next, FIG. 21 is a flowchart of the power-off processing according to the subroutine of step 1900 in FIG. First, in step 1902, the CPUC 100 saves the stack pointer based on the data in the first ROM / RAM area. Next, in step 1904, the CPUC 100 turns on the power-off process completed flag based on the data in the first ROM / RAM area (for example, a value corresponding to ON in the power-off process completed flag area of the first RAM area). Update with). Next, in step 1906, the CPUC 100 calls a checksum calculation process for the second ROM area based on the data in the first ROM / RAM area, and proceeds to step 1908.

<Processing in the second ROM / RAM area>
Next, in step 1908, the CPUC 100 calculates a checksum from the start address of the first RAM area to the address immediately before the checksum area based on the data in the second ROM / RAM area, and detects an error based on the calculated checksum. Information (for example, the lower 1 byte in the calculated checksum or its complement) is set in the checksum area (the address relating to the checksum area is the “memory map relating to RAM” in the lower part of the figure) See). Next, in step 1910, the CPUC 100 returns to the caller of the first ROM area based on the data in the second ROM / RAM area, and proceeds to step 1912.

<Processing in the first ROM / RAM area>
Next, in step 1912, the CPUC 100 prohibits writing to the first RAM / second RAM based on the data in the first ROM / RAM area, and proceeds to step 1914. Next, in step 1914, the CPUC 100 executes an infinite loop process for waiting for reset based on the data in the first ROM / RAM area.

  With the configuration as described above, according to the swivel type gaming machine according to the present embodiment, the first RAM area (or the register area) is processed by the CPUC 100 based on the program code arranged in the second ROM area. ) Is configured so that it can be updated and referenced, and fraudulent acts are performed on gaming machines such as error detection and error display (for example, unauthorized access to gaming media slot and payout port for illegal gaming media By configuring the program for preventing fraud to protect against this in the process of the second ROM / RAM area, the process and area relating to the progress of the game are clearly separated. This makes it easy to verify the validity of the program for preventing fraud.

(Second Embodiment)
In the present embodiment, error display processing or the like is also regarded as a program for preventing fraud, and an example is shown for implementation as program code arranged in the second ROM area. Is an indispensable process for controlling the progress of the game, so it may be easier to perform human verification if it is viewed as a program for implementing gameplay specifications rather than a program for preventing fraud There is. Therefore, in view of such circumstances, processing that may be more suitable as a program for implementing the gaming specifications is arranged in the first ROM area based on the example shown in the present embodiment. An example to be implemented as program code is a second embodiment, and changes from the present embodiment will be described in detail below.

<Processing in the first ROM / RAM area>
First, FIG. 22 shows a flow of processing executed for the first time by the CPUC 100 of the main control board M after turning on the power of the spinning-reel type gaming machine P according to the second embodiment (or at the time of system reset or user reset). It is the flowchart (1st sheet) which showed. The difference from the present embodiment is that step 1005-1 (second), step 1005-2 (second), step 1009-1 (second), step 1009-2 (second), step 1017 (second) ), Step 1019-1 (second) to step 1019-3 (second), step 1021-1 (second), step 1021-2 (second), step 1027 (second), step 1029 (second) ), Step 1035-1 (second) and step 1035-2 (second), that is, after executing the function setting of the chip in step 1004, in step 1005-1 (second), the CPUC 100 Based on the data in the first ROM / RAM area, a checksum from the head address of the first RAM area to the address immediately before the first checksum area is calculated. Here, as shown on the right side of the drawing (memory map related to the RAM), in the second embodiment, the checksum area (first checksum area) of the first RAM area and the checksum area (first area) of the second RAM area are shown. 2 checksum areas) and the checksum calculation of the first RAM area and the checksum calculation of the second RAM area are performed separately in the power-off process in the second embodiment to be described later. The error detection information based on the calculation result is stored in each area. Next, in step 1005-2, the CPUC 100 checks the first RAM based on the data in the first ROM / RAM area, and generates first RAM power-off recovery data (power-off recovery data related to the first RAM). 1006 is entered. Therefore, the “check first RAM” here is based on the checksum for the first RAM area and the error detection information held in the first checksum area, by power-off / power-off recovery. This is a process for checking whether or not the data stored in the built-in RAMC 120 is correctly held.

<Processing in the second ROM / RAM area>
On the other hand, after the power-off recovery process is called in step 1006, in step 1009-1 (second), the CPUC 100 determines the second checksum from the start address of the second RAM area based on the data in the second ROM / RAM area. Calculate the checksum up to the last address excluding the area. Next, in step 1009-2 (second), the CPUC 100 checks the second RAM based on the data in the second ROM / RAM area, and obtains the second RAM power-off recovery data (power-off recovery data related to the first RAM). Generate and move to step 1012. In other words, the “check the second RAM” here is based on the checksum for the second RAM area and the error detection information held in the second checksum area, by power-off / power-off recovery. This is a process for checking whether or not the data stored in the built-in RAMC 120 is correctly held.

<Processing in the first ROM / RAM area>
If all the switches are turned on in step 1016, in step 1017 (second), the CPUC 100 turns on the setting change operation flag based on the data in the first ROM / RAM area (for example, the first RAM The flag area with the region setting change operation is updated with a value corresponding to ON), and the process proceeds to Step 1018.

<Processing in the second ROM / RAM area>
After calling the initialization process at the time of non-setting change in step 1018, in step 1019-1 (second), the CPUC 100 sets a flag indicating that there is a setting operation in the first RAM area based on the data in the second ROM / RAM area. It is determined whether or not is off. If YES in step 1019-1 (second), in step 1019-2 (second), the CPUC 100 has normal power-off recovery data in the first RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the first RAM area is normal). In the case of Yes in step 1019-2 (second), in step 1019-3 (second), the CPUC 100 has normal power-off recovery data in the second RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the second RAM area is normal). If YES in step 1019-3 (second), the initialization range of the first RAM area and the second RAM area is determined and set as an unused RAM range in step 1028, and the second RAM is set in step 1027 (second). The power-off abnormality flag in the area is turned off, and the process proceeds to step 1036. On the other hand, if step 1019-2 (second) or step 1019-3 (second) is No, in step 1029 (second), the CPUC 100 determines whether the second RAM area is based on the data in the second ROM / RAM area. Is turned on, and the process proceeds to Step 1036.

  On the other hand, if NO in step 1019-1 (second), in step 1021-1 (second), CPUC 100 determines that the power-off recovery data in the first RAM area is normal based on the data in the second ROM / RAM area. (Particularly, whether or not the error detection result for the first RAM area is normal). In the case of Yes in step 1021-1 (second), in step 1021-2 (second), the CPUC 100 has normal power-off recovery data in the second RAM area based on the data in the second ROM / RAM area. (In particular, whether or not the error detection result for the second RAM area is normal). If YES in step 1021-2 (second), in step 1032 the CPUC 100 sets the initialization range of the first RAM area and the second RAM area to the set value in the first RAM area based on the data in the second ROM / RAM area. In step 1035-1 (second), the CPUC 100 turns off the power failure abnormality flag in the second RAM area based on the data in the second ROM / RAM area in step 1035-1 (second). 1036. On the other hand, if step 1021-1 (second) or step 1021-2 (second) is No, in step 1034, the CPUC 100 determines whether the first RAM area and the second RAM area are based on the data in the second ROM / RAM area. In step 1035-2 (second), the CPUC 100 turns on the power failure abnormality flag in the second RAM area based on the data in the second ROM / RAM area. Then, the process proceeds to step 1036.

<Processing in the first ROM / RAM area>
Next, FIG. 23 shows a process executed for the first time by the CPUC 100 of the main control board M after turning on the power of the rotary gaming machine P according to the second embodiment (or at the time of system reset or user reset). It is the flowchart (2nd sheet) which showed the flow. The difference from this embodiment is that step 1039-1 (second), step 1039-1 (second), step 1026 (second), step 1300 (second), step 1045 (second), step 1046. (Second) and step 1047 (second), that is, in step 1039-1 (second), the CPUC 100 sets the flag indicating that there is a setting operation in the first RAM area based on the data in the first ROM / RAM area. It is determined whether or not it is off. In the case of Yes in step 1039-1 (second), in step 1039-1 (second), the CPUC 100 has the power failure abnormality flag in the second RAM area turned off based on the data in the first ROM / RAM area. It is determined whether or not. If step 1039-1 (second) is Yes or step 1039-1 (second) is No, the process proceeds to step 1040 (that is, the setting change device is operated or the setting change device is operated). If not, including the fact that the separate error detection results for the first RAM area and the second RAM area are normal, the subsequent processing is continued when the power failure is restored normally), and step 1039-2 In the case of No in (second), in step 1026 (second), the CPUC 100 sets a backup error display based on the data in the first ROM / RAM area (for example, sets an error number in the register area). . Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area (that is, the first RAM area when the setting change device is not operated). In addition, if the result of the separate error detection for the second RAM area is abnormal, the state shifts to a state where it cannot be restored if the power interruption is not normally restored). Here, in this example, when the setting change device is not operated, when the separate error detection results for the first RAM area and the second RAM area are both normal, the subsequent processing is continued. However, the present invention is not limited to this. For example, if the error detection result for the first RAM area is normal, even if the error detection result for the second RAM area is abnormal (all of the second RAM area). It may be configured to continue the subsequent processing (after initializing the area).

<Processing in the second ROM / RAM area>
If the setting value in the first RAM area is within the normal range in step 1044, the CPUC 100 sets the setting in the second RAM area based on the data in the second ROM / RAM area in step 1045 (second). The value abnormality flag is turned off, the process returns to the caller of the first ROM area, and the process proceeds to step 1047 (second). On the other hand, in the case of No in Step 1044, in Step 1046 (second), the CPUC 100 turns on the set value abnormality flag in the second RAM area based on the data in the second ROM / RAM area, and calls the first ROM area. The process returns to step 1047 (second).

<Processing in the first ROM / RAM area>
Next, in step 1047 (second), the CPUC 100 determines whether or not the set value abnormality flag in the second RAM area is OFF based on the data in the first ROM / RAM area. If YES in step 1047 (second), the process proceeds to step 1050. If NO, in step 1048 (second), the CPUC 100 determines that a set value error has occurred based on the data in the first ROM / RAM area. Set the display (for example, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error processing and the set processing of the generated non-recoverable error display (backup error display, setting value error display) are executed in the first ROM / RAM area. It is configured as follows.

<Processing in the first ROM / RAM area>
Next, FIG. 24 is a flowchart of the game progress control process (second sheet) according to the subroutine of step 1200 in the second embodiment. The difference from this embodiment is that step 1228 (second), step 1700 (second), step 1400 (second), step 1237 (second), step 1750 (second), step 1450 (second) , Step 1249-1 (second), Step 1800 (second), Step 1500 (second), Step 1254-1 (second) to Step 1254-3 (second), Step 1256 (second) and step 1300 (second), that is, after accepting the insertion of a game medal in step 1227, or when the first insertion sensor D20s and the second insertion sensor D30s are not OFF in step 1230, step 1228 (second) In 2), the CPUC 100 calls the medal insertion check process in the second ROM area based on the data in the first ROM / RAM area. And, the process proceeds to step 1700 (second).

<Processing in the second ROM / RAM area>
Next, in step 1700 (second), the CPUC 100 executes medal insertion check processing based on the data in the second ROM / RAM area, and proceeds to step 1229. The purpose of the medal insertion check process in the second ROM area is the medal insertion check implemented separately in the game progress control process (loop process) and the timer interruption process (non-loop process) in this embodiment. This is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1229, in step 1400 (second), the CPUC 100 executes medal insertion error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1230. In the second embodiment, the medal insertion error detection process is executed in the first ROM / RAM area.

  Further, when the first payout sensor H10s or the second payout sensor H20s is turned on at step 1236, when the predetermined time has not elapsed after the hopper is driven at step 1241, or at step 1247, the first payout sensor H10s and the second payout sensor H10s. If the 2 payout sensor H20s is not OFF, in step 1237 (second), the CPUC 100 calls the medal payout check process in the second ROM area based on the data in the first ROM / RAM area, and step 1750 (second). ).

<Processing in the second ROM / RAM area>
Next, in step 1750 (second), the CPUC 100 executes medal payout check processing based on the data in the second ROM / RAM area, and proceeds to step 1240. The purpose of the medal payout check process in the second ROM area is the medal payout check implemented separately in the game progress control process (loop process) and the timer interrupt process (non-loop process) in this embodiment. This is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area in step 1240, in step 1450 (second), the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1247. In the second embodiment, the medal payout error detection process is executed in the first ROM / RAM area.

  If there is no operation of the settlement button D60 in step 1232, or if there are no remaining credits and bet medals in step 1233, in step 1249-1 (second), the CPUC 100 determines that the first ROM / RAM area On the basis of the data, the input / output error check process for the second ROM area is called, and the process proceeds to Step 1800 (second).

<Processing in the second ROM / RAM area>
Next, in step 1800 (second), the CPUC 100 executes input / withdrawal error check processing based on the data in the second ROM / RAM area, and proceeds to step 1250. The purpose of the second ROM area input / withdrawal error check process is that the game progress control process (loop process) and the timer interruption process (non-loop process) are separately implemented in this embodiment. -An example of a method for collectively implementing payout error check related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1250, in step 1500 (second), the CPUC 100 executes input / dispensing error detection processing, which will be described later, based on the data in the first ROM / RAM area. , The process proceeds to step 1251. In the second embodiment, the input / output error detection process is executed in the first ROM / RAM area.

<Processing in the second ROM / RAM area>
If the set value in the first RAM area is within the normal range in step 1253, in step 1254-2 (second), the CPUC 100 determines whether the setting value in the second RAM area is based on the data in the second ROM / RAM area. The set value abnormality flag is turned off, the process returns to the caller of the first ROM area, and the flow proceeds to step 1254-3 (second). On the other hand, if the set value in the first RAM area is not within the normal range in step 1253, in step 1254-1 (second), the CPUC 100 determines whether the set value in the second RAM area The set value abnormality flag is turned on, the process returns to the caller of the first ROM area, and the flow proceeds to step 1254-3 (second).

<Processing in the first ROM / RAM area>
Next, in step 1254-3 (second), the CPUC 100 determines whether or not the set value abnormality flag in the second RAM area is OFF based on the data in the second ROM / RAM area. If YES in step 1254-3 (second), the process proceeds to the next process (process in step 1257). If NO, in step 1256 (second), the CPUC 100 determines that the first ROM / RAM area is in the first ROM / RAM area. A set value error display is set based on the data (for example, an error number is set in the register area). Next, in step 1300 (second), the CPUC 100 sets non-recoverable error processing, which will be described later, based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error processing and the set processing of the generated non-recoverable error display (setting value error display) are executed in the first ROM / RAM area. Yes.

<Processing in the first ROM / RAM area>
Next, FIG. 25 is a flowchart of medal insertion error detection processing according to the subroutine of step 1400 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing an error display process related to a medal insertion error, the process implemented in the second ROM area is called. In the second embodiment, the process is performed by the first ROM. If an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area and executed. It is doing. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. It should be noted that the inserted medal backflow error flag, the inserted medal retention error flag, and the inserted number error are flags in the second RAM area for handing over information indicating that an error has been detected to the error display process implemented in the first ROM area. When the error is canceled, the flag may be directly turned off from the error display process implemented in the first ROM area as in this example, or the process for turning off the flag in the second ROM area. You may comprise so that a process may be called and turned off.

<Processing in the first ROM / RAM area>
Next, FIG. 26 is a flowchart of medal payout error detection processing according to the subroutine of step 1450 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing an error display process related to a medal payout error, the process implemented in the second ROM area is called, but in the second embodiment, the process is called the first ROM. If an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area and executed. It is doing. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. The payout medal retention error flag, which is a flag in the second RAM area for transferring information indicating that an error has been detected to the error display process implemented in the first ROM area, is displayed when the error is released. The error display process implemented in the first ROM area may be turned off directly as in this example, or the process for turning off the flag, which is the process of the second ROM area, is configured to be turned off. Also good.

<Processing in the first ROM / RAM area>
Next, FIG. 27 is a flowchart of input / withdrawal error detection processing according to the subroutine of Step 1500 (second) in FIG. 24 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing the error display process related to the input / withdrawal error, the process implemented in the second ROM area is called. In the second embodiment, the process is When an error is detected in various error detection processes in the second ROM / RAM area, information indicating that an error has been detected is transferred to the process implemented in the first ROM area. It is running. When configured in this way, an error display process, which is an indispensable process for controlling game progress, can be implemented as a program (program for controlling game progress) for implementing game play specifications. In other words, it is possible to use an error display processing program that has been conventionally implemented. It should be noted that the error input error flag and the abnormal payout error flag, which are flags in the second RAM for transferring information indicating that an error has been detected, to the error display processing implemented in the first ROM area, have been canceled. In this case, the error display process implemented in the first ROM area may be turned off directly as in this example, or the process for turning off the flag, which is a process in the second ROM area, is called off. It may be configured.

<Processing in the second ROM / RAM area>
Next, FIG. 28 is a flowchart of the game progress control process (third sheet) in the second embodiment. The difference from the present embodiment is that step 1269-1 (second) to step 1269-4 (second), step 1272 (second), step 1300 (second), step 1800 (second), step 1500. (Second), Step 1277-1 (Second), Step 1750 (Second), and Step 1450 (Second), that is, if the displayed symbol combination is normal in Step 1269, Step 1269 -1 (second), the CPUC 100 turns off the display determination abnormality flag in the second RAM area based on the data in the second ROM / RAM area, returns to the caller of the first ROM area, and returns to step 1269-3 ( Move to 2). On the other hand, if the combination of symbols displayed in step 1269 is not normal, in step 1269-2 (second), the CPUC 100 determines the display determination abnormality flag in the second RAM area based on the data in the second ROM / RAM area. Is turned on to return to the calling source of the first ROM area, and the flow proceeds to Step 1269-3 (second).

<Processing in the first ROM / RAM area>
Next, in Step 1269-3 (second), the CPUC 100 determines whether or not the display determination abnormality flag in the second RAM area is off based on the data in the first ROM / RAM area. In the case of Yes in step 1269-3 (second), in step 1269-4 (second), the CPUC 100 calls the input / output error check processing of the second ROM area based on the data in the first ROM / RAM area, The process proceeds to step 1500 (second). On the other hand, if NO in step 1269-3 (second), in step 1272 (second), CPUC 100 sets a display determination error display based on the data in the first ROM / RAM area (for example, register Set the error number in the area). Next, in step 1300 (second), the CPUC 100 sets the above-described unrecoverable error processing based on the data in the first ROM / RAM area. As described above, in the second embodiment, the setting process of the non-recoverable error process and the non-recoverable error display (display determination error display) that has occurred is executed in the first ROM / RAM area. Yes.

<Processing in the second ROM / RAM area>
Next, in step 1800 (second), the CPUC 100 executes input / withdrawal error check processing based on the data in the second ROM / RAM area, and proceeds to step 1270. The purpose of the second ROM area input / withdrawal error check process is that the game progress control process (loop process) and the timer interruption process (non-loop process) are separately implemented in this embodiment. -An example of a method for collectively implementing payout error check related processing in game progress control processing (loop processing).

<Processing in the first ROM / RAM area>
After returning to the calling source of the first ROM area in step 1270, in step 1500 (second), the CPUC 100 executes the aforementioned input / out error detection process based on the data in the first ROM / RAM area. Then, the process proceeds to step 1274. In the second embodiment, the input / output error detection process is executed in the first ROM / RAM area.

  On the other hand, if the first payout sensor H10s or the second payout sensor H20s is on in step 1277, the CPUC 100 determines in step 1277-1 (second) the second ROM area based on the data in the first ROM / RAM area. The medal payout check process is called, and the process proceeds to Step 1750 (second).

<Processing in the second ROM / RAM area>
Next, in step 1750 (second), the CPUC 100 executes medal payout check processing based on the data in the second ROM / RAM area, and proceeds to step 1284. The purpose of the medal payout check process in the second ROM area is the medal payout check implemented separately in the game progress control process (loop process) and the timer interrupt process (non-loop process) in this embodiment. This is to show an example of a method for implementing related processes collectively in a game progress control process (loop process).

<Processing in the first ROM / RAM area>
After returning to the caller of the first ROM area in step 1284, in step 1450 (second), the CPUC 100 executes medal payout error detection processing, which will be described later, based on the data in the first ROM / RAM area. Control goes to step 1286. In the second embodiment, the medal payout error detection process is executed in the first ROM / RAM area.

<Processing in the first ROM / RAM area>
Next, FIG. 29 is a flowchart of non-recoverable error processing according to the subroutine of step 1300 (second) in FIGS. 23, 24, 28, and 30 in the second embodiment. The difference from this embodiment is that the processing of this subroutine is processing in the first ROM / RAM area. That is, in the present embodiment, when executing the non-recoverable error process, the process implemented in the second ROM area is called. In the second embodiment, the process is implemented in the first ROM area. When an error is detected in various error detection processes in the second ROM / RAM area, information indicating that the error has been detected is transferred to the process implemented in the first ROM area and executed. It is. When configured in this way, a program for implementing a gameplay specification with a process having a forcible force to shift to a state in which it cannot be restored (that is, to make the spinning machine P inoperable) It can be implemented as a program for controlling the game progress.

<Processing in the second ROM / RAM area>
Next, FIG. 30 is a flowchart of timer interruption processing according to the subroutine of step 1600 in the second embodiment. The difference from this embodiment is step 1648 (second), step 1650 (second), and step 1654 (second), that is, if the update state of the built-in random number is normal in step 1642, In step 1648 (second), the CPUC 100 turns off the built-in random number abnormality flag in the second RAM area based on the data in the second ROM / RAM area, and returns to the caller of the first ROM area. ). On the other hand, if the frequency of the random number update clock is not normal in step 1640, or if the update state of the internal random number is not normal in step 1642, in step 1650 (second), the CPUC 100 determines that the second ROM Based on the data in the RAM area, the built-in random number abnormality flag in the second RAM area is turned on, the process returns to the caller of the first ROM area, and the process proceeds to step 1654 (second).

<Processing in the first ROM / RAM area>
Next, in step 1654 (second), the CPUC 100 determines whether or not the internal random number abnormality flag is off based on the data in the first ROM / RAM area. In the case of Yes in step 1654 (second), the process proceeds to step 1636. In the case of No, in step 1648 (second), the CPUC 100 determines whether the built-in random number error is based on the data in the first ROM / RAM area. Set the display (for example, set the error number in the register area). Next, in step 1300 (second), the CPUC 100 sets the above-described unrecoverable error processing based on the data in the first ROM / RAM area. As described above, in the second embodiment, the non-recoverable error process and the set process of the generated non-recoverable error display (built-in random number error display) are executed in the first ROM / RAM area. Yes.

<Processing in the first ROM / RAM area>
Next, FIG. 31 is a flowchart of the power-off process according to the subroutine of Step 1900 of FIG. 30 in the second embodiment. The difference from the present embodiment is step 1905 (second) and step 1909 (second), that is, after turning on the power-off processing flag in step 1904, in step 1905 (second), The CPUC 100 calculates a checksum from the first address of the first RAM area to the address immediately before the first checksum area based on the data in the first ROM / RAM area, and information for error detection based on the calculated checksum (for example, The lower 1 byte of the calculated checksum or its complement) is set in the first checksum area. Next, in step 1906, the checksum calculation process of the second ROM area is called, and the process proceeds to step 1909 (second).

<Processing in the second ROM / RAM area>
Next, in step 1909 (second), the CPUC 100 calculates a checksum from the start address of the second RAM area to the immediately preceding address of the second checksum area based on the data in the second ROM / RAM area, and the calculation is performed. Error detection information based on the checksum (for example, the lower 1 byte of the calculated checksum or its complement) is set in the second checksum area, and the process proceeds to step 1910. As described above, in the second embodiment, the checksum area is divided into the first checksum area and the second checksum area. As shown in the lower part of FIG. The second checksum area exists at the final address of the area, and the second checksum area exists at the final address of the second RAM area. The checksum calculation and set of the first RAM area are executed in the first ROM area, and the checksum calculation and set of the second RAM area are executed in the second ROM area.

  With the configuration as described above, according to the rotary type gaming machine according to the second embodiment, the second RAM area can be referred to by the processing of the CPUC 100 based on the program code arranged in the first ROM area. The first RAM area can be referred to by the processing of the CPUC 100 based on the program code that is configured and arranged in the second ROM area, and an illegal act is performed on the gaming machine such as error detection (for example, In the second ROM / RAM area, a program for preventing illegal acts is used to prevent unauthorized access to the game media slot and payout port to obtain game media by unauthorized means. By configuring so that it can be executed, the process and the area related to the progress of the game can be clearly separated, and the program for preventing illegal acts can be properly executed as in the present embodiment. It is easy to verify the sex.

(Summary)
The following concepts can be extracted (listed) based on the configuration shown in the above embodiments. However, the concepts listed below are merely examples, and the concepts based on the further configurations shown in the above embodiments are added to these concepts as well as the combination and separation (higher level conceptualization) of these listed concepts. May be.

  First, the problems to be solved by the above embodiments will be briefly described. The program capacity for controlling the operation of gaming machines, etc., is strictly restricted from the viewpoint of preventing unauthorized program mixing (guaranteeing the legitimacy of programs provided by gaming machine manufacturers), and implements gaming specifications. In addition to a program for the purpose, an illegal act is performed on a gaming machine (for example, illegally accessing a game medium slot or payout port to obtain a game medium by an illegal means). A number of programs for preventing fraud are also implemented for protection. However, at present, a program for implementing the game playability specification and a program for preventing fraud are often mixed on the ROM, and as a result, it is difficult to verify the legitimacy of these programs. There is a problem of becoming.

The rotary type gaming machine according to this aspect (1-1)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The gaming machine is configured to be divided into at least a second data area).

  According to the rotary type gaming machine according to the aspect (1-1), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU. Since they are arranged apart from each other on the memory map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or the dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

The rotary type gaming machine according to this aspect (1-2)
There is one or more address values that are larger than the second end point address value and smaller than the third start point address value, and for the one or more address values, the program and the data This is a gaming machine according to the aspect (1-1) in which special information that cannot be used is arranged.

  According to the rotary type gaming machine according to the aspect (1-2), in addition to the above-described effects, the program that exists in the first control area and is accessed by the CPU and the first control area are read out. The first block is the first block, and the program accessed in the second control area and accessed from the CPU and the data read and read in the second control area are the second block. Since special information that is not accessed by the CPU is arranged between the block and the second block, the special information is separated in the program source code or dump list, and the arrangement position of both blocks Can be clearly separated visually. As a result, for example, by arranging the first block as a control block for implementing the gaming specification and the second block as a control block for preventing fraud, both control blocks having different functional properties can be obtained. Since it is possible to clearly distinguish visually on the program source code or the dump list, it is easy to artificially verify the correctness of both control blocks.

The rotary type gaming machine according to this aspect (1-3)
The special information is the gaming machine according to the aspect (1-2) in which all bits are zero.

  According to the swivel type gaming machine according to the aspect (1-3), in addition to the above-described effects, the special information that is not accessed by the CPU is arranged between the first block and the second block. Since all bits of the special information are zero, the special information preferably serves as a delimiter in the program source code or dump list, and the arrangement positions of both blocks can be clearly separated visually. it can.

The rotary type gaming machine according to this aspect (1-4)
The special information is the gaming machine according to the aspect (1-2), in which information relating to the gaming machine is coded by a predetermined coding method.

  According to the swivel type gaming machine according to the present aspect (1-4), in addition to the above-described effects, when placing special information that is not accessed by the CPU between the first block and the second block, Since the special information becomes “information about the gaming machine”, the special information serves as a delimiter on the program source code or dump list, and the source of the program source code can be indicated at the same time. It becomes easier to artificially verify the validity of the control block.

The spinning machine according to this aspect (1-5)
The total number of bytes related to all the programs arranged in the second control area is smaller than the total number of bytes related to all the programs arranged in the first control area, and the first The total number of bytes related to all the data arranged in the two data areas is smaller than the total number of bytes related to all the data arranged in the first data area. ) Gaming machine.

  According to the swivel type gaming machine according to this aspect (1-5), in addition to the above-described effects, the first block = a control block for implementing the game play specification, and the second block = for preventing fraud In the case of being arranged as a control block, the data capacity for preventing fraud is smaller than the data capacity for implementing the game specification. Here, since the data for preventing fraud is likely to have different specifications for each gaming machine manufacturer, it is highly necessary to verify the validity artificially, but the data capacity is relatively small. If it is restricted, it is possible to reduce the labor for artificially verifying the validity of the data for preventing fraud.

The rotary type gaming machine according to this aspect (2)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When the CPU executes processing according to the program arranged in the first control area, the data arranged in the first data area can be read out, and the first The data arranged in two data areas is configured not to be read,
When the CPU executes processing according to the program arranged in the second control area, the data arranged in the second data area can be read out, and the first The gaming machine is configured such that the data arranged in one data area is not read out.

  According to the rotary type gaming machine according to the aspect (2), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the rotary type gaming machine according to the aspect (2), the program that exists in the first control area and that is accessed from the CPU can be applied to the data that exists in the first control area and is read out. A program that can only be accessed and exists in the second control area and that is accessed by the CPU exists in the first control area because it can only access data that is present in the second control area and read. The program that is accessed from the CPU and the data that is present and read in the first control area is the first block, the program that is present in the second control area and is accessed from the CPU and is present in the second control area. If the data to be read is the second block, it is easy to ensure that the first block and the second block are control blocks having different functional properties. It is easy to artificially verify the validity.

The spinning machine according to the aspect (3) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The program arranged in the second control area is configured to be able to execute processing by the CPU when there is a call instruction in the program arranged in the first control area. ,
It is a gaming machine characterized by this.

  According to the rotary type gaming machine according to the aspect (3), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (3), the program that exists in the second control area and is accessed by the CPU is called in the program that is present in the first control area and accessed by the CPU. Only when there is an instruction, processing by the CPU can be executed. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the execution timing of the program for preventing fraud can be limited only when this call instruction is issued, so the execution timing of the program for preventing fraud can be determined on the program source code or dump list. It becomes clear visually, and in particular, it becomes easy to artificially verify the legitimacy of the program for preventing fraud. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (4) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, The gaming machine is configured to be able to refer to information (for example, information held in a register in the CPUC 100) stored at the time when a call instruction is issued.

  According to the spinning machine according to the aspect (4), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not consecutive), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (4), the program that exists in the second control area and is accessed from the CPU is called in the program that is present in the first control area and accessed from the CPU. When there is an instruction, processing by the CPU can be executed. In this case, as information stored at the time when the call instruction is issued, for example, information held in a register in the CPU (that is, the information stored in the first control area immediately before the call instruction exists). The processing result processed by the program accessed from the CPU can be transferred to the program that exists in the second control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the program for implementing the main gameability specification is taken over, It becomes possible to execute a program for preventing fraud. Here, since the processing result of the program for implementing the main gaming specification can be highly confidential information, the information for misconduct notification can be output externally to the subordinate fraud prevention program If it is handed over darkly, it may lead to a decrease in security, but the execution timing of the program for preventing fraud can be limited to this call instruction. In the list, the execution timing of the program for preventing fraud is clarified visually, and the delivery timing of the processing result is also clarified in the program source code or the dump list. Artificially verify the legitimacy of anti-fraud programs (including the timing of delivery) Theft is facilitated. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (5) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, Processing of the CPU according to the program arranged in the second control area based on the information stored in the call control instruction (for example, information held in a register in the CPUC 100) when the call instruction is issued The gaming machine is configured to be updatable.

  According to the rotating type gaming machine according to the aspect (5), a program that exists in the first control area and is accessed from the CPU, and a program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (5), the program that exists in the second control area and is accessed by the CPU is called in the program that exists in the first control area and is accessed by the CPU. When there is an instruction, processing by the CPU can be executed. In this case, as information stored at the time when the call instruction is issued, for example, information held in a register in the CPU (that is, the information stored in the first control area immediately before the call instruction exists). The processing result processed by the program accessed from the CPU) can be updated with the processing result processed by the program that exists in the second control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the subordinate fraud prevention program is taken over to become the main game It becomes possible to execute a program for implementing the sex specification. Here, since the processing result of the program for implementing the main gaming specification can be highly confidential information, it is possible to output information for misconduct notification from a subsidiary program for preventing misconduct that can be output externally. If it is updated implicitly, there is a risk that security may be reduced, but the execution timing of the program for preventing fraud can be limited to the case where there is this call instruction. As a result of visually clarifying the execution timing of the program for preventing illegal acts on the dump list, the update timing of the processing result is also clarified on the program source code or the dump list. It is possible to artificially verify the legitimacy of anti-fraud programs (including the timing of updating results) To become. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The rotary type gaming machine according to the aspect (6)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, After the CPU returns the processing result according to the program arranged in the second control area based on the call instruction, the CPU executes the program arranged in the first control area after returning from the call instruction. The gaming machine is configured to be able to refer to when executing the process.

  According to the rotary type gaming machine according to the aspect (6), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (6), the program that exists in the second control area and that is accessed by the CPU is called in the program that exists in the first control area and is accessed by the CPU. When there is an instruction, processing by the CPU can be executed. In that case, as information stored at the time of returning from the call instruction, for example, information held in a register in the CPU (that is, in the second control area immediately before returning from the call instruction) The processing result processed by the program accessed from the CPU) can be transferred to the program that exists in the first control area and is accessed from the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When deployed as a program, the master-slave relationship between the program for implementing the gameability specification and the program for preventing fraud can be established, and the processing result of the subordinate fraud prevention program is taken over to become the main game It becomes possible to execute a program for implementing the sex specification. Here, since the program for implementing the main gaming specifications can process highly confidential information, the processing of the secondary fraud prevention program that can take in the information for fraud prevention from the outside If the result is handed over implicitly, security may be reduced. However, the execution timing of the program for preventing fraud can be limited to this call instruction. Alternatively, on the dump list, the execution timing of the program for preventing fraud is clarified visually, and the delivery timing of the processing result is also clarified on the program source code or on the dump list. Artificially verify the legitimacy of anti-fraud programs (including the timing of delivery of processing results) It becomes easy to testify. Here, the program for fraud prevention tends to have different specifications for each gaming machine manufacturer, so it is highly necessary to verify the validity artificially, but by configuring in this way, It is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to the aspect (7) is
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
When a first error (for example, an event in which the medal payout device H is full of game medals shown in step 1208) is detected by the processing of the CPU according to the program arranged in the first control area. And an error process associated with the first error (for example, a medal full error state control process shown in step 1210) can be executed,
The second error (for example, an event in which the data related to the set value is not within the normal range shown in step 1044) is detected by the processing of the CPU according to the program arranged in the second control area. The gaming machine is configured to be capable of executing error processing associated with two errors (for example, non-recoverable error processing shown in steps 1048 and 1300).

  According to the rotary type gaming machine according to the present aspect (7), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (7), the error processing accompanying the first error processed by the program that exists in the first control area and is accessed from the CPU, and the second control area Can be clearly separated on the program source code or the dump list from the error processing associated with the second error processed by the program accessed by the CPU. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the error handling associated with the first error is an error that can occur in the game progress (ie, even if no fraud is performed), and the error handling associated with the second error is It can be clarified that the roles of error processing are different from each other. Here, since the specification for the anti-fraud program is likely to be different for each gaming machine maker, it is highly necessary to verify the validity by hand, but the necessity of error processing associated with the second error Can be easily verified in comparison with the error processing associated with the first error, so that it is possible to reduce the labor for verifying the program for preventing fraud.

The spinning machine according to the aspect (8) is
A gaming machine including a ROM (for example, built-in ROMC110), a RAM (for example, built-in RAMC120), and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When performing error detection on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing result data stored in the first information storage area Error detection based on error detection information (for example, a method for performing checksum check) and error detection based on error detection information regarding processing result data stored in the second information storage area (for example, a method for performing checksum check) ) And the game machine are characterized by being performed separately.

  According to the rotary type gaming machine according to the present aspect (8), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the rotary type gaming machine according to the aspect (8), the processing result processed by the program that is present in the first control area and accessed from the CPU, and the processing result that is present in the second control area from the CPU. The processing results processed by the accessed program can be stored in separate information storage areas. In that case, when performing error detection of the stored processing results, each information storage area On the other hand, error detection can be performed separately. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game playability specification and the processing result processed by the program for preventing fraud are not mixedly stored, and the storage If the processed result is destroyed, it is possible to clearly know which of the two processed results has been destroyed. Therefore, for example, when the importance of the processing result processed by the program for preventing fraud is low, even if the processing result processed by the program for preventing fraud is destroyed, If the processing result processed by the program for implementing the game playability specification is held without being destroyed, the processing can be continued.

The spinning machine according to this aspect (9)
A gaming machine including a ROM (for example, built-in ROMC110), a RAM (for example, built-in RAMC120), and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
The RAM is
A first information storage area (for example, a first RAM area) for storing processing result data by the CPU according to the program arranged in the first control area;
A second information storage area (for example, a second RAM area) for storing processing result data by the CPU according to the program arranged in the second control area;
When error detection is performed on the processing result data stored in the first information storage area and the processing result data stored in the second information storage area, the processing result data stored in the first information storage area A gaming machine configured to perform error detection (for example, a method of performing a checksum check) based on error detection information added to the processing result data stored in the second information storage area is there.

  According to the swivel type gaming machine according to the present aspect (9), a program that exists in the first control area and is accessed by the CPU, and a program that exists in the second control area and is accessed by the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the spinning machine according to the aspect (9), the processing result processed by the program that exists in the first control area and is accessed from the CPU, and the processing result that exists in the second control area and from the CPU. The processing results processed by the accessed program can be stored in separate information storage areas. In this case, when performing error detection of the stored processing results, the respective information storage areas are stored. Error detection can be performed on the integrated one. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, it is possible to ensure that the processing result processed by the program for implementing the game playability specification and the processing result processed by the program for preventing fraud are not mixedly stored, and the storage If the processed result is destroyed, it can be easily known that one of the two processed results is destroyed. Therefore, for example, when the importance of the processing result processed by the program for preventing fraud is high, the processing result processed by the program for implementing the gaming specifications and the program for preventing fraud are processed. It can be configured to continue the processing only when it can be easily derived that none of the processing results is destroyed.

The spinning machine according to this aspect (10)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
Based on an input signal from a predetermined sensor unit (for example, the first input sensor D20s or the second input sensor D30s) by the processing of the CPU according to the program arranged in the first control region, a predetermined event ( For example, it is configured to be able to determine whether or not the occurrence of an event that received one game medal (shown in step 1227) occurs,
Based on the input signal from the predetermined sensor unit by the processing of the CPU according to the program arranged in the second control area, an abnormal event related to game progress (for example, shown in a subroutine of step 1400, The gaming machine is configured to be able to determine whether or not an inserted medal backflow error or an inserted medal staying error has occurred.

  According to the spinning cylinder gaming machine according to the aspect (10), the program that exists in the first control area and is accessed from the CPU, and the program that exists in the second control area and is accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (10), the presence / absence of a normal event related to the game progress based on the sensor signal is further determined by a program that exists in the first control area and is accessed from the CPU. The presence or absence of an abnormal event related to the game progress based on the sensor signal can be determined by a program that exists in the second control area and is accessed by the CPU. In any case, the determination is based on the same sensor signal. It can be. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, the same sensor signal is handled as an input signal necessary for the progress of the game in the program for implementing the gameability specification, and the same sensor signal is illegal in the program for preventing illegal acts. Since it can be handled as an input signal necessary for preventing action, it can be clarified that the same sensor signal is handled differently on the program source code or on the dump list. Here, since the specification for the fraud prevention program is likely to be different for each gaming machine manufacturer, it is highly necessary to verify the validity artificially. Since it becomes easy to verify by comparing points, it is possible to reduce labor for verifying a program for preventing fraud.

The spinning machine according to this aspect (11)
A gaming machine including a ROM (for example, built-in ROMC110) and a CPU (for example, CPUC100),
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order (for example, an example of the memory map of the main control chip C shown as <memory map> in the embodiment)
A first control area (for example, a first control area in the first ROM area) in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area (for example, in the first ROM area) in which the data is arranged with respect to the address value continuous from the second start address value larger than the first end address value to the second end address value. First data area),
A second control area (for example, in the second ROM area) in which the program is arranged for the address value continuous from a third start address value that is larger than the second end address value to a third end address value. Second control region),
A second data area (for example, in the second ROM area) in which the data is arranged with respect to the address value continuous from the fourth start point address value larger than the third end point address value to the fourth end point address value. The second data area), and
A control signal (for example, a hopper motor drive signal) for instructing payout of the game medium and a predetermined sensor unit (for example, the first payout sensor H10s or the like) by processing of the CPU according to the program arranged in the first control area Based on the non-detection time of the second payout sensor H20s), a payout operation for one game medal is performed after the hopper is driven, as shown in step 1279, which is an abnormal event related to game progress. It is possible to determine whether or not an event has occurred,
Based on the detection time of the predetermined sensor unit by the processing of the CPU according to the program arranged in the second control area, a second abnormal event (for example, step 1450) A gaming machine configured to be able to determine whether or not a payout medal retention error (shown in a subroutine) has occurred.

  According to the spinning cylinder gaming machine according to the aspect (11), the program that exists in the first control area and is accessed from the CPU, and the program that is present in the second control area and accessed from the CPU are stored in the memory. Since they are arranged apart from each other on the map (in an arrangement in which addresses are not continuous), the arrangement positions of both programs can be clearly separated visually on the program source code or dump list. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud By arranging it as a program, it is possible to clearly distinguish the placement position of the program for implementing the game playability specification and the program for preventing fraud on the program source code or the dump list. It becomes easy to artificially verify the legitimacy of the program. In addition, since the program that exists in the first control area and is accessed by the CPU is located at a lower address than the program that exists in the second control area and is accessed by the CPU, the CPU executes first. It is easy to limit the program to be executed to a program that exists in the first control area and is accessed by the CPU (that is, a program for implementing game play specifications).

  According to the swivel type gaming machine according to the aspect (11), there is further an event of an “exceptional” abnormal event related to a game progress based on a sensor signal by a program that exists in the first control area and is accessed from the CPU. The presence / absence of occurrence can be determined, and the presence / absence of a “serious” abnormal event related to the game progress based on the sensor signal can be determined by a program that exists in the second control area and is accessed by the CPU. The determination based on the same sensor signal can also be made. As a result, for example, a program that exists in the first control area and is accessed from the CPU = a program for implementing a game play specification, and a program that exists in the second control area and is accessed from the CPU = for preventing fraud When arranged as a program, in the program for implementing the gameability specification, the same sensor signal is handled as an input signal necessary for error detection that can occur during normal game progress, and in the program for preventing fraud Can handle the same sensor signal as an input signal necessary for preventing fraud (that is, necessary for error detection that is difficult to occur during normal game progression), and therefore can be used on program source code or dump list. , It can be clarified that the handling of the same sensor signal is different. . Here, since the specification for the fraud prevention program is likely to be different for each gaming machine manufacturer, it is highly necessary to verify the validity artificially. Since it becomes easy to verify by comparing points, it is possible to reduce labor for verifying a program for preventing fraud.

P Cylinder type game machine, DU front door (door)
D Door board, D10s Input acceptance sensor D20s First input sensor, D30s Second input sensor D40 Stop button, D41 Left stop button D42 Middle stop button, D43 Right stop button D50 Start lever, D60 Checkout button D70 Display panel, D80 Door switch D90 coin shooter, D100 blocker D130 upper panel, D140 lower panel D150 decoration lamp unit, D160 reel window D170 medal slot, D180 operation status indicator D190 payout number display device, D200 credit number display device D210 insertion number indicator light, D220 bet Button D230 Medal tray, D240 Release port D250 Special game state display device, D260 Key hole M Main control board, M10 Setting door switch M20 Setting key switch, M30 Setting / reset button C Main Control chip, M50 reel M51 Left reel, M52 Middle reel M53 Right reel S Sub control board, S10 LED lamp S20 Speaker, S30 Revolving backlight S40 Production display device, SC Sub control chip E Power board, E10 Power switch H Medal payout Device, H10s first payout sensor H20s second payout sensor, H40 hopper H50 disc, H50a disc rotation shaft H60 game medal outlet, H70 discharge urging means H80 hopper motor K spinner board, K10 spinner motor K20 spinner sensor IN relay board

Claims (1)

A gaming machine comprising a ROM and a CPU,
In the ROM, an address is assigned, and a program for managing instructions to the CPU and data read according to the program are stored.
On the memory map in which the address values in the ROM are continuous in ascending order,
A first control area in which the program is arranged for the address value continuous from a first start point address value to a first end point address value;
A first data area in which the data is arranged with respect to the address value continuous from a second start point address value larger than the first end point address value to a second end point address value;
A second control area in which the program is arranged with respect to the address value continuous from a third start point address value larger than the second end point address value to a third end point address value;
It is configured to be divided at least into a second data area in which the data is arranged for the address value continuous from a fourth start point address value larger than the third end point address value to a fourth end point address value. ,
When there is a call instruction in the program arranged in the first control area, and when the CPU executes processing according to the program arranged in the second control area, A gaming machine configured to be able to refer to information stored when a call instruction is issued.

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