JP2016073185A - Step-down charging system and power source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a step-down charging system that can perform stable charging in a circuit for performing step-down charging on low-voltage power storage means by a high-voltage power generation source without stopping an operation because the voltage of a circuit system for controlling the step-down operation is lowered due to an effect of the low voltage even when the terminal voltage of the power storage means is low.SOLUTION: A step-down charging system has power generating means 40, power storage means 20 and step-down means 100 for stepping down the output of the power generating means to charge the power storage means 20. Limit means 60 for applying a voltage limit with which the voltage of the output terminal of a step-down circuit 10 is not below a predetermined voltage is provided between the step-down circuit 10 and the power storage means 20. The limit means 60 has an MOS element, and a limit function is implemented by continuous impedance variation which is obtained by making the MOS element perform source follower operation.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure for receiving power obtained from a high-voltage power source and charging a secondary battery or the like while being self-started, and more particularly to its circuit configuration.

  Conventionally, charging circuits capable of charging power storage means such as secondary batteries and electric double layer capacitors of several volts from a power source that generates a relatively high voltage have been proposed in fields such as electronic watches and energy harvesting. Yes.

  An example of a conventional charging system is shown in FIG. This is an example of charging the output voltage of a generator whose power generation source is an electromagnetic induction type. The output of the power generation means 40, which is a generator that can be modeled as an AC voltage source 41 having an internal resistance 42, is half-wave or full-wave rectified by the rectification means 50, and the power storage means 93 that is an electric double layer capacitor having a rated voltage number V It is configured to charge.

  Further, a booster circuit 95 is connected to the power storage means 93 to boost the terminal voltage of the power storage means 93 and drive a load circuit 96 that is an electronic timepiece.

  In general, when the electric storage means 93 is completely discharged by self-discharge or the like, the terminal voltage becomes extremely small. In this example, a resistor 91 is provided so that the load circuit 96 can be activated even in such a state. At the time of starting the charging system, the resistor 91 is connected in series with the power storage means 93, and a voltage drop caused by the current generated by the power generation means 40 flowing through the resistor 91 is added to the power storage voltage. Thus, a voltage sufficient for starting the circuit is applied to both ends of the load circuit 96. That is, even if the power storage means 93 is discharged, the load circuit 96 can be activated.

  After the load circuit 96 is activated, the terminal voltage of the power storage means 93 is periodically voltage sampled. When the charging of the power storage means 93 proceeds and the terminal voltage rises to a level at which the load circuit 96 can be operated, this is detected, and an operation is performed in which both ends of the resistor 91 are short-circuited by the switch 92. After switch 92 becomes conductive, load circuit 96 continues to operate based on the voltage stored in power storage means 93.

Japanese Patent No. 2652057 (page 7, FIG. 1)

  Conventionally, in order to generate a voltage sufficient for starting the load circuit 96, a resistor element having a relatively high resistance value is used for the resistor 91, and a fixed value resistor is simply inserted in series. Since the resistance value of the resistor 91 is constant regardless of the power generation amount, for example, when the power generation amount is large, the generated current increases, so the voltage generated in the resistor 91 increases, but the power consumed by the resistor 91 is wasted. And the generated power cannot be efficiently stored in the power storage means 93.

  The electromagnetic induction method can be practically used even if the power extraction efficiency from the power generation means is not so high because the generated energy per unit time is relatively large. However, in the case of using a generator whose power generation capacity is not so high, it is not practical if the power extraction efficiency remains low.

  For example, in the case of an electrostatic induction generator such as an electret, a high power generation voltage is output, but since an amount of current that can be obtained with a high internal impedance is small, it is necessary to construct an efficient charging system. However, as described above, no particular consideration has been given to efficient charging in response to changes in the amount of power generation while ensuring the startability of the power storage means when the remaining amount is low.

  In this example, it is not considered to use a generator having a high generation voltage as the power generation means 40 of the charging system. In particular, in order to charge a small electric double layer capacitor having a rated voltage of several volts with high efficiency using a generator that generates a high generation voltage of several tens of volts, such as electrostatic induction power generation, Although it is necessary to charge by converting to a low voltage level, there is no description about application to a charging system having such a step-down function.

  The following configuration is adopted in the step-down charging system of the present invention.

That is, a step-down charging system (100) having a step-down charging output (102) for inputting a power generation output of a power generation unit (40) that outputs a high voltage and performing a step-down charging to a power storage unit (20), A step-down circuit (10) for stepping down the output;
Provided between the output of the step-down circuit (10) and the step-down charge output (102), the impedance is continuously changed so that the voltage at the output terminal of the step-down circuit (10) does not fall below a predetermined limit voltage. And limiting means (60).

  In this application, the conventional problem is improved, and the voltage on the charging side (voltage step-down circuit output terminal) is substantially monitored instead of the voltage on the charged side (power storage means), and the voltage exceeding the predetermined limit voltage is stepped down. Control to generate automatically at the output terminal. This control is similar to inserting a circuit element whose resistance value is continuously variable, but the power loss in this circuit element is minimized. Therefore, the efficiency of charging can be improved, and the characteristics when starting up the charging of the power storage means from a low remaining amount can be improved.

  In the charging system of the step-down method, the voltage at the output terminal of the step-down circuit affects the voltage at the input terminal of the step-down circuit. For this reason, when the voltage at the output terminal of the step-down circuit becomes too small, the voltage at the input terminal of the step-down circuit is reduced by being drawn into this.

  Since the voltage at the input terminal of the step-down circuit needs to be higher than the minimum operable voltage of the step-down circuit, if the voltage at the input terminal of the step-down circuit becomes too small, the operation of the circuit that performs step-down control cannot be maintained. . In the present application, the voltage that is obtained by multiplying the above limit voltage by the step-down magnification is higher than the minimum operable voltage of the circuit that performs step-down control, thereby avoiding this, and the circuit that performs step-down control operates. It can be continued.

  Furthermore, a reference voltage generation circuit is provided which is arranged on the input side (generator side) of the step-down circuit having a higher voltage than the step-down output terminal and starts operation before the step-down operation of the step-down circuit. A reference voltage for determining the limit voltage is generated. Therefore, when the generator output is received, the reference voltage generation circuit, which is a circuit that performs step-down control, starts operating, and the limit function immediately works, so that even when the terminal voltage of the power storage means is low, the step-down charging system is ensured. Can continue to operate.

Therefore, according to the present application, even when the power storage means is in a low remaining amount state, it is possible to start up correctly and perform a step-down operation, and to charge the power storage means with a low loss at the initial stage of charging. In particular, even when an electrostatic induction generator that generates a high voltage such as an electret element is used, it is possible to provide a step-down charging system that can be charged with high efficiency from the generator.

  In addition, the analog limit function as described above can be realized with a simple and space-saving configuration without using a voltage sampling circuit, which is disadvantageous in terms of power consumption under high voltage. Have.

It is the circuit diagram which showed the structure of the pressure | voltage fall charging system of this invention. It is the circuit diagram which showed the structure of the pressure | voltage fall means of this invention. It is a circuit diagram showing a circuit state of a step-down circuit of the present invention. FIG. 6 is a waveform diagram showing timing signal waveforms for driving a step-down circuit. It is the circuit diagram which showed another structure of the pressure | voltage fall charging system of this invention. It is the wave form diagram which showed the principal part voltage waveform of the pressure | voltage fall charging system of this invention. It is the circuit diagram which showed the structure of the conventional charging system. It is the circuit diagram which showed the structure of the pressure | voltage fall charging system of 2nd Embodiment. It is the circuit diagram which showed the structure of the pressure | voltage fall means of 2nd Embodiment. It is the circuit diagram which showed the structure of the pressure | voltage fall charging system of 3rd Embodiment. It is the wave form diagram which showed the principal part voltage waveform of the pressure | voltage fall charging system of 2nd Embodiment. FIG. 6 is a circuit diagram illustrating an operating current path of a timing generation circuit according to a second embodiment.

  Hereinafter, an embodiment for realizing such a step-down charging system will be described in detail with reference to the drawings.

First, an overall configuration of an embodiment of the present invention will be described with reference to FIGS.
Thereafter, the configuration and operation of the step-down circuit will be described with reference to FIGS.
Finally, the overall operation of the embodiment of the present invention will be described with reference to FIGS.

[Description of overall configuration of step-down charging system: Fig. 1]
The step-down charging system of the present invention is a circuit system shown as step-down means 100. By connecting the power generation means 40, the rectification means 50, and the power storage means 20 before and after the step-down charging system, the output of the power generation means 40 is full-wave rectified by the rectification means 50, and the rectified output is stepped down by the voltage reduction means 100. Then, the operation of charging the power storage means 20 can be performed.

  The power generation means 40 is an AC generator that outputs a high voltage alternating voltage. The rectifier 50, which is a so-called diode bridge, is configured to be capable of full-wave rectifying the output of the power generator 40 and applying the rectified output to the step-down device 100. The step-down means 100 can store power in the power storage means 20 that is a secondary battery connected to the step-down charge output terminal 102 via the step-down circuit 10 that converts the rectified output input from the step-down input terminal 101 into a voltage. ing. The power generation means 40 is assumed to be an AC generator that can be expressed as a simple model in which a voltage source 41 having a generated voltage amplitude (single amplitude) V0 of 30 V and an internal resistance 42 having an output resistance value R are connected in series.

  The step-down unit 100 includes a step-down circuit 10 that is a circuit block that can convert the input voltage to a substantially lower voltage by switching the connection state of the capacitor between series and parallel. The configuration of the step-down unit 100 will be described in detail next.

[Configuration explanation of step-down means: FIG. 2]
The step-down unit 100 includes a step-down circuit 10, a timing generation circuit 13, a limit unit 60, and a reference voltage generation circuit 30. The step-down means 100 is composed of a MOS element having a withstand voltage that is not destroyed by the input power generation voltage because it is a high voltage. In general, since the threshold voltage of a high voltage MOS element is high, the operable voltage of the step-down means 100 is assumed to be 5V or more.

  The reference voltage generation circuit 30 is a so-called beta multiplication type reference current source composed of PMOS elements 31 and 35, NMOS elements 32 and 34, and a standard resistor 33.

  The PMOS elements 31 and 35 are in a current mirror connection, and are connected so as to pass an equal current to the NMOS elements 32 and 34. A reference resistor 33 is inserted between the source terminal of the NMOS element 34 and the ground potential VSS, and is connected so that the operating point of the reference voltage generation circuit 30 is determined by the source degeneration effect acting on the NMOS element 32. . As a result, a substantially constant current that does not depend on the power supply voltage flows through each MOS element.

  Since the NMOS element 34 is diode-connected, a constant voltage close to the threshold voltage of the NMOS element is generated between the drain and source terminals. This voltage signal is the first reference voltage Vr1. That is, the first reference voltage Vr1 is obtained from the connection point between the drain terminal of the PMOS element 35 and the drain terminal of the NMOS element 34.

  The voltage of the first reference voltage Vr1 is a predetermined voltage value obtained based on the threshold voltage of the NMOS element. Here, it is assumed that the first reference voltage Vr1 is 0.5 V when viewed from the ground potential VSS.

  The step-down circuit 10 is a circuit that step-down outputs an input voltage by switching a series connection state and a parallel connection state of capacitors. A detailed configuration will be described later.

  The timing generation circuit 13 is a clock source for the switching operation of the step-down circuit 10. The timing generation circuit 13 includes an oscillation circuit (not shown) that is connected to the first reference voltage Vr1 and is biased with the reference voltage Vr1 as a reference voltage to oscillate. The first timing signal S31 is based on the output of the oscillation circuit. And a second timing signal S32. Since the timing generation circuit 13 can be realized with a known configuration, the configuration is omitted. The waveform of the timing signal will be described later.

  The power storage means 20 is a secondary battery having a low internal impedance. The power storage means 20 is configured to charge the output current of the step-down circuit 10 via a limit means 60 described later. The negative electrode of the electricity storage means 20 is grounded.

  Limit means 60 is provided between the output of the step-down circuit 10 and the step-down charge output terminal 102 connected to the power storage means 20.

  The limit means 60 includes a PMOS element 61. The source terminal is connected to the output of the step-down circuit 10, and the gate terminal is connected to the first reference voltage Vr1 in the reference voltage generation circuit 30. Here, it is assumed that the threshold voltage of the PMOS element 61 of the limit means 60 is about 0.5V.

The limit means 60 further includes a diode 62 having a low forward voltage, represented by a Schottky barrier diode, and is connected so that the rectification direction from the drain terminal of the PMOS element 61 to the positive electrode of the power storage means 20 is the forward direction. To do.
[Description of Step-Down Circuit Configuration: FIGS. 3 and 4]
The configuration of the step-down circuit 10 will be described with reference to FIGS. The step-down circuit 10 includes a first step-down block 11 and a second step-down block 12. For simplicity, the step-down circuit 10 is assumed to be fixed 6 times, and the output of the step-down circuit 10 will be described as being connected directly to the power storage unit 20 without passing through the limit unit 60.

  The first step-down block 11 and the second step-down block 12 have the same configuration, but operate in opposite phases to each other, that is, one is configured to perform a discharging operation while the other performs a storage operation. Circuit.

  Each step-down block includes a plurality of capacitors, and the connection state between the capacitors is switched by a so-called analog switch configured by combining MOS transistors. The switch is not shown because it is a known configuration. Each step-down block has a first step-down stage 110A that steps down the output of the rectifying unit 50 twice as shown in FIG. 3, and outputs the output of the first step-down step 110A three times down to the power storage unit 20 And the second step-down stage 110B.

  The first step-down stage 110A includes two capacitors, a capacitor 111 and a capacitor 112, in order to perform a double step-down operation. The first step-down stage 110A operates to switch all of the capacitors 111 and 112 in series or all in parallel.

  The second step-down stage 110B includes three capacitors, a capacitor 113, a capacitor 114, and a capacitor 115, in order to perform a triple step-down operation. The second step-down stage 110B operates to switch all three capacitors of the capacitor 113, the capacitor 114, and the capacitor 115 in series or in parallel.

  The operation clock is a two-phase clock signal as shown in FIG. The state a and the state b in FIG. 3 are switched alternately according to the first timing signal S31 and the second timing signal S32. The same applies to state a and state b in FIG.

  In the period A in FIG. 4, that is, in the period in which the first timing signal S31 is at a high level, the state a in FIG. 3 is set. Further, during the period B, that is, the period when the second timing signal S32 is at the high level, the switching control is performed so as to be in the state b of FIG. Period A and period B are 50 milliseconds.

  The first timing signal S31, which is one of the clocks, and the second timing signal S32, which is the other, have a relationship that can be almost regarded as an inverted signal, but at the moment of switching, the switches constituting each step-down block are simultaneously turned on. Thus, a switching delay period D is provided so as not to short-circuit each capacitor. The period D can be set to a necessary minimum time width of about several nanometers to several tens of nanoseconds by a known delay time generation method.

[Description of operation of step-down circuit: FIGS. 3 to 4]
The operation of the step-down circuit 10 will be briefly described with reference to FIGS.

  When the step-down circuit 10 performs a step-down operation according to the first timing signal S31 and the second timing signal S32, the capacitor that is charged from the output of the rectifying means 50 has a terminal voltage slightly increased by storing electric charge. When the capacitor is discharged, the electric charge stored in the capacitor is instantaneously sucked into the power storage means 20 and becomes equal to the terminal voltage of the power storage means 20. This is because the impedance of the power storage means 20 is low.

  Therefore, when the step-down circuit 10 performs a step-down operation, the voltage between terminals of each capacitor of the second step-down stage 110B is always substantially equal to the storage voltage VBT, and the voltage between terminals of each capacitor of the first step-down stage 110A is stored. As a result, the load voltage VL, which is the input side voltage of the step-down circuit 10, becomes almost six times the storage voltage VBT.

Thus, a voltage value obtained by multiplying the storage voltage VBT by the step-down magnification n appears on the input side of the step-down circuit 10. Since the voltage at the input side terminal of the step-down circuit 10 hardly changes even when the generated current flows, the step-down circuit 10 is excluded except for a very short period (period D in FIG. 4) in which the connection state of the step-down circuit 10 is switched. Always behaves as if it is a voltage source of n · VBT. The voltage value of the load that looks like this constant voltage source corresponds to the aforementioned load voltage VL,
VL = n · VBT
Comes to hold.

  In particular, by operating the two step-down blocks in a complementary manner, the other step-down block can be connected to the power generation unit 40 and charged while the one step-down block is in a discharging state and not connected to the power generation unit 40. Therefore, it is possible to make a state where a constant voltage load is always connected to the power generation means 40, and it is possible to always take out the electric power at that time when the power generation means 40 is generating power.

  Further, in this step-down operation, since all the capacitors in the step-down circuit 10 have only a slight voltage change in the terminal voltage even through the operation of transferring charges, loss due to charge transfer is suppressed, and as a result, The step-down circuit 10 can transfer charges with little loss to the power storage means 20 whose terminal voltage is lower than the input voltage.

  Therefore, by configuring the step-down circuit 10 in this way, it is possible to connect a load that can always be regarded as a constant voltage source without a time during which the power generation means 40 is unloaded, and load the generated output with low loss. It can be sent to the means 30.

[Description of operation of step-down charging system: FIG. 1, FIG. 2, FIG. 6]
The operation of the embodiment of the present invention will be briefly described with reference to FIG. 1, FIG. 2, and FIG.

  First, description will be made on the assumption that the storage means 20 is almost discharged and the operation starts from the state where the terminal voltage VBT is 0V.

  When the power generation means 40 starts power generation and a rectified current flows from the rectification means 50, a current flows through the reference voltage generation circuit 30 and a predetermined voltage value is generated in the first reference voltage Vr1 (FIG. 6). Time t1).

  Thereafter, the timing generation circuit 13 also starts to operate, and outputs the first timing signal S31 and the second timing signal S32. With this timing signal, the step-down circuit 10 starts the above-described step-down operation (time t2 in FIG. 6).

  The step-down circuit 10 converts the rectified output of the rectifying means 50 into a voltage and supplies a charging current to the power storage means 20.

Since the terminal voltage VBT of the storage means 20 is 0V, the drain terminal of the PMOS element 61 of the limit means 60 is similarly drawn to near 0V. However, the reference voltage Vr1 is applied to the gate terminal of the PMOS element 61. In this state, the PMOS element 61 operates as a source follower circuit. Therefore, the source terminal of the PMOS element 61 in the limit means 60 is substantially fixed at a voltage obtained by adding the threshold voltage VTP of the PMOS element 61 to the voltage value of the first reference voltage Vr1, which is about 1.0 V in this example. Will be.

  As the step-down circuit 10 performs a step-down operation, the input voltage of the step-down circuit 10 appears as six times the output terminal voltage of the step-down circuit 10 as described above. This voltage is 6 × (Vr1 + VTP) ≈6V, which is sufficiently higher than the reference voltage generation circuit 30 necessary for controlling the step-down circuit 10 and the minimum operable voltage of the timing generation circuit 13 which is 5V. That is, since the input terminal voltage of the step-down circuit 10 is not excessively lowered due to the influence of the terminal voltage of the power storage unit 20, the step-down circuit 10 can continue to operate stably even when the terminal voltage of the power storage unit 20 is extremely low. It becomes like this.

  In this configuration, the limit means 60 behaves like a resistance element whose resistance value changes continuously. When the terminal voltage of the power storage means 20 is close to 0V, the power loss in the limit means 60 is maximized. However, if the generated current obtained from the power generation means 40 is small, this loss is the minimum necessary, and the terminal voltage of the power storage means 20 is Even if it rises gradually, this loss is minimized. That is, it operates so as to be automatically controlled so that the power loss in the limit means 60 is minimized within a range in which the step-down circuit 10 can continue operation.

  In particular, when the first reference voltage Vr1 is generated, the limit means 60 operates immediately because it is a source follower circuit. This is due to the fact that the source follower circuit generally operates at high speed. On the other hand, the timing generation circuit 13 includes an oscillation circuit that oscillates based on the first reference voltage Vr1. Generally, since it takes several milliseconds or more to start oscillation of the oscillation circuit, the timing signals S31 and S32 are output later than the limit means 60 starts a predetermined operation. Thereby, since the limit operation precedes the operation of the step-down circuit 10, the above operation is guaranteed.

  Next, a case will be described in which charging of the power storage means 20 has progressed and the terminal voltage of the power storage means 20 has risen until it slightly exceeds 1.0V.

  The drain terminal of the PMOS element 61 in the limit means 60 has a voltage slightly higher than about 1.0 V, but the gate terminal of the PMOS element 61 remains applied with the first reference voltage Vr1. Since the first reference voltage Vr1 is about 0.5V, the potential relationship of the limit means 60 is | VGS |> | VDS |. In this potential relationship, the PMOS element 61 does not maintain the source follower operation, but simply operates as a conducting MOS switch. For this reason, the voltage at the output terminal of the step-down circuit 10 is pulled by the terminal voltage of the power storage means 20, and becomes substantially equal to the terminal voltage of the power storage means 20 (time t3 in FIG. 6).

  When the step-down circuit 10 performs a step-down operation, the input voltage of the step-down circuit 10 appears six times as high as the output terminal voltage of the step-down circuit 10 as described above. That is, at this time, a voltage higher than 6 × 1.0 V = 6 V appears at the input terminal of the step-down circuit 10. Since this voltage is also sufficiently higher than the reference voltage generation circuit 30 necessary for controlling the step-down circuit 10 and the minimum operable voltage of the timing generation circuit 13, the step-down circuit 10 increases the terminal voltage of the storage means 20. Even so, the operation can be continued stably. The same applies to the case where the charging of the power storage means 20 further proceeds. For example, when the terminal voltage of the power storage means 20 becomes 1.5 V, 6 × 1.5 V = 9 V appears at the input terminal of the step-down circuit 10.

Finally, a case where power generation by the power generation means 40 is stopped will be described.
When the power generation of the power generation means 40 is stopped, the step-down circuit 10 cannot supply current to the power storage means 20, and the timing generation circuit 13 and the reference voltage generation circuit 30 cannot maintain operation, and the timing signals S31 and S32 stop. (Time t4 in FIG. 6). However, since the diode 62 in the limit means 60 is connected in a direction prohibiting discharge from the power storage means 20, the charge stored in the power storage means 20 does not flow backward, and the power once charged is wasted. There is no external discharge.

  That is, according to the present invention, even when the charging state of the power storage unit 20 becomes empty, the voltage step-down unit 100 can be correctly started and the charging operation to the power storage unit 20 can be continuously performed.

  In the above example, it is assumed that the operation of the limit unit 60 starts immediately. However, for the purpose of delaying the time for the step-down circuit 10 to start the operation relatively further than the limit unit 60 starts the operation, the first step is performed. The reference voltage Vr1 may be connected to the timing generation circuit 13 via a delay circuit having an appropriate time constant.

  In the example shown above, the backflow prevention of the limit means 60 is performed by the diode 62, but it may be replaced with an active ideal diode by a MOS element and an OP amplifier. An example of the configuration at this time is shown in FIG.

  That is, in this example, a rectifying function is realized by using an OP amplifier 64 and a switch 63 by an NMOS element instead of the diode 62. The switch 63 is connected so that the source and drain terminals correspond to the cathode and anode terminals of the diode 62, respectively. The gate terminal of the switch 63 is driven by the output of the OP amplifier 64. The non-inverting input terminal (+) of the OP amplifier 64 is connected to the output terminal of the step-down circuit 10, and the inverting input terminal (−) is connected to the positive electrode of the power storage means 20.

  The operation of the limit means 60 shown in FIG. 5 will be briefly described. The OP amplifier 64 monitors the difference voltage between the output terminal voltage of the step-down circuit 10 and the terminal voltage VBT of the storage means 20, and if the difference is positive, it determines that the storage means 20 from the step-down circuit 10 is forward biased. The switch 63 is turned on. On the contrary, when the voltage difference between the output terminal voltage of the step-down circuit 10 and the terminal voltage VBT of the storage means 20 is negative, it is determined that the reverse bias is applied, and the switch 63 is turned off. To do. In this example, the forward / reverse determination of the bias can be realized by using the resistance component of the switch 63 and the PMOS element 61 as the galvanic resistance without using the galvanic resistance separately.

  The overall operation of the step-down charging system when the limit means 60 shown in FIG. 5 is used will be briefly described.

  When the step-down circuit 10 starts the above-described step-down operation after the power generation unit 40 starts power generation and the reference voltage generation circuit 30 starts operating with the current rectified from the rectification unit 50, the power is stored from the output terminal of the step-down circuit 10. The means 20 is forward biased. Therefore, the limit means 60 becomes conductive and the power storage means 20 is charged. When the power generation means 40 becomes non-power generation, it becomes a reverse bias, so that the limit means 60 becomes non-conductive and discharge from the power storage means 20 is prevented.

  In particular, the function of the limit operation of controlling the output terminal voltage of the step-down circuit 10 as described above to a predetermined value or more by the PMOS element 61 is obtained similarly.

  According to the ideal diode shown in FIG. 5, the effect of the limit operation is maintained, and the forward voltage generated when the diode is used is eliminated, so that the loss is reduced and the charging efficiency is improved.

[Explanation of Second Embodiment: FIGS. 8, 9, 11, 12]
Subsequently, the step-down charging system according to the second embodiment of the present invention will be described with reference to FIGS. This example of a step-down charging system is an example in which the intermediate output of a step-down circuit is used as a steady-state operation power source of a timing generation circuit in order to reduce power consumption in a control system circuit with relatively high power consumption such as a timing generation circuit. is there.

  In particular, this example is an example in which two power supply circuits are used to supply operation power for the timing generation circuit, and the two power supply circuits are switched without active detection of the system state.

[Configuration of Second Embodiment: FIGS. 8 and 9]
The overall configuration of the second embodiment will be described with reference to FIG. 8, and then the details of the power supply circuit will be described with reference to FIG. FIG. 3 is used supplementarily in some explanations.

  Of the configuration of the step-down charging system according to the second embodiment, differences from the step-down charging system of the first embodiment described above and added components will be mainly described.

  In this example, since the same configuration as that of the first embodiment is included, the same reference numerals are given thereto. In this example, for the timing generation circuit 13, the minimum operable voltage is lowered to 1.5V. Further, the reference voltage generating circuit 30 ′ is configured to output a plurality of reference voltages.

  Further, the step-down means 100 of this embodiment is characterized by including two power supply circuits, a first power supply circuit 71 and a second power supply circuit 72.

  The first power supply circuit 71 is a circuit that functions as a constant voltage circuit having at least a current source capability. A second reference voltage Vr2 obtained from the reference voltage generation circuit 30 ′ is connected to the first power supply circuit 71.

  The second power supply circuit 72 also functions as a constant voltage circuit having at least a current source capability. A third reference voltage Vr3 obtained from the reference voltage generation circuit 30 ′ is connected to the first power supply circuit 71. The configuration of these power supply circuits will be described later.

  The configuration of the reference voltage generation circuit 30 ′ is substantially the same as that of the reference voltage generation circuit 30 of the first embodiment, but a plurality of reference voltages can be output. The reference voltage generation circuit 30 ′ can easily output different voltages from its drain terminal by serializing a plurality of diode-connected MOS elements 36 to 39 between the PMOS element 35 and the NMOS element 34. Yes.

  Here, it is assumed that the voltage value of the second reference voltage Vr2 is 2.0V. The voltage value of the third reference voltage Vr3 is 2.5V.

  Note that the intermediate output Vm of the step-down circuit 10 is the output of the first step-down stage 110A of the first step-down block 11 in FIG.

  Here, the configuration of the power supply circuit will be described with reference to FIG. In this example, a constant voltage circuit using the simplest source follower circuit is used.

  As shown in FIG. 9, the first power supply circuit 71 is composed of one NMOS element 71A, and its drain terminal is connected to the step-down input terminal 101 of the step-down circuit 10, and the source terminal is the power supply terminal of the timing generation circuit 13. It is said. A second reference voltage Vr2 is connected to the gate terminal.

  With this connection, the NMOS element 71A operates as a source follower circuit. Therefore, the output voltage of the first power supply circuit 71 is approximately 1.5 V obtained by subtracting 0.5 V, which is the threshold voltage of the NMOS element 71A, from 2.0 V, which is the voltage value of the second reference voltage Vr2.

  The second power supply circuit 72 is a circuit in which an NMOS element 72A and an NMOS element 72B are connected in series. The NMOS element 72A has a so-called diode connection. The drain terminal of the NMOS element 72A is connected to the intermediate output Vm of the step-down circuit 10, the gate terminal of the NMOS element 72B is connected to the third reference voltage Vr3, and the source terminal is used as the power supply terminal of the timing generation circuit 13. Yes.

  With this connection, the NMOS element 72B also operates as a source follower circuit. Therefore, the output voltage of the second power supply circuit 72 is approximately 2.0 V, which is obtained by subtracting 0.5 V, which is the threshold voltage of the NMOS element 71B, from 2.5 V, which is the voltage value of the third reference voltage Vr3.

  However, in order for the second power supply circuit 72 to perform a desired circuit operation, it is necessary to increase the intermediate output Vm to a voltage exceeding about 2.5V. This is because since the NMOS element 72A is connected in series to the NMOS element 72B, 0.5V corresponding to the threshold voltage is further required in order for the NMOS element 72A to become conductive. On the other hand, in the state where the intermediate output Vm of the step-down circuit 10 is lower than 2.5V, the NMOS element 72A is reverse-biased and thus becomes non-conductive.

[Description of Operation of Second Embodiment: FIGS. 8, 9, 11, and 12]
Next, the operation of the step-down charging system according to the second embodiment will be described.

  First, the operation when the terminal voltage of the power storage means 20 is low will be described.

  When the power generation means 40 starts power generation, the reference voltage generation circuit 30 ′ is activated and a predetermined reference voltage is output. Further, the limit means 60 immediately starts to operate (time t1 in FIG. 11).

  During the period when the step-down circuit 10 does not start operation, the capacitor in the step-down circuit 10 is in a discharged state, so the intermediate output Vm is almost at the ground potential. Then, since the NMOS element 72A is reverse-biased, the second power supply circuit 72 becomes non-conductive.

  On the other hand, since the second reference voltage Vr2 having a predetermined value is applied to the first power supply circuit 71 and the first reference voltage Vr1 is further applied to the timing generation circuit 13, the timing generation circuit 13 performs a predetermined operation. The output of the first and second timing signals S31 and S32 is started (time t2 in FIG. 11).

  In particular, due to the operation of the first power supply circuit 71, the voltage supplied to the timing generation circuit 13 is about 1.5V.

  When the timing generation circuit 13 outputs the first and second timing signals S31 and S32, the step-down circuit 10 starts a step-down operation. At this time, when the storage means 20 is almost discharged and the storage voltage VBT is low, the output terminal of the step-down circuit 10 is fixed at 1.0 V by the limit operation of the limit means 60. The step-down magnification of the second step-down stage was three times. Therefore, a voltage of Vm = 1.0V × 3 = 3.0V appears in the intermediate output Vm of the step-down circuit 10 (time t3 in FIG. 11).

  If the intermediate output Vm of the step-down circuit 10 is 3.0V, since the third reference voltage Vr3 has already been applied to the second power supply circuit 72, the second power supply circuit 72 becomes conductive.

  As a result, about 2.0 V obtained by subtracting the threshold voltage of the NMOS element 72B from the voltage value of the third reference voltage Vr3 is applied to the timing generation circuit 13 as the power supply voltage, and the intermediate output Vm of the step-down circuit 10 is applied. The power is supplied from. On the other hand, the first power supply circuit 71 is turned off, and no current flows through the first power supply circuit 71. This is due to the following reason.

  Immediately after the start of power generation by the power generation means 40, the first power supply circuit 71 was in a potential relationship enabling a source follower operation, so that the power supply voltage of the timing generation circuit 13 could be 1.5V. However, when the potential of the source terminal of the NMOS element 71A of the first power supply circuit 71 is raised by the second power supply circuit 72, the first power supply circuit 71 does not have a sink capability, and therefore cannot be pulled back. As a result, the gate-source voltage of the NMOS element 71A which is the first power supply circuit 71 is reduced below the threshold voltage, and as a result, the first power supply circuit 71 becomes non-conductive. .

  That is, the power supply source for operating the timing generation circuit 13 is the system of the step-down input (rectifier 50 output) of the step-down circuit 10 immediately after the start of power generation, but the step-down circuit 10 operates when the step-down circuit 10 operates and enters a steady state. The system automatically switches to the system of the intermediate output Vm of the circuit 10. Obviously, this control does not require complicated and power consuming circuits such as voltage measurement.

  Next, an operation when the terminal voltage of the power storage unit 20 is high will be described.

  When the power generation means 40 starts power generation when the power storage means 20 has been charged and the power storage voltage VBT is 1.5 V (time t4 in FIG. 11), reference is made by the same starting operation as described above. Although the voltage generation circuit 30 ′ starts operating (time t3 in FIG. 11), the limit operation of the limit means 60 is stopped at this time. Therefore, when the step-down circuit 10 starts the step-down operation, the output terminal receives the stored voltage VBT. It appears as it is. At this time, a voltage of Vm = 1.5V × 3 = 4.5V appears in the intermediate output Vm.

  The intermediate output Vm becomes a sufficiently high voltage, and the third reference voltage Vr3 has already been applied to the second power supply circuit 72, so that the NMOS element 72A in the second power supply circuit 72 performs a source follower operation.

  As a result, a voltage of about 2.0 V obtained by subtracting the threshold voltage of the NMOS element 72A from the voltage value of the third reference voltage Vr3 is applied to the timing generation circuit 13, and power is supplied from the intermediate output Vm. (Time t6 in FIG. 11).

  On the other hand, also at this time, the first power supply circuit 71 becomes non-conductive, and the power supply source for operating the timing generation circuit 13 is automatically switched to the system of the intermediate output Vm of the step-down circuit 10 in a steady state.

  Here, paying attention to the power required to operate the timing generation circuit 13, when viewed as a step-down charging system, the power consumption is ½ compared to the first embodiment. This will be briefly described with reference to FIG.

  The step-down circuit 10 performs step-down with high efficiency as described in the previous embodiment. For example, when paying attention to the first step-down block 11, the power input to the first step-down stage 110A and the output power are equal and the loss is negligible.

In other words, the product of the voltage applied to the input side of the first step-down stage 110A and the flowing current is equal to the product of the output voltage and the flowing current. In particular, since the step-down magnification of the first step-down stage 110A is 2, the output-side voltage of the first step-down stage 110A is ½ of the input-side voltage, but the flowing out current is twice the flowing-in current.

  A part of the flowing out current is supplied to the timing generation circuit 13 and consumed, but this amount of current is compressed to 1/2 when converted into the input current of the step-down circuit 10.

  If the operating current is controlled to be constant (Iosc) by being biased at a constant current by the first reference voltage Vr1, the timing generation circuit 13 is equivalent to this amount as shown in FIG. When the current is converted into a load current flowing into the input terminal 101 of the step-down means 10, Iosc / 2 is obtained. Since the product of this and the load voltage VL substantially corresponds to the power consumed to operate the timing generation circuit 13, this converted power is VL · Iosc / 2.

  On the other hand, in the first embodiment, the timing generation circuit 13 supplies power directly on the input side of the step-down circuit 10. For this reason, as shown in FIG. 12A, the operation current Iosc of the timing generation circuit 13 is the same even if converted into the load current flowing into the input terminal 101 of the step-down means 10. Therefore, the power consumed substantially is VL · Iosc. As is apparent from a comparison between this and the above-described converted power, the substantial power consumption for operating the timing generation circuit 13 in the second embodiment is ½ that of the first embodiment. .

  In other words, in the second embodiment, in addition to the functions of the first embodiment, the power consumption of the system itself can be further suppressed, and charging is performed by increasing the charge amount of the power storage means 20 accordingly. It turns out that there exists an effect which can raise efficiency.

  As described above, in the second embodiment, two power supply circuits are used as the operation power supply system of the timing generation circuit, and the two power supplies are not detected without actively detecting the system state. The circuit was switched. Although it is somewhat complicated as a system, active detection of the state of the system may be performed. Such an example will be described next.

[Third Embodiment: FIG. 10]
A step-down charging system according to a third embodiment of the present invention will be described with reference to FIG. This example of the step-down charging system is also an example in which the intermediate output of the step-down circuit is used as an operation power source of the timing generation circuit for the purpose of reducing power consumption in a control system circuit such as a timing generation circuit.

  In particular, this example is an example in which one power supply circuit is used to supply operating power to the timing generation circuit, and the state of the system is actively detected to switch the power supply system to the timing generation circuit.

  The configuration and operation of the third embodiment will be described briefly with reference to FIG.

  Of the configuration of the step-down charging system according to the third embodiment, differences from the step-down charging system of the second embodiment and added components will be mainly described.

  Since this example includes the same configuration as that of the above-described second embodiment, the same reference numerals are given thereto.

[Description of Configuration of Third Embodiment: FIG. 10]
The reference voltage generation circuit 30 ″ has substantially the same configuration as the reference voltage generation circuit 30 ′ in the second embodiment. The reference voltage generation circuit 30 ″ outputs three voltages, and outputs a fourth reference voltage Vr4 in addition to the first reference voltage Vr1 and the second reference voltage Vr2. The fourth reference voltage Vr4 is set to about 2.5V, which is slightly lower than three times the limit voltage 1.0V of the limit means 60 described above. The factor of 3 is the step-down magnification of the second step-down stage 110B.

  Further, the third power supply circuit 73, the comparison circuit 74, and the switch circuit 75 are provided.

  The third power supply circuit 73 is a circuit having the same function as the second power supply circuit 72, and outputs a constant voltage of 1.5V as a source follower circuit.

  The comparison circuit 74 is a low power comparator, and the comparison circuit 74 inputs the fourth reference voltage Vr4 and the intermediate output Vm of the step-down circuit 10 so that these voltage values can be compared.

  The switch circuit 75 is a well-known analog switch circuit that can select one from two systems of the step-down input terminal 101 of the step-down circuit 10 and the intermediate output Vm of the step-down circuit 10. The power supply system selected by the switch circuit 75 is configured to be able to supply power to the timing generation circuit 13 via the third power supply circuit 73.

  The selection operation of the switch circuit is performed based on the comparison result of the comparison circuit 74, and when the intermediate output Vm of the step-down circuit 10 is higher than the fourth reference voltage Vr4, the system of the intermediate output Vm of the step-down circuit 10 is selected. Is configured such that a step-down input system of the step-down circuit 10 can be selected.

[Description of Operation of Third Embodiment: FIG. 10]
Next, the operation of the step-down charging system according to the third embodiment will be described briefly.

  When the power generation means 40 starts power generation, the reference voltage generation circuit 30 ″ and the limit means 60 start to operate. Before the step-down circuit 10 starts its operation, the intermediate output Vm of the step-down circuit 10 is almost at ground potential, and the comparison circuit 74 detects this, and the power supply system to the timing generation circuit 13 is connected to the input side of the step-down circuit 10. The switch circuit 75 is switched so that 2.0 V is applied to the timing generation circuit 13 by the third power supply circuit 73.

  Thereafter, the step-down circuit 10 starts operating, and the power storage means 20 is charged. The limit voltage of the limit means 60 is 1.0V, and the voltage of the intermediate output Vm of the step-down circuit 10 is always higher than 3.0V. Since this voltage is higher than 2.5 V, which is the voltage value of the fourth reference voltage Vr4, the comparison circuit 74 detects this, and the power supply system to the timing generation circuit 13 is connected to the intermediate output Vm side of the step-down circuit 10. The switch 75 is switched as follows.

  This switching operation is the same regardless of the terminal voltage of the power storage means 20. In the third embodiment, similarly to the second embodiment, the power consumption of the system itself can be suppressed, and the efficiency can be increased by increasing the charge amount of the power storage unit 20 correspondingly. It turns out that there is an effect.

  As described above, in the third embodiment, the operation power supply system of the timing generation circuit is switched by actively detecting the system state. The circuit element that receives the switching of the power supply system is only the timing generation circuit, but is not limited thereto. As long as the start sequence of the system is not affected, a further effect can be obtained by including a circuit element with relatively large power consumption.

DESCRIPTION OF SYMBOLS 10 Voltage step-down circuit 11 1st voltage step-down block 12 2nd voltage step-down block 13 Timing generation circuit 14 Variable resistance element 20 Power storage means 30,30 ', 30''Reference voltage generation circuit 40 Power generation means 50 Rectification means 60 Limit means 61 PMOS element 62 Diode 71 First power circuit 72 Second power circuit 73 Third power circuit 74 Comparison circuit 75 Switch circuit 100 Step-down means

Claims (10)

A step-down charging system (100) having a step-down charging output (102) for inputting a power generation output of a power generation means (40) for outputting a high voltage and performing step-down charging to a power storage means (20),
A step-down circuit (10) for stepping down the power generation output;
A timing generation circuit (13) for generating a timing signal for the step-down circuit (10) to perform a step-down operation;
Provided between the output of the step-down circuit (10) and the step-down charge output (102);
A step-down charging system comprising: limit means (60) for continuously changing impedance so that the voltage at the output terminal of the step-down circuit (10) does not fall below a predetermined limit voltage. 2. The step-down charging system according to claim 1, wherein a voltage value obtained by multiplying the limit voltage by a step-down ratio of the step-down circuit is higher than a minimum operable voltage of the step-down circuit. The reference voltage generation circuit (30) for generating a predetermined reference voltage based on the power generation output is provided, and the limit means (60) determines the limit voltage based on the reference voltage. The step-down charging system described. The step-down charging system according to claim 3, wherein the limit means (60) includes a source follower circuit including a MOS transistor (61) whose gate terminal is biased by the reference voltage. The timing generation circuit (13) generates the timing signal by applying the reference voltage,
The step-down charging system according to claim 3 or 4, wherein the limit means (60) starts operating earlier than the step-down circuit (10) starts the step-down operation. The limit means (60) includes a switch (63) connected in series to the source follower circuit, and the switch (63) according to a potential difference between the power storage means (20) and the output terminal of the step-down circuit (10). 6. The step-down charging system according to claim 4 or 5, further comprising a circuit (64) for controlling a conduction state of the power supply. As a system for supplying power to the timing generation circuit (13),
A first system using the input (VL) of the step-down circuit (10) as a supply source;
A second system using the intermediate output (Vm) of the step-down circuit (10) as a supply source;
Have
The step-down charging system according to any one of claims 1 to 6, wherein the first system and the second system are switched to serve as a power source for the timing generation circuit (13). The voltage value (Vm) of the intermediate output of the step-down circuit (10) is
When the step-down magnification from the intermediate output of the step-down circuit (10) to the output of the step-down circuit (10) is equal to or greater than the value obtained by multiplying the limit voltage,
The step-down charging system according to claim 7, wherein the first system is switched to the second system. A step-down charging system according to any one of claims 1 to 8,
A power supply comprising a power generation means (40) for outputting a high voltage and a power storage means (20). 10. The power source according to claim 9, wherein the power generation means (40) is an electrostatic induction generator.

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