JP2016072400A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP2016072400A
JP2016072400A JP2014199387A JP2014199387A JP2016072400A JP 2016072400 A JP2016072400 A JP 2016072400A JP 2014199387 A JP2014199387 A JP 2014199387A JP 2014199387 A JP2014199387 A JP 2014199387A JP 2016072400 A JP2016072400 A JP 2016072400A
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electrode
semiconductor chip
adhesive film
semiconductor
solder layer
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周治郎 定永
Shujiro Sadanaga
周治郎 定永
幸平 竹田
Kohei Takeda
幸平 竹田
紀憲 藤田
Noritoshi Fujita
紀憲 藤田
麻衣 永田
Mai NAGATA
麻衣 永田
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Sekisui Chemical Co Ltd
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Sekisui Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which when laminating a semiconductor chip with a through electrode on a semiconductor wafer, suppresses voids and causes the through electrode to be favorably conducted and suppresses lengths of burrs projecting around the semiconductor chip.SOLUTION: A semiconductor device manufacturing method comprises: a first process of temporarily placing on a semiconductor wafer 5, a semiconductor chip 2 with a through electrode which has a semiconductor layer with adhesive film 1 being attached, by using a first pressing tool 7 while heating the semiconductor chip 2 at a temperature equal to or higher than a solder melting temperature; and a second process of heating the semiconductor chip 2 temporarily placed on the semiconductor wafer 5 by using a second pressing tool 8 at a temperature equal to or higher than the solder melting temperature to cause the through electrode (via) 4 having the semiconductor layer 3 to be electrically continuous. When assuming that a length of one side of the semiconductor chip 2 is A, a length of one side of the first pressing tool 7 is B and a length of one side of the second pressing tool 8 is C, a ratio B/A is 0.9 and over and a ratio C/A is 0.85 and under.SELECTED DRAWING: Figure 2

Description

本発明は、半導体ウエハ上に貫通電極付き半導体チップを積層する際に、ボイドを抑制でき、貫通電極を良好に導通させることができ、半導体チップの周囲に突出するバリの長さを抑制できる半導体装置の製造方法に関する。 The present invention can suppress a void when laminating a semiconductor chip with a through electrode on a semiconductor wafer, can satisfactorily connect the through electrode, and can suppress the length of a burr protruding around the semiconductor chip. The present invention relates to a device manufacturing method.

近年、半田層等からなる突起電極(バンプ)を有する半導体チップを用いたフリップチップ実装が注目されている。
フリップチップ実装のなかでも、複数の半導体チップを積層してデバイスを飛躍的に高性能化、小型化したTSV(Si貫通ビヤ/Through Silicon via)を使った3次元積層技術が注目されている。TSV積層技術においては、一般的に、半導体ウエハ上の格子状に区切られた各接合部位に、接着フィルムを介して複数の貫通電極付き半導体チップ(TSVチップ)を多層積層したのち、格子状のダイシングラインに沿って半導体ウエハをダイシングすることで多層半導体チップ積層体が製造される。
In recent years, flip chip mounting using a semiconductor chip having protruding electrodes (bumps) made of a solder layer or the like has attracted attention.
Among flip-chip mounting, a three-dimensional stacking technique using a TSV (Through Silicon Via) that has been dramatically improved in performance by stacking a plurality of semiconductor chips has attracted attention. In the TSV stacking technique, generally, a plurality of semiconductor chips with penetrating electrodes (TSV chips) are stacked in multiple layers via an adhesive film at each bonding portion partitioned in a grid pattern on a semiconductor wafer, A semiconductor wafer stack is manufactured by dicing the semiconductor wafer along the dicing line.

例えば、特許文献1には、半硬化状態の樹脂層を介して半導体部品同士を接着した後、半導体部品の端子間を半田接合する半導体装置の製造方法が記載されており、該半導体装置の製造方法によれば、生産性および信頼性を向上することができることが記載されている。また、特許文献1には、樹脂層の60〜150℃における溶融粘度は0.1〜100,000Pa・sが好ましいことが記載されている。 For example, Patent Document 1 describes a method for manufacturing a semiconductor device in which semiconductor components are bonded to each other via a semi-cured resin layer and then solder-bonded between terminals of the semiconductor components. It is described that according to the method, productivity and reliability can be improved. Patent Document 1 describes that the melt viscosity at 60 to 150 ° C. of the resin layer is preferably 0.1 to 100,000 Pa · s.

半導体チップを多層積層した場合、半田層を有する貫通電極を導通させる際、半田変形とともに接着フィルムを構成する樹脂が流動し、半導体チップの周囲に樹脂がバリ状に突出する(これを「バリ」という)。バリが発生した場合、隣接する半導体チップに付着したり這い上がったりすることにより、不良を引き起こすことがある。ダイシングラインの間隔を広げることでこのような問題は解決するが、生産性の観点からは、ダイシングラインの間隔は狭いことが望ましい。 When semiconductor chips are stacked in multiple layers, when a through electrode having a solder layer is made conductive, the resin constituting the adhesive film flows along with solder deformation, and the resin protrudes in the shape of a burr around the semiconductor chip (this is referred to as “burr”). Called). When a burr | flash generate | occur | produces, it may cause a defect by adhering to the adjacent semiconductor chip or creeping up. Such a problem can be solved by widening the distance between the dicing lines, but from the viewpoint of productivity, it is desirable that the distance between the dicing lines is narrow.

バリを減らす方法として半田変形を少なくする方法が考えられるが、その場合半田の濡れ性が悪化し、貫通電極を良好に導通させることが難しくなる。従って、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制することは難しかった。 As a method of reducing burrs, a method of reducing solder deformation is conceivable. However, in this case, the wettability of the solder deteriorates, and it becomes difficult to make the through electrode conductive well. Therefore, it has been difficult to suppress the length of burrs protruding around the semiconductor chip while maintaining the solder wettability and allowing the through electrode to conduct well.

特開2013−33952号公報JP2013-33952A

本発明は、半導体ウエハ上に貫通電極付き半導体チップを積層する際に、ボイドを抑制でき、貫通電極を良好に導通させることができ、半導体チップの周囲に突出するバリの長さを抑制できる半導体装置の製造方法を提供することを目的とする。 The present invention can suppress a void when laminating a semiconductor chip with a through electrode on a semiconductor wafer, can satisfactorily connect the through electrode, and can suppress the length of a burr protruding around the semiconductor chip. An object is to provide a method for manufacturing a device.

本発明は、接着フィルムを貼り合わせた半田層を有する貫通電極付き半導体チップを、第一の加圧ツールを用いて半田溶融温度以下の温度に加熱しながら半導体ウエハ上に仮置きする第一工程と、前記半導体ウエハ上に仮置きされた前記半田層を有する貫通電極付き半導体チップを、第二の加圧ツールを用いて半田溶融温度以上の温度に加熱して前記半田層を有する貫通電極を導通させる第二工程とを有し、前記半田層を有する貫通電極付き半導体チップの一辺の長さをA、前記第一の加圧ツールの一辺の長さをB、前記第二の加圧ツールの一辺の長さをCとした場合、比率B/Aが0.9以上であり、比率C/Aが0.85以下である半導体装置の製造方法である。
以下、本発明を詳述する。
The present invention provides a first step of temporarily placing a semiconductor chip with a through electrode having a solder layer bonded with an adhesive film on a semiconductor wafer while being heated to a temperature equal to or lower than a solder melting temperature using a first pressure tool. A through-electrode having the solder layer by heating a semiconductor chip with a through-electrode having the solder layer temporarily placed on the semiconductor wafer to a temperature equal to or higher than a solder melting temperature using a second pressure tool. A length of one side of the semiconductor chip with a through electrode having the solder layer, B, a length of one side of the first pressure tool, and the second pressure tool. When the length of one side is C, the ratio B / A is 0.9 or more and the ratio C / A is 0.85 or less.
The present invention is described in detail below.

本発明者らは、接着フィルムを貼り合わせた半田層を有する貫通電極付き半導体チップを、第一の加圧ツールを用いて半田溶融温度以下の温度に加熱しながら半導体ウエハ上に仮置きする第一工程と、前記半導体ウエハ上に仮置きされた前記半田層を有する貫通電極付き半導体チップを、第二の加圧ツールを用いて半田溶融温度以上の温度に加熱して前記半田層を有する貫通電極を導通させる第二工程とを有する半導体装置の製造方法において、第一の加圧ツールの大きさと第二の加圧ツールの大きさとを変えることで、ボイドを抑制したうえで、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制できることを見出した。
即ち、第一工程では、空気の噛み込みによるボイドを排除するため、半田層を有する貫通電極付き半導体チップを該貫通電極付き半導体チップと同程度の大きさの比較的大きい加圧ツールで平行に押圧する必要がある。しかしながら、このような比較的大きい加圧ツールをそのまま第二工程で用いると、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制することは難しい。これに対して、第二工程では、半田層を有する貫通電極付き半導体チップを比較的小さい加圧ツールで押圧することで、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制することができる。
The present inventors temporarily place a semiconductor chip with a through electrode having a solder layer bonded with an adhesive film on a semiconductor wafer while heating it to a temperature not higher than the solder melting temperature using a first pressure tool. The semiconductor chip with a through electrode having the solder layer temporarily placed on the semiconductor wafer is heated to a temperature equal to or higher than a solder melting temperature using a second pressure tool, and the through hole having the solder layer is formed. In the manufacturing method of the semiconductor device having the second step of conducting the electrode, by changing the size of the first pressing tool and the size of the second pressing tool, the void is suppressed and the solder wettability It was found that the length of the burrs protruding around the semiconductor chip can be suppressed while maintaining the above and making the through electrode satisfactorily conductive.
That is, in the first step, in order to eliminate voids due to air entrapment, a semiconductor chip with a through electrode having a solder layer is parallelized with a relatively large pressure tool having the same size as the semiconductor chip with a through electrode. It is necessary to press. However, if such a relatively large pressure tool is used in the second step as it is, the length of burrs protruding around the semiconductor chip is suppressed while maintaining the solder wettability and satisfactorily conducting the through electrode. It ’s difficult. On the other hand, in the second step, the semiconductor chip having the solder layer is pressed with a relatively small pressure tool to maintain the solder wettability and to make the through electrode satisfactorily conductive. It is possible to suppress the length of burrs protruding around

本発明の半導体装置の製造方法では、まず、接着フィルムを貼り合わせた半田層を有する貫通電極付き半導体チップを、第一の加圧ツールを用いて半田溶融温度以下の温度に加熱しながら半導体ウエハ上に仮置きする第一工程を行う。 In the method for manufacturing a semiconductor device of the present invention, first, a semiconductor wafer with a through electrode having a solder layer bonded with an adhesive film is heated to a temperature not higher than the solder melting temperature using a first pressure tool. The first step of temporary placement is performed.

図1は、本発明の半導体装置の製造方法における第一工程の一例を模式的に示す図である。即ち、図1は、半田層を有する貫通電極付き半導体チップ2を、第一の加圧ツール7を用いて加熱しながら半導体ウエハ5上に仮置きする工程を示している。
ここで、半田層を有する貫通電極付き半導体チップ2は、半田層3及びビヤ4を有するものである。また、半田層を有する貫通電極付き半導体チップ2には、半田層3を有する面に接着フィルム1が貼り合わされている。また、半導体ウエハ5は、半田層3に対向する電極6を有している。
FIG. 1 is a diagram schematically showing an example of the first step in the method for manufacturing a semiconductor device of the present invention. That is, FIG. 1 shows a process of temporarily placing the semiconductor chip 2 with a through electrode having a solder layer on the semiconductor wafer 5 while being heated using the first pressure tool 7.
Here, the through-electrode-attached semiconductor chip 2 having a solder layer has a solder layer 3 and a via 4. In addition, the adhesive film 1 is bonded to the surface having the solder layer 3 in the semiconductor chip 2 with a through electrode having the solder layer. Further, the semiconductor wafer 5 has an electrode 6 facing the solder layer 3.

上記接着フィルムを、上記半田層を有する貫通電極付き半導体チップに貼り合わせる方法は特に限定されず、例えば、上記接着フィルムを、上記半田層を有する貫通電極付き半導体チップにラミネートする方法、上記接着フィルムを、半田層を有する貫通電極付き半導体ウエハにラミネートした後、該半田層を有する貫通電極付き半導体ウエハを半導体チップに個片化する方法等が挙げられる。 The method of bonding the adhesive film to the semiconductor chip with a through electrode having the solder layer is not particularly limited. For example, the method of laminating the adhesive film on the semiconductor chip with the through electrode having the solder layer, the adhesive film Is laminated on a semiconductor wafer with a through electrode having a solder layer, and then the semiconductor wafer with a through electrode having the solder layer is separated into semiconductor chips.

上記半田溶融温度以下の温度に加熱する温度(仮置き温度ともいう)及び時間(仮置き時間ともいう)を制御することより、上記接着フィルムを完全には硬化させずに、上記半導体ウエハ上に上記半田層を有する貫通電極付き半導体チップをある程度接着させる(即ち、仮置きする)ことができる。
なお、このような仮置きされた状態において、上記半田層を有する貫通電極はまだ導通していない。上記半田層を有する貫通電極の導通は、後述する第二工程において行われる。
By controlling the temperature (also referred to as temporary placement temperature) and the time (also referred to as temporary placement time) for heating to a temperature below the solder melting temperature, the adhesive film is not completely cured, and is thus formed on the semiconductor wafer. The semiconductor chip with a through electrode having the solder layer can be adhered to some extent (that is, temporarily placed).
In such a temporarily placed state, the through electrode having the solder layer is not yet conductive. Conduction of the through electrode having the solder layer is performed in a second step to be described later.

上記仮置き温度は特に限定されず、仮置き可能な温度で上記接着フィルムの硬化温度より低い温度を採用すればよく、上記接着フィルムの硬化温度との差の好ましい下限が20℃、好ましい上限が150℃であり、より好ましい下限は40℃、より好ましい上限は130℃である。上記仮置き温度は、具体的には、好ましくは60〜160℃程度、より好ましくは80〜140℃程度である。
上記仮置き時間は、好ましくは0.1〜60秒である。
The temporary placement temperature is not particularly limited, and a temperature lower than the curing temperature of the adhesive film may be adopted at a temperature at which temporary placement is possible. A preferable lower limit of the difference from the curing temperature of the adhesive film is 20 ° C., and a preferable upper limit is It is 150 degreeC, a more preferable minimum is 40 degreeC and a more preferable upper limit is 130 degreeC. Specifically, the temporary placement temperature is preferably about 60 to 160 ° C, more preferably about 80 to 140 ° C.
The temporary placement time is preferably 0.1 to 60 seconds.

本発明の半導体装置の製造方法では、上記第一工程の後、上記半導体ウエハ上に仮置きされた上記半田層を有する貫通電極付き半導体チップ上に、半田層を有する貫通電極付き半導体チップを更に1段以上積層する工程を行ってもよい。
この工程を行うことにより、上記半導体ウエハ上に仮置きされた複数の貫通電極付き半導体チップに対してまとめて導通を行うことができ、1段ずつ貫通電極付き半導体チップを重ね順々に導通を行う場合と比較して、生産性を向上させることができる。更に、上記半導体ウエハ上の複数の仮置き積層体に対してまとめて導通を行うことで、生産性を更に向上させることができる。
In the method for manufacturing a semiconductor device of the present invention, after the first step, a semiconductor chip with a through electrode having a solder layer is further formed on the semiconductor chip with a through electrode having the solder layer temporarily placed on the semiconductor wafer. A step of laminating one or more stages may be performed.
By carrying out this process, it is possible to conduct continuity to a plurality of semiconductor chips with penetrating electrodes temporarily placed on the semiconductor wafer, and the semiconductor chips with penetrating electrodes are stacked one by one in order. Productivity can be improved compared with the case where it performs. Further, productivity can be further improved by conducting conduction to the plurality of temporarily placed laminated bodies on the semiconductor wafer.

本発明の半導体装置の製造方法では、次いで、上記半導体ウエハ上に仮置きされた上記半田層を有する貫通電極付き半導体チップを、第二の加圧ツールを用いて半田溶融温度以上の温度に加熱して上記半田層を有する貫通電極を導通させる第二工程を行う。 In the semiconductor device manufacturing method of the present invention, the through-electrode semiconductor chip having the solder layer temporarily placed on the semiconductor wafer is then heated to a temperature equal to or higher than the solder melting temperature using a second pressure tool. Then, a second step of conducting the through electrode having the solder layer is performed.

図2は、本発明の半導体装置の製造方法における第二工程の一例を模式的に示す図である。即ち、図2は、半導体ウエハ5上に仮置きされた半田層を有する貫通電極付き半導体チップ2を、第二の加圧ツール8を用いて加熱する工程を示している。 FIG. 2 is a diagram schematically showing an example of the second step in the method for manufacturing a semiconductor device of the present invention. That is, FIG. 2 shows a process of heating the semiconductor chip 2 with a through electrode having a solder layer temporarily placed on the semiconductor wafer 5 using the second pressure tool 8.

上記半田溶融温度以上の温度に加熱する方法は特に限定されず、例えば、60〜220℃程度の接触温度(電極を接触させる温度)で0.1〜60秒程度加熱した後、230〜300℃程度の半田溶融温度以上の温度で0.1〜60秒程度加熱する方法等が挙げられる。加熱条件を制御することより、良好に上記半田層を有する貫通電極の導通を行うことができる。また、加熱条件によっては上記接着フィルムを完全に硬化させて上記半田層を有する貫通電極付き半導体チップを良好に接着することもできる。 The method of heating to a temperature equal to or higher than the solder melting temperature is not particularly limited. For example, after heating for about 0.1 to 60 seconds at a contact temperature of 60 to 220 ° C. (temperature at which the electrode is brought into contact), 230 to 300 ° C. A method of heating for about 0.1 to 60 seconds at a temperature equal to or higher than the solder melting temperature. By controlling the heating conditions, the through electrode having the solder layer can be conducted well. Also, depending on the heating conditions, the adhesive film can be cured completely and the semiconductor chip with a through electrode having the solder layer can be adhered well.

上記第二工程では、上記第二の加圧ツールを用いて上記半田層を有する貫通電極付き半導体チップを押圧し、上記半田層を有する貫通電極を導通させるとともに上記接着フィルムを封止領域に充填することが好ましい。
上記押圧する際の圧力は特に限定されないが、1〜200Nが好ましい。また、電極1つ当たりの圧力は、0.0001〜1Nが好ましい。上記電極1つ当たりの圧力が0.0001N未満であると、電極同士が接触しないことがある。上記電極1つ当たりの圧力が1Nを超えると、電極がつぶれすぎて隣の電極と接触し、ショートすることがある。
In the second step, the semiconductor chip with a through electrode having the solder layer is pressed using the second pressurizing tool, the through electrode having the solder layer is conducted, and the sealing film is filled with the adhesive film. It is preferable to do.
Although the pressure at the time of the said press is not specifically limited, 1-200N is preferable. Further, the pressure per electrode is preferably 0.0001 to 1N. If the pressure per electrode is less than 0.0001 N, the electrodes may not contact each other. When the pressure per one electrode exceeds 1N, the electrode may be crushed so that it contacts the adjacent electrode and may be short-circuited.

本発明の半導体装置の製造方法では、上記半田層を有する貫通電極付き半導体チップの一辺の長さをA(図1及び2参照)、上記第一の加圧ツールの一辺の長さをB(図1参照)、上記第二の加圧ツールの一辺の長さをC(図2参照)とした場合、比率B/Aが0.9以上であり、比率C/Aが0.85以下である。
上記第一工程では、空気の噛み込みによるボイドを排除するため、上記半田層を有する貫通電極付き半導体チップを該貫通電極付き半導体チップと同程度の大きさの比較的大きい加圧ツールで平行に押圧する必要がある。しかしながら、このような比較的大きい加圧ツールをそのまま上記第二工程で用いると、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制することは難しい。これに対して、上記第二工程では、上記半田層を有する貫通電極付き半導体チップを比較的小さい加圧ツールで押圧することで、半田濡れ性を維持して貫通電極を良好に導通させつつ、半導体チップの周囲に突出するバリの長さを抑制することができる。
In the method for manufacturing a semiconductor device of the present invention, the length of one side of the semiconductor chip with a through electrode having the solder layer is A (see FIGS. 1 and 2), and the length of one side of the first pressure tool is B (see FIG. 1), when the length of one side of the second pressure tool is C (see FIG. 2), the ratio B / A is 0.9 or more and the ratio C / A is 0.85 or less. is there.
In the first step, in order to eliminate voids due to air entrapment, the semiconductor chip with the through electrode having the solder layer is parallelized with a relatively large pressure tool having the same size as the semiconductor chip with the through electrode. It is necessary to press. However, if such a relatively large pressure tool is used in the second step as it is, the length of the burrs protruding around the semiconductor chip is suppressed while maintaining the solder wettability and allowing the through electrode to conduct well. Difficult to do. On the other hand, in the second step, by pressing the semiconductor chip with the through electrode having the solder layer with a relatively small pressure tool, while maintaining the solder wettability and making the through electrode satisfactorily conductive, The length of the burr protruding around the semiconductor chip can be suppressed.

なお、上記半田層を有する貫通電極付き半導体チップ、上記第一の加圧ツール及び上記第二の加圧ツールが正方形の場合は、上記比率B/A及び上記比率C/Aとは、それぞれの一辺、即ち、X軸の長さ同士を比較した比と定義する。
また、上記半田層を有する貫通電極付き半導体チップ、上記第一の加圧ツール及び上記第二の加圧ツールが長方形の場合は、上記比率B/A及び上記比率C/Aとは、それぞれのX軸の長さをAx、Bx及びCx、Y軸の長さをAy、By及びCyとして同じ軸の長さ同士を比較した比と定義する。
In addition, when the semiconductor chip with a through electrode having the solder layer, the first pressure tool, and the second pressure tool are square, the ratio B / A and the ratio C / A are respectively It is defined as a ratio of comparison of lengths of one side, that is, the X-axis.
Further, when the semiconductor chip with a through electrode having the solder layer, the first pressure tool, and the second pressure tool are rectangular, the ratio B / A and the ratio C / A are respectively The length of the X axis is defined as Ax, Bx, and Cx, and the length of the Y axis is defined as Ay, By, and Cy.

上記比率B/Aが0.9未満であると、ボイドを充分に排除することができず、半導体装置の信頼性が低下する。上記比率B/Aの好ましい下限は0.92である。
上記比率B/Aの上限は特に限定されないが、上記接着フィルムを構成する樹脂が上記半田層を有する貫通電極付き半導体チップに這い上がることを抑制する観点から、好ましい上限は0.97である。
If the ratio B / A is less than 0.9, voids cannot be sufficiently eliminated, and the reliability of the semiconductor device is lowered. A preferable lower limit of the ratio B / A is 0.92.
Although the upper limit of the ratio B / A is not particularly limited, the preferable upper limit is 0.97 from the viewpoint of suppressing the resin constituting the adhesive film from creeping up to the semiconductor chip with a through electrode having the solder layer.

上記比率C/Aが0.85を超えると、バリの長さを充分に抑制することができず、不良が生じやすくなる。また、バリを減らすために半田変形を少なくしようとすると、半田の濡れ性が悪化し、貫通電極を良好に導通させることが難しくなる。上記比率C/Aの好ましい上限は0.80である。
上記比率C/Aの下限は特に限定されないが、好ましい下限は0.50、より好ましい下限は0.65である。
When the ratio C / A exceeds 0.85, the burr length cannot be sufficiently suppressed, and defects are likely to occur. Further, if it is attempted to reduce solder deformation in order to reduce burrs, the wettability of the solder deteriorates and it becomes difficult to make the through-electrodes conductive. A preferable upper limit of the ratio C / A is 0.80.
Although the minimum of the said ratio C / A is not specifically limited, A preferable minimum is 0.50 and a more preferable minimum is 0.65.

上記第二工程では、上記接着フィルムは、完全に硬化してもよいし、途中段階まで硬化していてもよい。上記半田層を有する貫通電極を導通させる際に上記接着フィルムが完全に硬化せず途中段階まで硬化している場合には、上記半田層を有する貫通電極を導通させた後に上記接着フィルムを完全に硬化させる2段階の加熱を行ってもよい。 In the second step, the adhesive film may be completely cured or may be cured halfway. In the case where the adhesive film is not completely cured when the through electrode having the solder layer is made conductive, the adhesive film is completely cured after the through electrode having the solder layer is made conductive. Two-stage heating for curing may be performed.

上記第二工程の後、更に、上記接着フィルムを完全に硬化させる工程を別途行ってもよい。必要に応じて上記半田層を有する貫通電極を導通させた後に上記接着フィルムを完全に硬化させればよく、上記半田層を有する貫通電極の導通と上記接着フィルムの硬化とを同時に行うために一挙に加熱する必要がないため、貫通電極付き半導体チップの厚み又は電極高さのばらつきに起因して均一に加熱できず歩留りが低下するという問題を防ぐことができる。 After the second step, a step of completely curing the adhesive film may be performed separately. If necessary, the adhesive film may be completely cured after the through electrode having the solder layer is conducted. In order to simultaneously conduct the through electrode having the solder layer and cure the adhesive film, Therefore, it is possible to prevent the problem that the yield cannot be reduced due to the uneven heating due to the variation in the thickness or the electrode height of the semiconductor chip with the through electrode.

上記接着フィルムは、熱硬化性樹脂及び熱硬化剤を含有することが好ましい。
上記熱硬化性樹脂は特に限定されず、例えば、付加重合、重縮合、重付加、付加縮合、開環重合等の反応により硬化する化合物が挙げられる。上記熱硬化性樹脂として、具体的には例えば、ユリア樹脂、メラミン樹脂、フェノール樹脂、レゾルシノール樹脂、エポキシ樹脂、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリベンズイミダゾール樹脂、ジアリルフタレート樹脂、キシレン樹脂、アルキル−ベンゼン樹脂、エポキシアクリレート樹脂、珪素樹脂、ウレタン樹脂等が挙げられる。
The adhesive film preferably contains a thermosetting resin and a thermosetting agent.
The said thermosetting resin is not specifically limited, For example, the compound hardened | cured by reaction, such as addition polymerization, polycondensation, polyaddition, addition condensation, ring-opening polymerization, is mentioned. Specific examples of the thermosetting resin include urea resin, melamine resin, phenol resin, resorcinol resin, epoxy resin, acrylic resin, polyester resin, polyamide resin, polybenzimidazole resin, diallyl phthalate resin, xylene resin, alkyl -A benzene resin, an epoxy acrylate resin, a silicon resin, a urethane resin, etc. are mentioned.

上記エポキシ樹脂は特に限定されず、例えば、軟化点が150℃以下のエポキシ樹脂、常温で液体又は結晶性固体のエポキシ樹脂等が挙げられる。これらのエポキシ樹脂は、単独で用いられてもよく、二種以上が併用されてもよい。 The epoxy resin is not particularly limited, and examples thereof include an epoxy resin having a softening point of 150 ° C. or lower, an epoxy resin that is liquid or crystalline solid at room temperature, and the like. These epoxy resins may be used independently and 2 or more types may be used together.

上記エポキシ樹脂を含有する場合、上記接着フィルムは、更に、上記エポキシ樹脂と反応可能な官能基を有する高分子化合物(単に、高分子化合物ともいう)を含有してもよい。上記高分子化合物は、造膜成分としての役割を果たす。また、上記高分子化合物を含有することで、上記接着フィルムの硬化物は靭性をもち、優れた耐衝撃性を発現することができる。 When the epoxy resin is contained, the adhesive film may further contain a polymer compound having a functional group capable of reacting with the epoxy resin (also simply referred to as a polymer compound). The polymer compound serves as a film forming component. Moreover, the hardened | cured material of the said adhesive film has toughness by containing the said high molecular compound, and can express the outstanding impact resistance.

上記高分子化合物は特に限定されないが、エポキシ基を有する高分子化合物が好ましい。上記エポキシ基を有する高分子化合物は、末端及び/又は側鎖(ペンダント位)にエポキシ基を有する高分子化合物であれば特に限定されず、例えば、エポキシ基含有アクリルゴム、エポキシ基含有ブタジエンゴム、ビスフェノール型高分子量エポキシ樹脂、エポキシ基含有フェノキシ樹脂、エポキシ基含有アクリル樹脂、エポキシ基含有ウレタン樹脂、エポキシ基含有ポリエステル樹脂等が挙げられる。 Although the said high molecular compound is not specifically limited, The high molecular compound which has an epoxy group is preferable. The polymer compound having an epoxy group is not particularly limited as long as it is a polymer compound having an epoxy group at the terminal and / or side chain (pendant position). For example, an epoxy group-containing acrylic rubber, an epoxy group-containing butadiene rubber, Examples thereof include bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing urethane resin, and epoxy group-containing polyester resin.

上記熱硬化剤は特に限定されず、例えば、フェノール系硬化剤、チオール系硬化剤、アミン系硬化剤、酸無水物等が挙げられる。なかでも、酸無水物が好ましい。酸無水物を用いることにより、上記接着フィルムの硬化後のガラス転移温度Tgを上げて、α1領域を拡大し、硬化後の平均線膨張率を低下させることができる。これにより、半導体装置の信頼性を高めることができる。 The said thermosetting agent is not specifically limited, For example, a phenol type hardening | curing agent, a thiol type hardening | curing agent, an amine type hardening | curing agent, an acid anhydride etc. are mentioned. Of these, acid anhydrides are preferred. By using an acid anhydride, the glass transition temperature Tg after curing of the adhesive film can be increased, the α1 region can be enlarged, and the average linear expansion coefficient after curing can be reduced. Thereby, the reliability of the semiconductor device can be improved.

上記熱硬化剤の含有量は特に限定されないが、上記熱硬化性樹脂と上記高分子化合物との合計100重量部に対する好ましい下限が5重量部、好ましい上限が150重量部である。上記熱硬化剤の含有量が5重量部未満であると、上記接着フィルムの硬化物が固く脆くなり接合信頼性が低下することがある。上記熱硬化剤の含有量が150重量部を超えることでも、上記接着フィルムの接合信頼性が低下することがある。上記熱硬化剤の含有量のより好ましい下限は10重量部、より好ましい上限は140重量部である。 Although content of the said thermosetting agent is not specifically limited, The preferable minimum with respect to a total of 100 weight part of the said thermosetting resin and the said high molecular compound is 5 weight part, and a preferable upper limit is 150 weight part. When the content of the thermosetting agent is less than 5 parts by weight, the cured product of the adhesive film becomes hard and brittle, and the bonding reliability may be lowered. Even if the content of the thermosetting agent exceeds 150 parts by weight, the bonding reliability of the adhesive film may be lowered. The minimum with more preferable content of the said thermosetting agent is 10 weight part, and a more preferable upper limit is 140 weight part.

上記接着フィルムは、更に、硬化促進剤を含有してもよい。
上記硬化促進剤は特に限定されないが、イミダゾール化合物が好ましい。上記イミダゾール化合物は上記エポキシ樹脂との反応性が高いことから、上記エポキシ樹脂と上記イミダゾール化合物とを含有することで、上記接着フィルムの速硬化性が向上する。
The adhesive film may further contain a curing accelerator.
Although the said hardening accelerator is not specifically limited, An imidazole compound is preferable. Since the said imidazole compound has high reactivity with the said epoxy resin, the quick curability of the said adhesive film improves by containing the said epoxy resin and the said imidazole compound.

上記接着フィルムは、更に、無機フィラーを含有することが好ましい。上記無機フィラーを上記接着フィルムに配合することにより、全温度領域での硬化後の線膨張率を低減することができ、半導体装置の信頼性を高めることができる。 The adhesive film preferably further contains an inorganic filler. By mix | blending the said inorganic filler with the said adhesive film, the linear expansion coefficient after hardening in a whole temperature range can be reduced, and the reliability of a semiconductor device can be improved.

上記無機フィラーの含有量は、前述の熱硬化性樹脂と熱硬化剤と高分子化合物との合計100重量部に対する好ましい下限は40重量部、好ましい上限は400重量部である。上記無機フィラーの含有量が40重量部未満であると、上記無機フィラーを添加する効果をほとんど得ることができないことがある。上記無機フィラーの含有量が400重量部を超えると、上記接着フィルムの硬化後の線膨張率は低下するものの、電極接続信頼性が低下することがある。上記無機フィラーの含有量のより好ましい下限は50重量部、より好ましい上限は350重量部、更に好ましい下限は60重量部、更に好ましい上限は300重量部である。 As for the content of the inorganic filler, a preferable lower limit with respect to 100 parts by weight of the total of the thermosetting resin, the thermosetting agent, and the polymer compound is 40 parts by weight, and a preferable upper limit is 400 parts by weight. If the content of the inorganic filler is less than 40 parts by weight, the effect of adding the inorganic filler may be hardly obtained. When content of the said inorganic filler exceeds 400 weight part, although the linear expansion coefficient after hardening of the said adhesive film falls, electrode connection reliability may fall. The more preferable lower limit of the content of the inorganic filler is 50 parts by weight, the more preferable upper limit is 350 parts by weight, the still more preferable lower limit is 60 parts by weight, and the still more preferable upper limit is 300 parts by weight.

上記接着フィルムは、本発明の効果を阻害しない範囲内で希釈剤を含有してもよい。上記希釈剤は特に限定されないが、上記接着フィルムの硬化系に取り込まれる反応性希釈剤が好ましい。なかでも、上記接着フィルムの接合信頼性を悪化させないために、1分子中に2以上の官能基を有する反応性希釈剤がより好ましい。 The said adhesive film may contain a diluent within the range which does not inhibit the effect of this invention. Although the said diluent is not specifically limited, The reactive diluent taken in into the hardening system of the said adhesive film is preferable. Among these, in order not to deteriorate the bonding reliability of the adhesive film, a reactive diluent having two or more functional groups in one molecule is more preferable.

上記希釈剤の含有量は特に限定されないが、上記熱硬化性樹脂と上記高分子化合物との合計100重量部に対する好ましい下限は1重量部、好ましい上限は100重量部である。上記希釈剤の含有量が1重量部未満であると、上記希釈剤を添加する効果をほとんど得ることができないことがある。上記希釈剤の含有量が100重量部を超えると、上記接着フィルムの硬化物が固く脆くなり接合信頼性が低下することがある。上記希釈剤の含有量のより好ましい下限は5重量部、より好ましい上限は70重量部である。 The content of the diluent is not particularly limited, but a preferred lower limit for the total of 100 parts by weight of the thermosetting resin and the polymer compound is 1 part by weight, and a preferred upper limit is 100 parts by weight. If the content of the diluent is less than 1 part by weight, the effect of adding the diluent may be hardly obtained. When content of the said diluent exceeds 100 weight part, the hardened | cured material of the said adhesive film may become hard and brittle, and joining reliability may fall. A more preferable lower limit of the content of the diluent is 5 parts by weight, and a more preferable upper limit is 70 parts by weight.

上記接着フィルムは、必要に応じて、無機イオン交換体を含有してもよい。上記無機イオン交換体の含有量は特に限定されないが、上記接着フィルム中の好ましい下限が1重量%、好ましい上限が10重量%である。
上記接着フィルムは、その他必要に応じて、ブリード防止剤、シランカップリング剤、フラックス剤や増粘剤等の添加剤を含有してもよい。
The said adhesive film may contain an inorganic ion exchanger as needed. Although content of the said inorganic ion exchanger is not specifically limited, The preferable minimum in the said adhesive film is 1 weight%, and a preferable upper limit is 10 weight%.
The said adhesive film may contain additives, such as a bleed inhibitor, a silane coupling agent, a flux agent, and a thickener, as needed.

上記接着フィルムは、100〜180℃における最低溶融粘度が50〜1500Pa・sであることが好ましい。このような狭い範囲の最低溶融粘度を有する接着フィルムを用いることにより、空気の噛み込みによるボイドの発生を低減することで、更に信頼性の高い半導体装置が得られる。
上記最低溶融粘度が50Pa・s未満であると、上記接着フィルムと上記半田層を有する貫通電極との間にボイドが発生しやすくなることがある。上記最低溶融粘度が1500Pa・sを超えると、上記半田層を有する貫通電極と、この貫通電極に対向する基板や半導体ウエハや半導体チップに形成された電極との接続が阻害されることがある。上記最低溶融粘度のより好ましい下限は100Pa・s、より好ましい上限は1000Pa・sである。
なお、上記100〜180℃における最低溶融粘度とは、100〜180℃における最低複素粘度η*minであり、上記接着フィルムについて、レオメーター(例えば、REOLOGICA社製のSTRESSTECH)を用いて、サンプル厚み600μm、歪制御(1rad)、周波数10Hz、昇温速度20℃/minの条件で測定温度範囲30〜180℃で測定を行うことで求めることができる。
The adhesive film preferably has a minimum melt viscosity at 100 to 180 ° C. of 50 to 1500 Pa · s. By using such an adhesive film having a minimum melt viscosity in a narrow range, the generation of voids due to air entrapment is reduced, and thus a more reliable semiconductor device can be obtained.
If the minimum melt viscosity is less than 50 Pa · s, a void may easily occur between the adhesive film and the through electrode having the solder layer. When the minimum melt viscosity exceeds 1500 Pa · s, connection between the through electrode having the solder layer and an electrode formed on a substrate, a semiconductor wafer, or a semiconductor chip facing the through electrode may be hindered. A more preferable lower limit of the minimum melt viscosity is 100 Pa · s, and a more preferable upper limit is 1000 Pa · s.
The minimum melt viscosity at 100 to 180 ° C. is the minimum complex viscosity η * min at 100 to 180 ° C., and the adhesive film is measured using a rheometer (for example, STRESSTECH manufactured by REOLOGICA Co.). It can be determined by performing measurement in the measurement temperature range of 30 to 180 ° C. under the conditions of 600 μm, strain control (1 rad), frequency 10 Hz, and heating rate 20 ° C./min.

上記接着フィルムは、硬化後の25〜265℃における平均線膨張率が100ppm/℃未満であることが好ましい。上記硬化後の平均線膨張率が100ppm/℃以上であると、信頼性評価において、導通部分への変形応力が大きくなり、電極接続が破断することがある。上記平均線膨張率のより好ましい上限は90ppm/℃、更に好ましい上限は80ppm/℃である。上記平均線膨張率の下限は、上記半田層を有する貫通電極の導通が阻害されなければ、特に限定されないが、無機フィラー充填率が90%以上になり平均線膨張率が低下しすぎると、導通が阻害されることがある。上記平均線膨張率の好ましい下限は、25ppm/℃である。
なお、上記硬化後の25〜265℃における平均線膨張率は、熱応力歪測定装置(例えば、エスアイアイ・ナノテクノロジー社製のTMA/SS6000)を用いて0℃から300℃の範囲で上記接着フィルムの硬化物の線膨張率を測定し、このとき得られた25℃から265℃までの線膨張率のSSカーブの傾きから平均値を算出することで求めることができる。
The adhesive film preferably has an average linear expansion coefficient at 25 to 265 ° C. after curing of less than 100 ppm / ° C. When the average coefficient of linear expansion after the curing is 100 ppm / ° C. or more, in the reliability evaluation, the deformation stress to the conductive portion is increased, and the electrode connection may be broken. A more preferable upper limit of the average linear expansion coefficient is 90 ppm / ° C., and a more preferable upper limit is 80 ppm / ° C. The lower limit of the average linear expansion coefficient is not particularly limited as long as the conduction of the through electrode having the solder layer is not hindered. However, when the inorganic filler filling ratio is 90% or more and the average linear expansion coefficient is too low, the conduction is reduced. May be inhibited. A preferable lower limit of the average linear expansion coefficient is 25 ppm / ° C.
In addition, the average linear expansion coefficient in 25-265 degreeC after the said hardening is the said adhesion | attachment in the range of 0 degreeC to 300 degreeC using a thermal-stress-strain measuring apparatus (For example, TMA / SS6000 by SII nanotechnology company). The linear expansion coefficient of the cured product of the film can be measured, and the average value can be calculated from the slope of the SS curve of the linear expansion coefficient from 25 ° C. to 265 ° C. obtained at this time.

上記最低溶融粘度と上記平均線膨張率とを上記範囲に調整する方法としては、例えば、好ましくは熱硬化性樹脂及び熱硬化剤を含有する上記接着フィルムに対して、更に、無機フィラーを配合する方法が挙げられる。なかでも、無機フィラーの平均粒子径及び含有量を調整する方法が好ましい。 As a method for adjusting the minimum melt viscosity and the average linear expansion coefficient to the above ranges, for example, an inorganic filler is preferably further blended with the adhesive film preferably containing a thermosetting resin and a thermosetting agent. A method is mentioned. Especially, the method of adjusting the average particle diameter and content of an inorganic filler is preferable.

上記接着フィルムは、硬化後のガラス転移温度Tgが160〜260℃であることが好ましく、170〜240℃であることがより好ましい。このような範囲のTgを有する接着フィルムを用いることにより、更に信頼性に優れた半導体装置が得られる。
なお、上記硬化後のTgは、熱応力歪測定装置(例えば、エスアイアイ・ナノテクノロジー社製のTMA/SS6000)を用いて0℃から300℃の範囲で上記接着フィルムの硬化物の線膨張率を測定し、このとき得られたSSカーブの変曲点から求めることができる。
The adhesive film preferably has a glass transition temperature Tg after curing of 160 to 260 ° C, and more preferably 170 to 240 ° C. By using an adhesive film having Tg in such a range, a semiconductor device with further improved reliability can be obtained.
In addition, Tg after the said hardening is a linear expansion coefficient of the hardened | cured material of the said adhesive film in the range of 0 degreeC to 300 degreeC using a thermal stress strain measuring apparatus (for example, TMA / SS6000 by SII nanotechnology company). Can be obtained from the inflection point of the SS curve obtained at this time.

上記接着フィルムを製造する方法は特に限定されず、例えば、必要に応じて熱硬化性樹脂、熱硬化剤、硬化促進剤、高分子化合物、無機フィラー、溶剤、その他の添加剤等を所定量配合して混合し、得られた樹脂組成物を離型フィルム上に塗工し、乾燥させる方法等が挙げられる。上記混合の方法は特に限定されず、例えば、ホモディスパー、万能ミキサー、バンバリーミキサー、ニーダー等を使用する方法が挙げられる。 The method for producing the adhesive film is not particularly limited. For example, a predetermined amount of a thermosetting resin, a thermosetting agent, a curing accelerator, a polymer compound, an inorganic filler, a solvent, or other additives is blended as necessary. And a method of coating the resulting resin composition on a release film and drying it. The mixing method is not particularly limited, and examples thereof include a method using a homodisper, a universal mixer, a Banbury mixer, a kneader and the like.

本発明によれば、半導体ウエハ上に貫通電極付き半導体チップを積層する際に、ボイドを抑制でき、貫通電極を良好に導通させることができ、半導体チップの周囲に突出するバリの長さを抑制できる半導体装置の製造方法を提供することができる。 According to the present invention, when a semiconductor chip with a through electrode is stacked on a semiconductor wafer, voids can be suppressed, the through electrode can be conducted well, and the length of burrs protruding around the semiconductor chip is suppressed. A method of manufacturing a semiconductor device that can be provided can be provided.

本発明の半導体装置の製造方法における第一工程の一例を模式的に示す図である。It is a figure which shows typically an example of the 1st process in the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法における第二工程の一例を模式的に示す図である。It is a figure which shows typically an example of the 2nd process in the manufacturing method of the semiconductor device of this invention.

以下に実施例を掲げて本発明の態様を更に詳しく説明するが、本発明はこれら実施例のみに限定されない。 Examples of the present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

(実施例1〜6及び比較例1〜2)
(1)接着フィルムの製造
表1に記載の組成に従って、下記に示す材料を溶剤に添加して攪拌混合し、樹脂組成物を調製した。得られた樹脂組成物を離型フィルム上に塗工し、乾燥させて、接着フィルムを得た。
1.エポキシ樹脂
ビスフェノールA型エポキシ樹脂(1004AF、ジャパンエポキシレジン社製)
ビスフェノールA型エポキシ樹脂(EXA−830CRP、DIC社製)
2.高分子化合物
アクリル樹脂(G−2050M、日油社製)
3.熱硬化剤及び硬化促進剤
酸無水物(YH−309、三菱化学社製)
イミダゾール(2MA−OK、四国化成社製)
4.無機フィラー
球状シリカ(YA050C−SP1、アドマテックス社製)
球状シリカ(SE−1050−SPJ、アドマテックス社製)
(Examples 1-6 and Comparative Examples 1-2)
(1) Manufacture of adhesive film According to the composition described in Table 1, the following materials were added to a solvent and mixed by stirring to prepare a resin composition. The obtained resin composition was applied onto a release film and dried to obtain an adhesive film.
1. Epoxy resin bisphenol A type epoxy resin (1004AF, manufactured by Japan Epoxy Resin Co., Ltd.)
Bisphenol A type epoxy resin (EXA-830CRP, manufactured by DIC)
2. High molecular compound acrylic resin (G-2050M, NOF Corporation)
3. Thermosetting agent and curing accelerator acid anhydride (YH-309, manufactured by Mitsubishi Chemical Corporation)
Imidazole (2MA-OK, manufactured by Shikoku Chemicals)
4). Inorganic filler spherical silica (YA050C-SP1, manufactured by Admatechs)
Spherical silica (SE-1050-SPJ, manufactured by Admatechs)

(2)最低溶融粘度の測定
得られた接着フィルムについて、レオメーター(REOLOGICA社製のSTRESSTECH)を用いて、サンプル厚み600μm、歪制御(1rad)、周波数10Hz、昇温速度20℃/minの条件で測定温度範囲30〜180℃℃で測定を行うことで、100〜180℃における最低複素粘度η*minを求め、最低溶融粘度とした。
(2) Measurement of Minimum Melt Viscosity About the obtained adhesive film, using a rheometer (STRESSTECH manufactured by REOLOGICA), sample thickness 600 μm, strain control (1 rad), frequency 10 Hz, heating rate 20 ° C./min The minimum complex viscosity η * min at 100 to 180 ° C. was determined by measuring at a measurement temperature range of 30 to 180 ° C., and was defined as the minimum melt viscosity.

(3)半導体装置の製造
シリコンチップA1、A2、A3(一辺7.3μmの正方形、厚み50μm、片面に直径20μm、高さ10μmのNi/Auめっきされた電極が形成されており、もう一方の面に直径20μm、高さ10μmの銅バンプが形成され、銅バンプの上に厚み5μmのSn−3.5Ag半田層が形成されているTSVチップ)と、シリコンチップB(片面に直径20μm、高さ10μmのNi/Auめっきされた電極が形成されており、もう一方の面には電極やバンプが形成されていないチップ)とを準備した。
シリコンチップA1、A2、A3の半田層を有する銅バンプが形成されている面に、接着フィルムを真空ラミネーター(ATM−812M、タカトリ社製)を用いてステージ温度80℃、真空度100Pa・sの条件下でラミネートし、その後、チップからはみ出した余分な接着フィルムをカッターで切断除去した。
(3) Manufacture of semiconductor device Silicon chips A1, A2 and A3 (a square of 7.3 μm on a side, a thickness of 50 μm, a Ni / Au plated electrode having a diameter of 20 μm and a height of 10 μm on one side is formed. A TSV chip in which a copper bump having a diameter of 20 μm and a height of 10 μm is formed on the surface, and a Sn-3.5Ag solder layer having a thickness of 5 μm is formed on the copper bump, and a silicon chip B (a diameter of 20 μm, high on one side) A 10 μm-thick Ni / Au plated electrode and a chip on which the electrode and bump are not formed on the other surface were prepared.
Using a vacuum laminator (ATM-812M, manufactured by Takatori), an adhesive film is formed on the surface on which the copper bumps having the solder layers of the silicon chips A1, A2, and A3 are formed. The stage temperature is 80 ° C. and the degree of vacuum is 100 Pa · s. Lamination was performed under the conditions, and then the excess adhesive film protruding from the chip was cut off with a cutter.

下記に示す方法により、11個の仮置き積層体を作製した。
フリップチップボンダ(FC3000S、東レエンジニアリング社製)及び第一の加圧ツール(表1に記載の一辺の長さを有する正方形)を用いて、シリコンチップA1の接着フィルムが付着した面を、ステージ温度60℃、加圧ツール温度(仮置き温度)100℃で2秒間、20NでシリコンチップBの電極が形成されている側に仮置きした。次に、シリコンチップA2の接着フィルムが付着した面を、同じ条件でシリコンチップA1の接着フィルムが付着していない面に対して仮置きした。更に、シリコンチップA3の接着フィルムが付着した面を、同じ条件でシリコンチップA2の接着フィルムが付着していない面に対して仮置きした。これにより、シリコンチップBの電極が形成されている面側に接着フィルムを介してシリコンチップA1、A2、A3が3段積層された仮置き積層体を作製した。なお、この時点ではそれぞれのシリコンチップの半田層を有する銅バンプはまだ半田接合(導通)していない。
次いで、フリップチップボンダ(FC−3000S、東レエンジニアリング社製)及び第二の加圧ツール(表1に記載の一辺の長さを有する正方形)を用いて、11個の仮置き積層体を大気圧下、以下の温度条件で加熱してそれぞれのシリコンチップの半田層を有する銅バンプを半田接合した。その後、170℃で30分間加熱しながら加圧し、接着フィルムを完全に硬化させ、11個の半導体装置を得た。なお、加圧時の荷重は20Nとした。
(温度条件)
1.160℃で5秒間加熱
2.2秒間で160℃から280℃まで昇温
3.280℃で5秒間維持
4.3秒間で280℃から160℃まで降温
Eleven temporary stacks were produced by the method described below.
Using a flip chip bonder (FC3000S, manufactured by Toray Engineering Co., Ltd.) and a first pressurizing tool (a square having a length of one side described in Table 1), the surface of the silicon chip A1 with the adhesive film adhered thereto is measured at the stage temperature. Temporary placement was performed on the side on which the electrode of the silicon chip B was formed at 20 N at 60 ° C. and a pressure tool temperature (temporary placement temperature) of 100 ° C. for 2 seconds. Next, the surface of the silicon chip A2 to which the adhesive film was attached was temporarily placed on the surface of the silicon chip A1 to which the adhesive film was not attached under the same conditions. Furthermore, the surface to which the adhesive film of the silicon chip A3 adhered was temporarily placed on the surface to which the adhesive film of the silicon chip A2 did not adhere under the same conditions. In this way, a temporary stacked body was produced in which the silicon chips A1, A2, and A3 were stacked in three layers on the surface side where the electrodes of the silicon chip B were formed via the adhesive film. At this time, the copper bumps having the solder layers of the respective silicon chips are not yet soldered (conducted).
Then, using the flip chip bonder (FC-3000S, manufactured by Toray Engineering Co., Ltd.) and the second pressurizing tool (square having the length of one side described in Table 1), the 11 temporarily placed laminates were atmospheric pressure. Below, the copper bump which has the solder layer of each silicon chip was solder-joined by heating on the following temperature conditions. Thereafter, pressure was applied while heating at 170 ° C. for 30 minutes to completely cure the adhesive film, thereby obtaining 11 semiconductor devices. The load during pressurization was 20N.
(Temperature conditions)
1. Heating at 160 ° C for 5 seconds Heating from 160 ° C to 280 ° C in 2.2 seconds 3. Maintaining at 280 ° C for 5 seconds 4.3 Temperature falling from 280 ° C to 160 ° C in 3 seconds

<評価>
実施例及び比較例で得られた半導体装置について、下記の評価を行った。結果を表1に示した。
<Evaluation>
The following evaluation was performed about the semiconductor device obtained by the Example and the comparative example. The results are shown in Table 1.

(1)電極接続信頼性
得られた11個の半導体装置を断面研磨し、電極接続がなされていないものを×とした。貫通電極に対向する半導体チップに形成された電極面と貫通電極の電極面との間が電極接続しておらず、対向する電極面の一部部分に樹脂が挟まった状態(樹脂噛み)が見られたものを△とし、電極接続部分に樹脂噛みが見られなかったものを○とした。
(1) Electrode connection reliability The 11 semiconductor devices obtained were subjected to cross-sectional polishing, and those having no electrode connection were marked with x. There is no electrode connection between the electrode surface formed on the semiconductor chip facing the through electrode and the electrode surface of the through electrode, and a state in which resin is sandwiched between a part of the facing electrode surface (resin bite) is seen. The case where the resin bite was not observed in the electrode connection portion was indicated as ◯.

(2)ボイド
得られた11個の半導体装置を超音波探傷装置SAT(日立建機ファインテック社製「mi−scope」)にて観察し、シリコンチップの剥離が見られた面積が5%未満のものを○、10%以上のものを×と評価した。
(2) Eleven semiconductor devices obtained with voids were observed with an ultrasonic flaw detector SAT (“mi-scope” manufactured by Hitachi Construction Machinery Finetech Co., Ltd.), and the area where the silicon chip was peeled was less than 5% The thing of 10% or more was evaluated as x.

(3)バリの長さ
得られた11個の半導体装置を光学顕微鏡で300倍に拡大し、観察視野にある半導体装置をそれぞれ上から写真撮影した。得られたそれぞれの写真を眺め、それぞれの半導体装置についてシリコンチップの周囲に突出しているバリの長さが一番長い部分を選んでその長さ(バリの最大長さ)を測定した。
半導体装置11個についてのバリの最大長さの平均値を求め、平均値が40μm以下のものを○、40μmを超えるものを×と評価した。
なお、バリの最大長さを測定する際には、バリが伸びている根元の半導体チップの端部から、バリが半導体チップの端部から一番離れている部分までの長さを測定した。
(3) Burr length The eleven semiconductor devices obtained were magnified 300 times with an optical microscope, and each semiconductor device in the observation field was photographed from above. Each of the obtained photographs was looked at, and for each semiconductor device, the part having the longest burr protruding around the silicon chip was selected and the length (maximum burr length) was measured.
The average value of the maximum burr length for 11 semiconductor devices was determined, and the average value of 40 μm or less was evaluated as “◯” and the average value exceeding 40 μm was evaluated as “X”.
When measuring the maximum length of the burr, the length from the end of the base semiconductor chip where the burr extends to the part where the burr is farthest from the end of the semiconductor chip was measured.

Figure 2016072400
Figure 2016072400

本発明によれば、半導体ウエハ上に貫通電極付き半導体チップを積層する際に、ボイドを抑制でき、貫通電極を良好に導通させることができ、半導体チップの周囲に突出するバリの長さを抑制できる半導体装置の製造方法を提供することができる。 According to the present invention, when a semiconductor chip with a through electrode is stacked on a semiconductor wafer, voids can be suppressed, the through electrode can be conducted well, and the length of burrs protruding around the semiconductor chip is suppressed. A method of manufacturing a semiconductor device that can be provided can be provided.

1 接着フィルム
2 半田層を有する貫通電極付き半導体チップ
A 半田層を有する貫通電極付き半導体チップの一辺の長さ
3 半田層
4 ビヤ
5 半導体ウエハ
6 電極
7 第一の加圧ツール
B 第一の加圧ツールの一辺の長さ
8 第二の加圧ツール
C 第二の加圧ツールの一辺の長さ
DESCRIPTION OF SYMBOLS 1 Adhesive film 2 Semiconductor chip A with penetration electrode which has solder layer Length of one side of semiconductor chip with penetration electrode which has solder layer 3 Solder layer 4 Beer 5 Semiconductor wafer 6 Electrode 7 First pressurizing tool B First addition Length of one side of the pressure tool 8 Second pressure tool C Length of one side of the second pressure tool

Claims (2)

接着フィルムを貼り合わせた半田層を有する貫通電極付き半導体チップを、第一の加圧ツールを用いて半田溶融温度以下の温度に加熱しながら半導体ウエハ上に仮置きする第一工程と、
前記半導体ウエハ上に仮置きされた前記半田層を有する貫通電極付き半導体チップを、第二の加圧ツールを用いて半田溶融温度以上の温度に加熱して前記半田層を有する貫通電極を導通させる第二工程とを有し、
前記半田層を有する貫通電極付き半導体チップの一辺の長さをA、前記第一の加圧ツールの一辺の長さをB、前記第二の加圧ツールの一辺の長さをCとした場合、比率B/Aが0.9以上であり、比率C/Aが0.85以下である
ことを特徴とする半導体装置の製造方法。
A first step of temporarily placing a semiconductor chip with a through electrode having a solder layer bonded with an adhesive film on a semiconductor wafer while being heated to a temperature equal to or lower than a solder melting temperature using a first pressure tool;
A semiconductor chip with a through electrode having the solder layer temporarily placed on the semiconductor wafer is heated to a temperature equal to or higher than a solder melting temperature by using a second pressure tool, and the through electrode having the solder layer is made conductive. A second step,
When the length of one side of the semiconductor chip with a through electrode having the solder layer is A, the length of one side of the first pressing tool is B, and the length of one side of the second pressing tool is C The ratio B / A is 0.9 or more, and the ratio C / A is 0.85 or less.
接着フィルムは、100〜180℃における最低溶融粘度が50〜1500Pa・sであることを特徴とする請求項1記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the adhesive film has a minimum melt viscosity at 100 to 180 ° C. of 50 to 1500 Pa · s.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022102181A1 (en) * 2020-11-13 2022-05-19 昭和電工マテリアルズ株式会社 Semiconductor device manufacturing method and adhesive used therein

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022102181A1 (en) * 2020-11-13 2022-05-19 昭和電工マテリアルズ株式会社 Semiconductor device manufacturing method and adhesive used therein

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