JP2016058660A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can suppress leakage current and achieve high breakdown voltage.SOLUTION: A semiconductor device comprises a MOS gate structure provided on a surface side of a silicon carbide semiconductor base substrate in which an n type silicon carbide epitaxial layer 2 is deposited on an ntype silicon carbide substrate 1. The MOS gate structure includes a p type base region 3 composed of a first p type base region 3a, a second p type base region 3b and a third ptype base region 3c, which have impurity concentrations different from each other and contact one another. The first p type base region 3a is arranged to be exposed on the surface of the base substrate. The second p type base region 3b is arranged to be opposite to the first p type base region 3a in a depth direction. The third ptype base region 3c is selectively provided inside the second p type base region 3b so as to be sandwiched by the first and second p type baser regions 3a, 3b. A circumference of a rear face side of the third ptype base region 3c is surrounded by the second p type base region 3b.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  In a semiconductor device using a silicon carbide (SiC) semiconductor (hereinafter referred to as a silicon carbide semiconductor device), it is difficult to form an impurity semiconductor region of any conductivity type by a thermal diffusion method. For this reason, an ion implantation method is used to form an impurity semiconductor region of any conductivity type. Further, an activation heat treatment is performed at a high temperature after ion implantation, and the implanted dopant is replaced with a lattice point of the silicon carbide semiconductor to generate carriers, whereby the impurity semiconductor region is operated as an arbitrary conductive semiconductor. However, it has been reported that when an impurity semiconductor region having a high impurity concentration is formed by ion implantation, the high-temperature activation treatment adversely affects lattice defects existing in the silicon carbide semiconductor substrate and adversely affects electrical characteristics. (For example, refer to the following non-patent document 1.)

  For example, when a high breakdown voltage MOSFET (Metal Oxide Field Effect Transistor) is manufactured (manufactured) as a silicon carbide semiconductor device (see, for example, Non-Patent Document 2 below), there are the following problems. Usually, the p-type base region is formed by ion implantation. When the impurity concentration of the p-type base region is low, the substrate surface is depleted at a low voltage, so that a high breakdown voltage cannot be obtained. Further, when the impurity concentration of the p-type base region is high, the adverse effect of lattice defects appears as described above, and the leakage current increases. These problems can be avoided by increasing the thickness of the p-type base region.

However, since the thickness (depth) of the p-type base region is limited by the performance of a manufacturing apparatus such as an ion implantation apparatus, it is not practical to increase the thickness of the p-type base region. Further, p-type base region the n ^- since it is formed in the surface layer of the type drift layer, in anticipation of the thickness of the p-type base region n ^- need to increase the thickness of the type drift layer, causing increased costs . Therefore, at present, it is common to fabricate a MOSFET using a silicon carbide semiconductor by limiting conditions other than the thickness of the p-type base region (for example, the following Patent Document 1 (paragraph 0053) and the following) (See Patent Document 2 (paragraph 0064).)

JP-A-10-308510 Japanese Patent No. 5408248

T. Tsuji, 11 others, Analyzes of High Leakage Currents in Al + Implanted in Al + Implanted 4H SiC pn Diodes Caused by Threading Screw Dislocations by Threading Screed Dislocations), Materials Science Forum, 2010, 645-648, p. 913-916 By B. Jayant Baliga, Silicon Carbide Power Devices (USA), World Scientific Publishing Co. (World Scientific Publishing Co.), 30th March, 200 p. . 260

  However, in the method for limiting the conditions of the p-type base region described above, there is a high possibility that the conditions of the p-type base region deviate from suitable conditions due to device performance, and the yield decreases. Further, in the high breakdown voltage element, since the impurity concentration of the p-type base region needs to be increased, the leakage current increases as described above. For this reason, it is difficult to manufacture an element in which leakage current is suppressed.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of suppressing a leakage current and achieving a high breakdown voltage in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A first conductive type first semiconductor layer made of a silicon carbide semiconductor having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate made of a silicon carbide semiconductor. A second conductivity type first semiconductor region is selectively provided in a surface layer of the first semiconductor layer opposite to the semiconductor substrate side. A second semiconductor region of a first conductivity type is selectively provided inside the first semiconductor region. A gate electrode is provided on a surface of a portion of the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor region via a gate insulating film. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate. The first semiconductor region includes a first semiconductor part, a second semiconductor part, and a third semiconductor part. The first semiconductor portion faces the gate electrode in the depth direction through the gate insulating film. The second semiconductor part is provided closer to the second electrode than the first semiconductor part, and is adjacent to the first semiconductor part in the depth direction. The third semiconductor part has an impurity concentration higher than that of the second semiconductor part selectively provided inside the second semiconductor part.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following characteristics. A first conductive type first semiconductor layer made of a silicon carbide semiconductor having an impurity concentration lower than that of the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate made of a silicon carbide semiconductor. A second conductivity type second semiconductor layer made of a silicon carbide semiconductor is provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side. A first semiconductor region of a second conductivity type is selectively provided at a depth extending from the surface of the second semiconductor layer opposite to the first semiconductor layer side to the surface layer of the first semiconductor layer. Yes. A second semiconductor region of a first conductivity type is selectively provided inside the first semiconductor region. A third semiconductor region of the first conductivity type is provided at a depth reaching the first semiconductor layer at a portion sandwiched between the adjacent first semiconductor regions of the second semiconductor layer. A gate electrode is provided on a surface of a portion of the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor region via a gate insulating film. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. A second electrode is provided on the back surface of the semiconductor substrate. The first semiconductor region includes a first semiconductor part, a second semiconductor part, and a third semiconductor part. The first semiconductor part is constituted by a part of the second semiconductor layer, and faces the gate electrode in the depth direction through the gate insulating film. The second semiconductor portion is provided in a surface layer of the first semiconductor layer on the second semiconductor layer side, and is adjacent to the first semiconductor portion in the depth direction. The third semiconductor part has an impurity concentration higher than that of the second semiconductor part selectively provided inside the second semiconductor part.

  In the semiconductor device according to the present invention as set forth in the invention described above, the third semiconductor portion is in contact with the first semiconductor portion on the first electrode side, and the periphery of the second electrode side is the second semiconductor portion. It is characterized by being surrounded.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor portion is not more than 0.1 times the impurity concentration of the third semiconductor portion.

  In the semiconductor device according to the present invention, in the above-described invention, the width of the portion of the third semiconductor portion sandwiched between the first semiconductor layer and the second semiconductor portion is 0.1 μm or more. Features.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor portion is higher than the impurity concentration of the first semiconductor portion.

  In the semiconductor device according to the present invention as set forth in the invention described above, the front surface of the semiconductor substrate is inclined at 10 degrees or less with respect to a plane parallel to the (000-1) plane or the (000-1) plane. It is characterized by a flat surface.

  In the semiconductor device according to the present invention, in the above-described invention, the front surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane tilted to 10 degrees or less with respect to the (0001) plane. It is characterized by that.

  According to the above-described invention, it is possible to suppress the depletion of the substrate surface at a low voltage by providing the third semiconductor portion having an impurity concentration higher than that of the second semiconductor portion inside the second semiconductor portion. it can. Thereby, it can suppress that a proof pressure falls, and can achieve a high proof pressure. According to the above-described invention, the third semiconductor portion is surrounded by the second semiconductor portion having an impurity concentration lower than that of the third semiconductor portion, so that a high leakage current is generated due to crystal defects caused by the high concentration impurity ion implantation. The electric field load on the third semiconductor part that is likely to be caused can be reduced. Thereby, it is possible to prevent an increase in leakage current due to an adverse effect of crystal defects.

  According to the semiconductor device of the present invention, a high breakdown voltage and a low leakage current can be realized. Thereby, it is possible to produce (manufacture) a semiconductor device having a high yield and a high withstand voltage regardless of the performance of the semiconductor manufacturing apparatus.

1 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment. FIG. 3 is a cross sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross sectional view schematically showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the first embodiment. 10 is a cross sectional view showing a configuration of a silicon carbide semiconductor device of Comparative Example 1. FIG. 3 is a frequency distribution diagram showing leakage current characteristics of the silicon carbide semiconductor device according to Example 1. FIG. FIG. 6 is a characteristic diagram showing a relationship between an impurity concentration ratio of a p-type base region and a leakage current of the silicon carbide semiconductor device according to Example 1; FIG. 5 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment. 12 is a cross sectional view showing a configuration of a silicon carbide semiconductor device of Comparative Example 2. FIG. FIG. 6 is a frequency distribution diagram showing leakage current characteristics of the silicon carbide semiconductor device according to Example 2; 6 is a characteristic diagram showing a relationship between an impurity concentration ratio of a p-type base region and a leakage current of a silicon carbide semiconductor device according to Example 2. FIG.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. When the notations of n and p including + and − are the same, it means that the layer or region to which it is attached has a close impurity concentration, and the impurity concentration is not necessarily equal. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In the Miller index notation, “−” means a bar attached to the index immediately after it, and “−” is added before the index to indicate a negative index.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured using a semiconductor having a wider band gap than a silicon (Si) semiconductor (hereinafter referred to as a wide band gap semiconductor). In the first embodiment, a silicon carbide semiconductor device using, for example, a silicon carbide (SiC) semiconductor as a wide band gap semiconductor will be described by taking a MOSFET (hereinafter referred to as a silicon carbide MOSFET) as an example. FIG. 1 is a cross-sectional view showing a configuration of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment has an n-type silicon carbide epitaxial layer (first semiconductor layer) 2 stacked on the main surface of an n ⁺ -type silicon carbide substrate (semiconductor substrate) 1. It is comprised using the silicon carbide epitaxial substrate (semiconductor chip) formed.

The n ⁺ type silicon carbide substrate 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N), and constitutes an n ⁺ type drain layer. The main surface (front surface) of n ⁺ -type silicon carbide substrate 1 has, for example, a (000-1) plane or an off angle of about 10 degrees or less in the <11-20> direction (000-1). It may be a surface. N-type silicon carbide epitaxial layer 2 is doped with, for example, nitrogen at an impurity concentration lower than that of n ⁺ -type silicon carbide substrate 1, and constitutes an n-type drift layer. Hereinafter, an n ⁺ type silicon carbide substrate 1 alone or a silicon carbide epitaxial substrate formed by laminating n type silicon carbide epitaxial layer 2 on n ⁺ type silicon carbide substrate 1 is referred to as a silicon carbide semiconductor substrate. Here, an example will be described in which a silicon carbide epitaxial substrate formed by laminating n type silicon carbide epitaxial layer 2 on n ⁺ type silicon carbide substrate 1 is used as a silicon carbide semiconductor substrate.

  On the silicon carbide semiconductor substrate, an active region 101 and a pressure-resistant structure portion 102 surrounding the periphery of the active region 101 are provided. The active region 101 is a region through which current flows when in the on state. The breakdown voltage structure portion 102 is a region that relaxes the electric field on the front surface side of the silicon carbide semiconductor substrate and maintains the breakdown voltage. In active region 101, a planar gate type MOS gate (insulating gate made of metal-oxide film-semiconductor) structure is provided on the front surface side (n-type silicon carbide epitaxial layer 2 side) of the silicon carbide semiconductor substrate. ing.

The MOS gate structure includes a p-type base region (first semiconductor region) 3, an n ⁺ -type source region (second semiconductor region) 6, a p ⁺ -type contact region 7, a gate insulating film 8 and a gate electrode 9. Specifically, the p-type base region 3 is formed on the surface layer of the n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate). Is selectively provided. The p-type base region 3 has a different impurity concentration, and the first p-type base region (first semiconductor portion) 3a, the second p-type base region (second semiconductor portion) 3b, and the third p ⁺ -type base region (first 3 semiconductor parts) 3c. The first p-type base region 3a, the second p-type base region 3b, and the third p ⁺ -type base region 3c are diffusion regions doped with, for example, aluminum (Al) by ion implantation.

The first p-type base region 3a is disposed so as to be exposed on the front surface of the base. The second p-type base region 3b is disposed so as to face the first p-type base region 3a in the depth direction, and is in contact with the base back side of the first p-type base region 3a. The impurity concentration of the first p-type base region 3a is lower than the impurity concentration of the second p-type base region 3b. Thereby, even when the total impurity concentration of the p-type base region is low, it is possible to suppress the entire p-type base region from being depleted. Further, the MOS gate can be operated even when the total impurity concentration of the p-type base region is high. For this reason, the allowable range of the total impurity concentration of the p-type base region can be widened. The third p ⁺ type base region 3c is selectively provided inside the second p type base region 3b so as to be sandwiched between the first p type base region 3a and the second p type base region 3b. That is, the third p ⁺ -type base region 3c is in contact with the first p-type base region 3a on the substrate front surface side, and the periphery of the substrate rear surface side is surrounded by the second p-type base region 3b.

The impurity concentration of the third p ⁺ type base region 3c is higher than the impurity concentration of the second p type base region 3b. Specifically, the ratio of the impurity concentration of the second p-type base region 3b to the impurity concentration of the third p ⁺ -type base region 3c is preferably about 0.1 or less (impurity concentration of the second p-type base region 3b / Impurity concentration of third p ⁺ -type base region 3c ≦ 0.1). The reason is that the leakage current can be reduced to such an extent that no adverse effects due to the leakage current such as failure or malfunction occur. The width w4 of the portion of the third p ⁺ type base region 3c sandwiched between the n type silicon carbide epitaxial layer 2 and the second p type base region 3b is preferably about 0.1 μm or more, for example. The reason is that by depleting the second p-type base region 3b, the electric field load on the third p ⁺ -type base region 3c, which is likely to cause a high leakage current due to crystal defects caused by high-concentration impurity ion implantation, can be alleviated. .

Inside the first p-type base region 3a, an n ⁺ -type source region 6 and a p ⁺ -type contact region 7 are selectively provided on the front surface of the substrate. The n ⁺ type source region 6 and the p ⁺ type contact region 7 may reach the third p ⁺ base region 3c. The n ⁺ -type source region 6 is disposed closer to the end of the first p-type base region 3a (the end in the horizontal direction (lateral direction) to the main surface of the substrate). The p ⁺ -type contact region 7 is arranged near the center of the first p-type base region 3 a than the n ⁺ -type source region 6. The n ⁺ type source region 6 and the p ⁺ type contact region 7 are in contact with each other. On the surface of the portion of first p-type base region 3 a sandwiched between n ⁺ -type source region 6 and n-type silicon carbide epitaxial layer 2, gate electrode 9 is provided via gate insulating film 8.

  Gate electrode 9 may be provided over the surface of the portion sandwiched between adjacent first p-type base regions 3a of n-type silicon carbide epitaxial layer 2 with gate insulating film 8 interposed therebetween. FIG. 1 shows one MOS gate structure constituting two unit cells 103 (element functional units) in the active region 101. A plurality of unit cells (not shown) are arranged in parallel so as to be adjacent to the unit cells. May be arranged (the same applies to FIG. 9). On gate electrode 9, interlayer insulating film 10 is provided on the entire front surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 9.

In the contact hole that penetrates the interlayer insulating film 10 in the depth direction, the n ⁺ type source region 6 and the p ⁺ type contact region 7 are exposed. The source electrode (first electrode) 11 is provided in the contact hole and contacts the n ⁺ type source region 6 and the p ⁺ type contact region 7 exposed in the contact hole. The source electrode 11 is electrically insulated from the gate electrode 9 by the interlayer insulating film 10. A front electrode pad 12 is provided on the source electrode 11 and the interlayer insulating film 10. The front surface electrode pad 12 is provided on almost the entire active region 101. An end portion of the front electrode pad 12 extends on the interlayer insulating film 10 of the breakdown voltage structure portion 102.

In breakdown voltage structure 102, first p ⁻ type region 5 a and second p ⁻ type region 5 b are provided on the surface layer of n type silicon carbide epitaxial layer 2 opposite to n ⁺ type silicon carbide substrate 1 side. It has been. The first p ⁻ -type region 5 a is in contact with the p-type base region 3 constituting the unit cell closest to the breakdown voltage structure 102 and surrounds the periphery of the active region 101. The first p ⁻ -type region 5a may be in contact with all of the first p-type base region 3a, the second p-type base region 3b, and the third p ⁺ -type base region 3c constituting the p-type base region 3, or these first p It may be in contact with any one or two of the type base region 3a, the second p type base region 3b, and the third p ⁺ type base region 3c.

The 2p ^- type region 5b is a 1p ^- contact with the outer end of the mold region 5a (chip outer peripheral side), the 1p ^- surround type region 5a. That is, the p-type base region 3, the first p ⁻ -type region 5 a, and the second p ⁻ -type region 5 b are arranged in parallel and in contact with each other in the direction from the active region 101 side to the breakdown voltage structure portion 102 side. . The impurity concentration of the first p ^- type region 5a is lower than the impurity concentration of the second p-type base region 3b. The 2p ^- impurity concentration type region 5b is a 1p ^- lower than the impurity concentration type region 5a. The first p ⁻ type region 5a and the second p ⁻ type region 5b constitute a double zone JTE (Junction Termination Extension) structure. The double zone JTE structure is a JTE structure having a configuration in which two p-type regions having different impurity concentrations are arranged in parallel so as to contact each other.

An interlayer insulating film 10 is provided on the first p ⁻ type region 5a and the second p ⁻ type region 5b. The first p ⁻ type region 5 a and the second p ⁻ type region 5 b are electrically insulated from the element structure of the active region 101 by the interlayer insulating film 10. A protective film 13 such as a passivation film made of polyimide, for example, is provided on the interlayer insulating film 10 so as to cover almost the entire breakdown voltage structure 102. The protective film 13 has a function of preventing discharge. The end portion of the protective film 13 extends on the front electrode pad 12 and covers the end portion of the front electrode pad 12. A back electrode (first electrode) 14 is provided on the surface of n ⁺ type silicon carbide substrate 1 opposite to the n type silicon carbide epitaxial layer 2 side (the back surface of the silicon carbide semiconductor substrate). The back electrode 14 constitutes a drain electrode. A back electrode pad 15 is provided on the surface of the back electrode 14.

Next, the method for manufacturing the semiconductor device according to the first embodiment will be described by taking as an example the case of fabricating a silicon carbide MOSFET having a withstand voltage class of 1200 V, for example. 2 to 5 are cross-sectional views schematically showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. First, an n ⁺ type silicon carbide substrate (semiconductor wafer) 1 doped with nitrogen at an impurity concentration of about 2 × 10 ¹⁸ / cm ³ is prepared. The main surface of n ⁺ type silicon carbide substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction. Next, on the (000-1) plane of the n ⁺ type silicon carbide substrate 1, for example, an n type silicon carbide epitaxial layer having a thickness of 10 μm is doped with nitrogen at an impurity concentration of about 1.0 × 10 ¹⁶ / cm ^3. Grow two. The state up to this point is shown in FIG.

Next, an oxide film (not shown) is deposited (formed) on n-type silicon carbide epitaxial layer 2. Next, a portion of the oxide film corresponding to the formation region of the p-type base region 3 is removed by photolithography and etching. Next, ion implantation is performed twice with different acceleration voltages using the remainder of the oxide film as a mask, and the first and second p-type base regions 3a and 3b are selectively formed on the surface layer of the n-type silicon carbide epitaxial layer 2, respectively. Form. In this ion implantation, for example, the dopant is aluminum, and the impurity concentrations of the first and second p-type base regions 3a and 3b are 1.0 × 10 ¹⁶ / cm ³ and 2.0 × 10 ¹⁶ / cm ³ , respectively. The dose may be set to Further, the acceleration voltage of each ion implantation is appropriately set so that the depth of the second p-type base region 3b from the front surface of the base is deeper than the depth of the first p-type base region 3a from the front surface of the base. . The width p1 and the thickness t1 of the first p-type base region 3a may be 13 μm and 0.2 μm, respectively. The width p2 and thickness t2 of the second p-type base region 3b may be 13 μm and 0.3 μm, respectively. The distance w5 between the adjacent p-type base regions 3 may be 2 μm, for example.

Next, an oxide film (not shown) is further deposited on the oxide film used to form the first and second p-type base regions 3a and 3b. The thickness of the additionally deposited oxide film may be, for example, 0.1 μm. Next, a portion of the oxide film corresponding to the formation region of the third p ⁺ type base region 3c is removed by photolithography and etching. Next, ion implantation is performed using the remaining portion of the oxide film as a mask to form a third p ⁺ -type base region 3 c inside the second p-type base region 3 b. In this ion implantation, for example, the dopant may be aluminum, and the dose may be set so that the impurity concentration of the third p ⁺ -type base region 3c is 1.0 × 10 ¹⁹ / cm ³ . Further, the ion implantation acceleration voltage is appropriately set so that the depth of the third p ⁺ -type base region 3c from the front surface of the base becomes deeper than the depth of the first p-type base region 3a from the front surface of the base. . The width p3 and the thickness t3 of the third p ⁺ type base region 3c may be 12.8 μm and 0.2 μm, respectively. The width w4 of the portion of the third p ⁺ type base region 3c sandwiched between the n type silicon carbide epitaxial layer 2 and the second p type base region 3b may be, for example, 0.1 μm. Then, all the rest of the oxide film used for forming the p-type base region 3 is removed. The state up to here is shown in FIG.

Next, a resist mask (not shown) having an opening corresponding to the formation region of the first p ⁻ type region 5a is formed on the front surface of the substrate by photolithography. Next, ion implantation is performed using this resist mask as a mask to selectively form first p ⁻ -type region 5 a in the surface layer of n-type silicon carbide epitaxial layer 2. In this ion implantation, for example, the dopant may be aluminum and the dose may be 2.0 × 10 ¹³ cm / ² . Then, the resist mask used for forming the first p ⁻ type region 5a is removed. Next, a resist mask (not shown) having an opening corresponding to the formation region of the second p ⁻ type region 5b is formed on the front surface of the substrate by photolithography. Using this resist mask as a mask, ion implantation is performed to selectively form second p ⁻⁻ type region 5 b in the surface layer of n-type silicon carbide epitaxial layer 2. In this ion implantation, for example, the dopant may be aluminum and the dose may be 1.0 × 10 ¹³ cm / ² . Then, the 2p ^- the resist mask is removed using a forming mold region 5b. Although a resist is used here as an ion implantation mask, other substances such as an oxide film may be used. Further, the temperature of the substrate at the time of ion implantation may not be room temperature.

Next, a resist mask (not shown) having an opening corresponding to the formation region of the n ⁺ type source region 6 is formed on the front surface of the substrate by photolithography. Next, ion implantation is performed using this resist mask as a mask, and an n ⁺ -type source region 6 is selectively formed in the surface layer of the first p-type base region 3a. Then, the resist mask used for forming the n ⁺ type source region 6 is removed. Next, a resist mask (not shown) having an opening corresponding to the formation region of the p ⁺ -type contact region 7 is formed on the front surface of the substrate by photolithography. Next, ion implantation is performed using this resist mask as a mask to selectively form a p ⁺ -type contact region 7 on the surface layer of the first p-type base region 3a. Then, the resist mask used for forming the p ⁺ type contact region 7 is removed. Thereby, the n ⁺ type source region 6 and the p ⁺ type contact region 7 are selectively formed inside the first p type base region 3a. Although a resist is used here as an ion implantation mask, other substances such as an oxide film may be used. Further, the temperature of the substrate at the time of ion implantation may not be room temperature.

The order of forming the first p-type base region 3a, the second p-type base region 3b, the third p ⁺ -type base region 3c, the first p ⁻ -type region 5a and the second p ⁻ -type region 5b can be variously changed. The n ⁺ type source region 6 and the p ⁺ type contact region 7 may be formed after the formation of the p type base region 3, and the order of forming the n ⁺ type source region 6 and the p ⁺ type contact region 7 is variously changed. Is possible. Next, by heat treatment (annealing), the first p-type base region 3a, the second p-type base region 3b, the third p ⁺ -type base region 3c, the n ⁺ -type source region 6, the p ⁺ -type contact region 7, and the first p ⁻ -type region 5a and the second p ^- type region 5b are activated. The heat treatment temperature and heat treatment time at this time may be, for example, 1750 ° C. and 2 minutes, respectively. The heat treatment for activation may be performed every time each region is formed in n-type silicon carbide epitaxial layer 2. The state up to this point is shown in FIG.

Next, the front surface of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 8 having a thickness of, for example, 100 nm. This thermal oxidation may be performed, for example, by a heat treatment at a temperature of about 1000 ° C. in an oxygen (O ₂ ) atmosphere. Thereby, each region formed in the surface layer of n-type silicon carbide epitaxial layer 2 is covered with gate insulating film 8. Next, as the gate electrode 9, for example, a polycrystalline silicon (poly-Si) layer doped with phosphorus (P) is formed on the gate insulating film 8. Next, this polycrystalline silicon layer is selectively removed by patterning, on the surface of the portion of the first p-type base region 3a sandwiched between the n ⁺ -type source region 6 and the n-type silicon carbide epitaxial layer 2 Leave the polycrystalline silicon layer. At this time, the polycrystalline silicon layer may be left over the surface of the portion of n-type silicon carbide epitaxial layer 2 sandwiched between adjacent first p-type base regions 3a.

Next, an interlayer insulating film 10 having a thickness of, for example, about 1 μm is formed (formed) over the entire surface of the base so as to cover the gate electrode 9. The interlayer insulating film 10 may be a silicon oxide (SiO ₂ ) film made of phosphorous glass such as PSG (Phospho Silicate Glass) or BPSG (Boro Phospho Silicate Glass), or a non-doped silicon oxide film (NSG: Nondoped). (Silicate Glass). The state up to here is shown in FIG. Next, the interlayer insulating film 10 and the gate insulating film 8 are patterned and selectively removed to form contact holes, thereby exposing the n ⁺ -type source region 6 and the p ⁺ -type contact region 7. Next, heat treatment (reflow) for planarizing the interlayer insulating film 10 is performed.

Next, the source electrode 11 is formed on the surface of the interlayer insulating film 10 so as to be embedded in the contact hole. Thus, source electrode 11 is connected to n ⁺ type source region 6 and p ⁺ type contact region 7 exposed in the contact hole. Next, portions of the source electrode 11 other than the contact holes on the breakdown voltage structure 102 and the active region 101 are selectively removed. At this time, a part of the source electrode 11 may partially remain on the side surface of the contact hole or the surface of the interlayer insulating film 10.

Next, a nickel (Ni) film, for example, is formed as the back electrode 14 on the surface of the n ⁺ type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate). Next, ohmic contact (electrical contact portion) between n ⁺ type silicon carbide substrate 1 and back electrode 14 is formed by heat treatment at a temperature of about 970 ° C., for example. Next, front electrode pad 12 is deposited on the entire front surface of the silicon carbide semiconductor substrate, for example, by sputtering. As the front electrode pad 12, for example, an aluminum (Al—Si) layer containing silicon at a rate of 1% may be formed. Next, the front electrode pad 12 is patterned and selectively removed, leaving the front electrode pad 12 on the source electrode 11 and the interlayer insulating film 10 in the active region 101. The thickness of the surface electrode pad 12 on the interlayer insulating film 10 may be, for example, about 5 μm.

  Next, protective film 13 is formed on the entire front surface of the silicon carbide semiconductor substrate. Next, the protective film 13 is patterned to expose the surface electrode pad 12, and the protective film 13 is covered on the interlayer insulating film 10 of the breakdown voltage structure 102 so as to cover the end of the front electrode pad 12. Leave. Next, a back electrode pad 15 is formed on the surface of the back electrode 14 by laminating, for example, a titanium (Ti) film, a nickel (Ni) film, and a gold (Au) film in this order. Thereafter, the silicon wafer MOSFET shown in FIG. 1 is completed by dicing (cutting) the semiconductor wafer into chips.

(Example 1)
Next, the leakage current characteristics of the semiconductor device according to the first embodiment were verified. FIG. 6 is a cross sectional view showing a configuration of the silicon carbide semiconductor device of Comparative Example 1. FIG. 7 is a frequency distribution diagram (histogram) showing leakage current characteristics of the silicon carbide semiconductor device according to the first example. FIG. 8 is a characteristic diagram showing the relationship between the impurity concentration ratio of the p-type base region and the leakage current of the silicon carbide semiconductor device according to the first example. The vertical axis of FIG. 7 shows the number of samples, and the horizontal axis shows the leakage current value classification of each sample. In FIG. 7, the leak current values within the range of 1.0 × 10 ⁻¹³ [A] to 1.0 × 10 ⁻² [A] are divided into data groups of 1.0 × 10 [A]. This is shown (the same applies to FIG. 11). The horizontal axis of FIG. 8 shows the impurity concentration ratio of the p-type base region 3, and the vertical axis shows the value of the leak current value section (hereinafter referred to as the leak current) having a high frequency (number of samples) in the first embodiment shown in FIG. Value mode). The impurity concentration ratio of the p-type base region 3 is the ratio of the impurity concentration of the second p-type base region 3b to the impurity concentration of the third p ⁺ -type base region 3c (= impurity concentration of the second p-type base region 3b / third p ⁺ -type). Impurity concentration of the base region 3c).

First, according to the semiconductor device manufacturing method according to the first embodiment described above, a p-type base including the first p-type base region 3a, the second p-type base region 3b, and the third p ⁺ -type base region 3c under the above-described various conditions. A MOSFET (see FIG. 1) provided with the region 3 was fabricated (hereinafter referred to as Example 1). As a comparison, as shown in FIG. 6, a MOSFET including a p-type base region 23 formed with a uniform impurity concentration in the depth direction was manufactured (hereinafter referred to as Comparative Example 1). The impurity concentration of the p-type base region 23 of Comparative Example 1 is equal to the impurity concentration of the second p-type base region 3b of Example 1. The configuration other than the p-type base region 23 of Comparative Example 1 is the same as that of Example 1. A plurality of these Examples 1 and Comparative Examples 1 were produced, and the leakage current of each sample was measured. Specifically, the leakage current when the source electrode 11 and the gate electrode 9 are set to the ground potential (0 V) and a voltage of 1200 V is applied to the back electrode pad 15 is measured. The results are shown in FIGS.

From the results shown in FIG. 7, it was confirmed that in Comparative Example 1, the number of samples that generated a leak current of the order of 1.0 × 10 ⁻⁶ [A] was the largest. On the other hand, in Example 1, the number of samples that generated a leakage current of the order of 1.0 × 10 ⁻⁹ [A] was the largest, and it was confirmed that the leakage current characteristics were improved as compared with Comparative Example 1. . Further, from the results shown in FIG. 8, in Example 1, when the impurity concentration ratio of the second p-type base region 3b with respect to the impurity concentration of the third p ⁺ -type base region 3c is 0.1 or less, failure, malfunction, etc. It has been confirmed that the effect of reducing the leakage current appears to the order of 1.0 × 10 ⁻⁸ [A] or less, which does not cause the occurrence of.

As described above, according to the first embodiment, the third p ⁺ type base region having an impurity concentration higher than that of the second p type base region is provided inside the second p type base region. It is possible to suppress depletion to the surface. Thereby, it can suppress that a proof pressure falls, and can achieve a high proof pressure. Further, according to the first embodiment, the periphery of the substrate rear surface side of the high impurity concentration the 3p ⁺ -type base region, by enclosing a low impurity concentration than the 3p ⁺ -type base region first 2p-type base region, The electric field load on the third p ⁺ type base region, which is likely to cause a high leakage current due to crystal defects caused by high concentration impurity ion implantation, can be reduced. Thereby, even if the impurity concentration of the p-type base region is partially increased, it is possible to prevent an increase in leakage current due to an adverse effect of crystal defects. Therefore, a high breakdown voltage and a low leakage current can be realized without increasing the thickness of the p-type base region as in the prior art. For this reason, it is possible to manufacture (manufacture) a semiconductor device having a high yield and a high withstand voltage regardless of the performance of the manufacturing apparatus. Further, according to the first embodiment, since it is not necessary to increase the thickness of the p-type base region in order to suppress the leakage current as in the prior art, the thickness of the n ⁻ -type drift layer is increased, which increases the cost. Does not occur.

(Embodiment 2)
Next, the configuration of the semiconductor device according to the second embodiment will be described using a silicon carbide MOSFET as an example. FIG. 9 is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that a first p-type base comprising a p-type silicon carbide epitaxial layer deposited on an n-type silicon carbide epitaxial layer 2 It is a point provided with the area | region 33a. That is, in the second embodiment, the p-type base region 3 includes the first p-type base region 33a made of an epitaxial layer, and the second p-type base region 33b and the third p ⁺ type base region 33c which are diffusion regions by ion implantation. Is configured.

More specifically, as shown in FIG. 9, the surface layer of n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side (front surface side of the silicon carbide semiconductor substrate). Only the second p-type base region 33b and the third p ⁺ -type base region 33c are provided. The second p-type base region 33b and the third p ⁺ -type base region 33c are exposed on the front surface of the base. A p-type silicon carbide epitaxial layer (second semiconductor layer) is deposited on n-type silicon carbide epitaxial layer 2 so as to cover second p-type base region 33b and third p ⁺ -type base region 33c over active region 101. ing. The p-type silicon carbide epitaxial layer is doped with, for example, aluminum. A portion of the p-type silicon carbide epitaxial layer on the second p-type base region 33b and the third p ⁺ -type base region 33c is the first p-type base region 33a.

The end of the first p-type base region 33a arranged closest to the withstand voltage structure 102 is terminated on the second p-type base region 33b in contact with the first p-type base region 33a. It does not extend on the first p ⁻ type region 5 a of the portion 102. The configuration of p type base region 3 is the same as that of the p type base region of the first embodiment except that first p type base region 33a is a p type silicon carbide epitaxial layer. An n-type region (third semiconductor region) 4 is provided in a portion sandwiched between adjacent first p-type base regions 33a of the p-type silicon carbide epitaxial layer. N type region 4 penetrates through the p type silicon carbide epitaxial layer in the depth direction and reaches n type silicon carbide epitaxial layer 2. The n-type region 4 may extend up to the third p ⁺ -type base region 33c. N type region 4 constitutes a drift region together with n type silicon carbide epitaxial layer 2.

An n ⁺ type source region 6 and a p ⁺ type contact region 7 are selectively provided inside the portion of the first p type base region 33a on the second p type base region 33b. The n ⁺ type source region 6 and the p ⁺ type contact region 7 are in contact with each other. The n ⁺ type source region 6 is arranged closer to the n type region 4 than the p ⁺ type contact region 7. The p ⁺ -type contact region 7 may be provided, for example, at a depth that penetrates the first p-type base region 33a in the depth direction and reaches the second p-type base region 33b. A gate electrode 9 is provided on the surface of the portion of the first p-type base region 33 a sandwiched between the n ⁺ -type source region 6 and the n-type region 4 with a gate insulating film 8 interposed therebetween. The gate electrode 9 may be provided over the surface of the n-type region 4 via the gate insulating film 8.

As with the first embodiment, the breakdown voltage structure 102 is provided with a first p ⁻ type region 5a and a second p ⁻ type region 5b that form a double zone JTE structure. In the second embodiment, the first p ⁻ type region 5a is in contact with the second p type base region 33b and the third p ⁺ type base region 33c constituting the p type base region 3 arranged closest to the breakdown voltage structure 102 side, It does not contact the first p-type base region 33a. That is, the second p-type base region 33b (including the third p ⁺ -type base region 33c), the first p ⁻ -type region 5a, and the second p ⁻ -type region 5b extend in the direction from the active region 101 side to the breakdown voltage structure portion 102 side. They are arranged in parallel and in contact with each other. The configurations of the interlayer insulating film 10, the source electrode 11, the front electrode pad 12, the protective film 13, the back electrode 14, and the back electrode pad 15 are the same as those in the first embodiment.

The semiconductor device according to the second embodiment may be formed by forming a p-type silicon carbide epitaxial layer serving as the first p-type base region 33a on the n-type silicon carbide epitaxial layer 2 in the semiconductor device according to the first embodiment. Specifically, first, similarly to the first embodiment, from the step of growing n-type silicon carbide epitaxial layer 2 on n ⁺ -type silicon carbide substrate 1, second p-type base region 33b and third p ⁺ -type base region are grown. The process up to the step of forming 33c is sequentially performed. At this time, the step of forming the first p-type base region in the first embodiment is not performed. Further, the ion implantation acceleration voltage is appropriately set so that the second p-type base region 33 b and the third p ⁺ -type base region 33 c are exposed on the surface of the n-type silicon carbide epitaxial layer 2.

Next, as in the first embodiment, a process of forming the first p ⁻ type region 5a and the second p ⁻ type region 5b is performed. Next, a p-type silicon carbide epitaxial layer to be first p-type base region 33a is grown on n-type silicon carbide epitaxial layer 2 so as to cover second p-type base region 33b and third p ⁺ -type base region 33c. Next, the n ⁺ type source region 6 and the p ⁺ type contact region 7 are selectively formed in the portion of the p type silicon carbide epitaxial layer that becomes the first p type base region 33a. The method for forming n ⁺ type source region 6 and p ⁺ type contact region 7 is the same as in the first embodiment. Next, a resist mask (not shown) having an opening corresponding to the formation region of n-type region 4 is formed on the p-type silicon carbide epitaxial layer by photolithography.

Next, ion implantation is performed using this resist mask as a mask to selectively form an n-type region 4 that reaches the n-type silicon carbide epitaxial layer 2 through the p-type silicon carbide epitaxial layer. Thereby, a portion other than n-type region 4 of the p-type silicon carbide epitaxial layer becomes first p-type base region 33a. Then, the resist mask used for forming the n-type region 4 is removed. Next, a resist mask (not shown) that covers active region 101 is formed on the p-type silicon carbide epitaxial layer. Next, etching is performed using this resist mask as a mask, and the p-type silicon carbide epitaxial layer in the breakdown voltage structure 102 is removed. As a result, the first p ⁻ type region 5a and the second p ⁻ type region 5b are exposed. Then, the resist mask for etching is removed. Although a resist is used here as an ion implantation mask, other substances such as an oxide film may be used. Further, the temperature of the substrate at the time of ion implantation may not be room temperature.

Next, as in the first embodiment, the first p-type base region 33a, the second p-type base region 33b, the third p ⁺ -type base region 33c, the n-type region 4, the n ⁺ -type source region 6, p ⁺ are formed by heat treatment. The type contact region 7, the first p ⁻ type region 5a and the second p ⁻ type region 5b are activated. The heat treatment for activation may be performed every time each region is formed. Further, the order of forming the n ⁺ type source region 6, the p ⁺ type contact region 7 and the n type region 4 can be variously changed. Further, a step of removing the p-type silicon carbide epitaxial layer in the breakdown voltage structure portion 102 may be performed before these regions are formed or after the heat treatment for activation. After that, the silicon carbide MOSFET shown in FIG. 9 is completed by sequentially performing the steps after forming the gate insulating film 8 in the same manner as in the first embodiment.

(Example 2)
Next, the leakage current characteristics of the semiconductor device according to the second embodiment were verified. FIG. 10 is a cross sectional view showing a configuration of the silicon carbide semiconductor device of Comparative Example 2. FIG. 11 is a frequency distribution diagram showing leakage current characteristics of the silicon carbide semiconductor device according to Example 2. FIG. 12 is a characteristic diagram showing the relationship between the impurity concentration ratio of the p-type base region and the leakage current of the silicon carbide semiconductor device according to the second example. The vertical axis of FIG. 11 shows the number of samples, and the horizontal axis shows the leakage current value classification of each sample. The horizontal axis of FIG. 12 shows the impurity concentration ratio of the p-type base region 3, and the vertical axis shows the mode value of the leakage current value section of FIG. The impurity concentration ratio of the p-type base region 3 is the ratio of the impurity concentration of the second p-type base region 33b to the impurity concentration of the third p ⁺ -type base region 33c (= impurity concentration of the second p-type base region 33b / third p ⁺ -type). Impurity concentration of the base region 33c).

First, according to the method of manufacturing a semiconductor device according to the second embodiment described above, a p-type base including the first p-type base region 33a, the second p-type base region 33b, and the third p ⁺ -type base region 33c under the above-described various conditions. A MOSFET having a region 3 (see FIG. 9) was fabricated (hereinafter referred to as Example 2). As a comparison, as shown in FIG. 10, a MOSFET having only a second p-type base region 43b on the surface layer of the n-type silicon carbide epitaxial layer 2 opposite to the n ⁺ -type silicon carbide substrate 1 side was produced. (Hereinafter referred to as Comparative Example 2). That is, the comparative example 2 includes a p-type base region 43 including a first p-type base region 43a made of an epitaxial layer and a second p-type base region 43b that is a diffusion region by ion implantation. The impurity concentration of the second p-type base region 43b of Comparative Example 2 is equal to the impurity concentration of the second p-type base region 33b of Example 2. The configuration other than the p-type base region 43 of Comparative Example 2 is the same as that of Example 2. A plurality of these Examples 2 and Comparative Examples 2 were produced, and the leakage current of each sample was measured. The measurement conditions for the leakage current are the same as in Example 1. The results are shown in FIGS.

From the results shown in FIG. 11, it was confirmed that in Comparative Example 2, the number of samples that generated a leak current of the order of 1.0 × 10 ⁻⁷ [A] was the largest. On the other hand, in Example 2, the number of samples that generated a leakage current of the order of 1.0 × 10 ⁻¹⁰ [A] was the largest, and it was confirmed that the leakage current characteristics were improved as compared with Comparative Example 2. . From the results shown in FIG. 12, in Example 2, when the impurity concentration ratio of the second p-type base region 33b to the impurity concentration of the third p ⁺ -type base region 33c is 0.1 or less (second p-type base) It has been confirmed that the impurity concentration of the region 33b / the impurity concentration of the third p ⁺ -type base region 33c ≦ 0.1) and the effect of further reducing the leakage current appear.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

In the present invention, the case where the main surface (front surface) of the n ⁺ type silicon carbide substrate is a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction is described as an example. However, the present invention is not limited to this, and the plane orientation of the main surface of the n ⁺ -type silicon carbide substrate can be variously changed according to the design conditions and the like. For example, the main surface of the n ⁺ -type silicon carbide substrate may be a (0001) plane or a (0001) plane having an off angle of about 10 degrees or less in the <11-20> direction. In each of the above-described embodiments, the case where a silicon carbide semiconductor is used as the wide band gap semiconductor is described as an example. However, the present invention is not limited to this, and other wide band gap semiconductors such as gallium nitride (GaN) and diamond are used. The same effect can be obtained in. In each of the above-described embodiments, the MOSFET is described as an example. However, the present invention is an IGBT (Insulated Gate Bipolar Transistor) having a MOS gate structure on the front surface side of the substrate. It is applicable to MOS type semiconductor devices such as.

  In the present invention, a case where a double-zone JTE structure is provided as the breakdown voltage structure is described as an example. However, a multi-zone JTE structure or a FLR (Field Limiting Ring) structure may be applied to the breakdown voltage structure portion. The multi-zone JTE structure is a structure in which three or more p-type regions having different impurity concentrations are arranged in parallel and in contact with each other in the direction from the active region side to the breakdown voltage structure portion side. The FLR structure is a structure in which a plurality of p-type regions are arranged in parallel at a predetermined interval in the direction from the active region side to the pressure-resistant structure side, and can be applied regardless of the difficulty of manufacturing. In the first embodiment described above, a case where a silicon carbide epitaxial substrate in which a silicon carbide epitaxial layer is deposited on a silicon carbide substrate is described as an example. However, the present invention is not limited to this, and a MOS gate structure, for example, is configured. It is good also as a diffusion area | region which formed all the area | regions to perform inside the silicon carbide bulk substrate. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device according to the present invention is useful for a high voltage semiconductor device used for a power conversion device, a power supply device such as various industrial machines and the like.

1 n ⁺ -type silicon carbide substrate 2 n-type silicon carbide epitaxial layer 3, 23, 43 p-type base region 3a, 33a, 43a first p-type base region 3b, 33b, 43b second p-type base region 3c, 33c third p ⁺ -type Base region 4 n-type region 5a first p ^- type region 5b second p ^- type region 6 n ⁺ -type source region 7 p ⁺ -type contact region 8 gate insulating film 9 gate electrode 10 interlayer insulating film 11 source electrode 12 front surface Electrode pad 13 Protective film 14 Back electrode 15 Back electrode pad 101 Active region 102 Withstand voltage structure 103 Unit cell

Claims (8)

A first conductivity type semiconductor substrate made of a silicon carbide semiconductor;
A first semiconductor layer of a first conductivity type formed of a silicon carbide semiconductor having a lower impurity concentration than the semiconductor substrate, provided on the front surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type selectively provided on a surface layer of the first semiconductor layer opposite to the semiconductor substrate side;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A gate electrode provided on a surface of a portion of the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor region via a gate insulating film;
A first electrode electrically connected to the first semiconductor region and the second semiconductor region;
A second electrode provided on the back surface of the semiconductor substrate;
With
The first semiconductor region is
A first semiconductor portion facing the gate electrode in the depth direction through the gate insulating film;
A second semiconductor part which is provided on the second electrode side of the first semiconductor part and is adjacent to the first semiconductor part in the depth direction;
A semiconductor device comprising: a third semiconductor portion selectively provided inside the second semiconductor portion and having an impurity concentration higher than that of the second semiconductor portion. A first conductivity type semiconductor substrate made of a silicon carbide semiconductor;
A first semiconductor layer of a first conductivity type formed of a silicon carbide semiconductor having a lower impurity concentration than the semiconductor substrate, provided on the front surface of the semiconductor substrate;
A second semiconductor layer of a second conductivity type made of a silicon carbide semiconductor, provided on the surface of the first semiconductor layer opposite to the semiconductor substrate side;
A second conductivity type first semiconductor region selectively provided at a depth extending from the surface opposite to the first semiconductor layer side of the second semiconductor layer to the surface layer of the first semiconductor layer;
A second semiconductor region of a first conductivity type selectively provided inside the first semiconductor region;
A third semiconductor region of a first conductivity type provided at a depth reaching the first semiconductor layer in a portion sandwiched between the adjacent first semiconductor regions of the second semiconductor layer;
A gate electrode provided on a surface of a portion of the first semiconductor region sandwiched between the first semiconductor layer and the second semiconductor region via a gate insulating film;
A first electrode electrically connected to the first semiconductor region and the second semiconductor region;
A second electrode provided on the back surface of the semiconductor substrate;
With
The first semiconductor region is
A first semiconductor portion that is formed of a part of the second semiconductor layer and faces the gate electrode in the depth direction with the gate insulating film interposed therebetween;
A second semiconductor portion provided in a surface layer of the first semiconductor layer on the second semiconductor layer side and adjacent to the first semiconductor portion in a depth direction;
A semiconductor device comprising: a third semiconductor portion selectively provided inside the second semiconductor portion and having an impurity concentration higher than that of the second semiconductor portion.   The said 3rd semiconductor part is in contact with the said 1st semiconductor part on the said 1st electrode side, The circumference | surroundings on the said 2nd electrode side are surrounded by the said 2nd semiconductor part, The Claim 1 or 2 characterized by the above-mentioned. The semiconductor device described.   4. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor portion is 0.1 times or less of an impurity concentration of the third semiconductor portion.   5. The width of a portion of the third semiconductor part sandwiched between the first semiconductor layer and the second semiconductor part is 0.1 μm or more. 6. Semiconductor device.   6. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor portion is higher than an impurity concentration of the first semiconductor portion.   The front surface of the semiconductor substrate is a plane parallel to the (000-1) plane or a plane inclined at 10 degrees or less with respect to the (000-1) plane. The semiconductor device according to any one of the above.   The front surface of the semiconductor substrate is a plane parallel to the (0001) plane or a plane inclined at 10 degrees or less with respect to the (0001) plane. A semiconductor device according to 1.

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