JP2016058630A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can remove deposited Cu while leaving a resist.SOLUTION: A semiconductor device manufacturing method comprises the steps of: depositing a first metal film 101a composing a lower pad layer 101, a second metal film 102a composing a hard layer 102 and a third metal film 103a composing an upper pad layer 103; performing a heat treatment to make the first through third metal films 101a-103a flow; and performing patterning on the first through third metal films 101a-103a. The process of performing patterning comprises: a process of performing anisotropic etching to remove the second and third metal films 102a, 103a and remove Cu 104 deposited in an interface between the first metal film 101a and the second metal film 102a during the heat treatment process and to leave portions of a resist 105 and the first metal film 101a on the side of a substrate 10; and a process of performing isotropic etching to remove the first metal film 101a exposed from the resist 105 while leaving the resist 105.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device having a pad layer electrically connected to a semiconductor element.

  2. Description of the Related Art Conventionally, a semiconductor device having a substrate on which a semiconductor element is formed has a pad layer that is electrically connected to the semiconductor element. Specifically, such a semiconductor device has a wiring layer in which wiring portions electrically connected to semiconductor elements and interlayer insulating films are alternately stacked on a substrate. In the wiring layer (interlayer insulating film), a via hole that exposes the wiring portion is formed, and a pad layer that is electrically connected to the wiring portion through the via hole is electrically connected to the semiconductor element. Has been placed.

  In such a semiconductor device, a probe needle is brought into contact with the pad layer to perform a characteristic inspection, or wire bonding is performed on the pad layer to electrically connect the pad layer to an external circuit.

  However, in the semiconductor device described above, stress is applied to the pad layer when the probe needle is brought into contact with the pad layer or when wire bonding is performed on the pad layer. In this case, a crack may occur in the pad layer, and as a result, the pad layer may be destroyed.

  In order to solve this problem, for example, Patent Document 1 proposes a semiconductor device in which the area of the pad layer is increased, and the area where the probe needle is brought into contact with the area where wire bonding is performed is different. According to this, since the region where the probe needle is contacted and the region where wire bonding is performed are different, the stress when contacting the probe needle and the stress when performing wire bonding are applied to the same region. It can suppress and it can suppress that a pad layer is destroyed.

JP 2010-153901 A

  However, even in the semiconductor device of Patent Document 1, if the stress applied at a time is large when the probe needle is brought into contact or when wire bonding is performed, the pad layer may be destroyed by the stress.

  For this reason, the present applicants have proposed a semiconductor device in which a pad layer is formed by sequentially laminating a lower layer pad layer, a hard layer, and an upper layer pad layer in Japanese Patent Application No. 2013-229502. Specifically, the lower layer pad layer and the upper layer pad layer are made of an Al-based alloy containing Cu, and the hard layer is made of a transition metal such as a Ti-based alloy or a W-based alloy that is harder than the lower layer pad layer and the upper layer pad layer. Configured.

  According to this, even when a large stress is applied at a time when the probe needle is brought into contact or when wire bonding is performed, a crack is generated in the upper pad layer, and the crack is propagated to the lower pad layer by the hard layer. Can be suppressed. That is, it can suppress that a pad layer is destroyed as a whole.

  Such a semiconductor device is manufactured as follows. That is, first, a substrate on which a semiconductor element is formed is prepared, and a wiring layer having a wiring portion and an interlayer insulating film is formed on the substrate. Then, after forming a via hole in the wiring layer, the first metal film constituting the lower layer pad layer, the second metal film constituting the hard layer, and the third metal film constituting the upper layer pad layer are embedded in the via hole. Are sequentially formed. Thereafter, a heat treatment step is performed to flow the first to third metal films to improve the embedding property in the via holes. Then, a resist is arranged on the third metal film, the resist is patterned, and etching is performed using the patterned resist as a mask to pattern the first to third metal films, thereby forming a lower layer pad layer, a hard layer, and an upper layer. A step of forming a pad layer having a pad layer is performed. Thereby, the semiconductor device is manufactured.

  However, in such a manufacturing method, since the second metal film constituting the hard layer is composed of a transition metal, the interface between the first and third metal films and the second metal film is performed when the heat treatment process is performed. , Al contained in the first and third metal films reacts with the second metal film to form an alloy layer, and Cu contained in the first and third metal films is precipitated.

  In this case, in the step of forming the pad layer, as shown in FIG. 5, when the metal film J101a is patterned by isotropic etching using the resist J105 as a mask, Cl radicals are etched mainly, so that the sputter component is increased. weak. For this reason, CuJ104 deposited from the metal film J101a remains without being removed.

  In order to solve this problem, in the step of forming the pad layer, it is considered to remove the deposited CuJ104 by strengthening the sputter component by performing anisotropic etching in which Ar ions are mainly etched. It is done. However, since the anisotropic etching has a small selectivity with respect to the resist, the resist is also easily removed, and the third metal film constituting the pad layer may be exposed. For this reason, it can be considered that the resist is formed thick.

  In the semiconductor device as described above, it is also desired to increase the thickness of the pad layer and reduce the wiring resistance of the pad layer. In this case, when anisotropic etching is performed in the step of forming the pad layer, a resist thicker than the thickness of the pad layer may be disposed. However, when the resist is thicker than the pad layer, the resist is patterned. Therefore, there is a possibility that the exposure accuracy by the exposure apparatus cannot be sufficiently performed and the processing accuracy of the photolithography is remarkably lowered.

  In view of the above points, the present invention provides a method for manufacturing a semiconductor device in which a metal film constituting a lower layer pad layer, a hard layer, and an upper layer pad layer is patterned using a resist thinner than the total thickness of these metal films as a mask. In the above, an object of the present invention is to provide a semiconductor device manufacturing method capable of removing the deposited Cu while leaving a resist.

  To achieve the above object, according to the first aspect of the present invention, there is provided a substrate (10) having one surface (10a) on which a semiconductor element (20) is formed, and a wiring part electrically connected to the semiconductor element. (31-33) and an interlayer insulating film (41-43) in order, a wiring layer (50), and a pad disposed in a via hole (80) formed in the wiring layer and electrically connected to the wiring portion A pad layer, a lower layer pad layer (101), a hard layer (102), and an upper layer pad layer (103) are laminated in that order from the substrate side, and the lower layer pad layer and the upper layer pad layer are made of Cu. In the method of manufacturing a semiconductor device in which the hard layer is higher in hardness than the lower layer pad layer and the upper layer pad layer and is composed of a transition metal, the hard layer is characterized by the following points.

  That is, a step of preparing a substrate, a step of forming a wiring layer on one surface of the substrate, a step of forming a via hole exposing the wiring portion on the wiring layer, and a lower layer so as to be embedded in the via hole on the wiring layer A step of sequentially forming a first metal film (101a) constituting a pad layer, a second metal film (102a) constituting a hard layer, and a third metal film (103a) constituting an upper pad layer; A heat treatment step for causing the first to third metal films to flow; a step of disposing a resist (105) thinner than the total thickness of the first to third metal films on the third metal film; A step of patterning the resist so that the resist remains on a portion of the metal film constituting the pad layer, a step of forming the pad layer by patterning the first to third metal films using the resist as a mask, And In the step of forming the metal layer, the second and third metal films are removed, and Cu (104) deposited at the interface between the first metal film and the second metal film during the heat treatment process is removed, And performing anisotropic etching so that a portion of the resist and the first metal film on the substrate side remains, and isotropic etching to remove the first metal film exposed from the resist while leaving the resist. And performing the process.

  According to this, Cu deposited on the interface between the first metal film and the second metal film is removed by anisotropic etching, and the resist remains on the first metal film remaining by anisotropic etching. It is removed by isotropic etching. For this reason, it is possible to remove the precipitated Cu while suppressing the resist from being completely removed.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the semiconductor device in 1st Embodiment of this invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2; FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; It is a schematic diagram which shows the state in which Cu remains at the time of performing isotropic etching.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. In the semiconductor device of this embodiment, as shown in FIG. 1, an SOI (Silicon on Insulator) substrate in which a support substrate 11, an insulating film 12, and a semiconductor layer 13 are sequentially stacked is used as a substrate 10. The semiconductor layer 13 is partitioned into a plurality of formation regions by embedding the insulating film 15 in the trench 14, and a semiconductor element 20 such as a MOS or IGBT having the gate electrode 16 and the LOCOS oxide film 17 is formed in each formation region. Has been.

  A protective film 18 that covers the gate electrode 16 and the LOCOS oxide film 17, etc., and first to third wiring portions 31 to 33 and first to third interlayer insulating films 41 to 43 are formed on the one surface 10 a of the substrate 10. The multilayer wiring layers 50 that are alternately stacked are formed. The first to third wiring portions 31 to 33 are electrically connected to each other via connection vias 41b and 42b embedded in via holes 41a and 42a formed in the first and second interlayer insulating films 41 and 42. The first wiring part 31 is electrically connected to the semiconductor layer 13 through a contact hole 18 a formed in the protective film 18.

  Note that BPSG is used as the protective film 18, TEOS is used as the first to third interlayer insulating films 41 to 43, and Al is used as the first to third wiring portions 31 to 33. In the cross section different from FIG. 1, the first wiring portion 31 is also electrically connected to the gate electrode 16 as appropriate.

  A passivation film 60 is formed on the multilayer wiring layer 50. For example, a nitride film having a Young's modulus of about 240 GPa and harder than the first to third interlayer insulating films 41 to 43 is used as the passivation film 60. Note that the TEOS used as the first to third interlayer insulating films 41 to 43 has a Young's modulus of about 70 GPa.

  On the passivation film 60, an adhesion film 70 for improving adhesion with a barrier metal film 90 described later is disposed. For example, TEOS or the like is used as the adhesion film 70.

  A via hole 80 is formed through the adhesion film 70, the passivation film 60, and the third interlayer insulating film 43 to expose a part of the third wiring portion 33. The via hole 80 extends along the wall surface of the via hole 80. A barrier metal film 90 is formed thereon. The barrier metal film 90 is made of, for example, TiN.

  A pad layer 100 is formed on the barrier metal film 90. The pad layer 100 is configured by laminating a lower layer pad layer 101, a hard layer 102, and an upper layer pad layer 103 in order, and the lower layer pad layer 101 and the upper layer pad layer 103 are electrically connected via the hard layer 102. Has been.

  In the present embodiment, the lower pad layer 101 and the upper pad layer 103 are made of AlCu as an Al-based alloy containing Cu and have a Young's modulus of less than 80 GPa. The hard layer 102 is harder than the lower layer pad layer 101 and the upper layer pad layer 103, and is made of a transition metal. Specifically, the hard layer 102 is made of Ti, a Ti-based alloy, W, a W-based alloy, or the like, and has a Young's modulus of 80 GPa or more.

  In the present embodiment, the lower pad layer 101 is formed thicker than the upper pad layer 103 so as to absorb the stress applied to the upper pad layer 103. In other words, the hard layer 102 is disposed above the center of the pad layer 100 (on the opposite side to the substrate 10 side) in a cross section orthogonal to the planar direction of the substrate 10.

  The above is the configuration of the semiconductor device in this embodiment. Next, a method for manufacturing the semiconductor device will be described.

  First, as shown in FIG. 2A, a substrate 10 on which a semiconductor element 20 is formed is prepared, and a multilayer wiring layer 50 is formed on the substrate 10. As is well known, the multilayer wiring layer 50 is formed by forming a metal film or an insulating film by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like, and patterning by etching or the like, or by a CMP (Chemical Mechanical Polishing) method. It is formed by flattening.

  Next, as shown in FIG. 2B, a passivation film 60 is formed by a plasma CVD method or the like, and a film 70a constituting the adhesion film 70 is formed by a CVD method or the like. Then, as shown in FIG. 2C, a part of the third wiring portion 33 is exposed through the film 70a constituting the adhesion film 70, the passivation film 60, and the third interlayer insulating film 43 by etching or the like. A via hole 80 to be formed is formed.

  Subsequently, as shown in FIG. 3A, a metal film 90a constituting the barrier metal film 90 and a metal film constituting the lower pad layer 101 are formed on the film 70a constituting the adhesion film 70 by sputtering or the like. 101a, a metal film 102a constituting the hard layer 102, and a metal film 103a constituting the upper pad layer 103 are sequentially formed.

  Next, as shown in FIG. 3B, heat treatment is performed to flow the metal films 90a, 101a to 103a, thereby improving the burying property in the via hole 80. At this time, since the metal film 102a constituting the hard layer 102 is made of a transition metal, an alloy layer (not shown) of Al and the metal film 102a is formed at the interface between the metal film 102a and the metal films 101a and 103a. As it is formed, Cu 104 contained in the metal films 101a and 103a is deposited.

  Subsequently, as shown in FIG. 3C, a resist 105 is disposed on the metal film 102a. Specifically, the resist 105 is disposed so as to be thinner than the total thickness of the metal films 101a to 103a. In the present embodiment, the total thickness of each of the metal films 101a to 103a is about 4 μm, and the thickness of the resist 105 is about 3.8 μm. Then, the resist 105 is patterned by photolithography so that the resist 105 remains on the portion constituting the pad layer 100.

  As is well known, if the thickness of the resist 105 is about 3.8 μm, patterning can be performed with high accuracy. In addition, the thickness here is the film thickness, in other words, the length in the normal direction relative to the one surface 10a of the substrate 10.

  Thereafter, as shown in FIG. 4A, anisotropic etching with a strong sputter component is performed using the resist 105 as a mask. At this time, the anisotropic etching removes the Cu 104 deposited on the interface between the metal film 102a and the metal film 101a from the metal film 103a side, and the portion of the resist 105 and the metal film 101a on the substrate 10 side remains. Do as follows. Thereby, the hard layer 102 and the upper pad layer 103 are formed.

  That is, the anisotropic etching can remove the deposited Cu 104 due to the strong sputter component, but the resist 105 is also removed because the selectivity with the resist 105 is small. Since the resist 105 is thinner than the total thickness of the metal films 101a to 103, if the metal films 101a to 103a are all removed by anisotropic etching, the resist 105 is also completely removed. For this reason, anisotropic etching is performed so that a portion on the substrate 10 side of the resist 105 and the metal film 101a remains, and only the hard layer 102 and the upper pad layer 103 are formed in this step. Note that the condition for terminating anisotropic etching may be performed, for example, by acquiring a plurality of experimental data in advance and reliably removing the deposited Cu 104 based on the experimental data.

  Subsequently, as shown in FIG. 4B, isotropic etching with a weak sputter component is performed again using the resist 105 as a mask, so that the metal film 101a remaining in the step of FIG. The metal film 90a constituting the barrier metal film 90 is removed to be exposed. Thereby, the pad layer 100 having the lower layer pad layer 101, the hard layer 102, and the upper layer pad layer 103 is formed. Note that isotropic etching has a weak sputter component but has a high selection ratio with the resist 105, so that the metal film 101a can be removed while the resist 105 remains.

  Next, as shown in FIG. 4C, using the resist 105 as a mask, the metal film 90a constituting the barrier metal film 90 and the film 70a constituting the adhesion film 70 exposed from the resist 105 are removed. By performing over-etching, the barrier metal film 90 and the adhesion film 70 are formed. Thereafter, although not particularly shown, the semiconductor device shown in FIG. 1 is manufactured by removing the resist 105.

  As described above, in this embodiment, isotropic etching is performed so that the resist 105 remains after anisotropic etching is performed until Cu 104 deposited on the interface between the metal film 101a and the metal film 102a is removed. Is going. Therefore, the deposited Cu 104 can be removed while suppressing the resist 105 from being completely removed.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the first embodiment, the multilayer wiring layer 50 having the first to third wiring portions 31 to 33 has been described. However, the multilayer wiring layer 50 may further include a plurality of wiring portions or one wiring portion. You may make it have only.

  In the first embodiment, the lower layer pad layer 101 may be formed thicker than the upper layer pad layer 103, or the lower layer pad layer 101 and the upper layer pad layer 103 may be equal in thickness.

DESCRIPTION OF SYMBOLS 10 Board | substrate 10a One side 31-33 Wiring part 41-43 Interlayer insulation film 50 Wiring layer 100 Pad layer 101 Lower layer pad layer 102 Hard layer 103 Upper layer pad layer

Claims (2)

A substrate (10) having a surface (10a) on which a semiconductor element (20) is formed;
A wiring layer (50) in which wiring portions (31 to 33) and interlayer insulating films (41 to 43) electrically connected to the semiconductor element are sequentially stacked;
A pad layer (100) disposed in the via hole (80) formed in the wiring layer and electrically connected to the wiring portion;
In the pad layer, a lower layer pad layer (101), a hard layer (102), and an upper layer pad layer (103) are laminated in order from the substrate side, and the lower layer pad layer and the upper layer pad layer include an Al-based alloy containing Cu. In the method of manufacturing a semiconductor device, the hard layer is higher in hardness than the lower layer pad layer and the upper layer pad layer, and is composed of a transition metal.
Preparing the substrate;
Forming the wiring layer on one surface of the substrate;
Forming the via hole exposing the wiring portion in the wiring layer;
A first metal film (101a) that constitutes the lower layer pad layer, a second metal film (102a) that constitutes the hard layer, and the upper layer pad layer are formed on the wiring layer so as to be embedded in the via hole. Forming a third metal film (103a) in sequence;
A heat treatment step of flowing the first to third metal films by heat treatment;
Disposing a resist (105) thinner than the total thickness of the first to third metal films on the third metal film;
Patterning the resist so that the resist remains on a portion of the first to third metal films constituting the pad layer;
Performing the step of forming the pad layer by patterning the first to third metal films using the resist as a mask,
In the step of forming the pad layer, the second and third metal films are removed, and Cu (104) deposited at the interface between the first metal film and the second metal film during the heat treatment step. Is removed and anisotropic etching is performed so that the substrate-side portion of the resist and the first metal film remains, and the first exposed from the resist while leaving the resist. And a step of performing isotropic etching to remove the metal film.   The method of manufacturing a semiconductor device according to claim 1, wherein the hard layer is made of Ti, a Ti-based alloy, W, or a W-based alloy.

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