JP2016052207A - High-efficiency power factor improvement circuit and switching power supply unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-efficiency power factor improvement circuit for improving efficiency by reducing a switching loss by performing a burst operation of a switching element when a load of a switching power supply is light or there is no load, and the switching power supply unit.SOLUTION: A rectified input voltage 30 is supplied to a burst circuit 50 that is externally mounted on a control IC 100. The input voltage 30 supplied to the burst circuit 50 is divided by a voltage dividing resistor Rb1 (51) and a voltage dividing resistor Rb2 (52) of the burst circuit 50, and the divided input voltage is AC-coupled to a COMP terminal via a capacitor Cb53 and superposed on an output voltage 12 of an error amplifier (ERRAMP) 10. Only in the vicinity of a voltage peak of a ripple 60 that is synchronized with the input voltage, namely, only when the ripple 60 exceeds a threshold voltage, a switching pulse for driving ON/OFF of a MOSFET Q1(20) is outputted from an OUT (Output) terminal 17.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power factor correction circuit and a switching power supply device that reduce switching loss and improve efficiency by performing a burst operation of a switching element when the load of the switching power supply device is light and no load.

  Non-Patent Document 1 shown below incorporates an error amplifier (error amplifier) that detects and amplifies the output voltage by comparing it with a reference voltage, and the ON width of the switching element according to the output of the error amplifier for a certain load. A power factor correction circuit (PFC (Power Factor Correction) circuit) by so-called fixed ON width control (constant ON time control) is described.

  FIG. 3 shows a configuration of a switching power supply device having a conventional PFC circuit described in Non-Patent Document 1 below. FIG. 4 is a diagram showing operation waveforms of the conventional power factor correction circuit shown in FIG.

The PFC circuit of FIG. 3 constitutes a step-up converter. When a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (Q1) 220 as a switching element is turned on, an inductor (L1) 232 is turned on. Current I _L1 rises from zero. At the same time, the output Vramp (carrier signal) of the ramp oscillator (RAMP OSC) 214 inside the control IC (Integrated Circuit) 200 rises with a slope determined by the resistance value of the resistor connected to the RT terminal. The comparator (PWM.comp) 213 compares the output Vramp of the ramp oscillator (RAMP OSC) 214 and the output Vcomp (212) of the error amplifier (ERRAMP) 210. When Vramp> Vcomp, the MOSFET Q1 (220) is turned off. The output Vramp of the ramp oscillator (RAMP OSC) 214 decreases. When the MOSFET Q1 (220) is turned off, the voltage across the inductor L1 (232) is inverted, and the current I _L1 of the inductor L1 (232) decreases while supplying current to the output voltage 236 side through the diode D1 (234). .

The timing at which the current I _L1 of the inductor L1 (232) becomes zero is detected by the current comparator (ZCD.comp) 215 based on the voltage 216 at the IS terminal. Then, after a delay time determined by the resistance value of the resistor of the RTZC terminal, the MOSFET Q1 (220) is turned on, and the next switching cycle is started. The control IC 200 continues the operation (critical operation) by repeating this operation.

In the switching operation described above, when the load of the PFC circuit is constant, the value of the output Vcomp (212) of the error amplifier (ERRAMP) 210 is constant, and the ON width of the MOSFET Q1 (220) is constant. At this time, the peak current of the inductor L1 (232) is given by the following equation. That is,
Imax = (Vin / L) t _on
Here, Imax is the peak current of the inductor L1, Vin is the input voltage, L is the inductance value of the inductor L1, and t _on is the ON width.

In the above, since L and t _on are constant, the peak current Imax of L1 (232) is proportional to Vin (input voltage) 230. The waveform is the same AC (Alternate Current) waveform as that of the input voltage 230, and the power factor can be improved by this operation. This control method is generally referred to as “fixed on width control (constant on time control)”, and it is not necessary to detect the input voltage. Therefore, the conventional control method detects the input voltage with the input voltage detection resistor during standby. It has the effect that electric power is reduced rather than.

  The operation of the PFC circuit having the boost converter configuration shown in FIG. 3 will be described. The output voltage 236 of the PFC is divided by the voltage dividing resistors R1 (237) and R2 (238) and input to the FB terminal of the control IC 200. The error amplifier (ERRAMP) 210 outputs a current corresponding to the difference between the divided voltage and the DC voltage 2.5 V of the reference voltage source 211 provided in the control IC 200 (the error amplifier (ERRAMP) 210 is constituted by a transconductance amplifier). This is integrated and smoothed by a capacitor 261 connected to the output terminal of the error amplifier (ERRAMP) 210 to generate a signal Vcomp (212). The control IC 200 uses the output Vcomp (212) of the error amplifier (ERRAMP) 210 so that the output voltage 236 of the PFC circuit becomes constant (the divided voltage of the output voltage 236 is set to the DC voltage 2.5 V of the reference voltage source 211). Controls the switching operation of MOSFET Q1 (220) to be equal.

  On the other hand, the output voltage 236 of the PFC circuit usually includes a ripple component synchronized with an alternating current (AC) input 222 based on a commercial power supply, but the output Vcomp (212) of the error amplifier (ERRAMP) 210. When this ripple appears, the PFC circuit does not operate stably. Therefore, a phase compensation circuit of CR (Capacitor and Resistor) connected to the COMP terminal, which is also the output of the error amplifier (ERRAMP) 210, cuts a band higher than twice the input frequency (the gain of the band is increased). (Below 0 dB). As a result, the voltage at the COMP terminal, which is also the output of the error amplifier (ERRAMP) 210, is substantially a DC voltage in the steady state (see the arrow line to the COMP terminal in FIG. 3 and the upper waveform in FIG. 4).

  The output Vcomp (212) of the error amplifier (ERRAMP) 210 is compared with the output Vramp of the ramp oscillator (RAMP OSC) 214 by the comparator (PWM.comp) 213 in the control IC 200, and the comparison result is output from the OUT terminal 217 to the switching element. The output voltage 236 of the PFC circuit is adjusted by outputting to the gate of Q1 (220) and controlling the ON width of the switching element Q1 (220).

  The PFC circuit shown in FIG. 3 is used in a critical mode (Critical Mode). Although the switching frequency is low at heavy load and the switching frequency is high at light load, the PFC circuit shown in FIG. Since the switching pulse is continuously output from the OUT (Output) terminal 217 in the light load state to the heavy load state (see the lower waveform in FIG. 4), the switching loss of the MOSFET Q1 (220) decreases as the load is lighter. There is a problem that the efficiency increases and the efficiency decreases.

  In Patent Document 1 below, a power factor correction circuit that is connected to an AC power source and obtains a DC voltage, and a DC voltage of the power factor correction circuit is input to a primary winding of a transformer and turned on / off by a switching element. In a switching power supply apparatus including a DC-DC converter that converts to a DC voltage and has a switching frequency that decreases or switches to intermittent oscillation at no load or light load, the voltage generated in the secondary winding of the transformer is rectified to be first smoothed A first rectifying / smoothing circuit that is smoothed by a capacitor and supplied to a load, a second rectifying / smoothing circuit that rectifies the voltage generated in the control winding of the transformer and smoothes it by a second smoothing capacitor, and an output of the second rectifying / smoothing circuit A light load detection circuit that stops the power factor correction circuit when the switching frequency decreases or shifts to intermittent oscillation when it is detected that the ripple has exceeded the specified value. Switching power supply device is described that.

  And when this switching power supply detects that the output ripple of the 2nd rectification smoothing circuit became more than predetermined value, it will stand by by stopping a power factor improvement circuit noting that a switching frequency fell or shifted to intermittent oscillation. Teaching to reduce power consumption at the time.

Specifically, at the time of light load becomes the control IC72 standby operation mode of the DC-DC converter, the switching element Q2 at a much lower frequency than the switching frequency at the normal time to intermittent oscillation (t ₁ ~t ₇ segment). At this time, the voltage V _C5 of the smoothing capacitor C5 corresponding to the first smoothing capacitor is controlled to be a substantially constant voltage even during heavy load and light load. On the other hand, when the load is light, the switching element Q2 intermittently oscillates at a frequency much lower than the normal switching frequency. Therefore, the voltage V _C4 of the smoothing capacitor C4 corresponding to the second smoothing capacitor is not oscillated (t ₁ ~t _{3 section,} the t 5 ~t ₇ segment), gradually decreases to discharge time constant of the smoothing capacitor C4 that the load impedance (the impedance of the light load detection circuit 15), a large ripple appears.

Light load detection circuit 15 compares the voltage _{V C4} of the reference voltage Vref and the smoothing capacitor C4, when the voltage _{V C4} of the smoothing capacitor C4 is equal to or less than the reference voltage Vref _(t 2 ~t _{4 sections, t} 6 ~ to t ₈ intervals), and outputs a voltage signal Vse1 which becomes L level to the PFC control circuit 6a to stop the PFC control circuit 6a. For this reason, the power factor correction circuit 5 can be stopped in most periods of intermittent oscillation. Further, during the intermittent oscillation period (t _{1 to} t ₇ ), if the time constant inside the light load detection circuit 15 is further increased so that the voltage V _C4 of the smoothing capacitor C4 does not rise to the reference voltage Vref, the light load detection is performed. The signal output from the circuit 15 to the PFC control circuit 6a is a voltage signal Vse2 shown in FIG. 6, and the power factor correction circuit 5 can be continuously stopped during the intermittent oscillation period. As described above, according to the switching power supply device of the embodiment, the light load detection circuit 15 detects that the output ripple of the smoothing capacitor C4 is equal to or higher than the predetermined value, and assumes that the PFC control circuit 6a has shifted to intermittent oscillation. Therefore, the fact that the DC-DC converter has shifted to the standby operation can be determined from the outside at low cost, and the power factor correction circuit 5 can be reliably stopped to reduce the standby power consumption.

Japanese Patent Laying-Open No. 2005-348560 (FIG. 1, FIG. 6, paragraphs 0044 to 0048)

Takahito Sugawara, two others, “2nd generation critical mode PFC control IC“ FA5590 series ””, Fuji Times, Fuji Electric Holdings Co., Ltd., November 10, 2010, Vol. 83, No. 6, p. 405-410

  As described above, in the case of the prior art shown in FIG. 3, the switching frequency becomes high and the loss of the switching element increases at the time of a light load, so that (1) efficiency is deteriorated, (2) switching element There was a problem that the temperature of this would rise.

  Further, the switching power supply device disclosed in Patent Document 1 has a problem that the output voltage of the PFC circuit fluctuates and the design of the subsequent converter becomes difficult because the PFC is turned on / off at a light load.

  Therefore, the present invention provides a high-efficiency power factor correction circuit and a switching power supply that improve the efficiency by reducing the switching loss by causing the switching element to perform a burst operation when the load of the switching power supply is light or no load. It is for the purpose.

  In order to solve the above problems, the power factor correction circuit according to the present invention is obtained by rectifying a commercial power supply to an output voltage of an error amplifier that amplifies a difference between a detected value of an output voltage of a switching power supply device and a reference value. An added output voltage is generated by weighted addition of the detected value of the input voltage to the switching power supply device, and a signal for turning on and off the switching element of the switching power supply device is generated by comparing the added output voltage with the carrier signal. It is characterized by that.

In the above, the carrier signal repeats generation of a ramp signal at a constant period.
Further, in the above, when the added output voltage is smaller than the minimum value of the carrier signal, the signal for turning on / off the switching element is a signal for turning off the switching element.

In the above, the input voltage is obtained by full-wave rectification of the commercial power supply.
In the above, the input voltage is obtained by half-wave rectifying the commercial power supply.

In the above, the error amplifier includes a transconductance amplifier and a first capacitor connected to the output of the transconductance amplifier.
Further, in the above, a voltage dividing circuit having a first resistor and a second resistor connected in series to which the input voltage is applied, and a connection point between the first resistor and the second resistor of the voltage dividing circuit And a second capacitor connected between the outputs of the error amplifier.

  In order to solve the above problems, a switching power supply device according to the present invention includes any one of the power factor correction circuits described above.

According to the present invention, since the power factor correction circuit can perform a burst operation at light load and no load of the switching power supply device, the switching loss is reduced and the efficiency is improved.
Further, according to the present invention, the burst operation is likely to occur particularly at a high input voltage (for example, AC 200 V) at which the switching loss becomes large.
(B) The power semiconductor element specification MOSFET, secondary diode, and transformer can be reduced in cost.
(B) The heat sink can be reduced in size.

  Further, the burst operation not synchronized with the AC input greatly reduces the power factor. However, according to the present invention, the burst operation is performed in synchronization with the AC input voltage, so that the power factor can be greatly improved.

It is a figure which shows the structure of the switching power supply device which has a highly efficient power factor improvement circuit which concerns on embodiment of this invention. It is a figure which shows the operation | movement waveform of the high efficiency power factor improvement circuit shown in FIG. It is a figure which shows the structure of the switching power supply device which has the conventional critical mode power factor improvement circuit. It is a figure which shows the operation | movement waveform of the conventional power factor improvement circuit shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail.
FIG. 1 is a diagram showing a configuration of a switching power supply device having a high-efficiency power factor correction circuit (PFC circuit) according to an embodiment of the present invention. FIG. 2 is a diagram showing operation waveforms of the high-efficiency power factor correction circuit shown in FIG.

  The difference between the configuration of the switching power supply apparatus according to the present embodiment shown in FIG. 1 and the configuration of the conventional switching power supply apparatus shown in FIG. 3 is that the switching power supply apparatus according to the embodiment of the present invention shown in FIG. A configuration is adopted in which the burst circuit 50 enclosed by the external circuit is externally connected to the control IC 100 and its output is AC coupled to the COMP terminal of the control IC 100 via the capacitor Cb (53) and added to the output 12 of the error amplifier (ERRAMP) 10. There is in being.

  A burst circuit 50 surrounded by a broken line includes a voltage dividing resistor Rb1 (51), a voltage dividing resistor Rb2 (52), and a capacitor Cb (53) connected in series, as shown in the drawing, and the voltage dividing resistor Rb1 ( 51) and the voltage dividing resistor Rb2 (52) are connected to one end of the capacitor Cb (53), and the other end of the capacitor Cb (53) is connected to the COMP terminal of the control IC 100. The other side of the voltage dividing resistor Rb1 (51) is connected to the output 30 of the rectifier circuit 24 having a full-wave rectified waveform of AC input. As a result, the divided input voltage (the output 30 of the rectifier circuit 24) is AC-coupled to the COMP terminal via the capacitor Cb (53), and the ripple 60 synchronized with this AC input is passed through the COMP terminal to the error amplifier (ERRAMP). ) Is superimposed (added) to the output Vcomp (12) of 10 to obtain Vcomp (12) actually observed. This addition is a weighted addition in which a weighting coefficient is determined by the capacitance values of the capacitor Cb (53) and the capacitor (C61 + C63). More specifically, a voltage (Cb / (Cb + C61 + C63)) times the divided voltage is added to the COMP terminal side. Here, Cb and (C61 + C63) are capacitance values of the capacitor C63 which is a component of the capacitor Cb (53), the capacitor 61, and the phase compensation circuit 62 described later, respectively.

  The operation of the switching power supply device having the high efficiency power factor correction circuit according to the embodiment of the present invention will be described with reference to FIGS. In FIG. 1, the voltage of the AC 22 that is a commercial power source is rectified by the rectifier circuit 24, and the rectified input voltage 30 is supplied to a burst circuit 50 externally attached to the control IC 100.

The PFC circuit of FIG. 1 constitutes a boost converter, similar to the conventional PFC circuit shown in FIG. 3. When the MOSFET Q1 (20) is turned on as a switching element, the current I of the inductor (L1) 32 _L1 rises from zero. At the same time, the output Vramp (carrier signal) of the ramp oscillator (RAMP OSC) 14 in the control IC 100 rises with a slope determined by the resistance value of the RT terminal resistor. The comparator (PWM.comp) 13 compares the output Vramp of the ramp oscillator (RAMP OSC) 14 and the output Vcomp (12) of the error amplifier (ERRAMP) 10, and when Vramp> Vcomp, the MOSFET Q1 (20) is turned off. The output Vramp of the ramp oscillator (RAMP OSC) 14 decreases.

When the MOSFET Q1 (20) is turned off, the voltage across the inductor L1 (32) is inverted, and the current I _L1 of the inductor L1 (32) decreases while supplying current to the output voltage 36 side through the diode D1 (34). .

The timing at which the current I _L1 of the inductor L1 (32) becomes zero is detected by a current comparator (ZCD.comp) 15 based on the voltage 16 at the IS terminal. Then, after a delay time determined by the resistance value of the resistor of the RTZC terminal, the MOSFET Q1 (20) is turned on, and the next switching cycle is started. This point will be further explained. If the current is turned on immediately after detecting the zero current, the Vds voltage (drain-source voltage) of the MOSFET Q1 (20) is turned on and the switching loss is large. However, by delaying the next on-timing by the delay circuit shown in FIG. 1, the Vds voltage is lowered by the resonance operation of the parasitic capacitance (not shown) of the inductor L1 (32) and the MOSFET Q1 (20), Since it can be turned on at an appropriate timing, switching loss can be reduced. The control IC 100 continues this operation (critical operation) by repeating this operation.

  Here, the output voltage 36 of the PFC circuit shown in FIG. 1 is divided by the voltage dividing resistors R1 (37) and R2 (38) and input to the FB terminal of the control IC 100. The error amplifier (ERRAMP) 10 outputs a current corresponding to the difference between the divided voltage and the DC voltage 2.5 V of the reference voltage source 11 provided in the control IC 100, and this is output to the output terminal of the error amplifier (ERRAMP) 10. The signal Vcomp (12) is generated by integrating and smoothing the connected capacitor 61. The control IC 100 uses the output Vcomp (12) of the error amplifier (ERRAMP) 10 so that the output voltage 36 of the PFC circuit becomes constant (the divided voltage of the output voltage 36 is set to the DC voltage 2.5V of the reference voltage source 11). Controls the switching operation of MOSFET Q1 (20) to be equal.

  The output voltage 36 of the PFC circuit usually includes a ripple synchronized with the AC (22) input based on the commercial power supply, but this ripple is output to the output Vcomp (12) of the error amplifier (ERRAMP) 10. When the minute appears, the PFC circuit does not operate stably. Therefore, normally, the gain of the band higher than the frequency twice the input frequency is reduced from 0 dB in the phase compensation circuit 62 of CR (Capacitor and Resistor) connected to the COMP terminal which is also the output of the error amplifier (ERRAMP) 10. To use.

  In the embodiment of the present invention, the input voltage 30 supplied to the burst circuit 50 is divided by the voltage dividing resistor Rb1 (51) and the voltage dividing resistor Rb2 (52) of the burst circuit 50, and the divided input voltage is converted into a capacitor. The AC terminal is configured to be AC-coupled to the COMP terminal via Cb (53). 1 and 2 illustrate an example in which the full-wave rectified input voltage 30 is supplied to the burst circuit 50. However, the half-wave rectified input voltage may be supplied to the burst circuit 50. Of course, it is operable.

  In FIG. 2, the input voltage 30 after full-wave rectification is divided by the voltage dividing resistor Rb1 (51) and the voltage dividing resistor Rb2 (52) of the burst circuit 50, and the divided input voltage is divided by the capacitor Cb53. The state of AC coupling to the COMP terminal is shown. As described above, FIG. 2 illustrates an example of full-wave rectification, but an example of half-wave rectification may be used.

  In the case of the input voltage 30 after full-wave rectification, a ripple 60 synchronized with a period twice the AC input frequency is superimposed on the output Vcomp (12) of the error amplifier (ERRAMP) 10 as shown in FIG. Added). As described above, by using the CR phase compensation circuit 62 connected to the COMP terminal, a gain in a band higher than a frequency twice the input frequency is used below 0 dB. The ripple 60 is attenuated by the voltage division ratio of the capacitor of the phase compensation circuit 62. In the example shown in FIG. 2, at a light load where the COMP terminal voltage is near the threshold voltage (see the broken line shown in the lower half of FIG. 2), near the voltage peak of the ripple 60 synchronized with the input voltage, that is, the COMP terminal voltage. When the voltage exceeds the threshold voltage, a switching pulse for driving the MOSFET Q1 (20) on / off is output to the OUT terminal 17, and when the voltage drops below the threshold voltage, the switching pulse is not output from the OUT terminal 17 and the MOSFET Q1 (20 ) Is a burst operation that remains off.

  The burst operation will be further described. As described above, the threshold voltage at the COMP terminal voltage indicates a voltage threshold at which a switching pulse is output to the OUT terminal 17, and no switching pulse is output from the OUT terminal 17 below the threshold voltage. This threshold voltage is the start voltage (minimum voltage) of the output Vramp of the ramp oscillator (RAMP OSC) 14. That is, in FIG. 1, the output Vramp of the ramp oscillator (RAMP OSC) 14 and the output Vcomp (12) of the error amplifier (ERRAMP) 10 are compared by the comparator (PWM.comp) 13, and if Vcomp (12) <Vramp, then RSF / F is reset. Therefore, if the output Vcomp (12) of the error amplifier (ERRAMP) 10 is equal to or lower than the start voltage, the output of the comparator (PWM.comp) 13 remains high and the RSF / F is always reset. No switching pulse is output.

On the other hand, the conventional configuration shown in FIG. 3 does not perform the burst operation (does not perform the intermittent operation) as shown in FIG.
Note that the pulse width of the switching pulse output from the OUT terminal 17 is wide at the peak of AC and becomes narrower as it approaches the zero crossing portion. That is, the ON width of the MOSFET Q1 (20) changes according to the magnitude of the AC input voltage 30 input to the burst circuit 50. This is because the voltage of the ripple 60 synchronized with the input voltage added to the output 12 of the error amplifier (ERRAMP) 10 is compared with the output of the ramp oscillator (RAMP OSC) 14 by the comparator (PWM.comp) 13 in the control IC 100. This is because the ON width of the switching pulse output from the OUT (Output) terminal 17 to the gate of the MOSFET Q1 (20) is controlled according to the result.

In the case of the embodiment of the present invention, a burst operation is likely to occur at a high input voltage, for example, AC 200V. The first reason is that the COMP voltage becomes low at a high input voltage. Supplementing this, the current I _L1 flowing through the inductor (L1) 32 when the MOSFET Q1 (20) is on increases rapidly as the input voltage 30, that is, the AC input voltage is higher. Since the energy stored in the inductor (L1) 32 and then supplied to the load is proportional to the square of the current _IL1 , the higher the AC input voltage for the same load, the shorter the on-time of the MOSFET Q1 (20). It's okay. Since the on-time is a time until Vramp becomes larger than Vcomp (12), Vcomp (12) becomes lower as the AC input voltage is higher in the equilibrium state. The second reason is that the voltage of the superimposed ripple 60 increases in proportion to the input voltage 30.

  The input voltage of the PFC circuit is generally set between 85 and 270 V AC, and in this case, the value of the component used in the circuit constituting the burst circuit 50 of the present invention is a voltage dividing resistor. Rb1 (51) should be set to 2-3 MΩ, voltage dividing resistor Rb2 (52) should be set to 20 to 30 kΩ, and capacitor Cb (53) should be set to a capacitance of 1/1000 to 1/10 of C61 + C63. . In this embodiment, the error amplifier (ERRAMP) 10 using a transconductance amplifier is exemplified, but the present invention is not limited to this.

  In addition, since the power factor correction circuit according to the embodiment of the present invention operates with high efficiency, the cost of the MOSFET Q1 (20), the secondary diode (not shown), and the transformer (not shown) of the power semiconductor element specification is reduced. Can be achieved. Further, the heat sink (not shown) can be made small.

  In addition, the burst operation that is not synchronized with the AC input greatly reduces (inefficiency) the power factor. However, as described above, in the embodiment of the present invention, the burst operation is performed in synchronization with the AC input voltage. The power factor can be improved satisfactorily by the small on-width control.

10 Error amplifier
11 Reference voltage source
12 Error amplifier output Vcomp
13 Comparator (PWM.comp)
14 Ramp oscillator (RAMP.OSC)
15 Current comparator (ZCD.comp)
16 Current detection voltage
17 OUT terminal
20 MOSFET Q1 (switching element)
22 Commercial power (AC power)
24 Rectifier circuit
30 Rectifier circuit output (input voltage)
32 Inductor (L1)
34 Diode (D1)
36 PFC circuit output voltage
37 Voltage divider resistor (R1)
38 Voltage divider resistor (R2)
50 burst circuit
51 Rb1 (voltage dividing resistor)
52 Rb2 (voltage dividing resistor)
53 Capacitor Cb
60 ripples
62 Phase compensation circuit
100 Control IC

Claims (8)

  Add by weighting and adding the detected value of the input voltage to the switching power supply obtained by rectifying the commercial power supply to the output voltage of the error amplifier that amplifies the difference between the detected value of the output voltage of the switching power supply and the reference value A power factor correction circuit that generates an output voltage and generates a signal for turning on and off the switching element of the switching power supply device by comparing the added output voltage with a carrier signal.   The power factor correction circuit according to claim 1, wherein the carrier signal repeats generation of a ramp signal at a constant period.   2. The power factor correction circuit according to claim 1, wherein when the added output voltage is smaller than a minimum value of the carrier signal, a signal for turning on / off the switching element is a signal for turning off the switching element.   The power factor correction circuit according to claim 1, wherein the input voltage is obtained by full-wave rectification of the commercial power supply.   The power factor correction circuit according to claim 1, wherein the input voltage is obtained by half-wave rectifying the commercial power source.   2. The power factor correction circuit according to claim 1, wherein the error amplifier includes a transconductance amplifier and a first capacitor connected to an output of the transconductance amplifier.   A voltage dividing circuit having a first resistor and a second resistor connected in series to which the input voltage is applied, a connection point between the first resistor and the second resistor of the voltage dividing circuit, and the error amplifier The power factor correction circuit according to claim 1, further comprising a second capacitor connected between the outputs of the first and second capacitors.   A switching power supply comprising the power factor correction circuit according to any one of claims 1 to 7.

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