JP2016048758A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device and a manufacturing method of the same, which ensure a low on-resistance value and high channel mobility in an insulated-gate transistor and improve reliability of the device.SOLUTION: A semiconductor device comprises: a gate insulation film 5 formed on a region which brackets both of a pair of base regions 3; a gate electrode 6 formed on a major portion except ends of the gate insulation film 5; a source electrode 7 formed on a source region 4 to be electrically independent from the gate electrode 6; and a drain electrode 8 formed on a rear face of a substrate 1. With the above-described construction, an N-type MOSFET which uses a surface region of a base region 3 as a channel region and has the gate electrode 6, the source electrode 7 and the drain electrode 8 can be achieved. In this case, a LaSiON film 5L as the gate insulation film 5 forms a boundary surface with the channel region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device having an insulated gate transistor formed in a semiconductor layer composed of silicon carbide (SiC) and a method for manufacturing the same.

SiC (silicon carbide) has superior performance compared to silicon (Si), which has been used mainly in conventional power devices, because of its physical properties, enabling the realization of power devices with high breakdown voltage and low loss. To. However, many interface states exist at the silicon carbide (SiC) / silicon dioxide (SiO ₂ ) interface. Due to the interface state close to this conduction band, the electron mobility (channel mobility) in the channel of an insulated gate transistor such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) becomes extremely small compared to the electron mobility in the bulk. The on-resistance value becomes higher than the ideal value.

  The term “MOS” has been used for a metal / oxide / semiconductor laminated structure in the past, and as mentioned above, it has been taken from the acronym Metal-Oxide-Semiconductor. However, especially in a MOSFET having a MOS structure, the material of the gate insulating film and the gate electrode has been improved from the viewpoint of recent integration and improvement of the manufacturing process.

  For example, in a MOSFET, polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner. From the viewpoint of improving electrical characteristics, a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.

  Therefore, the term “MOS” is not necessarily limited to the metal / oxide / semiconductor stacked structure, and is not presumed in this specification. That is, in view of technical common sense, here, “MOS” has not only an abbreviation derived from the word source but also a broad meaning including a laminated structure of a conductor / insulator / semiconductor.

Regarding gate insulating film materials used in SiC-MOS devices, in recent years, lanthanum silicon oxide (lanthanum silicate, LaSiO _x ) has attracted attention as an alternative material to conventional SiO ₂ . For example, Non-Patent Document 1 reports that by using LaSiO _x as a gate insulating film, higher channel mobility can be obtained as compared with a MOSFET using SiO ₂ as a gate insulating film.

As a reason why the channel mobility of a MOSFET using LaSiO _x as a gate insulating film is improved, relaxation of lattice strain at the SiC / LaSiO _x interface can be considered. LaSiO _x is the phase transition temperature is lower than the SiO _2, structural relaxation of the interface can be expected to match the lattice constant of the SiC crystal as compared to SiO _2.

Further, as a feature of LaSiO _x , the dielectric constant is higher than that of a conventional SiO ₂ film. The relative dielectric constant of LaSiO _x is “15”, which is about four times larger than “3.9” of SiO ₂ . The dielectric constant tends to decrease as the proportion of Si in LaSiO _x increases, but the relative dielectric constant is about “9” even when the ratio is the lowest.

When SiO ₂ having a thickness of 50 nm is used as the gate insulating film, assuming that there is no interface state density, the acceptor concentration in the channel region is 1 × 10 ¹⁷ cm ⁻³ and the threshold voltage is about 3V. If the acceptor concentration of the channel region is constant, and you change the material of the gate insulating film of SiO ₂ is LaSiO _x, thickness in consideration of the difference in dielectric constant is required LaSiO _x of 115 nm. In this case, when a gate voltage of 15 V is applied, an oxide film electric field of 3 MV / cm is applied in SiO ₂ , but in LaSiO _x having a large film thickness, the electric field is only about 1.3 MV / cm.

The dielectric breakdown electric field of each insulating film is about 10 MV / cm for SiO ₂ , while LaSiO _x is 16 MV / cm or more. Therefore, a significant improvement in reliability can be expected by changing the gate insulating film material from SiO ₂ to LaSiO _x .

Usually, in order to form a LaSiO _x film on a silicon carbide substrate, a La ₂ O ₃ film is deposited on the silicon carbide substrate, and further a SiO ₂ film is deposited thereon, and then La ₂ O ₃ and SiO ₂ are formed by heat treatment. ₂ is reacted to form a LaSiO _x film.

Although it is smaller than the SiC / SiO ₂ interface, there is also an interface state at the SiC / LaSiO _x interface, and in order to reduce the interface state density, passivation by nitriding is performed in the same manner as the SiC / SiO ₂ interface. It is valid.

Heat treatment in a nitrogen oxide gas atmosphere such as nitric oxide (NO) or dinitrogen monoxide (N ₂ O) is effective for nitriding, but oxygen atoms contained in the nitrogen oxide gas are contained in LaSiO _x . easily incorporated, the oxygen radicals in LaSiO _x. When SiC / LaSiO _x interface oxygen radicals is reached at the interface SiC / LaSiO _x silicon, carbon, interfacial layer made of oxygen is formed, it deteriorates the channel characteristics having originally SiC / LaSiO _x interface.

When N ₂ O annealing (treatment) at 1100 ° C. is performed on the SiO ₂ film, nitrogen in the order of the 21st power (atom / cm ³ ) is introduced into SiO ₂ . The concentration of silicon and oxygen in SiO ₂ is on the 22nd power level, and in the case of N ₂ O annealing, nitrogen is present at a ratio of about one-tenth of silicon and oxygen. When performing the _{N 2} O anneal to LaSiO _x film, the oxygen taken into the LaSiO _x film becomes radical, oxidation of SiC occurs at SiC / LaSiO _x interface. Growth of new oxide film, a low nitrogen diffusion rate in LaSiO _x, the concentration of nitrogen in LaSiO _x becomes less than 21 Nodai ones.

Also, when LaSiO _x is annealed in an NH ₃ atmosphere, the elemental composition ratio is La _9.7 Si ₆ O _22.6 N _2.7 , and the nitrogen concentration is lower than other elements, particularly oxygen.

  In addition to the passivation of the interface state by post-annealing after the gate insulating film is formed, when the gate insulating film is formed by thermal oxidation, the nitrogen atom concentration in the SiC substrate is increased in advance so that it is similar to the nitriding treatment. It is known that this effect can be obtained.

  In this case, in the process in which SiC is eroded by thermal oxidation, originally existing nitrogen atoms are segregated at the interface, and the same effect as in the nitriding treatment can be obtained.

By depositing a La ₂ O ₃ film on the SiC substrate and applying heat treatment, SiC and La ₂ O ₃ react to form a LaSiO _x film. Also in this case, nitrogen is segregated at the SiC / LaSiO _x interface, and the same effect as the nitriding treatment can be expected.

  When growing an epitaxial layer on a SiC substrate, a step flow growth technique using an off-wafer in which the wafer surface is exposed by tilting the wafer several degrees with respect to the crystal axis from the viewpoint of polymorph control is the mainstream.

  In a wafer with an off-angle, a surface {0001} called a terrace and a surface {1120} called a step exist on the exposed surface, and the growth rates of oxide films by thermal oxidation are different on each surface. Compared to the {0001} plane, the oxide film growth rate on the {1120} plane is approximately five times larger.

Even when SiC reacts with La ₂ O ₃ , there is a difference in reaction rate due to the difference in crystal plane. Due to this reaction speed difference, the composition ratio of the LaSiO _x film changes along the crystal plane of the step bunching of the SiC substrate and does not become an insulating film having uniform quality on the entire surface of the SiC substrate.

The reaction between the SiC substrate and La ₂ O ₃ should occur in an inert gas atmosphere, and is also suitable in an O ₂ atmosphere diluted with an inert gas or a gas containing oxygen atoms.

For example, a La ₂ O ₃ film and a SiO ₂ film are deposited on SiC and annealed at 900 ° C. in an N ₂ O atmosphere. In this case, it is considered that the reaction between La ₂ O ₃ and SiO ₂ occurs preferentially, but the reaction between SiC and La ₂ O ₃ and the thermal oxidation of SiC also occur simultaneously due to the oxygen element contained in N ₂ O. This is disclosed in Non-Patent Document 1, for example.

Due to the reaction between SiC and La ₂ O ₃ and the thermal oxidation of SiC, an interface layer SiCO is generated at the SiC interface, and the interface state density increases.

X. Yang et al., “High Mobility 4H-SiC MOSFETs Using Lanthanum Silicate Interface Engineering and ALD Deposited SiO2,” Materials Science Forum Vols. 778-780 (2014) pp 557-561.

As described above, at the same time in order to reduce the interface state density of SiC / LaSiO _x interface, when the nitrided in nitrogen oxide gas atmosphere, when the SiC / LaSiO _x interface can interface layer formed of SiCO, SiC Along with the step bunching of the substrate, the composition ratio of the LaSiO _x layer changes, and both the interface quality and the film quality deteriorate.

Therefore, even when LaSiO _x is used as the gate insulating film, a low on-resistance value and high channel mobility in a conventional insulated gate transistor such as a MOSFET cannot be secured, and the reliability of the entire device is increased. There was a problem that it was not possible.

  The present invention has been made in order to solve the above-described problems. A semiconductor device having a low on-resistance value and a high channel mobility in an insulated gate transistor to be formed, and a high reliability of the entire device, and its It aims at obtaining a manufacturing method.

  According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor layer made of silicon carbide; a gate insulating film formed on the semiconductor layer; and a gate electrode formed on the gate insulating film. And an insulating gate type transistor in which the surface of the semiconductor layer under the gate electrode through the gate insulating film serves as a channel region is configured, and the gate insulating film forms a lanthanum that forms an interface with the channel region. A silicon oxynitride film is included.

  According to a first aspect of the present invention, an insulated gate transistor in a semiconductor device according to the present invention includes a gate insulating film that forms an interface with a channel region and includes at least part of a silicon lanthanum oxynitride film containing nitrogen at a high concentration. Therefore, the channel region can be set to a lower interface state density than when a silicon oxide film or the like is used for the gate insulating film, and as a result, the on-resistance value of the insulated gate transistor can be kept low. There is an effect.

  Further, a nitrogen atom present in a high ratio in the gate insulating film including the silicon lanthanum oxynitride film can provide a passivation effect of the interface state at the interface with the channel region. This eliminates the need for nitriding treatment between the channel region and the gate insulating film, which has been necessary after forming a lanthanum silicon oxide film or the like as the gate insulating film. As a result, the present invention according to claim 1 can avoid the phenomenon that an interface layer composed of silicon, carbon, and oxygen is generated at the interface of the channel region due to the nitriding treatment. The effect is that high channel mobility can be secured.

  In addition, the semiconductor device of the present invention having the above gate insulating film suppresses an excessive oxidation reaction as in the case where a (lanthanum) silicon oxide film is used as the gate insulating film. Since the composition ratio of silicon nitride is stabilized, the reliability is improved.

It is sectional drawing which shows the structure of the semiconductor device which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. It is a graph which shows the band structure from the gate electrode in each of the conventional MOSFET and MOSFET of Embodiment 1 to a board | substrate. It is a graph which shows the carrier density of the channel when 15V gate voltage VG is applied to each of MOSFET of the past and this embodiment. FIG. 11 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device of the second embodiment. It is a graph which shows the electric charge trapped in the deposited film with respect to the film thickness of the SiN film in a pre-processing laminated structure. 6 is a graph showing a band structure immediately below a gate electrode when a MOSFET is turned off in the semiconductor device of the second embodiment. 6 is a graph showing a band structure immediately below a gate electrode when a MOSFET is turned on in the semiconductor device of the second embodiment. FIG. 10 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device in the third embodiment. FIG. 10 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device in the third embodiment. FIG. 10 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device in the fourth embodiment. FIG. 10 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device in the fourth embodiment. It is a graph which shows the element ratio with respect to the depth position containing the interface of a gate insulating film and a silicon carbide semiconductor layer.

<Embodiment 1>
(Device structure)
1 is a cross sectional view showing a structure of a (silicon carbide) semiconductor device using SiC as a constituent material according to the first embodiment of the present invention. The configuration example shown in FIG. 1 shows a cross-sectional structure of an N-channel silicon carbide MOSFET.

  In the figure, a silicon carbide drift layer 2 (semiconductor layer) made of SiC is formed on the surface (one main surface) of an N-type substrate 1 (semiconductor substrate). A pair of P-type base regions 3 are selectively formed in the upper layer portion of silicon carbide drift layer 2. An N-type source region 4 is selectively formed in the upper layer portion of each of the pair of base regions 3. Therefore, the surface region of silicon carbide drift layer 2 includes a part of silicon carbide drift layer 2, a part of base region 3, and a source region 4.

  And on one end region of the pair of source regions 4, on one surface region of the pair of base regions 3, on the surface region of the silicon carbide drift layer 2, on the other surface region of the pair of base regions 3, and A gate insulating film 5 is formed on the other end region of the pair of source regions 4. That is, the gate insulating film 5 is formed on a region sandwiching each region of the pair of base regions 3.

  The gate insulating film 5 has a single structure of a LaSiON film 5L (lanthanum oxynitride film).

  The gate electrode 6 is formed on the main portion except the end of the gate insulating film 5, the source electrode 7 is formed on the source region 4 electrically independent of the gate electrode 6, and the drain electrode 8 is formed on the substrate 1. It is formed on the back surface (the other main surface).

  In the semiconductor device of the first embodiment having such a structure, the surface region of base region 3 formed in the upper layer portion of silicon carbide drift layer 2 immediately below gate insulating film 5 via gate electrode 6 is used as a channel region, The main structure of the N-type MOSFET having the gate electrode 6, the source electrode 7, and the drain electrode 8 can be obtained. Therefore, the LaSiON film 5L, which is the gate insulating film 5 of the MOSFET, forms an interface with the channel region.

(Production method)
2 to 10 are cross-sectional views showing a method of manufacturing the semiconductor device of the first embodiment shown in FIG. Hereinafter, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to these drawings.

  First, as shown in FIG. 2, N-type carbonization using SiC as a constituent material on the surface (one main surface) of an N-type (first conductivity type) substrate 1 (semiconductor substrate) by an epitaxial crystal growth method. Silicon drift layer 2 is formed. For example, an N-type silicon carbide substrate is suitable as the N-type substrate 1.

  After the epitaxial crystal growth, as shown in FIG. 3, impurities are ion-implanted into a pair of regions separated by a predetermined interval in the upper layer portion of the silicon carbide drift layer 2 using a resist (not shown) as a mask. A P-type (second conductivity type) base region 3 is formed. FIG. 3 shows a cross-sectional structure after removing the resist. Examples of the P-type impurity in the silicon carbide drift layer 2 include boron (B) and aluminum (Al).

  Further, as shown in FIG. 4, in each of the pair of P-type base regions 3, impurities are ion-implanted using a resist (not shown) as a mask, and an N-type is selectively formed in the upper layer portion of each base region 3. A source region 4 is formed. FIG. 4 shows the cross-sectional structure after removing the resist. Examples of the N-type impurity include phosphorus (P) and nitrogen (N).

  After the N-type and P-type impurity ions are implanted, when the SiC wafer (forming the semiconductor device of the first embodiment) is heat-treated at a high temperature by a heat treatment apparatus, the implanted ions are electrically activated.

  Subsequently, as shown in FIG. 5, SiN film 5 a (silicon nitride film) is formed on the entire surface of the SiC wafer, that is, on the entire surface of silicon carbide drift layer 2 including base region 3 and source region 4.

  Various methods are conceivable as the method for depositing the SiN film 5a described above. For example, PECVD (Plasma Enhanced Chemical Vapor Deposition) may be used, and LPCVD (Low Pressure Chemical Vapor Deposition) may be used. Further, as a deposition method of the SiN film 5a, a PVD (Physical Vapor Deposition) method such as a sputtering method, an electron beam evaporation method, an MBE (Molecular Beam Epitaxy) method, or an ALD (Atomic Layer Deposition) method may be used.

Subsequently, as shown in FIG. 6, a La ₂ O ₃ film 5b (lanthanum oxide film) is formed on the SiN film 5a. As a result, a stacked structure of the SiN film 5a and the La ₂ O ₃ film 5b is obtained, and this stacked structure becomes a pre-processed stacked structure for obtaining the gate insulating film 5 made of a LaSiON film 5L described later.

Various methods are conceivable as a method for depositing the La ₂ O ₃ film 5b. For example, a MOCVD (Metal Organic Chemical Vapor Deposition) method, an electron beam evaporation method, an MBE method, or an ALD method may be used.

Thereafter, as shown in FIG. 7, the pretreatment laminated structure shown in FIG. 6 is heat-treated in an inert gas atmosphere, and SiN, La ₂ O _3, and SiN film 5a and La ₂ O ₃ film 5b To form a gate insulating film 5 having a single structure of the LaSiON film 5L.

  The heat treatment performed in the inert gas atmosphere described above is performed at 500 ° C. to 1300 ° C., and the heat treatment time is about 1 minute to 3 hours.

By adding 1% to 50% oxygen gas to the inert gas atmosphere, the above-described reaction between SiN and La ₂ O ₃ is promoted.

  FIG. 21 is a graph showing the element ratio with respect to the depth position including the interface between the gate insulating film and the silicon carbide semiconductor layer obtained by X-ray photoelectron spectroscopy after the heat treatment performed in the inert gas atmosphere. In the figure, the element ratio change ER1 indicates the ratio of oxygen atoms (O), the element ratio change ER2 indicates the ratio of silicon atoms (Si), the element ratio change ER3 indicates the ratio of carbon atoms (C), and the element The ratio change ER4 indicates the ratio of lanthanum atoms (La), and the element ratio change ER5 indicates the ratio of nitrogen atoms (N). As shown in the element ratio change ER5 in the same figure, at the interface between the gate insulating film 5 obtained in the present embodiment and the silicon carbide semiconductor layer (silicon carbide drift layer 2 including the base region 3 and the source region 4), It can be seen that nitrogen atoms with an element ratio of 10% are present, and nitrogen atoms are present at a relatively high ratio.

In addition to annealing in the above inert gas atmosphere, heat treatment may be performed in a nitrogen oxide gas atmosphere, and in particular, by performing heat treatment in an atmosphere containing N ₂ O and NO gas, the ratio of nitrogen in LaSiON is increased. be able to.

  Then, as shown in FIG. 8, a gate electrode material is formed on the gate insulating film 5 and then patterned to form the gate electrode 6. Gate electrode 6 is patterned such that the pair of base region 3 and source region 4 are positioned at both ends, and the surface region of silicon carbide drift layer 2 exposed between base regions 3 is positioned at the center. That is, the gate electrode 6 is formed on a region sandwiching the pair of base regions 3 with the gate insulating film 5 interposed therebetween.

  Further, as shown in FIG. 9, the most part of the gate insulating film 5 whose surface is exposed is removed by lithography and etching techniques using the gate electrode 6 as a mask, and the contents of the removal process of the gate insulating film 5 such as etching are as follows. By adjusting, the gate insulating film 5 is patterned so that the end portion extends in the horizontal direction from the gate electrode 6.

  Thereafter, as shown in FIG. 10, after forming an interlayer insulating film (not shown) covering the gate electrode 6, a source electrode material is formed on the entire surface including the source region 4, and then patterned to form the source electrode 4 on the source region 4. The source electrode 7 is selectively formed. At this time, the source electrode 7 is electrically independent of the gate electrode 6 due to the presence of the gate insulating film 5 and the like.

  Finally, the drain electrode 8 is formed on the back surface of the substrate 1 to complete the semiconductor device having the structure shown in FIG. 1 in which an N-type MOSFET is formed.

Compared to the relative dielectric constant “3.9” of SiO _2, the relative dielectric constant of LaSiON is as large as “9” or more, and when the gate insulating film is formed with the same film thickness, LaSiON is the threshold voltage of the MOSFET. Becomes smaller.

  The threshold voltage of the MOSFET can be controlled by the channel length, the gate insulating film (oxide film) thickness, and the dopant concentration in the channel region.

FIG. 11 shows the band structure between the gate electrode 6 and the base region 3 on the substrate 1 in the conventional MOSFET using the SiO ₂ film as the gate insulating film and the MOSFET of the first embodiment using the LaSiON film. It is a graph to show. In the figure, it shows the SiO ₂ energy change L2 in LaSiON energy change L1 and conventional MOSFET of the MOSFET according to the first embodiment. Each MOSFET controls the dopant concentration in the channel region, and the threshold voltage is set to 3V. As shown in the figure, towards the LaSiON energy change L1 is compared with the SiO ₂ energy change L2, energy change of the upper part of the base region 3 (the channel region) is steeper.

FIG. 12 is a graph showing the carrier density of the channel when the gate voltage VG of 15 V is applied to each of the conventional MOSFET and the MOSFET of this embodiment. In the figure, the LaSiON carrier concentration change L11 of the first embodiment and the conventional SiO ₂ carrier concentration change L12 are shown.

By replacing the gate insulating film with the LaSiON film from the conventional SiO ₂ film as in the first embodiment, the total number of carriers obtained as an integration result of each of the LaSiON carrier concentration change L11 and the SiO ₂ carrier concentration change L12 is 5. There is an approximately 2-fold increase from 1 × 10 ²² cm ⁻² to 1.2 × 10 ²³ cm ⁻² . Due to this increase in carriers, a reduction in channel resistance of the MOSFET of the first embodiment can be expected as compared with the conventional MOSFET.

(effect)
The MOSFET in the semiconductor device of the first embodiment manufactured by the manufacturing method shown in FIGS. 2 to 10 forms an interface with the channel region (surface region of base region 3), and contains nitrogen at a high concentration. Since the gate insulating film 5 having a single structure of the LaSiON film 5L is included, the channel region can be set to a lower interface state density than in the case of using a conventional gate insulating film composed of a SiO ₂ film or the like. As a result, the on-resistance value of the MOSFET can be kept low.

Furthermore, the passivation effect of the interface state at the interface with the channel region can be obtained by the nitrogen atoms present at a high ratio in the gate insulating film 5 (= LaSiON film 5L). This eliminates the need for nitriding treatment between the channel region and the gate insulating film 5, which is indispensable when LaSiO _x is used as the gate insulating film 5, and consists of silicon, carbon, and oxygen caused by this nitriding treatment. The phenomenon that the interface layer is generated at the interface with the channel region can be avoided, and the effect of ensuring high channel mobility in the MOSFET is achieved.

  Therefore, the semiconductor device of the first embodiment can exhibit an energy saving effect by reducing the on-resistance value and increasing the channel mobility in the MOSFET.

In addition, the semiconductor device of the first embodiment can suppress an excessive oxidation reaction when the LaSiO _x film is used as the gate insulating film by configuring the gate insulating film 5 with the LaSiON film 5L. As a result of the stabilization of the LaSiON composition ratio in the entire gate insulating film 5, the reliability of the device is improved.

In the first embodiment, the single-structure gate insulating film 5 made of the LaSiON film 5L can reliably avoid the adverse effect of using the SiO ₂ film or the LaSiO _x film as the gate insulating film.

Further, by the steps shown in FIG. 5 and FIG. 6, the pre-processed laminated structure is composed of the SiN film 5a and the La ₂ O ₃ film 5b, and a laminated structure containing silicon, nitrogen, oxygen and lanthanum components is formed. The gate insulating film 5 made of the LaSiON film 5L can be formed by a relatively simple manufacturing method in which the process shown in FIG. 7 is performed on the laminated structure.

In the first embodiment, the process of obtaining the pretreatment laminated structure by laminating the SiN film 5a and the La ₂ O ₃ film 5b in this order is shown. Conversely, the La ₂ O ₃ film and the SiN film are laminated in this order. A pre-processed laminated structure may be obtained.

<Embodiment 2>
(Device structure)
In contrast to the (silicon carbide) semiconductor device of the first embodiment, the (silicon carbide) semiconductor device of the second embodiment replaces the gate insulating film 5 having a single structure of the LaSiON film 5L with a LaSiON film 13 and a SiO2 film. _The difference is that a gate insulating film 15 having a laminated structure of _two films 14 is provided. The semiconductor device of the second embodiment has the same structure as the semiconductor device of the first embodiment shown in FIG. 1 except that the gate insulating film 5 is replaced with the gate insulating film 15.

(Production method)
FIG. 13 is a cross-sectional view showing a part of the method for manufacturing the semiconductor device of the second embodiment. Hereinafter, the manufacturing method of Embodiment 2 is demonstrated. The manufacturing method of the semiconductor device of the second embodiment is the same as the manufacturing method of the first embodiment shown in FIGS. 2 to 7 until the step of obtaining the LaSiON film 13. However, the gate insulating film 5 (= LaSiON film 5L) shown in FIG.

Thereafter, as shown in FIG. 13, a SiO ₂ film 14 is deposited on the LaSiON film 13. As a result, the gate insulating film 15 having a laminated structure of the LaSiON film 13 and the SiO ₂ film 14 can be obtained.

  The subsequent processing is performed in the same manner as the manufacturing method of the first embodiment shown in FIGS.

(Suppression of charge trap function)
When the SiO ₂ film 14 is deposited on the LaSiON film 13, the gate voltage used for driving the MOSFET, which is an insulated gate transistor, is applied to the entire gate insulating film 15. Therefore, the LaSiON film 13 has a film thickness of the SiO ₂ film 14. It may be thinner than the film thickness. In order to form a thin LaSiON film 13, a SiN film (silicon nitride film) and a La ₂ O ₃ film (SiN film 5a and La ₂ O ₃ film 5b in FIGS. It is effective to reduce the deposited film thickness, and the heat treatment temperature during the reaction is preferably about 1000 ° C.

FIG. 14 shows the amount of charge trapped in the deposited film with respect to the thickness of the SiN film (corresponding to the SiN film 5a in FIGS. ^-2 )). FIG. 14 shows a case where the thickness of the La ₂ O ₃ film deposited on the SiN film is 10 nm.

As shown in the figure, the charge trapped in the vicinity of 2.7 nm by the SiN film becomes zero. That is, in the thickness of the SiN film (about 2.7 nm), SiN in the SiN film is consumed by reaction with _La 2 _{O 3} of _La 2 _{O 3} film, a channel region (a surface of the base region 3) It can be seen that the SiC / LaSiON interface is accurately formed at the interface with the gate insulating film 5.

On the other hand, when SiN reacts with La ₂ O ₃ and SiN remains without reacting, the SiC / LaSiON interface is not formed with high accuracy, and a laminated structure of SiC / SiN / LaSiON is formed. In this case, the remaining SiN film sandwiched between SiC and La ₂ O ₃ serves as a charge trap film, which functions undesirably.

  Therefore, as in the second embodiment, when a thin LaSiON film is formed by heat treatment at about 1000 ° C., the thickness of the SiN film deposited on the silicon carbide drift layer 2 including the base region 3 and the source region 4 The thickness is preferably 1 nm or more and 10 nm or less, particularly 3 nm or less. Note that the consideration regarding the SiN film shown in FIG. 14 also applies to the first embodiment.

In the second embodiment, a laminated structure of a LaSiON film 13 and a SiO ₂ film 14 is realized as the gate insulating film 15. In such a laminated structure, the LaSiON / SiO ₂ interface which is an interface between the LaSiON film 13 and the SiO ₂ film 14 also has a charge trap function depending on the applied voltage.

  15 and 16 are graphs showing a band structure immediately below the gate electrode 6 when the MOSFET is off and on. In these drawings, the horizontal axis indicates the depth position (Position (nm)), and the vertical axis indicates the energy (Potential (eV)).

As shown in FIG. 15, the potentials V _SiO2 (off) and V _LaSiON (off) applied to the SiO ₂ film 14 and the LaSiON film 13 when the MOSFET in a state where no voltage is applied to the gate (gate voltage VG = 0) are off are as follows. Small and evenly applied to the entire thickness of the gate insulating film 15.

On the other hand, as shown in FIG. 16, when the gate voltage VG (= gate potential variation ΔVG) is applied from 0 V and the MOSFET is turned on, the potential applied to the SiO ₂ film 14 and the LaSiON film 13 is V _SiO2 (on ) And V _LaSiON (on). When V _LaSiON (on) becomes larger than the SiC / LaSiON energy barrier height ΔEc, charge is trapped at the LaSiON / SiO ₂ interface.

  When the charge is trapped, the threshold voltage of the MOSFET changes, and the characteristics of the MOSFET change. Therefore, it is ideal that no charge is trapped in the gate insulating film 15, and in order to realize this ideal, it is desirable that the film thickness of the LaSiON film satisfies the following formula (1).

In formula (1), t _LaSiON and t _SiO2 mean the film thickness of the LaSiON film 13 and the SiO ₂ film 14, and ΔV _SiC and ΔVG are in the SiC substrate (base region 3) when the MOSFET is off to on. Ε _LaSiON and ε _SiO2 are relative dielectric constants of the LaSiON film 13 and the SiO ₂ film 14. When the gate voltage VG at the off time is 0V, the gate voltage change amount ΔVG is equal to the gate voltage VG at the on time.

Hereinafter, the derivation principle of Equation (1) will be described. The gate voltage displacement amount ΔVG in equation (1) satisfies the following equation (2). In the equation (2), ΔV _LaSiON and ΔV _SiO2 indicate the amount of change in the potentials V _LaSiON and V _SiO2 when the MOSFET is off (off) to on (on).

Further, ε _LaSiON , ε _SiO2 , t _LaSiON and t _SiO2 in the formula (1), and ΔV _LaSiON and ΔV _SiO2 in the formula (2) satisfy the following formula (3), and the gate insulating film of the gate insulating film 15 The thickness t15 satisfies the following formula (4).

Therefore, in order to satisfy the following formula (5), which is a condition where charge trapping is not performed, the film thicknesses t _LaSiON and t _SiO2 of the LaSiON film 13 and the SiO ₂ film 14 in the semiconductor device of the second embodiment are expressed by the above formula ( It must be formed to satisfy 1).

(effect)
In the semiconductor device of the second embodiment, the gate insulating film 15 having the LaSiON film 13 is formed at the interface of the channel region, thereby producing the same effects as the semiconductor device of the first embodiment and the effects described below.

The semiconductor device of the second embodiment, in addition to the LaSiON layer 13, by forming the gate insulating film 15 of the laminated structure further comprising a SiO ₂ film 14, possible to reduce the leakage current in the MOSFET by SiO ₂ film 14 Can do.

In addition, since the thickness _{t LaSiON} and _{t SiO2} of LaSiON film 13 and the SiO ₂ film 14 constituting the gate insulating film 15, which is set to satisfy the equation (1) above, LaSiON film 13 and SiO ₂ be implemented with a gate insulating film 15 of a laminated structure of the membrane 14, it is possible to reliably avoid a phenomenon that the interface between LaSiON film 13 and the SiO ₂ film 14 thus exerts a charge trapping function.

<Embodiment 3>
The (silicon carbide) semiconductor device of the third embodiment has the same substantial structure as the (silicon carbide) semiconductor device of the first embodiment, and a method of forming a LaSiON film to be a gate insulating film in the manufacturing method Is different.

(Production method)
17 and 18 are cross-sectional views showing a part of the method for manufacturing the semiconductor device in the third embodiment. Hereinafter, the manufacturing method of Embodiment 3 is demonstrated. The manufacturing method of the semiconductor device of the third embodiment is the same as that shown in FIGS. 2 to 6 until the step of obtaining the SiN film 5a (first silicon nitride film) and the La ₂ O ₃ film 5b (lanthanum oxide film). This is the same as the manufacturing method of Form 1.

Thereafter, as shown in FIG. 17, a SiN film 5c (second silicon nitride film) is further deposited on the La ₂ O ₃ film 5b. As a result, a stacked structure of the SiN film 5a, the La ₂ O ₃ film 5b, and the SiN film 5c is obtained, and this stacked structure is used to obtain the gate insulating film 25 of the third embodiment. It becomes the pre-processing laminated structure containing.

Thereafter, as shown in FIG. 18, the pretreatment laminated structure shown in FIG. 17 is heat-treated in an inert gas atmosphere, and between the SiN film 5a and the La ₂ O ₃ film 5b, and between the La ₂ O ₃ film 5b and the SiN. By reacting SiN and La ₂ O ₃ between the films 5c, the gate insulating film 25 constituted by a single structure of the LaSiON film 25L is formed.

At this time, since the reaction accompanying the heat treatment proceeds from both sides of the La ₂ O ₃ film 5b, the thickness of the LaSiON film 25L obtained at the same reaction temperature is compared with the heat treatment for the pretreatment laminated structure in the first embodiment. It can be made thicker than the LaSiON film 5L of the first embodiment.

Further, when the gate insulating film 25 is formed by the heat treatment for the pretreatment laminated structure, the SiN film 5c is also present on the upper side (outside) with respect to the La ₂ O ₃ film 5b. For this reason, the diffusion energy of oxygen in the gate insulating film material is 1.24 eV for SiO ₂ , 0.51 eV to 0.80 eV for LaSiO _x , and 3.67 eV for SiN, so the SiN film 5 c is on the outer side. By being present (upward), oxidation of SiC can be suppressed when La ₂ O ₃ and SiN react. The subsequent processing is performed in the same manner as the manufacturing method of the first embodiment shown in FIGS.

(effect)
Since the semiconductor device of the third embodiment has a structure substantially equivalent to that of the semiconductor device of the first embodiment, the same effect as that of the first embodiment is obtained. Furthermore, the following effects are produced by the manufacturing method unique to the third embodiment.

During the execution of the heat treatment in the step shown in FIG. 18, the SiN film 5a and the SiN film 5c _{for La} 2 _{O 3} film 5b is sandwiched, the SiN film 5a and _La 2 _{O 3} film 5b as in the first embodiment A LaSiON film 25L having a thick film thickness can be obtained as compared with the case of a two-layer structure.

In addition, since the SiN film 5c is formed on the upper side with respect to the La ₂ O ₃ film 5b at the time of performing the heat treatment in the process shown in FIG. 18, the diffusion of oxygen is effectively suppressed by the upper SiN film 5c. This can suppress the oxidation of SiC in the silicon carbide drift layer 2 including the base region 3 and the source region 4 when the SiN film 5a and the SiN film 5c react with the La ₂ O ₃ film 5b.

  As a result, a semiconductor device having a more reliable MOSFET can be obtained by the method for manufacturing a semiconductor device in the third embodiment.

In the method of manufacturing the semiconductor device according to the third embodiment, the gate insulating film 25 (= LaSiON film 25L) is obtained by heat treatment on the preprocessed laminated structure including the SiN film 5a, the La ₂ O ₃ film 5b, and the SiN film 5c. Although the process is shown, it is of course possible to form the LaSiON film 13 of the second embodiment using this process.

<Embodiment 4>
The (silicon carbide) semiconductor device of the fourth embodiment has the same substantial structure as the (silicon carbide) semiconductor device of the first embodiment, and a method of forming a LaSiON film to be a gate insulating film in the manufacturing method Is different.

(Production method)
19 and 20 are cross-sectional views showing a part of the method for manufacturing the semiconductor device in the fourth embodiment. Hereinafter, the manufacturing method of Embodiment 4 is demonstrated. The manufacturing method of the semiconductor device of the fourth embodiment is the same as the manufacturing method of the first embodiment shown in FIGS. 2 to 4 until the step of obtaining the source region 4.

Thereafter, as shown in FIG. 19, SiO ₂ film 35 a is formed on the entire surface of silicon carbide drift layer 2 including base region 3 and source region 4. Further, a La film 35b (lanthanum film) is formed on the SiO ₂ film 35a, and finally a SiN film 35c (silicon nitride film) is formed on the La film 35b. As a result, a laminated structure of SiO ₂ film 35a, La film 35b and SiN film 35c is obtained, and this laminated structure contains silicon, nitrogen, oxygen and lanthanum components for obtaining the gate insulating film 35 of the fourth embodiment. It becomes a pre-processing laminated structure.

Thereafter, as shown in FIG. 20, a heat treatment in an inert gas atmosphere with respect to pretreatment layered structure shown in FIG. 19, SiO ₂ film 35a, between La film 35b and the SiN film 35c, SiO ₂ and La By reacting with SiN, the gate insulating film 35 constituted by a single structure of the LaSiON film 35L is formed.

The subsequent processing is performed in the same manner as the manufacturing method of the first embodiment shown in FIGS. Further, the deposition order between the SiO ₂ film 35a, the La film 35b, and the SiN film 35c for obtaining the pretreatment laminated structure is arbitrary. However, when considering oxidation by oxygen diffusing from the outside, it is desirable that the SiN film 35c be present on the outermost side (uppermost portion) as shown in FIG.

(effect)
Since the semiconductor device according to the fourth embodiment has a structure substantially equivalent to that of the semiconductor device according to the first embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, the following effects are produced by the manufacturing method unique to the third embodiment.

In the method of manufacturing the semiconductor device according to the fourth embodiment, in the step of obtaining the pre-processed stacked structure shown in FIG. 19, the SiO ₂ film 35a, La film 35b, and SiN film 35c each having a relatively simple chemical structure are used. A processed laminated structure can be obtained.

In the method of manufacturing the semiconductor device according to the fourth embodiment, the step of obtaining the gate insulating film 35 (= LaSiON film 35L) by the heat treatment for the preprocessed laminated structure including the SiO ₂ film 35a, the La film 35b, and the SiN film 35c. Although shown, it is of course possible to form the LaSiON film 13 of the second embodiment using this process.

<Others>
It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  In the present invention, insulation of MOSFETs, IGBTs, etc., which is conventionally formed on a silicon carbide substrate (semiconductor layer) such as silicon carbide drift layer 2 and has conventionally been configured with a silicon dioxide film as a gate insulating film. The present invention can be applied to a semiconductor element having a gate type transistor structure. According to the present invention, it is possible to realize a semiconductor device using silicon carbide as a constituent material with low channel resistance and high insulation film reliability.

1 substrate, 2 silicon carbide drift layer, 3 base region, 4 source region, 5, 15, 25, 35 gate insulating film, 5a, 5c, 35c SiN film, 5b La ₂ O ₃ film, 5L, 13, 25L, 35L LaSiON film, 6 gate electrode, 7 source electrode, 8 drain electrode, 14, 35a SiO ₂ film, 35b La film.

Claims (11)

A semiconductor layer composed of silicon carbide;
A gate insulating film formed on the semiconductor layer;
An insulated gate transistor comprising a gate electrode formed on the gate insulating film, wherein a surface of the semiconductor layer under the gate electrode via the gate insulating film serves as a channel region,
The gate insulating film has a lanthanum silicon oxynitride film that forms an interface with the channel region,
Semiconductor device. The semiconductor device according to claim 1,
The gate insulating film has a single structure of the lanthanum silicon oxynitride film,
Semiconductor device. The semiconductor device according to claim 1,
The gate insulating film includes a stacked structure of the lanthanum silicon oxynitride film and a silicon oxide film,
Semiconductor device. The semiconductor device according to claim 3,
The film thickness and relative dielectric constant of the lanthanum silicon oxynitride film are t _LaSiON and ε _LaSiON , the film thickness and relative dielectric constant of the silicon oxide film are t _SiO2 and ε _SiO2, and the silicon lanthanum oxynitride film and the channel region The silicon lanthanum oxynitride film when the energy barrier height at the interface with ΔEc is ΔEc and the potential change amount and gate voltage change amount of the semiconductor layer when the insulated gate transistor is turned on and off are ΔV _SIC and ΔVG And the thickness of the silicon oxide film is set so as to satisfy the following formula (1):

Semiconductor device. (a) forming a semiconductor layer composed of silicon carbide on one main surface of the semiconductor substrate;
(b) forming a gate insulating film on the semiconductor layer;
(c) forming a gate electrode on the gate insulating film, and an insulated gate transistor in which a surface of the semiconductor layer under the gate electrode via the gate insulating film serves as a channel region is configured,
Step (b)
(b-1) forming a pretreatment laminated structure containing silicon, nitrogen, oxygen and lanthanum components on the semiconductor layer;
(b-2) performing a heat treatment on the pre-processed laminated structure and forming a silicon lanthanum oxynitride film that forms an interface with the channel region, wherein the gate insulating film is the silicon lanthanum oxynitride Having a membrane,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
The pretreatment laminated structure formed by the step (b-1) includes a laminated structure of a silicon nitride film and a lanthanum oxide film,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
The pretreatment laminated structure formed by the step (b-1) includes a laminated structure in which a first silicon nitride film, a lanthanum oxide film, and a second silicon nitride film are laminated in this order.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 5,
The pretreatment laminated structure formed by the step (b-1) includes a laminated structure of a silicon oxide film, a lanthanum film, and a silicon nitride film.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 5 to 8,
The gate insulating film has a single structure of the lanthanum silicon oxynitride film,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 5 to 8,
Step (b)
(b-3) further comprising the step of forming a silicon oxide film on the lanthanum oxynitride film, which is executed after the step (b-2),
The gate insulating film includes a laminated structure of the silicon lanthanum oxynitride film and the silicon oxide film,
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 10, comprising:
The film thickness and relative dielectric constant of the lanthanum silicon oxynitride film are t _LaSiON and ε _LaSiON , the film thickness and relative dielectric constant of the silicon oxide film are t _SiO2 and ε _SiO2, and the silicon lanthanum oxynitride film and the channel region The silicon lanthanum oxynitride film when the energy barrier height at the interface with ΔEc is ΔEc and the potential change amount and gate voltage change amount of the semiconductor layer when the insulated gate transistor is turned on and off are ΔV _SIC and ΔVG And the step (b) is performed so that the thickness of the silicon oxide film satisfies the following formula (1):

A method for manufacturing a semiconductor device.

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