JP2016046459A - Field-effect transistor and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor with a high heat dissipation property.SOLUTION: A field-effect transistor 2 comprises: a composite substrate 1 of high heat conduction arranged by bonding a support base 11 of high heat conduction with a thermal conductivity of 1.5 W cmKor more, and a Group III nitride film 13 to each other; a first Group III nitride layer 21 disposed on the Group III nitride film 13 of the composite substrate 1 of high heat conduction, and having the same chemical composition as that of the Group III nitride film 13; a second Group III nitride layer 22 disposed on the first Group III nitride layer 21 and having a chemical composition different from that of the first Group III nitride layer 21; and a source electrode 30s, a gate electrode 30g and a drain electrode 30d which are disposed on the second Group III nitride layer 22.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a field effect transistor with high heat dissipation and a method for manufacturing the same.

  A switching element for large current is required to have a high reverse breakdown voltage and a low on-resistance. A field effect transistor using a material having a large band gap energy such as a group III nitride semiconductor is excellent in terms of high breakdown voltage, high temperature operation, and the like, and thus has attracted attention as a control transistor for high power.

For example, Japanese Patent Application Laid-Open No. 2012-243792 (Patent Document 1) includes, as a field effect transistor, a different composition substrate having a different chemical composition from GaN and a GaN thin film bonded on the different composition substrate. High performance with reduced buffer leakage current and gate leakage current because the thickness is 0.1 μm or more and 100 μm or less and the hydrogen sheet concentration is 1 × 10 ¹⁴ cm ⁻² or more and 3 × 10 ¹⁷ cm ⁻² or less. HEMTs (High Electron Mobility Transistors) are disclosed.

JP 2012-243792 A

In the HEMT disclosed in JP2012-243792A (Patent Document 1), for example, a sapphire substrate is used as a different composition substrate, and the sapphire substrate has a thermal conductivity of 0.5 W · cm ⁻¹ · K ^{−. Since} the heat dissipation of the HEMT is low because it is as low as about ^1, there is a problem that high output operation is unlikely.

  Therefore, an object is to provide a field-effect transistor with high heat dissipation by using a high thermal conductive support substrate as a support substrate.

A field effect transistor according to an aspect of the present invention is a high thermal conductive composite in which a high thermal conductive support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together. A first group III nitride layer disposed on the group III nitride film of the high thermal conductivity composite substrate and having the same chemical composition as the group III nitride film, and the first group III nitride layer; A second group III nitride layer having a chemical composition different from that of the first group III nitride layer, a source electrode, a gate electrode, and a drain electrode disposed on the second group III nitride layer; including.

In a method of manufacturing a field effect transistor according to another aspect of the present invention, a high thermal conductive support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together. Preparing a high thermal conductive composite substrate, forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the high thermal conductive composite substrate, Forming a second group III nitride layer having a chemical composition different from that of the first group III nitride layer on the group III nitride layer, and a source electrode on the second group III nitride layer Forming a gate electrode and a drain electrode.

In a method for manufacturing a field effect transistor according to still another aspect of the present invention, a low thermal conductive support substrate having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ is bonded to a group III nitride film. Preparing a low heat conductive composite substrate, forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the low heat conductive composite substrate, Forming a second group III nitride layer having a chemical composition different from that of the first group III nitride layer on the first group III nitride layer, and forming a source on the second group III nitride layer. A step of forming an electrode, a gate electrode, and a drain electrode, a step of removing the low thermal conductive support substrate from the group III nitride film, and a heat of 1.5 W · cm ⁻¹ · K ⁻¹ or more on the group III nitride film A process of bonding a high thermal conductivity supporting substrate having conductivity , Including the.

  According to the above, a field effect transistor with high heat dissipation can be provided by using a high thermal conductive support substrate as the support substrate.

It is a schematic sectional drawing which shows a certain example of the field effect transistor concerning a certain aspect of this invention. It is a schematic sectional drawing which shows a certain example of the manufacturing method of the field effect transistor concerning another aspect of this invention. It is a schematic sectional drawing which shows a certain example of the manufacturing method of the field effect transistor concerning another aspect of this invention. It is a schematic sectional drawing which shows an example with the process of preparing a high heat conductive composite board | substrate in the manufacturing method of the field effect transistor concerning another aspect of this invention.

<Description of Embodiment of the Present Invention>
A field effect transistor according to an embodiment of the present invention has a high thermal conductivity in which a high thermal conductivity supporting substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together. On the composite substrate, a first group III nitride layer disposed on the group III nitride film of the high thermal conductivity composite substrate and having the same chemical composition as the group III nitride film, and on the first group III nitride layer A second Group III nitride layer disposed and having a different chemical composition than the first Group III nitride layer; and a source electrode, a gate electrode, and a drain electrode disposed on the second Group III nitride layer; ,including.

The field effect transistor of the present embodiment includes a high thermal conductive support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more, and thus has high heat dissipation and high output. .

  In the field effect transistor of this embodiment, the group III nitride film can be a GaN film, and the first group III nitride layer can be a GaN layer. Such a field effect transistor has high output characteristics due to the wide band gap of GaN.

  In the field effect transistor of the present embodiment, the high thermal conductivity support substrate may have a linear thermal expansion coefficient of a ratio of 0.8 to 1.2 in relation to the linear thermal expansion coefficient of the group III nitride film. Since such a field effect transistor includes a high quality first group III nitride layer and a high quality second group III nitride layer, high output is obtained.

  In the field effect transistor of this embodiment, the high thermal conductivity support substrate can include at least one crystal selected from the group consisting of AlN crystals and SiC crystals. Such a field effect transistor has high heat dissipation and high output because the high thermal conductivity support substrate has high thermal conductivity.

In a method of manufacturing a field effect transistor according to another embodiment of the present invention, a high thermal conductive support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together. Preparing a high thermal conductive composite substrate, forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the high thermal conductive composite substrate, Forming a second group III nitride layer having a chemical composition different from that of the first group III nitride layer on the first group III nitride layer, and forming a source on the second group III nitride layer. Forming an electrode, a gate electrode, and a drain electrode.

The manufacturing method of the field effect transistor of this embodiment has high heat dissipation and high output by using a high thermal conductivity supporting substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more. The resulting field effect transistor is obtained.

  In the method for manufacturing a field effect transistor according to the present embodiment, the high thermal conductivity support substrate may have a linear thermal expansion coefficient of a ratio of 0.8 to 1.2 with respect to the linear thermal expansion coefficient of the group III nitride film. . Thus, a field effect transistor including a high quality first group III nitride layer and a high quality second group III nitride layer and having a high output is obtained.

According to still another embodiment of the present invention, there is provided a method of manufacturing a field effect transistor, in which a low thermal conductive support substrate having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ and a group III nitride film are bonded. Preparing a combined low thermal conductive composite substrate; forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the low thermal conductive composite substrate; Forming a second group III nitride layer having a different chemical composition from the first group III nitride layer on the first group III nitride layer; on the second group III nitride layer; A step of forming a source electrode, a gate electrode, and a drain electrode; a step of removing the low thermal conductive support substrate from the group III nitride film; and a group III nitride film of 1.5 W · cm ⁻¹ · K ⁻¹ or more Bonding high thermal conductivity supporting substrate with thermal conductivity Including the extent, the.

In the manufacturing process of the field effect transistor according to the present embodiment, a group III nitride film is used instead of a low thermal conductivity supporting substrate having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ in the manufacturing process. By disposing a high thermal conductive support substrate having a thermal conductivity of 5 W · cm ⁻¹ · K ⁻¹ or more, a field effect transistor having high heat dissipation and high output can be obtained.

  In the method for manufacturing a field effect transistor according to the present embodiment, the low thermal conductive support substrate may have a linear thermal expansion coefficient of a ratio of 0.8 to 1.2 with respect to the linear thermal expansion coefficient of the group III nitride film. . Thus, a field effect transistor including a high quality first group III nitride layer and a high quality second group III nitride layer and having a high output is obtained.

<Details of Embodiment of the Present Invention>
[Embodiment 1: Field Effect Transistor]
Referring to FIG. 1, the field effect transistor 2 of the present embodiment includes a high thermal conductivity support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film 13. The high heat conductive composite substrate 1 bonded together, and a first group III nitride layer 21 disposed on the group III nitride film 13 of the high heat conductive composite substrate 1 and having the same chemical composition as the group III nitride film 13; A second group III nitride layer 22 disposed on the first group III nitride layer 21 and having a different chemical composition from the first group III nitride layer 21; and a second group III nitride layer 22 A source electrode 30s, a gate electrode 30g, and a drain electrode 30d disposed on the upper side.

Since the field effect transistor 2 of the present embodiment includes the high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more, the field effect transistor 2 has high heat dissipation and high output. can get.

(High thermal conductive composite substrate)
The high thermal conductive composite substrate 1 is obtained by bonding a high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film 13.

From the viewpoint of increasing the output of the field effect transistor 2 by increasing the heat dissipation of the field effect transistor 2, the high thermal conductivity support substrate 11 has a thermal conductivity of 1.5 W · cm ⁻¹ · K is ^{-1 or} more, preferably 1.8 W · cm ^-1 · K ^-1 or more, 3.0 W · cm ^-1 · K ^-1 or more is more preferable.

From the viewpoint of increasing the output of the field effect transistor 2 by increasing the quality of the first group III nitride layer 21 and the second group III nitride layer 22 of the field effect transistor 2, the high thermal conductivity support substrate 11 is The ratio of the linear thermal expansion coefficient of the high thermal conductive support substrate 11 to the linear thermal expansion coefficient of the group III nitride film 13 is preferably 0.8 or more and 1.2 or less, and more preferably 0.9 or more and 1.1 or less. Here, the directions of the linear thermal expansion coefficients of the high thermal conductivity support substrate 11 and the group III nitride film 13 to be compared are both parallel to their main surfaces. The high thermal conductivity support substrate 11 has its thermal conductivity. From the viewpoint of increasing the heat dissipation and output of the field effect transistor 2 by increasing the power, it is preferable to include at least one crystal selected from the group consisting of an AlN crystal and a SiC crystal. Specifically, the high thermal conductive support substrate 11 is preferably an AlN single crystal substrate, an SiC single crystal substrate, an AlN polycrystalline substrate, an SiC polycrystalline substrate, or the like.

  The group III nitride film 13 is not particularly limited, but is preferably a GaN film from the viewpoint of a large band gap and high crystallinity. The thickness of the group III nitride film 13 is preferably 0.1 μm or more, and preferably 1 μm or more from the viewpoint of improving the quality of the first group III nitride layer 21 and the second group III nitride layer 22. More preferably, from the viewpoint of reducing the cost of the field effect transistor, it is preferably 5 μm or less, and more preferably 2 μm or less.

The high thermal conductive composite substrate 1 includes a bonding film 12 interposed between the high thermal conductive support substrate 11 and the group III nitride film 13 from the viewpoint of increasing the bonding strength between the high thermal conductivity support substrate 11 and the group III nitride film 13. It is preferable to include. The bonding film 12 is preferably a SiO ₂ film, a SiN _x film, or the like from the viewpoint of increasing the bonding strength between the high thermal conductive support substrate 11 and the group III nitride film 13.

(First group III nitride layer)
The first group III nitride layer 21 is disposed on the group III nitride film 13 of the high thermal conductive composite substrate 1, and from the viewpoint of improving the quality of the first group III nitride layer 21, the group III nitride film 13. Have the same chemical composition. Here, from the viewpoint of matching the crystal lattice, the group III nitride film 13 is preferably a GaN film, and the first group III nitride layer 21 is preferably a GaN layer.

(Second group III nitride layer)
The second group III nitride layer 22 is disposed on the first group III nitride layer 21, and from the viewpoint of causing band discontinuity by bringing two semiconductor layers having different band gaps into contact with each other, The group III nitride layer 21 has a different chemical composition. For example, when the first group III nitride layer 21 is a GaN layer, the second group III nitride layer 22 is an Al _1-x Ga _x N layer (0 ≦ 0) from the viewpoint of generating piezoelectric charges by spontaneous polarization. x <1).

(Source electrode, gate electrode, drain electrode)
The source electrode 30s, the gate electrode 30g, and the drain electrode 30d are disposed on the second group III nitride layer 22, whereby the field effect transistor 2 is formed. These electrodes are not particularly limited as long as they exhibit the functions of these electrodes. As the source electrode 30s and the drain electrode 30d, an Al layer / Ti layer / Au layer alloyed, etc. may be used as the gate electrode. Preferred examples include Ni layer and Au layer.

In such a field effect transistor 2, for example, the first group III nitride layer 21 is a GaN layer, and the second group III nitride layer 22 is an Al _1-x Ga _x N layer (0 ≦ x < 1), the second group III nitride layer 22 has a lower band energy than the first group III nitride layer 21, and the electrons generated from the first group III nitride layer 21 A two-dimensional electron gas is formed in the group III nitride layer 22 and distributed in a region having a thickness of about 10 nm in the vicinity of the interface between the second group III nitride layer 22 and the first group III nitride layer 21; It is called HEMT (High Electron Mobility Transistor).

[Embodiment 2: Method for Manufacturing Field Effect Transistor]
{Embodiment 2-1}
Referring to FIG. 2, a manufacturing method of the field effect transistor 2 of the present embodiment includes a high thermal conductivity supporting substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride. The step of preparing the high thermal conductive composite substrate 1 bonded with the film 13 (FIG. 2A), and the same chemical composition as the group III nitride film 13 on the group III nitride film 13 of the high thermal conductive composite substrate 1 And forming a first group III nitride layer 21 having a chemical composition different from that of the first group III nitride layer 21 on the first group III nitride layer 21 (FIG. 2B). Forming the second group III nitride layer 22 (FIG. 2B), and forming the source electrode 30s, the gate electrode 30g, and the drain electrode 30d on the second group III nitride layer 22. And a process (FIG. 2C).

The manufacturing method of the field effect transistor 2 has high heat dissipation and high output by using the high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more. Thus, the obtained field effect transistor 2 is obtained.

(Process for preparing a high thermal conductive composite substrate)
First, referring to FIG. 2A and FIG. 4, the step of preparing the high thermal conductive composite substrate 1 is not particularly limited, but from the viewpoint of efficiently preparing the high thermal conductive composite substrate 1, the high thermal conductive support substrate 11. A sub-process for forming the bonding film 12a on the main surface of the substrate (FIG. 4A), forming the bonding film 12b on the main surface of the group III nitride film donor substrate 13D, and a group III nitride film donor substrate A sub-process (FIG. 4B) for forming an ion implantation region 13i at a predetermined depth from the main surface of 13D, a bonding film 12a formed on the high thermal conductivity support substrate 11, and a group III nitride film donor The sub-process (FIG. 4C) for forming the bonding substrate 1L by bonding the bonding film 12b formed on the substrate 13D together with the group III nitride film donor substrate 13D of the bonding substrate 1L in the ion implantation region 13i. Separation The Rukoto, including a substep of forming a composite substrate (FIG. 4 (D)) by removing the III nitride film donor substrate 13Dr otherwise leaving group III nitride film 13.

The bonding films 12a and 12b are formed by sputtering, CVD (Chemical Vapor Deposition), PLD (Pulse Laser Deposition), MBE (MBE) from the viewpoint of efficiently forming high-quality bonding films 12a and 12b. Molecular beam growth) and electron beam evaporation are preferred.
The formation of the ion implantation region 13i at a predetermined depth from the main surface of the group II nitride film donor substrate 13D is based on the side of the bonding film 12b formed on the main surface of the group III nitride film donor substrate 13D. Ion I is implanted from The ions I to be implanted are preferably ions having a small mass, for example, hydrogen ions, helium ions, etc., from the viewpoint of suppressing the deterioration of the crystal quality of the group III nitride film 13 to be ion implanted. The predetermined depth into which the ions I are implanted is preferably 0.001 μm to 1 μm, and more preferably 0.01 μm to 0.5 μm.

  The method of bonding the bonding film 12a formed on the high thermal conductive support substrate 11 and the bonding film 12b formed on the group III nitride film donor substrate 13D is not particularly limited, and the bonded surface is washed and bonded as it is. After that, a direct bonding method in which the temperature is raised to about 600 ° C. to 1200 ° C. and the surface is bonded, and the bonded surface is cleaned and activated with plasma or ions and then bonded at a low temperature of room temperature (for example, 25 ° C.) to about 400 ° C. The chemical method and the like are preferable. By the bonding, the bonding film 12a and the bonding film 12b are integrated by bonding to form the bonding film 12, and the high thermal conductive support substrate 11 and the group III nitride film donor substrate 13D are bonded with the bonding film 12 interposed therebetween. Thus, the bonded substrate 1L is formed.

  The method for separating the group III nitride film donor substrate 13D of the bonding substrate 1L in the ion implantation region 13i is not particularly limited as long as it is a method for applying some energy to the ion implantation region 13i of the group III nitride film donor substrate 13D. At least one of a method of applying stress to the ion implantation region 13i, a method of applying heat, a method of irradiating light, and a method of applying ultrasonic waves are possible. Since the ion-implanted region 13i is embrittled by the implanted ions, the group III nitride film donor substrate 13D is bonded onto the bonding film 12 on the high thermal conductivity supporting substrate 11 by receiving the energy described above. The group III nitride film 13 and the other group III nitride film donor substrate 13Dr are separated. The group III nitride film donor substrate 13Dr other than the group III nitride film 13 can be repeatedly used by polishing its main surface.

In this way, a high thermal conductive composite in which the high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and the group III nitride film 13 are bonded together with the bonding film 12 interposed therebetween. A substrate 1 is obtained.

  The high thermal conductive support substrate 11 used in the step of preparing the high thermal conductive composite substrate 1 includes a first group III nitride layer 21 and a second group III nitride that have low warpage and high crystal quality on the group III nitride film 13. From the viewpoint of growing the physical layer 22, the ratio of the linear thermal expansion coefficient of the high thermal conductive support substrate 11 to the linear thermal expansion coefficient of the group III nitride film 13 is preferably 0.8 or more and 1.2 or less, and 0.9 or more. 1.1 or less is more preferable. From such a viewpoint, the high thermal conductive support substrate 11 is preferably an AlN polycrystalline substrate, an SiC polycrystalline substrate, or the like.

(Step of forming the first group III nitride layer)
Next, referring to FIG. 2B, in the step of forming the first group III nitride layer 21, from the viewpoint of aligning the crystal lattice on the group III nitride film 13 of the high thermal conductive composite substrate 1. The first group III nitride layer 21 having the same chemical composition as the group III nitride film 13 is formed. The method for forming the first group III nitride layer 21 is not particularly limited, but from the viewpoint of growing the first group III nitride layer 21 with high crystal quality, an MOCVD (metal organic vapor deposition) method, MBE (molecular beam growth) method, HVPE (hydride vapor phase growth) method, vapor phase method such as sublimation method, liquid phase method such as high nitrogen pressure solution method and flux method are preferable.

(Step of forming the second group III nitride layer)
Next, referring to FIG. 2B, in the step of forming second group III nitride layer 22, two semiconductor layers having different band gaps are contacted on first group III nitride layer 21. From this point of view, a second group III nitride layer 22 having a chemical composition different from that of the first group III nitride layer 21 is formed from the viewpoint of causing band discontinuity. The method for forming the second group III nitride layer 22 is not particularly limited. From the viewpoint of growing the second group III nitride layer 22 having a high crystal quality, an MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam growth) method, HVPE (hydride vapor phase growth) method, vapor phase method such as sublimation method, liquid phase method such as high nitrogen pressure solution method and flux method are preferable.

(Process of forming source electrode, gate electrode, and drain electrode)
Next, referring to FIG. 2C, in the step of forming source electrode 30s, gate electrode 30g, and drain electrode 30d, source electrode 30s and gate electrode 30g are formed on second group III nitride layer 22. And a drain electrode 30d. The method of forming the source electrode 30s, the gate electrode 30g, and the drain electrode 30d is not particularly limited, but from the viewpoint of efficiently forming a high-quality electrode, formation of a pattern mask by photolithography, EB (electron beam) Preferred examples include formation of at least one metal layer by a vapor deposition method and removal of a pattern mask by a lift-off method.

In this way, the field effect transistor 2 is obtained. Here, when the first group III nitride layer 21 is a GaN layer and the second group III nitride layer 22 is an Al _1-x Ga _x N layer (0 ≦ x <1), the second group III The nitride layer 22 has a band energy lower than that of the first group III nitride layer 21, and electrons generated from the first group III nitride layer 21 gather in the second group III nitride layer 22, The two-dimensional electron gas distributed in a region having a thickness of about 10 nm in the vicinity of the interface between the group III nitride layer 22 and the first group III nitride layer 21 is formed, and an electric field called HEMT (High Electron Mobility Transistor) is formed. An effect transistor 2 is obtained.

{Embodiment 2-2}
Referring to FIG. 3, another method for manufacturing the field effect transistor 2 of the present embodiment includes a low thermal conductive support substrate 10 having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ and a group III nitride. Step of preparing the low thermal conductive composite substrate 1A bonded with the material film 13 (FIG. 3A), on the group III nitride film 13 of the low thermal conductive composite substrate 1A, the same chemical composition as the group III nitride film 13 And forming a first group III nitride layer 21 having a chemical composition different from that of the first group III nitride layer 21 on the first group III nitride layer 21 (FIG. 3B). Forming the second group III nitride layer 22 (FIG. 3B), and forming the source electrode 30s, the gate electrode 30g, and the drain electrode 30d on the second group III nitride layer 22. The process (FIG. 3C) and the low heat transfer from the group III nitride film 13 Step of removing the supporting substrate 10 (FIG. 3 (D) and (E)) and high thermal conductivity supporting substrate 11 having a 1.5W · cm ^-1 · K ^-1 or more thermal conductivity group III nitride film 13 And a step of bonding (FIGS. 3F and 3G).

In the manufacturing process of such a field effect transistor 2, the group III nitride film 13 is replaced with a low thermal conductivity supporting substrate 10 having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ in the manufacturing process. By disposing the high thermal conductivity supporting substrate 11 having a thermal conductivity of 5 W · cm ⁻¹ · K ⁻¹ or more, the field effect transistor 2 having high heat dissipation and high output can be obtained.

(Process for preparing a low thermal conductive composite substrate)
First, referring to FIG. 3A, in the step of preparing the low thermal conductive composite substrate 1A, the high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more is used instead of 1. except for using the low thermal conductive support substrate 10 having a .5W · cm ^-1 · K thermal conductivity of less than ^-1, in the same manner as in example 1, below 1.5 W · cm ^-1 · K ^-1 A low thermal conductive composite substrate 1A is obtained in which a low thermal conductive support substrate 10 having thermal conductivity and a group III nitride film 13 are bonded together with a bonding film 12 interposed therebetween.

  The low thermal conductive support substrate 10 used in the step of preparing the low thermal conductive composite substrate 1A includes the first group III nitride layer 21 and the second group III nitride that have low warpage and high crystal quality on the group III nitride film 13. From the viewpoint of growing the physical layer 22, the ratio of the linear thermal expansion coefficient of the low thermal conductive support substrate 10 to the linear thermal expansion coefficient of the group III nitride film 13 is preferably 0.8 or more and 1.2 or less, and 0.9 or more. 1.1 or less is more preferable. From this viewpoint, the low thermal conductive support substrate 10 is preferably a mullite substrate, an AlN substrate, or the like.

(Step of forming the first group III nitride layer)
Next, with reference to FIG. 3B, in the step of forming the first group III nitride layer 21, in the same manner as in Example 1, on the group III nitride film 13 of the low thermal conductive composite substrate 1A. The first group III nitride layer 21 having the same chemical composition as the group III nitride film 13 is formed.

(Step of forming the second group III nitride layer)
Next, referring to FIG. 3B, in the step of forming the second group III nitride layer 22, the first group III nitride layer 21 is formed on the first group III nitride layer 21 in the same manner as in the first embodiment. A second group III nitride layer 22 having a chemical composition different from that of group III nitride layer 21 is formed.

(Process of forming source electrode, gate electrode, and drain electrode)
Next, referring to FIG. 3C, in the step of forming the source electrode 30s, the gate electrode 30g, and the drain electrode 30d, the second group III nitride layer 22 is formed in the same manner as in the first embodiment. The source electrode 30s, the gate electrode 30g, and the drain electrode 30d are formed.

(Step of removing the low thermal conductive support substrate from the group III nitride film)
Next, referring to FIGS. 3D and 3E, the step of removing the low thermal conductive support substrate 10 from the group III nitride film 13 is not particularly limited, but the group III nitride film 13, the first From the viewpoint of efficiently removing the low thermal conductive support substrate 10 without degrading the quality of the group III nitride layer 21 and the second group III nitride layer 22, the source electrode 30s, the gate electrode 30g, and the drain electrode 30d And a sub-process of attaching the temporary support substrate 40 to the second group III nitride layer 22 formed with (FIG. 3D) and a sub-process of removing the low thermal conductive support substrate 10 from the group III nitride film 13 (FIG. 3E) is preferably included.

  Referring to FIG. 3D, in the sub-step of attaching the temporary support substrate 40, the temporary bonding agent is applied to the second group III nitride layer 22 in which the source electrode 30s, the gate electrode 30g, and the drain electrode 30d are formed. The temporary support substrate 40 is bonded with 41 interposed. Here, the temporary support substrate 40 is not particularly limited, but a Si substrate or the like is preferable from the viewpoint of high mechanical strength. The temporary bonding agent 41 is not particularly limited, but is preferably one that softens at a predetermined temperature from the viewpoint of easy bonding and removal.

  Referring to FIG. 3E, in the sub-process of removing low heat conductive support substrate 10, low heat conductive support substrate 10 and bonding film 12 are removed from group III nitride film 13. The method for removing the low thermal conductive support substrate 10 and the bonding film 12 is not particularly limited, and etching, cutting, grinding, and / or polishing can be applied.

(Process of bonding high thermal conductivity support substrate)
Referring to FIGS. 3F and 3G, the step of bonding the high thermal conductive support substrate 11 is not particularly limited, but from the viewpoint of efficiently bonding the high thermal conductive support substrate 11, the group III nitride film 13 is bonded. And a sub-process (FIG. 3 (F)) for bonding the high thermal conductivity support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more to the temporary support substrate 40 (FIG. 3). (G)).

Referring to FIG. 3 (F), in the sub-process for bonding high heat conductive support substrate 11, high heat conductive support having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more is applied to group III nitride film 13. The substrate 11 is bonded. The method for bonding the high thermal conductive support substrate 11 is not particularly limited, but from the viewpoint of increasing the bonding strength between the group III nitride film 13 and the high thermal conductive support substrate 11, the bonding is preferably performed with the bonding film 12 interposed. . The method of laminating the group III nitride film 13 and the high thermal conductive support substrate 11 with the bonding film 12 interposed is the same as the method for preparing the high thermal conductive composite substrate 1 described above.

  Referring to FIG. 3G, in the sub-step of removing temporary support substrate 40, temporary support substrate is formed from second group III nitride layer 22 in which source electrode 30s, gate electrode 30g, and drain electrode 30d are formed. 40 is removed. The method for removing the temporary support substrate 40 is not particularly limited, and examples thereof include a method of softening the temporary bonding agent 41 and removing the temporary support substrate 40 together with the temporary bonding agent 41.

In this way, the field effect transistor 2 is obtained. Here, when the first group III nitride layer 21 is a GaN layer and the second group III nitride layer 22 is an Al _1-x Ga _x N layer (0 ≦ x <1), the second group III The nitride layer 22 has a band energy lower than that of the first group III nitride layer 21, and electrons generated from the first group III nitride layer 21 gather in the second group III nitride layer 22, The two-dimensional electron gas distributed in a region having a thickness of about 10 nm in the vicinity of the interface between the group III nitride layer 22 and the first group III nitride layer 21 is formed, and an electric field called HEMT (High Electron Mobility Transistor) is formed. An effect transistor 2 is obtained.

(Example 1)
1. Preparation of High Thermal Conductive Composite Substrate First, referring to FIG. 2A, a high thermal conductive support substrate 11 having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or higher and a group III nitride film 13 are prepared. A high thermal conductive composite substrate 1 bonded with a bonding film 12 interposed therebetween was prepared. Here, the high thermal conductivity support substrate 11 has a thermal conductivity of 1.8 W · cm ⁻¹ · K ⁻¹ obtained by a sintering method and a linear thermal expansion coefficient in the direction parallel to the main surface of 3 × 10. ^-6 K ^-1 (ratio to linear thermal expansion coefficient parallel to the main surface of the GaN film is 1.0), an AlN polycrystalline substrate having a diameter of 5.0 cm and a thickness of 300 μm. The bonding film 12 was a SiO ₂ film having a diameter of 5.0 cm and a thickness of 0.5 μm. The group III nitride film 13 was a GaN film having a diameter of 5.0 cm and a thickness of 0.1 μm.

2. Formation of First Group III Nitride Layer and Second Group III Nitride Layer Next, referring to FIG. 2B, a first group III nitride is formed on group III nitride film 13 by MOCVD. An i-type GaN layer having a thickness of 3 μm is grown as the layer 21, and then an i-type GaN layer having a thickness of 0.025 μm is formed as the second group III nitride layer 22 on the first group III nitride layer 21 by MOCVD. A type Al _0.25 Ga _0.75 N layer was formed.

3. Formation of Source Electrode, Gate Electrode, and Drain Electrode Next, referring to FIG. 2C, a mask pattern is formed on the second group III nitride layer 22 by photolithography, and at least by EB vapor deposition. The source electrode 30s, the gate electrode 30g, and the drain electrode 30d were formed by forming one metal layer and removing the mask pattern by the lift-off method. The source electrode 30s and the drain electrode 30d are both alloyed by laminating a Ti layer having a thickness of 50 nm, an Al layer having a thickness of 100 nm, and an Au layer having a thickness of 200 nm, and performing heat treatment at 800 ° C. for 30 seconds. Was formed. The gate electrode 30g was formed of an Au layer having a thickness of 300 nm so that the gate width was 2 μm and the gate length was 150 μm.

4). Characteristic Evaluation of Field Effect Transistor The characteristic on-resistance (referred to as the resistance per channel area of the transistor; hereinafter the same) of the HEMT, which is the field effect transistor 2 obtained as described above, is a semiconductor parameter analyzer (Agilent Corporation). When measured by B1505), it was 1 mΩcm ² . This is because the heat dissipation of the AlN polycrystalline substrate which is the high thermal conductivity support substrate 11 is higher than that of Comparative Example 1 which will be described later. Therefore, the heat dissipation of the i-type GaN layer which is the first group III nitride layer 21 is higher. It was found that the characteristic on-resistance was low because of its high value.

(Example 2)
As the high thermal conductive support substrate, the thermal conductivity is 2.7 W · cm ⁻¹ · K ⁻¹ obtained by the sintering method instead of the AlN polycrystalline substrate, and the linear thermal expansion coefficient in the direction parallel to the main surface Is 3 × 10 ⁻⁶ K ⁻¹ (ratio to linear thermal expansion coefficient parallel to the main surface of the GaN film is 1.0), a SiC polycrystalline substrate having a diameter of 5.0 cm and a thickness of 300 μm is used. Except for this, a HEMT, which is a field effect transistor, was fabricated in the same manner as in Example 1. The characteristic on-resistance of the HEMT was 0.7 mΩcm ² . This is because the heat dissipation of the SiC polycrystalline substrate which is the high thermal conductivity support substrate 11 is higher than that of Comparative Example 1 described later, and therefore the heat dissipation of the i-type GaN layer which is the first group III nitride layer 21 is higher. It was found that the characteristic on-resistance was low because of its high value.

(Comparative Example 1)
Instead of the AlN polycrystalline substrate, which is a high thermal conductive support substrate, a low thermal conductive support substrate having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ obtained by a sintering method, the thermal conductivity is 0.5 W · cm ⁻¹ · K ⁻¹ and the linear thermal expansion coefficient in the direction parallel to the main surface is 3 × 10 ⁻⁶ K ⁻¹ (the ratio to the linear thermal expansion coefficient parallel to the main surface of the GaN film is 1 0.0) and a mullite substrate having a diameter of 5.0 cm and a thickness of 300 μm was used in the same manner as in Example 1 to fabricate a HEMT as a field effect transistor. The characteristic on-resistance of the HEMT was 5 mΩcm ² .

(Example 3)
1. Preparation of Low Thermal Conductive Composite Substrate First, referring to FIG. 3A, a low thermal conductive support substrate 10 having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ and a group III nitride film 13 are prepared. A low thermal conductive composite substrate 1A bonded with the bonding film 12 interposed therebetween was prepared. Here, the low thermal conductivity supporting substrate 10 has a thermal conductivity of 0.5 W · cm ⁻¹ · K ⁻¹ obtained by a sintering method and a linear thermal expansion coefficient in the direction parallel to the main surface of 3 × 10. It was a mullite substrate having a diameter of 5.0 cm and a thickness of 300 μm at ⁻⁶ K ⁻¹ (ratio to linear thermal expansion coefficient parallel to the main surface of the GaN film was 1.0). The bonding film 12 was a SiO ₂ film having a diameter of 5.0 cm and a thickness of 1 μm. The group III nitride film 13 was a GaN film having a diameter of 5.0 cm and a thickness of 0.1 μm.

2. Formation of First Group III Nitride Layer and Second Group III Nitride Layer Next, referring to FIG. 3B, a first group III nitride is formed on group III nitride film 13 by MOCVD. An i-type GaN layer having a thickness of 3 μm is grown as the layer 21, and then an i-type GaN layer having a thickness of 0.025 μm is formed as the second group III nitride layer 22 on the first group III nitride layer 21 by MOCVD. A type Al _0.25 Ga _0.75 N layer was formed.

3. Formation of Source Electrode, Gate Electrode, and Drain Electrode Next, referring to FIG. 3C, a mask pattern is formed on the second group III nitride layer 22 by photolithography, and at least by EB vapor deposition. The source electrode 30s, the gate electrode 30g, and the drain electrode 30d were formed by forming one metal layer and removing the mask pattern by the lift-off method. The source electrode 30s and the drain electrode 30d are both alloyed by laminating a Ti layer having a thickness of 50 nm, an Al layer having a thickness of 100 nm, and an Au layer having a thickness of 200 nm, and performing heat treatment at 800 ° C. for 30 seconds. Was formed. The gate electrode 30g was formed of an Au layer having a thickness of 300 nm so that the gate width was 2 μm and the gate length was 150 μm.

4). Removal of Low Thermal Conductive Support Substrate Next, referring to FIG. 3D, the temporary bonding agent 41 is applied to the second group III nitride layer 22 in which the source electrode 30s, the gate electrode 30g, and the drain electrode 30d are formed. The diameter of the temporary support substrate 40 is 5.0 cm using wafer bonding in an atmosphere heated to 200 ° C. in a vacuum with the application of a wafer bond HT-10, 10 manufactured by Brewer Sciences. And a sapphire substrate having a thickness of 300 μm was bonded. Next, referring to FIG. 3E, the low thermal conductive support substrate 10 and the bonding film 12 were dissolved and removed from the group III nitride film 13 by buffered hydrofluoric acid (BHF110 manufactured by Kanto Chemical Co., Inc.).

5). Next, referring to FIG. 3F, the thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more is obtained by interposing the bonding film 12 in the group III nitride film 13. A high thermal conductivity supporting substrate 11 having a laminate was attached. The high thermal conductivity support substrate 11 has a thermal conductivity of 1.8 W · cm ⁻¹ · K ⁻¹ obtained by a sintering method similar to that in Example 1, and a linear thermal expansion coefficient in a direction parallel to the main surface. Is 3 × 10 ⁻⁶ K ⁻¹ (ratio to linear thermal expansion coefficient parallel to the main surface of the GaN film is 1.0), an AlN polycrystalline substrate having a diameter of 5.0 cm and a thickness of 300 μm is used. . As in the method of forming the high thermal conductive composite substrate, bonding is performed by forming an SiO ₂ film as the bonding film 12 on each of the group III nitride film 13 and the high thermal conductive support substrate 11 and then bonding the respective SiO ₂ films. Was done. Next, referring to FIG. 3G, the second group III nitride in which the source electrode 30s, the gate electrode 30g, and the drain electrode 30d are formed by softening the temporary bonding agent 41 by heating to 200 ° C. The temporary support substrate 40 was removed from the physical layer 22 together with the temporary bonding agent 41.

6). Characteristic Evaluation of Field Effect Transistor The characteristic on-resistance of the HEMT, which is the field effect transistor 2 obtained as described above, was 1 mΩcm ² . This indicates that the characteristic on-resistance is lower than that of Comparative Example 1.

Example 4
Instead of the AlN polycrystalline substrate as the high thermal conductivity supporting substrate, the thermal conductivity was 2.7 W · cm ⁻¹ · K ⁻¹ obtained by the same sintering method as in Example 2 and parallel to the main surface. The linear thermal expansion coefficient in a specific direction is 3 × 10 ⁻⁶ K ⁻¹ (the ratio to the linear thermal expansion coefficient parallel to the main surface of the GaN film is 1.0), the diameter is 5.0 cm, and the thickness is 300 μm. A HEMT, which is a field effect transistor, was fabricated in the same manner as in Example 3 except that a SiC polycrystalline substrate was used. The characteristic on-resistance of the HEMT was 0.7 mΩcm ² . This indicates that the characteristic on-resistance is lower than that of Comparative Example 1.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 High heat conductive composite substrate 1A Low heat conductive composite substrate 1L Joint substrate 2 Field effect transistor 10 Low heat conductive support substrate 11 High heat conductive support substrate 12, 12a, 12b Bond film 13 Group III nitride film 13D, 13Dr Group III nitride film donor Substrate 13i Ion implantation region 21 First group III nitride layer 22 Second group III nitride layer 30d Drain electrode 30g Gate electrode 30s Source electrode 40 Temporary support substrate 41 Temporary bonding agent.

Claims (8)

A high thermal conductivity composite substrate in which a high thermal conductivity support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together;
A first group III nitride layer disposed on the group III nitride film of the high thermal conductive composite substrate and having the same chemical composition as the group III nitride film;
A second group III nitride layer disposed on the first group III nitride layer and having a different chemical composition than the first group III nitride layer;
A field effect transistor comprising a source electrode, a gate electrode, and a drain electrode disposed on the second group III nitride layer.   2. The field effect transistor according to claim 1, wherein the group III nitride film is a GaN film, and the first group III nitride layer is a GaN layer.   3. The field effect transistor according to claim 1, wherein the high thermal conductivity supporting substrate has a linear thermal expansion coefficient of 0.8 to 1.2 in a ratio to a linear thermal expansion coefficient of the group III nitride film. .   4. The field effect transistor according to claim 1, wherein the high thermal conductive support substrate includes at least one crystal selected from the group consisting of an AlN crystal and an SiC crystal. 5. Preparing a high thermal conductive composite substrate in which a high thermal conductive support substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more and a group III nitride film are bonded together;
Forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the high thermal conductive composite substrate;
Forming a second group III nitride layer having a chemical composition different from that of the first group III nitride layer on the first group III nitride layer;
Forming a source electrode, a gate electrode, and a drain electrode on the second group III nitride layer.   6. The method of manufacturing a field effect transistor according to claim 5, wherein the high thermal conductivity supporting substrate has a linear thermal expansion coefficient of 0.8 to 1.2 in a ratio to the linear thermal expansion coefficient of the group III nitride film. Preparing a low thermal conductive composite substrate in which a low thermal conductive support substrate having a thermal conductivity of less than 1.5 W · cm ⁻¹ · K ⁻¹ and a group III nitride film are bonded together;
Forming a first group III nitride layer having the same chemical composition as the group III nitride film on the group III nitride film of the low thermal conductive composite substrate;
Forming a second group III nitride layer having a chemical composition different from that of the first group III nitride layer on the first group III nitride layer;
Forming a source electrode, a gate electrode, and a drain electrode on the second group III nitride layer;
Removing the low thermal conductivity support substrate from the group III nitride film;
Bonding a high thermal conductivity supporting substrate having a thermal conductivity of 1.5 W · cm ⁻¹ · K ⁻¹ or more to the group III nitride film, and a method for manufacturing a field effect transistor.   8. The method of manufacturing a field effect transistor according to claim 7, wherein the low thermal conductive support substrate has a linear thermal expansion coefficient of 0.8 to 1.2 in a ratio to the linear thermal expansion coefficient of the group III nitride film.

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