JP2016046458A - Chip resistor and packaging structure therefor - Google Patents

Chip resistor and packaging structure therefor Download PDF

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JP2016046458A
JP2016046458A JP2014171450A JP2014171450A JP2016046458A JP 2016046458 A JP2016046458 A JP 2016046458A JP 2014171450 A JP2014171450 A JP 2014171450A JP 2014171450 A JP2014171450 A JP 2014171450A JP 2016046458 A JP2016046458 A JP 2016046458A
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resistor
insulating substrate
chip resistor
electrodes
electrode
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JP6339452B2 (en
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平沢 浩一
Koichi Hirasawa
浩一 平沢
裕也 竹上
Yuya TAKEUE
裕也 竹上
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Koa Corp
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Koa Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/06Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material including means to minimise changes in resistance with changes in temperature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/08Cooling, heating or ventilating arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C1/00Details
    • H01C1/14Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/148Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals embracing or surrounding the resistive element
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/003Thick film resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C7/00Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/20Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material the resistive layer or coating being tapered

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Details Of Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wire bonding connection type chip resistor which improves heat dissipation and surge resistance, and a packaging structure therefor.SOLUTION: A chip resistor 1 includes: an insulation substrate 2 in a rectangular parallelepiped shape; a pair of front-side electrodes 3 and 4 which are formed along sides 2a and 2b opposing each other on a front face of the insulation substrate 2; and a resistive element 5 which is formed to be connected to the front-side electrodes 3 and 4. A planar shape of the pair of front-side electrodes 3 and 4 is formed in a trapezoidal shape that occupies one side (2a or 2b) of the insulation substrate 2, and inclined side parts 3a and 4a of the front-side electrodes 3 and 4 are disposed oppositely in parallel with each other while interposing the resistive element 5 therebetween. In a portion where an interval between the sides 2a and 2b of the insulation substrate 2 and the inclined side parts 3a and 4a becomes substantially maximum in the front-side electrodes 3 and 4, two parts which are positioned on a diagonal on the front face of the insulation substrate 2 are defined as connection parts C for a bonding wire, respectively.SELECTED DRAWING: Figure 1

Description

本発明は、耐サージ性に優れたワイヤボンディング接続型のチップ抵抗器と、そのようなチップ抵抗器を回路基板に搭載した実装構造に関するものである。   The present invention relates to a wire bonding connection type chip resistor excellent in surge resistance and a mounting structure in which such a chip resistor is mounted on a circuit board.

従来より、耐サージ性に優れたチップ抵抗器として、図8に示すような構造のチップ抵抗器が提案されている(例えば、特許文献1参照)。同図において、符号100は直方体形状の絶縁基板であり、この絶縁基板100の表面における対角線上の2つの角部にはそれぞれ表電極101が形成されている。これら表電極101は絶縁基板100の角部を頂点とする平面視三角形状に形成されており、三角形の底辺をなす両表電極101の傾斜辺部101aは互いに平行に対向している。また、絶縁基板100の表面には平面視方形状の抵抗体102が形成されており、この抵抗体102の相対向する2つの角部はそれぞれ表電極101と接続されている。   Conventionally, a chip resistor having a structure as shown in FIG. 8 has been proposed as a chip resistor having excellent surge resistance (see, for example, Patent Document 1). In the figure, reference numeral 100 denotes a rectangular parallelepiped insulating substrate, and surface electrodes 101 are respectively formed at two corners on the diagonal line on the surface of the insulating substrate 100. These surface electrodes 101 are formed in a triangular shape in plan view with the corners of the insulating substrate 100 as vertices, and the inclined side portions 101a of the two surface electrodes 101 forming the bases of the triangles face each other in parallel. In addition, a resistor 102 having a rectangular shape in plan view is formed on the surface of the insulating substrate 100, and two corners facing each other of the resistor 102 are connected to the surface electrode 101.

このように構成されたチップ抵抗器では、一対の表電極101の傾斜辺部101aが抵抗体102を挟んで平行に対向配置されており、これら傾斜辺部101aで挟まれた領域に存する抵抗体102についてみると、いずれの部位も傾斜辺部101aと直交する方向に電流が流れるため、表電極101の特定の部位への電流集中を軽減することができる。また、絶縁基板100の表面における表電極101の存しない残り2つの角部側の領域、つまり両傾斜辺部101a間に挟まれた部分の外側の領域にも抵抗体102が形成されているため、抵抗体102の面積を広くとることができて耐サージ性に優れたチップ抵抗器となっている。   In the chip resistor configured as described above, the inclined side portions 101a of the pair of front electrodes 101 are arranged to face each other in parallel with the resistor 102 interposed therebetween, and the resistor exists in the region sandwiched between the inclined side portions 101a. As for 102, since current flows in a direction perpendicular to the inclined side portion 101a in any part, current concentration on a specific part of the front electrode 101 can be reduced. Further, the resistor 102 is also formed in the remaining two corner side regions where the surface electrode 101 does not exist on the surface of the insulating substrate 100, that is, the region outside the portion sandwiched between the two inclined side portions 101a. In this case, the resistor 102 can have a large area and is a chip resistor having excellent surge resistance.

特許第4594117号公報Japanese Patent No. 4594117

前述した従来例に係るチップ抵抗器では、抵抗体102を挟んで対向する両表電極101の傾斜辺部101aが角部のない直線状に形成されており、両表電極101の電極間距離が傾斜辺部101aに沿った全域で一定となるため、電極間距離の短い部分に電流が集中して当該部分の温度を上昇させる、という負荷特性の悪化をある程度は軽減することができる。   In the above-described chip resistor according to the conventional example, the inclined side portions 101a of the both surface electrodes 101 facing each other with the resistor 102 interposed therebetween are formed in a straight line having no corners, and the distance between the electrodes of both surface electrodes 101 is Since it becomes constant over the entire area along the inclined side portion 101a, it is possible to reduce to some extent the deterioration of load characteristics that current concentrates on a portion where the distance between the electrodes is short and the temperature of the portion increases.

しかしながら、図9に示すように、両表電極101で挟まれた抵抗体102内を傾斜辺部101aと直交方向に流れる電流(矢印A参照)の他に、その外側に形成された抵抗体102内を回り込んで表電極101に向かう電流(矢印B参照)が存在し、後者の電流Bが表電極101の傾斜辺部101aと抵抗体102の外側辺との交点であるエッジ部(符号Eを付した4か所)に集中するため、これらエッジ部Eの近傍に位置する抵抗体102が負荷集中によって温度上昇してしまうという問題があった。特に、耐サージ性を向上させるべく抵抗体102の面積を広くすると、それに反比例して表電極101の面積が小さくなってしまうため、上記したエッジ部E近傍の温度上昇が大きくなって負荷特性の悪化を招くことになり、最悪の場合、チップ抵抗器が発熱によって破壊してしまうことがある。   However, as shown in FIG. 9, in addition to the current flowing in the direction orthogonal to the inclined side portion 101a (see arrow A) in the resistor 102 sandwiched between both surface electrodes 101, the resistor 102 formed outside thereof There is a current (see arrow B) that wraps around the front electrode 101, and the latter current B is an edge portion (reference symbol E) that is the intersection of the inclined side portion 101a of the front electrode 101 and the outer side of the resistor 102. 4), the temperature of the resistor 102 located in the vicinity of the edge portion E rises due to load concentration. In particular, if the area of the resistor 102 is increased in order to improve surge resistance, the area of the surface electrode 101 decreases in inverse proportion to this, so that the temperature rise in the vicinity of the edge portion E increases and the load characteristics are increased. In the worst case, the chip resistor may be destroyed by heat generation.

本発明は、このような従来技術の実情に鑑みてなされたもので、その第1の目的は、放熱性と耐サージ性に優れたワイヤボンディング接続型のチップ抵抗器を提供することにあり、第2の目的は、そのようなチップ抵抗器の実装構造を提供することにある。   The present invention has been made in view of such a state of the art, and its first object is to provide a wire bonding connection type chip resistor excellent in heat dissipation and surge resistance, A second object is to provide such a chip resistor mounting structure.

上記第1の目的を達成するために、本発明は、直方体形状の絶縁基板と、この絶縁基板の表面における相対向する側辺に沿って形成された一対の表電極と、これら両表電極に接続するように形成された抵抗体とを備え、一対の前記表電極がワイヤボンディング用電極となっているチップ抵抗器において、一対の前記表電極にそれぞれ前記絶縁基板の側辺に対して傾斜方向へ延びる傾斜辺部を形成すると共に、これら両傾斜辺部どうしを前記抵抗体を介して互いに平行に対向配置し、前記表電極のうち、前記絶縁基板の側辺と前記傾斜辺部との間隔がほぼ最大で、前記絶縁基板の表面における対角線上に位置する部位をボンディングワイヤの接続部とした。   In order to achieve the first object, the present invention provides a rectangular parallelepiped insulating substrate, a pair of surface electrodes formed along opposite sides on the surface of the insulating substrate, and both the surface electrodes. In a chip resistor comprising a resistor formed to be connected and the pair of front electrodes being wire bonding electrodes, the pair of front electrodes are inclined with respect to the sides of the insulating substrate, respectively. Inclined sides extending to each other, and the two inclined sides are arranged opposite to each other in parallel through the resistor, and the distance between the side of the insulating substrate and the inclined sides of the surface electrode The portion located on the diagonal line on the surface of the insulating substrate is the bonding wire connecting portion.

このように構成されたチップ抵抗器では、一対の表電極の平面形状が絶縁基板の1つの側辺を占める台形(または直角三角形)状に形成されており、これら表電極の傾斜辺部どうしが抵抗体を介して互いに平行に対向配置されているため、電流の回り込みによって電流集中する部分がそれぞれの表電極について1箇所だけとなり、抵抗体の面積を広くして耐サージ性を向上させた上で、温度上昇に起因する負荷特性の悪化を抑制することができる。そして、電流集中によって温度上昇するのは、表電極のうち絶縁基板の側辺と傾斜辺部との間隔が最も大きい部位であり、当該部位をボンディングワイヤの接続部としているため、チップ抵抗器を回路基板に搭載してワイヤボンディング接続することにより、上昇した温度がボンディングワイヤを介して回路基板側へ放熱され、放熱性と耐サージ性に優れたワイヤボンディング接続型のチップ抵抗器を実現することができる。   In the chip resistor configured as described above, the planar shape of the pair of front electrodes is formed in a trapezoidal shape (or a right triangle) that occupies one side of the insulating substrate, and the inclined sides of the front electrodes are arranged between each other. Since they are arranged opposite to each other in parallel via resistors, there is only one portion where current concentrates due to current wrapping for each surface electrode, and the area of the resistor is increased to improve surge resistance. Thus, it is possible to suppress the deterioration of the load characteristics due to the temperature rise. The temperature rise due to current concentration is the portion of the surface electrode where the distance between the side of the insulating substrate and the inclined side is the largest, and this portion is used as a bonding wire connecting portion. By mounting on the circuit board and wire bonding connection, the elevated temperature is dissipated to the circuit board side via the bonding wire, realizing a wire bonding connection type chip resistor with excellent heat dissipation and surge resistance Can do.

上記の構成において、抵抗体は表電極に対して前記接続部を露出させた状態で接続されていれば、その形状は特に限定されるものでないが、抵抗体の平面形状を平行四辺形とし、この抵抗体の対辺を表電極の傾斜辺部に略同一幅で重ね合わせた接続状態とすれば、抵抗体を簡単かつ高精度に印刷形成することができて好ましい。   In the above configuration, the shape of the resistor is not particularly limited as long as the resistor is connected to the surface electrode with the connection portion exposed, but the planar shape of the resistor is a parallelogram, If the opposite side of the resistor is connected to the inclined side portion of the surface electrode with substantially the same width, the resistor can be printed easily and with high accuracy.

また、上記の構成において、絶縁基板の裏面のほぼ全体に放熱電極が形成されていると、チップ抵抗器を回路基板に搭載してワイヤボンディング接続したとき、抵抗体や表電極の温度上昇がボンディングワイヤを介して回路基板側へ放熱されるだけでなく、絶縁基板の内部を伝わる熱が放熱電極から回路基板側へも放熱されるため、より効果的に放熱性を高めることができる。   In the above configuration, if a heat dissipation electrode is formed on almost the entire back surface of the insulating substrate, when the chip resistor is mounted on the circuit board and wire-bonded, the temperature rise of the resistor and the surface electrode is bonded. Not only is the heat radiated to the circuit board side via the wire, but the heat transmitted through the inside of the insulating substrate is also radiated from the heat radiation electrode to the circuit board side, so the heat dissipation can be improved more effectively.

また、上記第2の目的を達成するために、本発明は、チップ抵抗器が、直方体形状の絶縁基板と、この絶縁基板の表面における相対向する側辺に沿って形成された一対の表電極と、これら両表電極に接続するように形成された抵抗体とを備えており、このチップ抵抗器が回路基板上に搭載されていると共に、前記回路基板に設けられた配線パターンと前記チップ抵抗器の前記表電極とがボンディングワイヤを介して接続されているチップ抵抗器の実装構造において、一対の前記表電極にそれぞれ前記絶縁基板の側辺に対して傾斜方向へ延びる傾斜辺部を形成すると共に、これら両傾斜辺部どうしを前記抵抗体を介して互いに平行に対向配置し、前記表電極のうち、前記絶縁基板の側辺と前記傾斜辺部との間隔がほぼ最大で、前記絶縁基板の表面における対角線上に位置する部位を前記ボンディングワイヤの接続部とした。   In order to achieve the second object, according to the present invention, a chip resistor includes a rectangular parallelepiped-shaped insulating substrate and a pair of front electrodes formed along opposite sides of the surface of the insulating substrate. And a resistor formed so as to be connected to both surface electrodes. The chip resistor is mounted on the circuit board, and the wiring pattern provided on the circuit board and the chip resistor are provided. In a chip resistor mounting structure in which the surface electrode of the device is connected via a bonding wire, a pair of the surface electrodes is formed with inclined sides extending in an inclined direction with respect to the side of the insulating substrate. In addition, the two inclined side portions are arranged opposite to each other in parallel through the resistor, and the insulating substrate has a maximum interval between the side of the insulating substrate and the inclined side portion of the surface electrode. Table The site located diagonally in the connecting portion of the bonding wire.

このように構成された実装構造では、チップ抵抗器に備えられる絶縁基板の相対向する2つの側辺に沿ってそれぞれ表電極が形成されており、これら表電極の平面形状は絶縁基板の1つの側辺を占める台形(または直角三角形)状であると共に、両表電極の傾斜辺部どうしが抵抗体を介して互いに平行に対向配置されているため、電流の回り込みによって電流集中する部分がそれぞれの表電極について1箇所だけとなり、抵抗体の面積を広くして耐サージ性を向上させた上で、温度上昇に起因する負荷特性の悪化を抑制することができる。そして、電流集中によって温度上昇するのは、表電極のうち絶縁基板の側辺と傾斜辺部との間隔が最も大きい部位であり、当該部位をボンディングワイヤの接続部としてチップ抵抗器が回路基板に搭載されているため、チップ抵抗器で発生した上昇温度がボンディングワイヤを介して回路基板側へ放熱され、チップ抵抗器の耐サージ性と放熱性を高めることができる。   In the mounting structure configured as described above, the surface electrodes are formed along two opposite sides of the insulating substrate provided in the chip resistor, and the planar shape of these surface electrodes is one of the insulating substrates. The trapezoidal (or right triangle) shape that occupies the sides, and the inclined sides of both surface electrodes are arranged opposite to each other in parallel through resistors, so that the current concentrated portions by the current wraparound Only one surface electrode is provided, and the area of the resistor is increased to improve the surge resistance, and the deterioration of the load characteristics due to the temperature rise can be suppressed. The temperature rises due to the current concentration at the part of the surface electrode where the distance between the side of the insulating substrate and the inclined side is the largest, and the chip resistor is attached to the circuit board with this part as the connecting part of the bonding wire. Since it is mounted, the rising temperature generated in the chip resistor is radiated to the circuit board side through the bonding wire, and the surge resistance and heat dissipation of the chip resistor can be improved.

この場合において、絶縁基板の裏面のほぼ全体に放熱電極が形成されていると共に、配線パターンに放熱電極よりも大きな外形を有する接続ランド部が形成されており、放熱電極を接続ランド部に半田付けした状態でチップ抵抗器が回路基板上に搭載されていると、抵抗体や表電極の温度上昇がボンディングワイヤを介して回路基板側へ放熱されるだけでなく、絶縁基板の内部を伝わる熱が放熱電極から回路基板側へも放熱されるため、より効果的に放熱性を高めることができる。   In this case, a heat radiation electrode is formed on almost the entire back surface of the insulating substrate, and a connection land portion having an outer shape larger than the heat radiation electrode is formed on the wiring pattern, and the heat radiation electrode is soldered to the connection land portion. When the chip resistor is mounted on the circuit board in this state, the temperature rise of the resistor and the surface electrode is not only radiated to the circuit board side via the bonding wire, but also the heat transmitted inside the insulating board Since heat is radiated also from the heat radiation electrode to the circuit board side, the heat dissipation can be improved more effectively.

本発明によれば、放熱性と耐サージ性に優れたワイヤボンディング接続型のチップ抵抗器を提供することができる。   According to the present invention, it is possible to provide a wire bonding connection type chip resistor excellent in heat dissipation and surge resistance.

本発明の実施形態例に係るチップ抵抗器の平面図である。It is a top view of the chip resistor concerning the example of an embodiment of the present invention. 図1のII−II線に沿う断面図である。It is sectional drawing which follows the II-II line of FIG. 図1のIII−III線に沿う断面図である。It is sectional drawing which follows the III-III line of FIG. 図1のIV−IV線に沿う断面図である。It is sectional drawing which follows the IV-IV line of FIG. 該チップ抵抗器に備えられる表電極と抵抗体の説明図である。It is explanatory drawing of the surface electrode and resistor which are provided in this chip resistor. 該チップ抵抗器を回路基板に搭載した実装構造を示す断面図である。It is sectional drawing which shows the mounting structure which mounted this chip resistor on a circuit board. 該チップ抵抗器の製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of this chip resistor. 従来例に係るチップ抵抗器の平面図である。It is a top view of the chip resistor concerning a conventional example. 該チップ抵抗器における電流の分布状態を示す説明図である。It is explanatory drawing which shows the distribution state of the electric current in this chip resistor.

発明の実施の形態について図面を参照して説明すると、図1〜図4に示すように、本発明の実施形態例に係るチップ抵抗器1は、直方体形状の絶縁基板2と、この絶縁基板2の表面における相対向する側辺2a,2bに沿って形成された一対の表電極3,4と、これら両表電極3,4に接続するように形成された抵抗体5と、両表電極3,4と抵抗体5を覆うように形成された保護コート6と、絶縁基板2の裏面におけるほぼ全体に形成された裏電極7とによって構成されている。   DESCRIPTION OF EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 1 to 4, a chip resistor 1 according to an embodiment of the present invention includes a rectangular parallelepiped insulating substrate 2 and the insulating substrate 2. A pair of surface electrodes 3, 4 formed along opposite sides 2a, 2b on the surface, a resistor 5 formed so as to be connected to both surface electrodes 3, 4, and both surface electrodes 3 , 4 and the protective coating 6 formed so as to cover the resistor 5, and the back electrode 7 formed almost entirely on the back surface of the insulating substrate 2.

絶縁基板2はセラミック(アルミナ96やアルミナ99)等からなり、この絶縁基板2は大判の集合基板を縦横の分割溝に沿って分割して多数個取りしたものである。   The insulating substrate 2 is made of ceramic (alumina 96 or alumina 99) or the like, and this insulating substrate 2 is obtained by dividing a large aggregate substrate along vertical and horizontal dividing grooves and taking a large number.

一対の表電極3,4はAg(またはAg/Pd)ペーストをスクリーン印刷して乾燥・焼成させたものであり、両表電極3,4は対応する絶縁基板2の側辺2a,2bに対して傾斜方向へ延びる傾斜辺部3a,4aを有している。これら傾斜辺部3a,4aは互いに平行に対向しており、両表電極3,4は絶縁基板2の中心に関して点対称な台形状をしている。   The pair of front electrodes 3 and 4 is obtained by screen-printing Ag (or Ag / Pd) paste, dried and fired, and both front electrodes 3 and 4 correspond to the side edges 2a and 2b of the corresponding insulating substrate 2. And inclined side portions 3a and 4a extending in the inclined direction. The inclined side portions 3 a and 4 a face each other in parallel, and both the surface electrodes 3 and 4 have a trapezoidal shape that is point-symmetric with respect to the center of the insulating substrate 2.

抵抗体5は酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものである。この抵抗体5は2組の対辺がそれぞれ平行な平行四辺形に形成されており、そのうち左右方向に位置する1組の対辺がそれぞれ表電極3,4の傾斜辺部3a,4aとほぼ一定幅で重なり合っている。   The resistor 5 is a resistor paste such as ruthenium oxide screen-printed, dried and fired. This resistor 5 is formed in a parallelogram shape in which two pairs of opposite sides are parallel to each other, and one pair of opposite sides located in the left-right direction has a substantially constant width with the inclined sides 3a and 4a of the surface electrodes 3 and 4, respectively. Are overlapping.

ここで、図5に示すように、両表電極3,4の傾斜辺部3a,4aの間に挟まれた抵抗体5のうち、傾斜辺部3a,4aに直交する2つの直線Lと2つの傾斜辺部3a,4aとで囲まれた矩形状の領域S1(ハッチングが施された部分)は、電極間距離が一定で電流の集中する角部が存在しない部位であり、この領域S1の上下に隣接する三角形状の領域S2,S3は、三角形の頂点に位置する表電極3,4に向かって電流が回り込む部位となっている。これにより、図示左側の表電極3についてみると、一方の直線Lと傾斜辺部3aとの交点がエッジ部Eとなり、図示右側の表電極4についてみると、他方の直線Lと傾斜辺部4aとの交点がエッジ部Eとなり、これらエッジ部Eの近傍が負荷集中に伴って温度が上昇する部分となる。   Here, as shown in FIG. 5, of the resistor 5 sandwiched between the inclined sides 3a and 4a of the surface electrodes 3 and 4, two straight lines L and 2 orthogonal to the inclined sides 3a and 4a are provided. A rectangular region S1 (hatched portion) surrounded by the two inclined sides 3a and 4a is a portion where the distance between the electrodes is constant and there is no corner where current is concentrated. Triangular regions S2 and S3 that are vertically adjacent to each other are portions where current flows toward the surface electrodes 3 and 4 located at the apexes of the triangle. As a result, when the left surface electrode 3 is viewed, the intersection of one straight line L and the inclined side portion 3a becomes the edge portion E, and when the right front electrode 4 is viewed, the other straight line L and the inclined side portion 4a. The point of intersection with the edge part E becomes an edge part E, and the vicinity of the edge part E becomes a part where the temperature rises with load concentration.

保護コート6はガラスペーストをスクリーン印刷して焼成させたものであるが、それ以外にもエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたものでも良い。保護コート6は抵抗体5の全体を覆うように形成されており、抵抗体5は保護コート6によって外部環境から保護されている。また、保護コート6は前述したエッジ部Eの近傍を除いた両表電極3,4を覆うように形成されており、両表電極3,4における保護コート6によって覆われていない部位が後述するボンディングワイヤの接続部Cとなっている。これら接続部Cは絶縁基板2の側辺2a,2bと傾斜辺部3a,4aとの間隔がほぼ最大となる部分(図1に示す長方形の白抜き部分)であり、具体的には、絶縁基板2の表面における対角線上に位置する表電極3の上側角部と表電極4の下側角部とがそれぞれ接続部Cとなっている。   The protective coat 6 is obtained by screen-printing and baking a glass paste, but other than that, an epoxy-based resin paste may be screen-printed and heat-cured. The protective coat 6 is formed so as to cover the entire resistor 5, and the resistor 5 is protected from the external environment by the protective coat 6. Further, the protective coat 6 is formed so as to cover both the front electrodes 3 and 4 except for the vicinity of the edge portion E described above, and a portion of the front electrodes 3 and 4 that is not covered by the protective coat 6 will be described later. This is a bonding wire connection C. These connecting portions C are portions where the distance between the side edges 2a, 2b of the insulating substrate 2 and the inclined side portions 3a, 4a is substantially maximized (rectangular white portions shown in FIG. 1). The upper corner portion of the front electrode 3 and the lower corner portion of the front electrode 4 located on the diagonal line on the surface of the substrate 2 are connection portions C, respectively.

裏電極7はAgペーストやCuペースト等をスクリーン印刷して乾燥・焼成させたものであり、この裏電極7は絶縁基板2の外縁部を除くほぼ裏面全体に形成されている。図示省略されているが、この裏電極7および保護コート6から露出する両表電極3,4の接続部CにはNiメッキやNi/AuメッキあるいはPdメッキ等が施されており、これらメッキの種類は接続部Cに超音波接続されるボンディングワイヤの材質に応じて適宜選択される。なお、両表電極3,4がポーラスでなく緻密な厚膜で形成されている場合、例えば、ガラス成分が少なく金属成分(Ag)を多く含むAg系厚膜からなる場合は、前述したメッキ処理を省略することができる。   The back electrode 7 is obtained by screen-printing Ag paste, Cu paste or the like, drying and firing, and this back electrode 7 is formed on almost the entire back surface except the outer edge portion of the insulating substrate 2. Although not shown in the drawing, the connection portion C of both the front electrodes 3 and 4 exposed from the back electrode 7 and the protective coat 6 is subjected to Ni plating, Ni / Au plating, Pd plating or the like. The type is appropriately selected according to the material of the bonding wire that is ultrasonically connected to the connection portion C. In the case where both the front electrodes 3 and 4 are formed of a dense thick film rather than porous, for example, in the case of an Ag-based thick film with a small glass component and a large amount of metal component (Ag), the above-described plating treatment is performed. Can be omitted.

図6に示すように、このように構成されたチップ抵抗器1は回路基板8上に実装された状態で使用され、回路基板8に設けられた配線パターン9の2箇所とチップ抵抗器1の両表電極3,4とがボンディングワイヤ10を介して接続されるようになっている。   As shown in FIG. 6, the chip resistor 1 configured as described above is used in a state where it is mounted on the circuit board 8, and two places of the wiring pattern 9 provided on the circuit board 8 and the chip resistor 1 are arranged. Both surface electrodes 3 and 4 are connected via a bonding wire 10.

回路基板8は、アルミナや窒化アルミ等のセラミックスをベースとし、その表裏両面に配線パターン9となる銅回路版を共晶反応によって接合したDBC基板であるが、それ以外にも高放熱の多層ガラスエポキシ基板を用いることも可能である。回路基板8の表面に設けられた配線パターン9の一部は接続ランド部9aとなっており、この接続ランド部9a上にチップ抵抗器1が搭載される。   The circuit board 8 is a DBC board based on ceramics such as alumina and aluminum nitride, and a copper circuit plate to be a wiring pattern 9 is bonded to both front and back surfaces by a eutectic reaction. It is also possible to use an epoxy substrate. A part of the wiring pattern 9 provided on the surface of the circuit board 8 forms a connection land portion 9a, and the chip resistor 1 is mounted on the connection land portion 9a.

チップ抵抗器1を回路基板8に実装する手順について説明すると、まず、回路基板8の接続ランド部9a上に半田ペースト(ソルダーペースト)10を印刷形成する。次に、裏電極7を下向きにした状態でチップ抵抗器1を半田ペースト11上に搭載した後、そのままリフロー炉に搬入して半田ペースト11を溶融・固化することにより、チップ抵抗器1の裏電極7と回路基板8の接続ランド部9aとを半田付けする。   The procedure for mounting the chip resistor 1 on the circuit board 8 will be described. First, a solder paste (solder paste) 10 is printed on the connection land portion 9 a of the circuit board 8. Next, after the chip resistor 1 is mounted on the solder paste 11 with the back electrode 7 facing downward, the chip resistor 1 is carried into the reflow furnace as it is, and the solder paste 11 is melted and solidified. The electrode 7 and the connection land portion 9a of the circuit board 8 are soldered.

しかる後、超音波溶着により1本のボンディングワイヤ10の両端部を表電極3の接続部Cと配線パターン9に接続すると共に、別のボンディングワイヤ10の両端部を表電極4の接続部Cと配線パターン9に接続する。ここで、接続部Cは台形状に形成された両表電極3,4の幅広い箇所に設定されているため、かかるボンディングワイヤ10の接続作業を容易に行うことができる。   Thereafter, both ends of one bonding wire 10 are connected to the connection portion C of the surface electrode 3 and the wiring pattern 9 by ultrasonic welding, and both ends of another bonding wire 10 are connected to the connection portion C of the surface electrode 4. Connect to wiring pattern 9. Here, since the connection part C is set in a wide part of the both surface electrodes 3 and 4 formed in the trapezoidal shape, the connection work of the bonding wire 10 can be easily performed.

なお、回路基板8にチップ抵抗器1の他にCPUやパワートランジスタ等の発熱の激しい電子部品が搭載されている場合は、回路基板8の裏面に設けられた配線パターン9にペースト状の放熱グリスを塗布し、この放熱グリスを介して回路基板8を図示せぬヒートシンクに取り付けるようにすることが好ましい。   In addition, in the case where electronic components such as a CPU and a power transistor other than the chip resistor 1 are mounted on the circuit board 8, paste-like heat radiation grease is formed on the wiring pattern 9 provided on the back surface of the circuit board 8. It is preferable that the circuit board 8 is attached to a heat sink (not shown) through this heat radiation grease.

次に、上記のごとく構成されたチップ抵抗器1の製造工程について、図7を参照しながら説明する。   Next, the manufacturing process of the chip resistor 1 configured as described above will be described with reference to FIG.

まず、絶縁基板2が多数個取りされる集合基板2Aを準備する。この集合基板2Aには予め1次分割溝と2次分割溝(いずれも図示省略)が格子状に設けられており、両分割溝によって区切られたマス目の1つ1つが1個分のチップ領域となる。なお、図7では1個分のチップ領域に相当する集合基板2Aが代表的に示されているが、実際は多数個分のチップ領域に相当する集合基板2Aに対して以下に説明する各工程が一括して行われる。   First, an aggregate substrate 2A from which a large number of insulating substrates 2 are taken is prepared. In this aggregate substrate 2A, primary division grooves and secondary division grooves (both not shown) are provided in a lattice shape in advance, and each square divided by both division grooves is one chip. It becomes an area. In FIG. 7, the collective substrate 2A corresponding to one chip region is representatively shown. However, in reality, each process described below is performed on the collective substrate 2A corresponding to many chip regions. It is done in a lump.

すなわち、図7(a)に示すように、集合基板2Aの裏面にAg系ペーストをスクリーン印刷した後、これを乾燥・焼成することにより、集合基板2Aの裏面に裏電極7を形成する(裏電極形成工程)。   That is, as shown in FIG. 7A, after the Ag-based paste is screen-printed on the back surface of the collective substrate 2A, the back electrode 7 is formed on the back surface of the collective substrate 2A by drying and baking this (back surface). Electrode forming step).

次に、この裏電極形成工程に前後して集合基板2Aの表面にAg(またはAg/Pd)ペーストをスクリーン印刷した後、これを乾燥・焼成することにより、図7(b)に示すように、集合基板2Aの左右両側部に一対の表電極3,4を形成する(表電極形成工程)。前述したように、これら表電極3,4は絶縁基板2の中心に関して点対称な台形状に形成されており、両表電極3,4の傾斜辺部3a,4aは互いに平行に対向している。   Next, before and after the back electrode formation step, Ag (or Ag / Pd) paste is screen-printed on the surface of the aggregate substrate 2A, and then dried and fired, as shown in FIG. 7B. Then, a pair of front electrodes 3 and 4 are formed on the left and right sides of the collective substrate 2A (surface electrode forming step). As described above, the surface electrodes 3 and 4 are formed in a trapezoidal shape that is point-symmetric with respect to the center of the insulating substrate 2, and the inclined sides 3a and 4a of the surface electrodes 3 and 4 face each other in parallel. .

次に、集合基板2Aの表面に酸化ルテニウム等の抵抗体ペーストをスクリーン印刷した後、これを乾燥・焼成することにより、図7(c)に示すように、左右の対辺を傾斜辺部3a,4aに重ね合わせた平行四辺形状の抵抗体5を形成する(抵抗体形成工程)。   Next, after a resistor paste such as ruthenium oxide is screen-printed on the surface of the aggregate substrate 2A, this is dried and fired, so that the left and right opposite sides are inclined side portions 3a, 3a, A parallelogram-shaped resistor 5 superimposed on 4a is formed (resistor forming step).

しかる後、抵抗体5の全体と両表電極3,4の大部分を覆う領域にガラスペーストをスクリーン印刷して焼成することにより、図7(d)に示すように、両表電極3,4の一部を接続部Cとして露出させた保護コート6を形成する(保護コート形成工程)。前述したように、これら接続部Cは絶縁基板2の側辺2a,2bと表電極3,4の傾斜辺部3a,4aとの間隔がほぼ最大となる部分であり、これら接続部Cにボンディングワイヤ10の一端部が接続されるようになっている。   Thereafter, a glass paste is screen-printed on a region covering the entire resistor 5 and most of the surface electrodes 3 and 4 and baked, as shown in FIG. A protective coat 6 in which a part of the protective coat 6 is exposed as the connection portion C is formed (protective coat forming step). As described above, these connection portions C are portions where the distances between the side edges 2a, 2b of the insulating substrate 2 and the inclined sides 3a, 4a of the surface electrodes 3, 4 are substantially maximized. One end of the wire 10 is connected.

次に、必要に応じて両表電極3,4の接続部Cと裏電極7にNiメッキやNi/Auメッキ等を施した後、集合基板2Aを1次分割溝と2次分割溝に沿って個片状に分割することにより、図1〜図4に示すようなチップ抵抗器1が得られる。   Next, after applying Ni plating, Ni / Au plating, or the like to the connecting portion C and the back electrode 7 of the front electrodes 3 and 4 as necessary, the collective substrate 2A is moved along the primary divided grooves and the secondary divided grooves. Then, the chip resistor 1 as shown in FIGS. 1 to 4 is obtained by dividing into pieces.

以上説明したように、本実施形態例に係るチップ抵抗器1では、一対の表電極3,4の平面形状が絶縁基板2の1つの側辺(2aまたは2b)を占める台形状に形成されており、これら表電極3,4の傾斜辺部3a,4aどうしが抵抗体5を介して互いに平行に対向配置されているため、電流の回り込みによって電流集中する部分がそれぞれの表電極3,4について1箇所(エッジ部E)だけとなり、抵抗体5の面積を広くして耐サージ性を向上させた上で、温度上昇に起因する負荷特性の悪化を抑制することができる。そして、電流集中によって温度上昇するエッジ部Eの周囲は、表電極3,4のうち絶縁基板2の側辺2a,2bと傾斜辺部3a,4aとの間隔がほぼ最大となる部位であり、当該部位をボンディングワイヤ10の接続部Cとしているため、チップ抵抗器1を回路基板8に搭載してワイヤボンディング接続した実装構造において、エッジ部Eの周囲で上昇した温度がボンディングワイヤ10を介して回路基板8側へ放熱され、放熱性と耐サージ性に優れたワイヤボンディング接続型のチップ抵抗器1を実現することができる。   As described above, in the chip resistor 1 according to this embodiment, the planar shape of the pair of front electrodes 3 and 4 is formed in a trapezoidal shape that occupies one side (2a or 2b) of the insulating substrate 2. In addition, since the inclined sides 3a and 4a of the surface electrodes 3 and 4 are arranged to face each other in parallel with each other via the resistor 5, a portion where current concentrates due to current wraparound is related to each of the surface electrodes 3 and 4. Only one location (edge portion E) is provided, and the area of the resistor 5 is increased to improve surge resistance, and deterioration of load characteristics due to temperature rise can be suppressed. The periphery of the edge portion E where the temperature rises due to the current concentration is a portion where the distance between the side edges 2a, 2b of the insulating substrate 2 and the inclined side edges 3a, 4a of the surface electrodes 3, 4 is substantially maximum. Since this portion is used as the connection portion C of the bonding wire 10, in the mounting structure in which the chip resistor 1 is mounted on the circuit board 8 and wire bonding is connected, the temperature that rises around the edge portion E is passed through the bonding wire 10. It is possible to realize the wire bonding connection type chip resistor 1 that is radiated to the circuit board 8 side and is excellent in heat dissipation and surge resistance.

また、本実施形態例に係るチップ抵抗器1では、絶縁基板2の裏面のほぼ全体に裏電極7が形成されているため、チップ抵抗器1を回路基板8に搭載してワイヤボンディング接続したとき、抵抗体5や表電極3,4の温度上昇がボンディングワイヤ10を介して回路基板8側へ放熱されるだけでなく、絶縁基板2の内部を伝わった熱が裏電極7から回路基板8側へも放熱されるため、より効果的に放熱性を高めることができる。   Further, in the chip resistor 1 according to the present embodiment example, since the back electrode 7 is formed on almost the entire back surface of the insulating substrate 2, when the chip resistor 1 is mounted on the circuit substrate 8 and wire-bonded. The temperature rise of the resistor 5 and the front electrodes 3 and 4 is not only radiated to the circuit board 8 side via the bonding wires 10, but the heat transmitted through the inside of the insulating substrate 2 is transferred from the back electrode 7 to the circuit board 8 side. Since heat is also radiated, heat dissipation can be improved more effectively.

なお、上記実施形態例では、一対の表電極3,4の平面形状を絶縁基板2の1つの側辺を占める台形状としたが、これら表電極3,4の平面形状を台形の代わりに直角三角形とすることも可能であり、要は、一対の表電極3,4が絶縁基板2の側辺2a,2bに対して傾斜方向へ延びる傾斜辺部3a,4aを有し、これら傾斜辺部3a,4aが抵抗体5を介して互いに平行に対向していれば良い。   In the above embodiment, the planar shape of the pair of front electrodes 3 and 4 is a trapezoid that occupies one side of the insulating substrate 2, but the planar shape of these front electrodes 3 and 4 is a right angle instead of the trapezoid. In short, the pair of front electrodes 3 and 4 have inclined side portions 3a and 4a extending in the inclined direction with respect to the side sides 2a and 2b of the insulating substrate 2, and these inclined side portions. It suffices that 3a and 4a face each other in parallel through the resistor 5.

また、上記実施形態例では、平行四辺形状に形成した抵抗体5の1組の対辺を表電極3,4の傾斜辺部3a,4aに重ね合わせるようにしたため、単純構造の印刷マスクを用いて抵抗体5を簡単かつ高精度に印刷形成することができるが、抵抗体5を平行四辺形以外の形状に形成することも可能である。例えば、抵抗体5の傾斜辺部3a,4aと重なる部分を直線状から段付き状に変更することで、抵抗体5の平面形状を保護コート6と同様に形成することも可能であり、要は、一対の表電極3,4に設定された接続部Cが抵抗体5と保護コート6に覆われずに露出していれば良い。   Further, in the above embodiment, since a pair of opposite sides of the resistor 5 formed in a parallelogram shape is superimposed on the inclined sides 3a and 4a of the surface electrodes 3 and 4, a printing mask having a simple structure is used. Although the resistor 5 can be printed and formed easily and with high accuracy, the resistor 5 can be formed in a shape other than a parallelogram. For example, the planar shape of the resistor 5 can be formed in the same manner as the protective coat 6 by changing the portion of the resistor 5 that overlaps the inclined sides 3a and 4a from a linear shape to a stepped shape. The connection part C set to a pair of surface electrodes 3 and 4 should just be exposed without being covered with the resistor 5 and the protective coat 6.

また、上記実施形態例では、絶縁基板2の裏面のほぼ全体に放熱電極としての裏電極7が形成されており、この裏電極7を回路基板8の接続ランド部9aに半田付けするようにしているが、この裏電極7は省略することも可能であり、その場合、チップ抵抗器1は接着剤を用いて回路基板8上に搭載すれば良い。   In the above embodiment, the back electrode 7 as a heat radiation electrode is formed on almost the entire back surface of the insulating substrate 2, and the back electrode 7 is soldered to the connection land portion 9 a of the circuit board 8. However, the back electrode 7 can be omitted. In this case, the chip resistor 1 may be mounted on the circuit board 8 using an adhesive.

また、上記実施形態例では、抵抗体ペーストをスクリーン印刷して抵抗体5が形成されているが、抵抗体材料は厚膜ペーストに限定されるものではなく、ニクロムや銅ニッケル等の金属板、金属箔、薄膜であっても良い。   Further, in the above embodiment, the resistor 5 is formed by screen printing the resistor paste, but the resistor material is not limited to the thick film paste, but a metal plate such as nichrome or copper nickel, It may be a metal foil or a thin film.

1 チップ抵抗器
2 絶縁基板
2a,2b 側辺
2A 集合基板を
3,4表電極
3a,4a 傾斜辺部
5 抵抗体
6 保護コート
7 裏電極(放熱電極)
8 回路基板
9 配線パターン
9a 接続ランド部
10 ボンディングワイヤ
11 半田ペースト
C 接続部
E エッジ部
DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulation board | substrate 2a, 2b Side 2A Collective board 3, 4 Front electrode 3a, 4a Inclined side part 5 Resistor 6 Protective coating 7 Back electrode (heat dissipation electrode)
8 Circuit board 9 Wiring pattern 9a Connection land portion 10 Bonding wire 11 Solder paste C Connection portion E Edge portion

Claims (5)

直方体形状の絶縁基板と、この絶縁基板の表面における相対向する側辺に沿って形成された一対の表電極と、これら両表電極に接続するように形成された抵抗体とを備え、一対の前記表電極がワイヤボンディング用電極となっているチップ抵抗器において、
一対の前記表電極にそれぞれ前記絶縁基板の側辺に対して傾斜方向へ延びる傾斜辺部を形成すると共に、これら両傾斜辺部どうしを前記抵抗体を介して互いに平行に対向配置し、前記表電極のうち、前記絶縁基板の側辺と前記傾斜辺部とのほぼ間隔が最大で、前記絶縁基板の表面における対角線上に位置する部位をボンディングワイヤの接続部としたことを特徴とするチップ抵抗器。
A rectangular parallelepiped insulating substrate, a pair of surface electrodes formed along opposite sides of the surface of the insulating substrate, and a resistor formed so as to be connected to both surface electrodes, In the chip resistor in which the surface electrode is an electrode for wire bonding,
The pair of front electrodes are formed with inclined side portions extending in the inclined direction with respect to the side sides of the insulating substrate, and both the inclined side portions are arranged opposite to each other in parallel through the resistor, A chip resistor characterized in that, among the electrodes, a portion located on a diagonal line on the surface of the insulating substrate is a bonding wire connecting portion having a maximum distance between the side of the insulating substrate and the inclined side. vessel.
請求項1の記載において、前記抵抗体の平面形状を平行四辺形とし、この抵抗体の対辺を前記表電極の前記傾斜辺部に略同一幅で重ね合わせたことを特徴とするチップ抵抗器。   2. The chip resistor according to claim 1, wherein a planar shape of the resistor is a parallelogram, and opposite sides of the resistor are overlapped with the inclined side portion of the surface electrode with substantially the same width. 請求項1または2の記載において、前記絶縁基板の裏面のほぼ全体に放熱電極が形成されていることを特徴とするチップ抵抗器。   3. The chip resistor according to claim 1, wherein a heat radiation electrode is formed on substantially the entire back surface of the insulating substrate. チップ抵抗器が、直方体形状の絶縁基板と、この絶縁基板の表面における相対向する側辺に沿って形成された一対の表電極と、これら両表電極に接続するように形成された抵抗体とを備えており、このチップ抵抗器が回路基板上に搭載されていると共に、前記回路基板に設けられた配線パターンと前記チップ抵抗器の前記表電極とがボンディングワイヤを介して接続されているチップ抵抗器の実装構造において、
一対の前記表電極にそれぞれ前記絶縁基板の側辺に対して傾斜方向へ延びる傾斜辺部を形成すると共に、これら両傾斜辺部どうしを前記抵抗体を介して互いに平行に対向配置し、前記表電極のうち、前記絶縁基板の側辺と前記傾斜辺部との間隔がほぼ最大で、前記絶縁基板の表面における対角線上に位置する部位を前記ボンディングワイヤの接続部としたことを特徴とするチップ抵抗器の実装構造。
A chip resistor includes a rectangular parallelepiped insulating substrate, a pair of surface electrodes formed along opposite sides of the surface of the insulating substrate, and a resistor formed so as to be connected to both surface electrodes. The chip resistor is mounted on the circuit board, and the wiring pattern provided on the circuit board and the surface electrode of the chip resistor are connected via a bonding wire. In the resistor mounting structure,
The pair of front electrodes are formed with inclined side portions extending in the inclined direction with respect to the side sides of the insulating substrate, and both the inclined side portions are arranged opposite to each other in parallel through the resistor, Of the electrodes, the chip is characterized in that a portion located on a diagonal line on the surface of the insulating substrate is used as a connecting portion of the bonding wire, with the gap between the side of the insulating substrate and the inclined side portion being substantially maximum. Resistor mounting structure.
請求項4の記載において、前記絶縁基板の裏面のほぼ全体に放熱電極が形成されていると共に、前記配線パターンに前記放熱電極よりも大きな外形を有する接続ランド部が形成されており、前記放熱電極を前記接続ランド部に半田付けした状態で前記チップ抵抗器が前記回路基板上に搭載されていることを特徴とするチップ抵抗器の実装構造。   5. The heat radiation electrode according to claim 4, wherein a heat radiation electrode is formed on substantially the entire back surface of the insulating substrate, and a connection land portion having an outer shape larger than the heat radiation electrode is formed on the wiring pattern. A chip resistor mounting structure, wherein the chip resistor is mounted on the circuit board in a state where the chip resistor is soldered to the connection land portion.
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