JP2016039495A - Imaging device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device in which image quality deterioration due to variation in the power supply voltage supplied to a solid imaging element can be reduced, and to provide a control method therefor.SOLUTION: An imaging device includes a solid imaging element having a capacitor CTs1 for holding optical signals outputted from a plurality of pixels, a capacitor CTn1 for holding noise signals outputted from a plurality of pixels, a capacitor CTs2 connected with a capacitor CTs1, and holding optical signals via the capacitor CTs1, and a capacitor CTn2 connected with a capacitor CTn1, and holding noise signals via the capacitor CTn1. The optical signals are held in the capacitor CTs2 at a timing of superposing noise of the same phase as the noise superposed when the noise signal is held in the capacitor CTn1, and the noise signals are held in the capacitor CTn2 at a timing of superposing noise of the same phase as the noise superposed when the optical signal is held in the capacitor CTs1.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an imaging apparatus having a solid-state imaging device and a control method thereof.

  In general, in an imaging apparatus such as a digital camera, a solid-state imaging device such as a CCD or CMOS image sensor is used, and an electric signal output from the solid-state imaging device according to an optical image is recorded as a still image or a moving image.・ Playing. In an imaging device using a CMOS image sensor as a solid-state image sensor, the charge generated in the photodiode of the CMOS image sensor is converted into a signal voltage by a readout circuit according to the optical image at the time of shooting, and the signal voltage is amplified. And output from the output terminal.

  In such an imaging apparatus, various noises that cause image quality degradation occur in the process of converting an optical image into an electrical signal and outputting the electrical signal by a solid-state imaging device. Typical noise includes noise due to pixel defects generated due to manufacturing variation for each pixel, fixed pattern noise due to manufacturing variation of components such as an amplifier constituting the readout circuit, and the like. Furthermore, random noise that changes every time an imaging operation such as reset noise of pixels and readout circuits and dark current generated in the pixel region is performed is also known as representative noise.

  As a method for removing the noise as described above inside the solid-state imaging device, “SN operation” as described below is known (for example, see Patent Document 1). First, after resetting the photodiode in the pixel, the solid-state imaging device is exposed to perform photoelectric conversion and charge accumulation in the photodiode. Then, in accordance with the timing when the exposure of the solid-state imaging device is completed, the photodiode rear-stage circuit in the pixel (hereinafter, also referred to as “rear-stage circuit”) and the readout circuit are reset except for the photodiode.

  When the reset is completed, a signal at a pixel reset level is transferred as a noise component to the first line memory of the readout circuit without outputting the charge accumulated in the photodiode to the subsequent circuit, and the noise component is Hold in the first line memory. Hereinafter, the noise component signal is also referred to as “N signal”, and the transfer operation of the N signal is also referred to as “N transfer”. Subsequently, the charge accumulated as an optical signal in the photodiode is output to the subsequent circuit and held in the second line memory included in the reading circuit. Hereinafter, the optical signal is also referred to as “S signal”, and the transfer of the S signal is also referred to as “S transfer”.

  After the S transfer is completed, the S signal held in the second line memory and the N signal held in the first line memory are sequentially sent to the last output circuit block. Finally, the difference between the S signal and the N signal is obtained by a differential circuit provided in the output circuit block or the like. This difference signal is sent as an image signal to an image processing circuit at the subsequent stage of the solid-state imaging device. Among the operations described above, the N transfer, the S transfer, and the difference calculation operation between the N signal and the S signal are the outline of an operation generally called an SN operation. By performing the above-described SN operation, it is possible to appropriately remove noise components that differ for each pixel and readout circuit and obtain an image signal with good image quality at every imaging operation.

JP 2004-134752 A

  However, when the above-described SN operation is performed, a new noise component may be generated and the image quality may be deteriorated. If the power supply and GND (ground) supplied to the solid-state image sensor are always stable, and the power supply voltage is constant during N transfer and S transfer, excessive and insufficient noise components are obtained by performing SN operation. Can be removed. However, the power supply voltage supplied to the solid-state image sensor varies due to a load variation outside the solid-state image sensor.

  If the power supply voltage supplied to the solid-state imaging device fluctuates between N transfer and S transfer, different level offsets are superimposed at each timing of N transfer and S transfer. If the difference between the S signal and the N signal is calculated in this state, the difference between the offset superimposed on the N signal and the offset superimposed on the S signal appears as new noise in the image signal, degrading the image quality. End up.

  In general, the SN operation is performed at the same timing with respect to signals of pixel groups arranged in the same pixel row. Therefore, the same level offset is superimposed on the N signals from the pixels in the same row, and the same level offset different from the level superimposed on the N signals is superimposed on the S signals from the pixels in the same row. Will be. That is, the noise resulting from the difference between the offset superimposed on the N signal and the offset superimposed on the S signal is the same level between pixels in the same row, and appears as horizontal stripe pattern noise in the image.

  An object of the present invention is to provide an imaging apparatus capable of reducing image quality degradation caused by fluctuations in power supply voltage supplied to a solid-state imaging device, and a control method therefor.

  An imaging apparatus according to the present invention includes a plurality of pixels, a first optical signal holding unit that holds optical signals output from the plurality of pixels, and a first that holds noise signals output from the plurality of pixels. Noise signal holding means, second optical signal holding means connected to the first optical signal holding means and holding the optical signal via the first optical signal holding means, and the first noise A solid-state imaging device connected to the signal holding means and having a second noise signal holding means for holding the noise signal via the first noise signal holding means; and the noise to the first noise signal holding means The second optical signal holding unit holds the optical signal at a timing at which noise having the same phase as the superimposed noise is held, and the first optical signal holding unit holds the optical signal. Superimposed when holding And a controlling means for noise size and same phase to hold the noise signal to said second noise signal holding means at a timing to be superimposed.

  According to the present invention, it is possible to cancel noise generated between a light signal and a noise signal due to fluctuations in a power supply voltage supplied to a solid-state imaging device, and to reduce image quality deterioration due to fluctuations in the supplied power supply voltage. it can.

It is a figure which shows the structural example of the imaging device which concerns on embodiment of this invention. It is an equivalent circuit diagram which shows the structural example of the solid-state image sensor in this embodiment. It is a timing chart for demonstrating the signal read-out operation | movement of the solid-state image sensor in this embodiment. It is a figure which shows the determination method of the drive timing of the 2nd vertical transfer period in 1st Embodiment. It is a figure which shows the determination method of the drive timing of the 2nd vertical transfer period in 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to an embodiment of the present invention. The imaging apparatus according to the present embodiment includes a solid-state imaging element 3. The lens 1 forms an optical image of the subject on the solid-state image sensor 3. The diaphragm 2 changes the amount of light that has passed through the lens 1. The solid-state image sensor 3 converts an optical image into an electrical signal (image signal) by photoelectric conversion and outputs the electrical signal.

  An image signal (also referred to as an imaging signal) output from the solid-state imaging device 3 is supplied to the imaging signal processing circuit 4. The imaging signal processing circuit 4 has a variable gain amplifier for amplifying the image signal and a gain correction circuit for correcting the gain value. The image signal output from the imaging signal processing circuit 4 is A / D converted by an analog-digital (A / D) converter 5 and supplied to the signal processor 6 as image data.

  The signal processing unit 6 performs various corrections on the image data output from the A / D conversion unit 5 and performs data compression as necessary. Various timing pulses are supplied from the timing generation unit 13 to the solid-state imaging device 3, the imaging signal processing circuit 4, the A / D conversion unit 5, and the signal processing unit 6.

  The overall control / arithmetic unit 12 performs various calculations and controls the imaging apparatus. The memory unit 7 temporarily stores image data. An external interface (I / F) unit 10 communicates with an external device 11 such as an external computer, for example. Note that the external I / F unit 10 can also perform wireless communication with the external device 11 such as transmitting image data via the wireless unit 18.

  A recording medium 9 can be attached to and detached from the recording medium control interface (I / F) unit 8. When the recording medium 9 is attached to the recording medium control I / F unit 8, image data is recorded on and read from the recording medium 9 by the recording medium control I / F unit 8. The recording medium 9 is composed of, for example, a semiconductor memory.

  The strobe unit 14 performs AF (autofocus) auxiliary light projection and flash light control. The power supply circuit 15 includes a DC / DC circuit that converts a voltage supplied from a battery or the like as a power supply means into a desired voltage, and includes each part including the recording medium 9 for a required period of time in the imaging apparatus for a necessary period. To supply. The lens barrel of the lens 1 is driven by a motor 16 under the control of the overall control / arithmetic unit 12, and the diaphragm 2 is driven by a motor 17.

  In the imaging apparatus having the above-described configuration, devices and components that can be a noise source that fluctuates the power supply voltage supplied to the solid-state imaging device 3 are in the vicinity of the solid-state imaging element, that is, in the imaging apparatus or in the vicinity of the imaging apparatus. Has been placed. For example, to communicate with an external device 11 such as a strobe 14, a DC / DC circuit of a power supply circuit 15, motors 16 and 17 for driving a lens barrel or a diaphragm 2 of the lens 1, or a computer. External I / F unit 10 and wireless unit 18.

  When each part that can be a noise source operates, power fluctuations and electromagnetic waves with a predetermined period are generated as each part is driven, and the power supply voltage supplied to the solid-state imaging device 3 becomes unstable due to the influence. When such power supply fluctuations or electromagnetic waves occur during signal readout of the solid-state image sensor, the potential of the power source supplied to the solid-state image sensor changes with time, causing noise in the read pixel signal and improving image quality. It will deteriorate. In addition to the devices and components shown in FIG. 1, devices and components that can change the power supply of the imaging apparatus and the magnetic field around the solid-state imaging device by operation can be noise sources.

  FIG. 2 is a diagram showing an equivalent circuit diagram of the solid-state imaging device 3 shown in FIG. Each of the transistors shown in FIG. 3 is, for example, a MOS (Metal Oxide Semiconductor) transistor. Each circuit element constituting the solid-state imaging element 3 is formed on one semiconductor substrate such as single crystal silicon by a semiconductor integrated circuit manufacturing technique. Here, the number of rows and the number of columns of the pixel array are assumed to be n rows × m columns (each of n and m is an integer of 2 or more).

  The solid-state imaging device 3 has a plurality of unit pixels 300 arranged in a two-dimensional matrix, and a pixel unit is configured by these unit pixels 300. The unit pixel 300 includes a photodiode PD, and the photodiode PD receives light and generates an optical signal that is an electrical signal. In the illustrated example, the anode of the photodiode PD is grounded. The cathode of the photodiode PD is connected to the gate of the amplification transistor MAmp through a transfer transistor MTx for transferring the optical signal charge accumulated in the photodiode PD. The gate of the amplification transistor MAmp is connected to the source of the reset transistor MRes for resetting the amplification transistor MAmp, and the drain of the reset transistor MRes is connected to the reset power source. The drain of the amplification transistor MAmp is directly connected to the power supply.

  The gate of the transfer transistor MTx in the unit pixel 300 in the i-th row (1 ≦ i ≦ n) is connected to a pixel signal transfer line PTxi arranged extending in the horizontal direction. The gate of the reset transistor MRes in the unit pixel 300 in the i-th row is connected to a pixel reset line PREsi arranged extending in the horizontal direction. The gate of the selection transistor MSel in the unit pixel 300 in the i-th row is connected to a pixel selection line PSeli arranged extending in the horizontal direction. The pixel signal transfer line PTxi, the pixel reset line PREsi, and the pixel selection line PSeli are connected to the vertical scanning circuit (VSR) block 302.

  The pixel signal transfer line PTxi is supplied with a control pulse (pixel signal transfer pulse) generated by the vertical scanning circuit block 302 for controlling the transfer of the pixel signal at a timing described later. A control pulse (pixel reset pulse) generated by the vertical scanning circuit block 302 and used to control resetting of the unit pixel 300 is supplied to the pixel reset line PREsi at a timing described later. To the pixel selection line PSeli, a control pulse (pixel selection pulse) for selecting a pixel row generated by the vertical scanning circuit block 302 and performing signal transfer is supplied at a timing described later.

  The source of the amplification transistor MAmp in the unit pixel 300 in the j-th column (1 ≦ j ≦ m) is connected via a selection transistor MSel to a vertical (column direction) output line VLj arranged extending in the vertical direction. The vertical output line VLj is connected to the constant current source I and to the clamp capacitor C0. The clamp capacitor C0 is connected to the inverting input terminal of the operational amplifier 301. An output terminal is connected to the inverting input terminal of the operational amplifier 301 via a feedback capacitor Cf. In parallel with the feedback capacitor Cf, a capacitor reset transistor MC0R for discharging each capacitor connected to the operational amplifier 301 is connected. The non-inverting input terminal of the operational amplifier 301 is connected to the clamp voltage VC0R (VREF).

  The output terminal of the operational amplifier 301 is connected to a capacitor CTn1 (first noise signal holding means) for temporarily holding a noise signal (reference signal of the imaging signal) via the first noise signal transfer transistor MTn1. The output terminal of the operational amplifier 301 is connected to a capacitor CTs1 (first optical signal holding means) for temporarily holding an optical signal (imaging signal) via the first optical signal transfer transistor MTs1. The terminals on the opposite side of the capacitors CTn1 and CTs1 are connected to a reference potential (GND). Note that the GND to which the terminals on the opposite side of the capacitors CTn1 and CTs1 are connected is connected to other GNDs with high impedance, and the power supply level is likely to fluctuate.

  A connection point between the first noise signal transfer transistor MTn1 and the capacitor CTn1 is connected to a capacitor CTn2 (second noise signal holding means) for temporarily holding the noise signal via the second noise signal transfer transistor MTn2. Is done. A connection point between the first optical signal transfer transistor MTs1 and the capacitor CTs1 is connected to a capacitor CTs2 (second optical signal holding unit) for temporarily holding an optical signal via the second optical signal transfer transistor MTs2. Is done. The terminals on the opposite side of the capacitors CTn2 and CTs2 are grounded.

  A connection point between the second noise signal transfer transistor MTn2 and the capacitor CTn2 and a connection point between the second optical signal transfer transistor MTs2 and the capacitor CTs2 are respectively connected to the horizontal output lines OUTn, MCHn and MCHs, respectively. Connected to OUTs. The horizontal output lines OUTn and OUTs transmit a noise signal and an optical signal to a subsequent circuit (not shown). A subsequent circuit (not shown) is provided with a differential means capable of performing a differential operation between the noise signal (N signal) and the optical signal (S signal), and performs differential processing between the noise signal and the optical signal. .

  The gates of the first noise signal transfer transistors MTn1 in each column are commonly connected to the first noise signal transfer line PTn1, and a control pulse (first noise signal transfer pulse) is supplied at a timing described later. The gates of the first optical signal transfer transistors MTs1 in each column are commonly connected to the first optical signal transfer line PTs1, and a control pulse (first optical signal transfer pulse) is supplied at a timing described later.

  The gates of the second noise signal transfer transistors MTn2 in each column are commonly connected to the second noise signal transfer line PTn2, and a control pulse (second noise signal transfer pulse) is supplied at a timing described later. The gates of the second optical signal transfer transistors MTs2 in each column are commonly connected to the second optical signal transfer line PTs2, and a control pulse (second optical signal transfer pulse) is supplied at a timing described later. The gates of the horizontal transfer transistors MCHn and MCHs in the j-th column are connected to the horizontal scanning circuit (HSR) block 303 via the column selection line PHj, and a control pulse (horizontal transfer pulse) is supplied for each column at a timing described later. The

  FIG. 3 is a timing chart showing drive timings for explaining the signal readout operation of the solid-state imaging device 3 in the present embodiment. Here, the signal reading operation from the first row to the n-th row in the pixel region in the solid-state imaging device 3 is defined as one frame. At this time, the signal readout operation for one frame starts from the first row of the pixel region to be read out, the first row, the second row,..., (I−1) th row, ith row, (i + 1) It is assumed that the processing is performed in the order of the line,.

  With reference to FIG. 2 and FIG. 3, focusing on the i-th row of the solid-state imaging device 3, the reading operation will be described. In the following description, it is assumed that each transistor is turned on (becomes conductive) when an “H” (high level) control pulse is input to the gate of each transistor included in the solid-state imaging device 3.

  First, as a first vertical transfer period, a pixel in the i-th row is selected, a noise signal (reference signal of imaging signal, N signal) is held in the capacitor CTn1, and an optical signal (imaging signal, S signal) is held in the capacitor CTs1. The operation until holding is described. At time T1, the line feed pulse PV is input to the vertical scanning circuit (VSR) 302 as a trigger clock signal. At the moment when the line feed pulse PV becomes “H”, the line feed of the pixel row selected as the read target is performed, and the read target moves from the pixel in the (i−1) -th row to the pixel in the i-th row. At time T2, the pixel selection pulse PSeli becomes “H”, the selection transistor MSel of the i-th row pixel is turned on, and the i-th row pixel 300 is connected to the vertical output line VLj corresponding to each pixel column. Is done.

  At time T3, the pixel reset pulse PREsi becomes “L”, the reset of the floating diffusion portion of the pixel 300 in the i-th row is released, and the reset level of the floating diffusion portion is determined. At time T4, the first optical signal transfer pulse PTs1 and the first noise signal transfer pulse PTn1 become “H”, and resetting of the capacitors CTs1 and CTn1 is started. At time T5, the first optical signal transfer pulse PTs1 and the first noise signal transfer pulse PTn1 become “L”, and the resetting of the capacitors CTs1 and CTn1 is completed. At time T6, the clamp pulse PC0R becomes “L”, and the reset of the clamp capacitor C0 is completed.

  At time T7, the first noise signal transfer pulse PTn1 becomes “H”, and the potential (voltage) of the floating diffusion portion of the pixel 300 is output to the capacitor CTn1. At time T8, the first noise signal transfer pulse PTn1 becomes “L”, and the potential (voltage) of the floating diffusion portion at this time is held in the capacitor CTn1 as a noise signal.

  At time T9, the first optical signal transfer pulse PTs1 becomes “H”, and the potential (voltage) of the floating diffusion portion of the pixel 300 is output to the capacitor CTs1. The pixel signal transfer pulse PTxi becomes “H” at time T10 during a period in which the first optical signal transfer pulse PTs1 is “H”. When the pixel signal transfer pulse PTxi becomes “H”, the transfer transistor MTx of the pixel in the i-th row is turned on, and the charge accumulated in the photodiode PD of the pixel in the i-th row is transferred to the floating diffusion portion. Is done.

  At time T11, the pixel signal transfer pulse PTxi becomes “L”, the transfer transistor MTx is turned off, and charge transfer from the photodiode PD to the floating diffusion portion is completed. After waiting for the operational amplifier 301 to respond to the potential fluctuation corresponding to the amount of charge transferred from the photodiode PD of the pixel of the vertical output line VLj, the operation proceeds to the next operation. At time T12, the first optical signal transfer pulse PTs1 becomes “L”, and a potential (voltage) corresponding to the amount of charge accumulated in the floating diffusion portion at this time is held in the capacitor CTs1 as an optical signal.

  The operation performed during the period of time T1 to T12 described above selects the pixel in the i-th row as the first vertical transfer period, holds the noise signal in the capacitor CTn1, and holds the optical signal in the capacitor CTs1. It is operation until.

  After the first vertical transfer period, the pixel reset pulse PREsi becomes “H” at time T13, and resetting of the floating diffusion portion is started. Note that the reset of the floating diffusion portion may be performed at an arbitrary timing after the end of the first vertical transfer period and before the deselection of an i-th pixel row (time T19) described later. At time T14, the clamp pulse PC0R becomes “H”, and reset of the clamp capacitor C0 is started. The clamp capacitor is reset after the first vertical transfer period is over, and the row feed pulse PV is input to the vertical scanning circuit (VSR) 302 in order to set the next row (here, i + 1th row) as a reading target. It may be performed at an arbitrary timing before being performed.

  Next, as the second vertical transfer period, the noise signal (reference signal of imaging signal, N signal) held in the capacitor CTn1 is held in the capacitor CTn2, and the optical signal (imaging signal, S signal) held in the capacitor CTs1 Will be described until the capacitor CTs2 is held. At time T15, the signal holding capacitor reset pulse PCTR becomes “H”, and resetting of the capacitors CTn2 and CTs2 is started. At time T16, the signal holding capacitor reset pulse PCTR becomes “L”, and the resetting of the capacitors CTn2 and CTs2 is completed.

  At time T17, the second optical signal transfer pulse PTs2 becomes “H”, and the capacitors CTs1 and CTs2 are connected. At time T18, the second optical signal transfer pulse PTs2 becomes “L”, and the optical signal held in the capacitor CTs1 is held in the capacitor CTs2. At time T20, the second noise signal transfer pulse PTn2 becomes “H”, and the capacitor CTn1 and the capacitor CTn2 are connected. At time T21, the second noise signal transfer pulse PTn2 becomes “L”, and the noise signal held in the capacitor CTn1 is held in the capacitor CTn2.

  The operation performed during the period of time T15 to T21 described above is performed as the second vertical transfer period, the noise signal held in the capacitor CTn1 is held in the capacitor CTn2, and the optical signal held in the capacitor CTs1 is held in the capacitor CTs2. This is the operation until holding.

  Details of how to determine the timing of each operation in the second vertical transfer period will be described later. Here, at time T19, the pixel selection pulse PSeli is set to “L” to turn off the selection transistor MSel of the pixel in the i-th row to cancel the selection of the pixel in the i-th row. Is not essential during the second vertical transfer period. This operation is performed after the first vertical transfer period ends, rather than when the row feed pulse PV is input to the vertical scanning circuit (VSR) 302 in order to set the next row (here, i + 1th row) as a reading target. It may be performed at any previous timing.

  Next, as a horizontal transfer period, the noise signal (reference signal of the imaging signal, N signal) held in the capacitor CTn2 and the optical signal (imaging signal, S signal) held in the capacitor CTs2 are transferred to the subsequent circuit. The operation until output will be described. After the second vertical transfer period, when the column feed pulse PH is input to the horizontal scanning circuit (HSR) 303 as a trigger clock signal, the column transfer pulse is sequentially selected from the first column to the last column in the readout region. Is input. Therefore, the signals held in the capacitors CTs2 and CTn2 are sequentially sent to the horizontal output lines OUTs and OUTn one column at a time from time T22 to time T23, and output to the subsequent circuit. The operation performed during the period of time T22 to T23 described above is an operation until the noise signal held in the capacitor CTn2 and the optical signal held in the capacitor CTs2 are output to the subsequent circuit as a horizontal transfer period. It is.

  A series of operations in the first vertical transfer period, the second vertical transfer period, and the horizontal transfer period described above is a signal read operation for one row of pixels in the i-th row. By repeating this operation, signal reading for one frame is performed. Note that when the second vertical transfer period of the i-th row ends, the optical signal of the pixel of the i-th row is held in the capacitor CTs2, and the noise signal of the pixel of the i-th row is held in the capacitor CTn2. Therefore, the capacitors CTs1 and CTn1 can be reset to hold signals from the pixels in the next row (i + 1 row). That is, as shown in FIG. 3, the operation in the i-th horizontal transfer period and the operation in the (i + 1) -th first vertical transfer period can be performed in parallel.

  4A to 4C are conceptual diagrams illustrating a method for determining the drive timing of each operation in the first vertical transfer period to the second vertical transfer period. Here, before describing the method for determining the drive timing of each operation in the second vertical transfer period, noise generation due to fluctuations in the reference potential input to the solid-state imaging device 3 with reference to FIG. Describe the mechanism.

  The image pickup apparatus shown in FIG. 1 has many elements that can be a noise source that fluctuate the power supply voltage supplied to the solid-state image pickup device 3 in or near the inside as described above. When these devices and the like operate, the power supply voltage supplied to the solid-state imaging device 3 becomes unstable due to power fluctuations or electromagnetic waves in a predetermined cycle due to the operation. In addition, each noise source produces electromagnetic waves and power supply fluctuations that are noises with a specific period. In the solid-state imaging device 3 shown in FIG. 2, the GND to which the capacitor CTn1 and the capacitor CTs1 are connected is connected to other GND with high impedance, and the power supply level is likely to fluctuate.

  In FIG. 4A, Vin schematically shows that the power supply voltage supplied to the GND to which the capacitor CTn1 and the capacitor CTs1 are connected varies depending on the noise source. Here, consider a case where the noise source operates during signal readout of the solid-state image sensor, and the power supply voltage Vin supplied to the solid-state image sensor fluctuates at a frequency f1 [Hz] as shown in FIG. .

As described above, the noise signal is held in the capacitor CTn1 at time T8. At this time, the noise signal is held in the capacitor CTn1 in a state where the amplitude Vrn1 of the power supply voltage Vin at that time is superimposed as noise. Become. At time T12, the optical signal is held in the capacitor CTs1, and at this time, the optical signal is held in the capacitor CTs1 with the amplitude Vrs1 of the power supply voltage Vin at that time superimposed as noise. Since the power supply voltage Vin fluctuates between time T8 and time T12, between the noise signal held in the capacitor CTn1 and the optical signal held in the capacitor CTs1,
(Vrs1-Vrn1)
This corresponds to the occurrence of noise.

At time T18a, the optical signal is held in the capacitor CTs2. At this time, the optical signal is held in the capacitor CTs2 with the amplitude Vrs2 of the power supply voltage Vin at that time superimposed as noise. At time T21a, the noise signal is held in the capacitor CTn2. At this time, the noise signal is held in the capacitor CTn2 in a state where the amplitude Vrn2 of the power supply voltage Vin at that time is superimposed as noise. Since the power supply voltage Vin varies between the time T18a and the time T21a, between the noise signal held in the capacitor CTn2 and the optical signal held in the capacitor CTs2,
(Vrs2-Vrn2)
This corresponds to the occurrence of noise.

Therefore, the final signals output from the capacitors CTs2 and CTn2 are
(Vrs1-Vrn1) + (Vrs2-Vrn2)
Noise will occur. When this value changes for each pixel row, the noise appears as horizontal stripe pattern noise in the image signal. The above is the mechanism of noise generation due to fluctuations in the power supply voltage input to the solid-state imaging device.

Next, with reference to FIG. 4A, a method for determining the drive timing of each operation in the second vertical transfer period for reducing such noise will be described. In order to reduce the noise as described above,
| (Vrs1-Vrn1) + (Vrs2-Vrn2) |
The signal may be held in the capacitor CTs2 and the capacitor CTn2 at a timing at which the value becomes the minimum.

  Note that the longer the interval between the time T8 when the noise signal is held in the capacitor CTn1 and the time T12 when the optical signal is held in the capacitor CTs1, the darker current is generated between the time T8 and the time T12 due to the dark current generated in the pixel. A difference in current noise occurs. Therefore, it is not preferable to make the interval between time T8 and time T12 longer than necessary. On the other hand, for the time T12, it is necessary to secure and set a period until the operational amplifier 301 sufficiently responds to the maximum potential fluctuation of the vertical output line VLj. Therefore, the interval between time T8 and time T12 is set to a period that is not excessive or insufficient in order for the operational amplifier 301 to sufficiently respond to the maximum potential fluctuation of the vertical output line VLj.

Therefore, for the noises Vrn1 and Vrs1 superimposed on the power supply voltage at the drive timing set in this way,
| (Vrs1-Vrn1) + (Vrs2-Vrn2) |
The timing of signal holding in the capacitors CTs2 and CTn2 is determined so that the noises Vrs2 and Vrn2 that minimize the value of are held.

  For example, in a state where all devices that may be driven during the signal reading operation of the solid-state image sensor 3 are driven, signals are read from the solid-state image sensor, and a drive pattern that minimizes noise is determined and imaged. You can memorize it in the device. Specifically, signals are read from the solid-state image sensor while all devices that may be driven during the signal readout operation of the solid-state image sensor are driven. This is repeated while changing the signal holding timing in the capacitors CTs2 and CTn2.

  As described above, the noise component | (Vrs1−Vrn1) + (Vrs2−Vrn2) | appears as horizontal stripe noise in the image signal. Therefore, for example, if the mapping in the row direction is obtained from the obtained image signal, and the driving pattern when the image having the minimum mapping amplitude is acquired is selected as the driving pattern with the least noise. Good. Alternatively, the waveform or fluctuation frequency of the power supply voltage supplied to the solid-state imaging device is measured in a state where all devices that may be driven during the signal readout operation of the solid-state imaging device are driven, or by simulation or the like Ask. A drive pattern that minimizes noise may be determined by calculation from the obtained waveform and fluctuation frequency, and stored in the imaging device in advance before the imaging device is shipped.

There are the following methods as a method for obtaining a drive pattern that minimizes the noise by calculation from the fluctuating frequency obtained by measurement or simulation. For example, when the power supply voltage Vin fluctuates at the frequency f1 [Hz], as shown in FIG. 4A, the holding timing interval ΔT1 between the capacitors CTn1 and CTs2 is the fluctuation cycle 1 / f1 [s of the power supply voltage Vin. ] Is determined so as to be an integral multiple of the timing T18a.
ΔT1 = T18a−T8 = k × (1 / f1) (k = integer)
Further, the timing T21a is determined so that the holding timing interval ΔT2 of the capacitors CTs1 and CTn2 is an integral multiple of the fluctuation period 1 / f1 [s] of the power supply voltage Vin.
ΔT2 = T21a−T12 = 1 × (1 / f1) (1 = integer)

  In the example shown in FIGS. 4B and 4C, the method for determining the holding timing of the capacitor CTs2 and the holding timing of the capacitor CTn2 is the same as that in FIG. That is, the timings T18b and T18c are determined so that the holding timing interval ΔT1 of the capacitors CTn1 and CTs2 is an integral multiple of the fluctuation period 1 / f1 [s] of the power supply voltage Vin. Further, the timings T21b and T21c are determined so that the holding timing interval ΔT2 of the capacitors CTs1 and CTn2 is an integral multiple of the fluctuation period 1 / f1 [s] of the power supply voltage Vin. However, while l = k in FIG. 4A, l ≠ k as shown in FIGS. 4B and 4C. Note that in FIG. 4C, the order of the holding timing of the capacitor CTs2 and the holding timing of the capacitor CTn2 is reversed from the example shown in FIGS. 4A and 4B. Either the holding in CTs2 or the holding in the capacitor CTn2 may be performed first. The above is the method for determining the drive timing of each operation in the second vertical transfer period.

  By doing so, the holding timing T8 of the capacitor CTn1 and the holding timing T18 of the capacitor CTs2 are set in the same phase with respect to the fluctuation of the power supply voltage, and the noises Vrn1 and Vrs2 superimposed on the reference voltage become the same level. . Further, the holding timing T12 of the capacitor CTs1 and the holding timing T21 of the capacitor CTn2 are set in the same phase with respect to the fluctuation of the power supply voltage, and the noises Vrs1 and Vrn2 superimposed on the reference voltage are at the same level. Therefore, noise generated between the noise signal held in the capacitor CTn2 and the optical signal held in the capacitor CTs2 generates between the noise signal held in the capacitor CTn1 and the optical signal held in the capacitor CTs1. Can cancel the noise. That is, (Vrs1-Vrn1) + (Vrs2-Vrn2) = (Vrs1-Vrn2) + (Vrs2-Vrn1) = 0. Therefore, according to the drive timing determined by the method described in the present embodiment, it is possible to reduce image quality degradation caused by fluctuations in the power supply voltage supplied to the solid-state imaging device.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. Hereinafter, a driving timing determination method for reducing image quality degradation caused by fluctuations in the power supply voltage supplied to the solid-state imaging device according to the second embodiment will be described. In the present embodiment, the imaging apparatus has a plurality of noise sources, and each noise source operates in a plurality of combinations different from each other at each timing. In addition, it is assumed that the period of noise generated by each noise source is different.

  In the present embodiment, in such an imaging apparatus, a plurality of solid-state imaging element drive patterns suitable for noise reduction are prepared for each combination of noise sources operating simultaneously. A suitable drive pattern is selected according to which noise source is operating. This is the difference between the second embodiment and the first embodiment. Since the configuration of the imaging apparatus according to the present embodiment is the same as the configuration of the imaging apparatus according to the first embodiment illustrated in FIG. 1, description thereof is omitted. In addition, the configuration and basic drive timing of the solid-state imaging device in the present embodiment are the same as the configuration of the solid-state imaging device in the first embodiment shown in FIG. 2 and the solid-state imaging device in the first embodiment shown in FIG. Since this is the same as the drive timing, the description is omitted.

  In the imaging apparatus having the configuration as shown in FIG. 1, equipment or components that can be a noise source that fluctuates the power supply voltage supplied to the solid-state imaging element 3 are in the vicinity of the solid-state imaging element, that is, inside the imaging apparatus or imaging apparatus. Located in the immediate vicinity. For example, to communicate with an external device 11 such as a strobe 14, a DC / DC circuit of a power supply circuit 15, motors 16 and 17 for driving a lens barrel or a diaphragm 2 of the lens 1, or a computer. External interface unit 10 and wireless unit 18. In addition to the devices and components shown in FIG. 1, devices and components that can change the power supply of the imaging apparatus and the magnetic field around the solid-state imaging device by operation can be noise sources.

  Since these noise sources generate power fluctuations and electromagnetic waves with a specific period for each noise source, the fluctuation period of the power supplied to the solid-state imaging device differs depending on which noise source is operating. Become. The drive timing suitable for reducing noise caused by fluctuations in the power supply voltage supplied to the solid-state image sensor varies depending on the fluctuation frequency of the power supply voltage supplied to the solid-state image sensor. Therefore, in the present embodiment, when reading a signal from the solid-state imaging device, a driving pattern suitable for reducing noise is selected according to which noise source is operating.

  For example, in addition to a noise source such as a DC / DC circuit that is constantly operating in the power supply circuit 15, the first noise source other than the noise source operates, so that the power supply voltage supplied to the solid-state image sensor is a frequency. It fluctuates at f1 [Hz]. At this time, as shown in FIG. 4A, for example, the holding timing T18a of the capacitor CTs2 and the holding of the capacitor CTn2 are canceled so as to cancel the noise generated between the holding timing T8 of the capacitor CTn1 and the holding timing T12 of the capacitor CTs1. Timing T21a is determined. This is stored in the imaging apparatus as the first drive timing.

  In addition to a noise source that is always operating, such as a DC / DC circuit of the power supply circuit 15, a second noise source that is different from the first noise source is operated to supply the solid-state imaging device. Assume that the power supply voltage fluctuates at a frequency f2 [Hz]. At this time, for example, as shown in FIG. 5, the holding timing T18d of the capacitor CTs2 and the holding timing T21d of the capacitor CTn2 are determined so as to cancel out noise generated between the holding timing T8 of the capacitor CTn1 and the holding timing T12 of the capacitor CTs1. To do. This is stored in the imaging apparatus as the second drive timing.

  And when reading a signal from a solid-state image sensor, the operation of determining whether or not each noise source is operating is performed before starting the reading. When the signal is read from the solid-state imaging device, if the first noise source is operating, the signal is read at the first drive timing, and if the second noise source is operating, the second noise source is operating. The signal is read out according to the drive timing. By doing so, it is possible to drive the solid-state imaging device with an appropriate driving pattern according to the combination of operating noise sources, and to reduce image quality degradation due to fluctuations in the power supply voltage supplied to the solid-state imaging device. .

  Although two examples of frequencies have been described, different timings may be stored for each combination of noise sources that operate simultaneously, and drive timings to be used may be selected according to the results of operation determination of each noise source. For example, the imaging apparatus having the configuration shown in FIG. 1 communicates with the strobe 14, the DC / DC circuit of the power supply circuit 15, the motors 16 and 17 for driving the lens barrel and the diaphragm 2 of the lens 1, and the external device 11. The external I / F unit 10 and the wireless unit 18 for performing the above are noise sources. Therefore, in addition to the DC / DC circuit of the power supply circuit 15, noise reduction is performed for each of the motors 16 and 17, the strobe 14, and the external I / F unit 10 and the wireless unit 18. A suitable drive pattern may be stored. Then, the drive timing to be used may be selected according to the result of the operation determination of each noise source.

  A method for obtaining a drive pattern that minimizes noise is the same as in the first embodiment. If devices such as a lens, strobe, and wireless unit are replaceable, a drive pattern suitable for noise reduction may be stored for each connectable device. Then, information that can acquire the frequency of the noise source of the connected device is acquired by communication, and the drive timing to be used when each device operates is selected. When the frequency of the noise source of the connected device cannot be acquired through communication, the noise sources connected as pre-photographing are driven and stored for each combination of simultaneously operating noise sources before the main shooting. A shaded image is acquired at each driving timing. Then, the drive timing with the least noise may be selected as the drive pattern when the corresponding device operates according to the combination of noise sources that operate simultaneously.

(Third embodiment)
Next, a third embodiment of the present invention will be described. Hereinafter, a driving timing determination method for reducing image quality degradation caused by fluctuations in the power supply voltage supplied to the solid-state imaging device according to the third embodiment will be described. Since the configuration of the imaging apparatus according to the present embodiment is the same as the configuration of the imaging apparatus according to the first embodiment illustrated in FIG. 1, description thereof is omitted. In addition, the configuration and basic drive timing of the solid-state imaging device in the present embodiment are the same as the configuration of the solid-state imaging device in the first embodiment shown in FIG. 2 and the solid-state imaging device in the first embodiment shown in FIG. Since this is the same as the drive timing, the description is omitted.

  In the imaging apparatus having the configuration as shown in FIG. 1, equipment or components that can be a noise source that fluctuates the power supply voltage supplied to the solid-state imaging element 3 are in the vicinity of the solid-state imaging element, that is, inside the imaging apparatus or imaging apparatus. Located in the immediate vicinity. For example, to communicate with an external device 11 such as a strobe 14, a DC / DC circuit of a power supply circuit 15, motors 16 and 17 for driving a lens barrel or a diaphragm 2 of the lens 1, or a computer. External interface unit 10 and wireless unit 18. In addition to the devices and components shown in FIG. 1, devices and components that can change the power supply of the imaging apparatus and the magnetic field around the solid-state imaging device by operation can be noise sources.

  These noise sources generate power fluctuations and electromagnetic waves at a specific frequency for each noise source. In particular, the frequency of the electromagnetic waves generated by the DC / DC circuit of the power supply circuit 15 is a voltage supplied from the power supply means. It will be different depending on. For example, in a general imaging device, a battery is used as power supply means. Since the voltage supplied from the battery varies depending on the progress of the discharge of the battery, etc., the frequency of the electromagnetic wave generated by the DC / DC circuit also changes as the drive frequency of the DC / DC circuit changes, so it is supplied to the solid-state image sensor. The frequency of fluctuations in the power supply will change.

  In order to reduce noise caused by fluctuations in the power supply voltage supplied to the solid-state imaging device, a suitable drive timing varies depending on the fluctuation frequency of the power supply voltage supplied to the solid-state imaging device. Therefore, in the present embodiment, when a signal is read from the solid-state imaging device, a driving pattern suitable for reducing noise according to the power supply voltage supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is used. select.

  For example, when the voltage level supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is the first voltage level, the power supply voltage supplied to the solid-state imaging device fluctuates at the frequency f1 [Hz]. To do. At this time, as shown in FIG. 4A, for example, the holding timing T18a of the capacitor CTs2 and the holding of the capacitor CTn2 are canceled so as to cancel the noise generated between the holding timing T8 of the capacitor CTn1 and the holding timing T12 of the capacitor CTs1. Timing T21a is determined. This is stored in the imaging apparatus as the first drive timing.

  Further, when the voltage level supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is the second voltage level lower than the first voltage level, the power supply voltage supplied to the solid-state imaging device has the frequency f2 [ Hz]. At this time, as shown in FIG. 5, for example, the holding timing T18d of the capacitor CTs2 and the holding timing T21d of the capacitor CTn2 are set so as to cancel noise generated between the holding timing T8 of the capacitor CTn1 and the holding timing T12 of the capacitor CTs1. decide. This is stored in the imaging apparatus as the second drive timing.

  When the voltage level supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is equal to or higher than a predetermined threshold value between the first voltage level and the second voltage level, a signal is output from the solid-state imaging device. When reading, the first drive timing is used. Further, when the voltage level supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is less than a predetermined threshold value between the first voltage level and the second voltage level, a signal is output from the solid-state imaging device. When reading, the second drive timing is used. By doing so, the solid-state imaging device is driven with an appropriate driving pattern in accordance with the voltage level supplied from the power supply means to the DC / DC circuit of the power supply circuit 15, and the power supply voltage supplied to the solid-state imaging device can be reduced. It is possible to reduce image quality deterioration due to fluctuations.

  Although two examples of frequencies have been described, the voltage level is further divided into sub-divisions, and different driving timings are stored for the respective voltages, and the voltage supplied from the power supply means to the DC / DC circuit of the power supply circuit 15 is stored. The driving timing to be used may be selected according to the level.

(Other embodiments of the present invention)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

3: Solid-state imaging device 4: Imaging signal processing circuit 7: Memory unit 12: Overall control / calculation unit 13: Timing generation unit 15: Power supply circuit 300: Pixel CTs1: Capacitance (first optical signal holding means) CTn1: Capacitance ( CTs2: Capacitance (second optical signal holding means) CTn2: Capacitance (second noise signal holding means) MTs1: First optical signal transfer transistor MTn1: First noise signal transfer transistor MTs2: second optical signal transfer transistor MTn2: second noise signal transfer transistor PTs1: first optical signal transfer pulse PTn1: first noise signal transfer pulse PTs2: second optical signal transfer pulse PTn2: second Noise signal transfer pulse

Claims (6)

A plurality of pixels, first optical signal holding means for holding optical signals output from the plurality of pixels, first noise signal holding means for holding noise signals output from the plurality of pixels, Connected to the first optical signal holding means, connected to the second optical signal holding means for holding the optical signal through the first optical signal holding means, and to the first noise signal holding means, A solid-state imaging device having second noise signal holding means for holding the noise signal via first noise signal holding means;
The second optical signal holding unit holds the optical signal at a timing at which noise having the same phase as the noise superimposed when holding the noise signal is held by the first noise signal holding unit; Control means for causing the second noise signal holding means to hold the noise signal at a timing at which noise having the same phase as the noise superimposed when holding the optical signal is held in one optical signal holding means. An imaging apparatus characterized by that.   The timing at which the second optical signal holding unit holds the optical signal and the timing at which the second noise signal holding unit holds the noise signal are the period of the superimposed noise and the first optical signal. The imaging apparatus according to claim 1, wherein the imaging apparatus is determined based on a timing at which the holding unit holds the optical signal and a timing at which the first noise signal holding unit holds the noise signal. The timing at which the second optical signal holding unit holds the optical signal and the second noise signal for each combination of the noise sources that operate simultaneously among the plurality of noise sources that generate the noise in each cycle. The timing for holding the noise signal in the holding means is stored,
The control means is configured to cause the second optical signal holding means to hold the optical signal and the second noise signal in accordance with a combination of the noise sources that operate simultaneously with a signal readout operation from the solid-state imaging device. The imaging apparatus according to claim 2, wherein a timing for holding the noise signal in a holding unit is selected.   The timing at which the second optical signal holding unit holds the optical signal and the timing at which the second noise signal holding unit holds the noise signal are further determined based on a supplied power supply voltage. The imaging apparatus according to claim 2 or 3.   Causing the second optical signal holding unit to hold the optical signal so that an interval from the timing at which the first noise signal holding unit holds the noise signal is an integral multiple of the period of the superimposed noise. Timing is determined, and the second noise signal holding unit is set to the second noise signal holding unit so that an interval from the timing at which the first optical signal holding unit holds the optical signal is an integral multiple of the period of the superimposed noise. The imaging apparatus according to claim 2, wherein a timing for holding the noise signal is determined. A plurality of pixels, first optical signal holding means for holding optical signals output from the plurality of pixels, first noise signal holding means for holding noise signals output from the plurality of pixels, Connected to the first optical signal holding means, connected to the second optical signal holding means for holding the optical signal through the first optical signal holding means, and to the first noise signal holding means, A control method for an imaging apparatus comprising a solid-state imaging device having second noise signal holding means for holding the noise signal via first noise signal holding means,
Holding the optical signals output from the plurality of pixels in the first optical signal holding means;
Holding the noise signal output from the plurality of pixels in the first noise signal holding means;
Holding the optical signal in the second optical signal holding means at a timing at which noise having the same phase as the noise superimposed when holding the noise signal in the first noise signal holding means is superimposed;
The noise signal is held in the second noise signal holding unit at a timing at which noise having the same phase as the noise superimposed when holding the optical signal is held in the first optical signal holding unit. A method for controlling the imaging apparatus.

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