JP5219775B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an image pickup device (solid-state image pickup device) and an image pickup device such as a video camera and a digital camera equipped with the image pickup device, and more particularly to an image pickup device and an image pickup device characterized by a technique for improving the image quality of video signals.

  In an imaging apparatus such as a digital camera or a video camera, a CCD, a CMOS image sensor, or the like is used as an imaging element.

  In general, an image sensor includes an optical black region that is shielded so as not to react to light in order to obtain a signal (black reference signal) that serves as a reference signal of a signal level, and an effective pixel signal is in the optical black region. Calculation processing is performed based on the obtained level. Such a pixel is called an “OB pixel (optical black pixel)”.

  When such an image sensor is used in an image pickup apparatus and photographing is performed in the long exposure mode, dark current accumulated in the pixel increases and output of the OB pixel also increases. At this time, since the dynamic range of the internal circuit of the image sensor and the external signal processing circuit is fixed, the optical signal obtained from the aperture pixel decreases.

  In order to solve this, it is well known to obtain a signal from the aperture pixel after clamping the OB pixel output to a predetermined level.

  As shown in FIG. 1 to be described later, the OB pixel of the image sensor has a VOB portion at the top of the screen and a HOB portion at the left of the screen. Signals from the pixels are read out as indicated by arrows from the upper left of the figure.

  The operation of clamping the OB pixel output to a predetermined level will be briefly described.

  First, while monitoring the signal output in the VOB region, a clamping operation (hereinafter, high-speed clamping) is performed by feeding back with a large gain so that the output signal becomes a predetermined level at high speed. Then, after clamping to the target level, the monitoring area is moved to the HOB area, and the clamping operation is continued by feeding back with a small gain so that the output signal becomes a predetermined level at a low speed (hereinafter referred to as low speed clamping). .

  The reason why the high-speed clamping is performed in the VOB region first is to make it possible to clamp the OB pixel output at a predetermined level at a high speed even if the dark current is very large by taking a large region used for the clamping.

  The reason why the low-speed clamping is performed in the HOB region is to correct the shading in the vertical direction of the dark signal.

  Consider the case where the dark signal has horizontal shading in the imaging device that performs the operation of clamping the OB pixel output to a predetermined level (hereinafter referred to as OB clamping operation).

  Horizontal shading in a general CMOS image sensor is often caused by a readout circuit, and the amount of shading is constant regardless of image capturing conditions, and the shape of horizontal shading even if the readout pixel changes in the vertical direction. Does not change.

  Therefore, the correction can be easily performed by having a one-dimensional correction value in the horizontal direction and subtracting the one-dimensional correction value from the obtained image.

  FIG. 14 is a diagram for explaining an image in the case where there is horizontal shading in the dark signal. The pixel signal of the odd column (CH1) and the pixel signal of the even column (CH2) are read by separate circuits, An image sensor that performs a clamping operation separately is shown.

  A straight line rising to the right shown on the pixel portion layout of the entire screen shows a shaded output from the left to the right from the screen.

  When high-speed clamping is performed in the VOB area, the VOB pixel output reaches the target level at some position in the horizontal direction. Thereafter, the process shifts to low-speed clamping in the HOB area. Since there is a difference in the horizontal position between the VOB area and the HOB area when the high-speed clamping is finished, there is a difference in output between the horizontal shading.

  For example, CH1 has finished high-speed clamping at the horizontal position P, so the level difference from HOB is a, and CH2 has finished high-speed clamping at the horizontal position Q, so the level difference from HOB is b.

  That is, the CH1 HOB area low-speed clamp is clamped from the level a lower than the target level of the OB pixel output, and the CH2 HOB area low-speed clamp is clamped from the level lower than the target level of the OB pixel output to the target level. Be started. For this reason, shading occurs in the vertical direction of the screen.

  Further, the HOB level at that time is shown by the stepped lines shown on the left side of the pixel portion layout of the entire screen, which respectively indicate CH1 (solid line) and CH2 (dashed line). As can be seen from this stepped line, since the difference between CH1 and CH2 is large up to the nth row in the vertical direction, the output image (the image obtained by combining the output of CH1 and the output of CH2) is vertically striped at the top. It becomes an image with.

In addition, there exists a thing of patent document 1 as a thing relevant to the said technique.
JP 2007-6538 A

  As described with reference to FIG. 14, in the case of an output having shading in the horizontal direction, if high-speed clamping of the VOB area is terminated and low-speed clamping of the HOB area is performed as it is, shading in the vertical direction is caused. When the difference between CH1 and CH2 is large, the output image is an image having vertical stripes at the top.

  In order to correct the image that has caused such shading in the vertical direction correctly, it is necessary to perform the clamping process on the obtained image output again only in the HOB area for each CH, which is inefficient. It is.

  An object of the present invention is to provide an imaging device and an imaging apparatus that can output a suitable image while suppressing shading in the vertical direction of the image even when the dark current is very large.

In order to achieve the above object, the image pickup device according to claim 1 , wherein the photoelectric conversion device is two-dimensionally arranged and has an aperture pixel region and a light-shielded optical black region serving as a reference. A first clamp mode for clamping the output signal from the first region of the region to a first predetermined level; and a second region of the optical black region after the operation of the first clamp mode is completed. so that the output signal from becomes a second predetermined level, have a, a second clamping mode of clamping slower than the first clamping mode, said second predetermined level, said first After the operation in the clamp mode is completed, the determination is made according to the output difference between the first region and the second region .

In order to achieve the above object, an imaging apparatus according to claim 4 is an imaging apparatus including an imaging element in which photoelectric conversion elements are two-dimensionally arranged and have an aperture pixel area and a light-shielded optical black area as a reference. First clamping means for clamping the output signal from the first area of the optical black area to a first predetermined level; and after completion of the operation of the first clamping means, so that the output signal from the second region becomes a second predetermined level, have a, a second clamping means for clamping slower than the first clamping mode, said second predetermined level And after the operation of the first clamping means is finished, it is determined according to the output difference between the first area and the second area .

According to the onset bright, even a very large dark current, by suppressing vertical shading of the image, it is possible to output a suitable image.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a pixel portion layout of the entire screen of an image pickup device (CMOS type image pickup device) according to an embodiment of the present invention.

  The imaging device has photoelectric conversion elements arranged two-dimensionally, and has an aperture pixel region and a light-shielded optical black (OB) region serving as a reference.

  The OB pixel has a VOB portion at the top of the screen and a HOB portion at the left of the screen. Signals from the pixels are read out as indicated by arrows from the upper left of the figure.

  FIG. 2 is a block diagram illustrating a configuration example of the pixel cell Pixel of the image sensor of FIG.

  In this example, the photodiode 201 generating the optical signal charge is grounded on the anode side. The cathode side of the photodiode 201 is connected to the gate of the amplification MOS transistor MOS transistor 204 via the transfer MOS transistor MOS transistor 202.

  The gate of the amplification MOS transistor MOS transistor 204 is connected to the source of a reset MOS transistor MOS transistor 203 for resetting the gate. The drain of the reset MOS transistor MOS transistor 203 is connected to the power supply voltage VDD.

  Further, the amplification MOS transistor 204 has a drain connected to the power supply voltage VDD and a source connected to the drain of the selection MOS transistor 205.

  FIG. 3 is a block diagram illustrating a configuration example of the image sensor of FIG. In order to simplify the description, it is assumed to be composed of 3 × 3 pixels.

  The vertical shift register 301 outputs signals of the first to third row selection lines Pres1, Ptx1, and Psel1 to the pixel region 308. The pixel region 308 has the configuration of FIG. 1 and includes a plurality of pixel cells Pixel. Each pixel cell Pixel outputs pixel signals to the vertical signal lines of CH1 and CH2, respectively, in even columns and odd columns.

  The current source 307 is connected to each vertical signal line. The readout circuit 302 inputs a pixel signal on the vertical signal line, and outputs the pixel signal to the differential amplifier 305 via the n-channel MOS transistor 303. Further, the read circuit 302 outputs a noise signal to the differential amplifier 305 via the n-channel MOS transistor 304.

  The horizontal shift register 306 controls on / off of the transistors 303 and 304. The differential amplifier 305 outputs a difference between the pixel signal and the noise signal.

  The gate of the transfer MOS transistor 202 in FIG. 2 is connected to a first row selection line (vertical scanning line) Ptx1 (FIG. 3) arranged extending in the horizontal direction. The gates of similar transfer MOS transistors 202 of other pixel cells Pixel arranged in the same row are also commonly connected to the first row selection line Ptx1.

  The gate of the reset MOS transistor 203 is connected to a second row selection line (vertical scanning line) Pres1 (FIG. 3) arranged extending in the horizontal direction. The gates of similar reset MOS transistors 203 of other pixel cells Pixel arranged in the same row are also commonly connected to the second row selection line Pres1.

  The gate of the selection MOS transistor 205 is connected to a third row selection line (vertical scanning line) Psel1 that extends in the horizontal direction. The gates of similar selection MOS transistors 205 of other pixel cells Pixel arranged in the same row are also commonly connected to the third row selection line Psel1.

  These first to third row selection lines Ptx1, Pres1, and Psel1 are connected to the vertical shift register 301 and supplied with a signal voltage.

  In the remaining rows shown in FIG. 3, pixel cells Pixel having a similar configuration and row selection lines are provided. The row selection lines Ptx2 to Ptx3, Pres2 to Pres3, and Psel2 to Psel3 formed by the vertical shift register 301 are supplied to these row selection lines.

  The source of the selection MOS transistor 205 in FIG. 2 is connected to a terminal of a vertical signal line that is arranged extending in the vertical direction. The source of the similar selection MOS transistor 205 of the pixel cell Pixel arranged in the same column is also connected to the terminal of the vertical signal line.

  In FIG. 3, the terminal OUT of the vertical signal line is connected to a constant current source 307 as a load means.

  FIG. 4 is a diagram illustrating a circuit example of one block of the read circuit 302 in FIG.

  A portion surrounded by a broken line is provided for each column in the direction of CH1 and CH2, and a terminal OUT is connected to each vertical signal line.

  FIG. 5 is a timing chart showing an operation example of the image sensor of FIGS.

  Prior to reading of the optical signal charge from the photodiode 201, the gate line Pres1 of the reset MOS transistor 203 is set to the high level. As a result, the gate of the amplification MOS transistor 204 is reset to the reset power supply voltage.

  At the same time that the gate line Pres1 of the reset MOS transistor 203 returns to the low level, the gate line Psel1 of the selection MOS transistor 205 becomes the high level after the gate line PC0r (FIG. 4) of the clamp switch becomes the high level.

  As a result, the reset signal (noise signal) on which the reset noise is superimposed is read to the vertical signal line OUT and clamped to the clamp capacitor C0 (FIG. 4) of each column.

  Next, after the gate line PC0r of the clamp switch returns to the low level, the gate line PCtn (FIG. 4) of the noise signal side transfer switch changes from the high level to the low level, so that the noise holding capacitors provided in each column A reset signal is held in Ctn.

  Next, after the gate line pcts (FIG. 4) of the pixel signal side transfer switch becomes the high level, the gate line Ptx1 of the transfer MOS transistor 202 becomes the high level, and the optical signal charge of the photodiode 201 becomes the amplification MOS transistor 204. At the same time, the optical signal is read out to the vertical signal line OUT.

  Next, after the gate line Ptx1 of the transfer MOS transistor 202 returns to the low level, the gate line Pcts of the pixel signal side transfer switch becomes the low level. As a result, the amount of change (optical signal) from the reset signal is read out to the signal holding capacitors Cts (FIG. 4) provided in each column.

  With the operation so far, the optical signals of the pixel cells Pixel connected in the first row are held in the signal holding capacitors Ctn and Cts connected to the respective columns.

  Thereafter, the signal PH supplied from the horizontal shift register 306 sequentially turns the gates of the horizontal transfer switches in each column to the high level. The voltages held in the signal holding capacitors Ctn and Cts are sequentially read out to the horizontal output lines Chn and Chs, subjected to differential processing by the differential amplifier 305, and sequentially output to the output terminal OUT.

  The horizontal output lines Chn and Chs are reset to the reset voltages VCHRN and VCHRS by the reset switch between signal readings of each column. Thus, reading of the pixel cell Pixel connected to the first row is completed.

  Similarly, the signals of the pixel cells Pixel connected in the second and subsequent rows are sequentially read by the signal from the vertical shift register 301, and the reading of all the pixel cells Pixel is completed.

  FIG. 6 is a diagram showing output waveforms (a) and (b) and an image (c) at that time when the image sensor of FIGS. 2 to 4 is operated at a high temperature with a relatively large dark current. is there.

  FIG. 6C shows an aperture pixel area 101, a HOB area 102, and a VOB area 103. The VOB output of FIG. 6A shows the output waveform of the VOB area 103, and the HOB + open pixel output of FIG. 6B shows the output waveforms of the HOB area 102 and the open pixel area 101, respectively. The positional relationship in the horizontal direction is the same as (c).

  The fact that the VOB area 103 and the HOB area 102 are output even though they are light-shielded pixels is due to the dark current component. Further, it is assumed that a uniform amount of light is incident on each pixel in the aperture pixel region 101.

  The CLMP signals in FIGS. 6A and 6B perform a clamping operation so that the signals in the corresponding VOB region 103 and HOB region 102 are at a predetermined level in a high level state.

  FIG. 7 is a diagram showing output waveforms (a) and (b) and an image (c) at that time when there is shading in the horizontal direction in the dark in the image sensor of FIGS.

  The difference from FIG. 6 is that the output rises from the left to the right (dashed line). By the CLMP signal, the VOB area 103 performs high-speed clamping and the HOB area 102 performs low-speed clamping. Due to the high-speed clamping operation of the VOB region 103 and the low-speed clamping operation of the HOB region 102, vertical shading occurs below the boundary between the VOB region 103 and the HOB region 102.

  Here, the image sensor according to the present embodiment has a first clamping mode (high-speed clamping) in which the output signal from the first area (VOB area 103) of the optical black area is clamped to a first predetermined level. Mode).

  In addition, after the operation of the first clamp mode is finished, the image sensor of the present embodiment is configured so that the output signal from the second area (HOB area 102) of the optical black area becomes the second predetermined level. There is a second clamp mode (low-speed clamp mode) that clamps at a lower speed than the first clamp mode.

  FIG. 8 is a block diagram of a signal processing circuit of an image pickup apparatus including the image pickup device shown in FIGS.

  A sensor signal output from the image sensor is amplified by a programmable gain amplifier (PGA) 801. At this time, the reference signal is supplied after the digital signal generated by the OB clamp unit 803 is converted into an analog signal by a digital-analog converter (DAC) 804.

  An analog-to-digital converter (ADC) 802 converts the output signal of the programmable gain amplifier 801 from an analog format to a digital format and outputs the converted signal.

  In the OB clamp unit 803, a clamp target value is input from the target level setting unit 805, and an output signal is input from the ADC 802.

  The direction in which the difference between the sensor signal and the target value becomes zero, that is, the output signal of the optical black region (VOB region, HOB region) of the image sensor shown in FIGS. A reference signal that approaches the clamp target value by a value multiplied by a predetermined gain is generated. This operation is performed while the signal of the clamp signal generator 806 is input.

  The predetermined gain is 1/4 to 1/2 times in the case of high speed clamping and 1/64 to 1/32 times in the case of low speed clamping.

  The DAC 804 converts the reference signal generated by the OB clamp unit 803 from a digital format to an analog format and outputs the analog signal to the PGA 801. Thereby, the reference voltage of the signal input to the PGA 801 is determined. The ADC 802 converts the amplified sensor signal into a digital signal.

  The target level setting unit 805 inputs the clamp target value of the OB area to the OB clamp unit 803 as described above, but can arbitrarily set the value.

  The OB clamp unit 803 is operated by a CLAMP signal as shown in FIGS. 6A, 6B, 7A, and 7B.

  When the CLAMP signal is input longer than a predetermined time (for example, 10 clocks or more), high-speed clamping is performed. When the CLAMP signal is input shorter than the predetermined time (for example, less than 10 clocks), low-speed clamping is performed. When the CLAMP signal is not input, the clamping operation is not performed.

  During high-speed clamping, when the difference between the clamp target value and the output signal falls within a predetermined range, the clamp operation is stopped and a clamp stop signal is output from the clamp signal generator 806.

  In FIG. 8, if the clamping operation is continued with the clamp target value always fixed, the VOB area and the HOB area when the high-speed clamping is finished have a difference in horizontal position as shown in FIG. There is a difference between the outputs due to shading. For example, CH1 has finished high-speed clamping at the horizontal position P, so the level difference from HOB is a, and CH2 has finished high-speed clamping at the horizontal position Q, so the level difference from HOB is b.

  That is, the CH1 HOB area low-speed clamp is clamped from the level a lower than the target level of the OB pixel output, and the CH2 HOB area low-speed clamp is clamped from the level lower than the target level of the OB pixel output to the target level. Be started. For this reason, shading occurs in the vertical direction of the screen.

  Here, the clamp target value for performing the HOB area low-speed clamping operation is changed.

In particular,
CH1 HOB area low-speed clamp target value = VOB area clamp target value-a (Equation 1)
CH2 HOB area low-speed clamp target value = VOB area clamp target value−b (Equation 2)
FIG. 9 is a diagram showing an image (image signal) when the clamp target value is changed in the signal processing circuit of FIG.

  In FIG. 9, it can be seen that although there is a step in the effective portion including the VOB area and the HOB area, shading in the vertical direction as shown in FIG. 16 does not occur. However, since the offset is shifted by -a for CH1 and -b for CH2 with respect to the clamp target value, it is necessary to further perform offset correction for each CH in the signal processing circuit in the subsequent stage.

  FIG. 10 is a diagram illustrating an image obtained by performing offset correction on the image of FIG.

  In FIG. 10, although there is an offset shift between CH1 and CH2 in the VOB area, it can be seen that the effective portion including the HOB area is an ideal image without offset or vertical shading for each CH.

  Further, in FIGS. 9 and 10, for simplicity of explanation, there is no horizontal shading, but there is actually horizontal shading. However, it can be corrected by measuring the shading in the horizontal direction in advance. Specifically, the horizontal shading of the image sensor is corrected with a predetermined horizontal shading correction value.

  FIG. 11 is a block diagram showing a configuration of the imaging apparatus according to the embodiment of the present invention.

  In FIG. 11, an image sensor 1101 is shown in FIGS. 1 to 4, and a CCD or CMOS sensor is used. As shown in FIG. 8, the signal processing circuit 1102 amplifies the signal from the image sensor 1101 and performs OB clamping or the like.

  The signal processing circuit 1102 receives an OB clamp timing, an OB clamp target level, and the like from a timing generation circuit 1104, which will be described later, and operates according to it.

  A DSP (DigitalSignalProseCCer) 1103 stores in advance various correction processes for data from the signal processing circuit 1102 (one-dimensional correction values for correcting horizontal shading caused by the readout circuit of the image sensor 1101), and subtracts them from the signal. Etc.). Further, the DSP 1103 receives the OB clamp stop signal and performs various signal processing controls.

  The DSP 1103 controls various memories such as the ROM 1106 and the RAM 1107 and writes video data to the recording medium 1108.

  The timing generation circuit 1104 supplies a clock signal and a control signal to the image sensor 1101, the signal processing circuit 1102, and the DSP 1103, and is controlled by the CPU 1105. The drive pulse in FIG. 3 is output from the timing generation circuit 1104 to the image sensor 1101.

  The CPU 1105 controls the DSP 1103, the timing generation circuit 1104, and the camera (imaging device) function using each unit (not shown) such as photometry / ranging. In addition, the CPU 1105 is connected to each of the switches 1109 to 1111 and executes processing according to each state.

  The ROM 1106 stores a camera control program, a correction table, and the like. The RAM 1107 temporarily stores video data and correction data processed by the DSP 1103. The RAM 1107 can be accessed at a higher speed than the ROM 1106.

  A recording medium 1108 such as a compact flash (registered trademark) card (CF) is a memory for storing captured images, and is connected to a camera via a connector (not shown).

  A power switch 1109 is a switch for starting the camera. A shutter switch (SW1) 1110 is a switch for instructing the start of a photographing preparation operation such as a so-called EVF operation, in which a photometric process, a distance measurement process, and a subject image are displayed in real time.

  A shutter switch (SW2) 1111 drives a mirror and a shutter (not shown), and instructs to start a series of photographing operations for writing a signal read from the image sensor 1101 to the recording medium 1108 via the signal processing circuit 1102 and the DSP 1103. It is.

  A mode dial 1112 is a switch for instructing a shooting mode (for example, a continuous shooting mode, a single shooting mode, a flash emission mode, etc.) of the camera.

  The distance measuring circuit 1113 is for measuring the distance to the subject. The photometry circuit 1114 is for measuring subject brightness. The display device 1115 is for displaying captured images on the outside.

  FIG. 12 is a flowchart illustrating the procedure of the first embodiment of the OB clamping process executed by the imaging apparatus of FIG.

  This process is executed under the control of the CPU 1105 in FIG.

  Here, the case where the signal from the image sensor 1101 has shading in the dark horizontal direction in FIG. 7 will be described.

  In step S <b> 101, the CPU 1105 sequentially reads signals from the image sensor 1101 into the signal processing circuit 1102 by starting reading.

  In step S102 (first clamping means), in response to an instruction from the CPU 1105, the signal processing circuit 1102 starts high-speed clamping during the VOB period according to the CLAMP signal output from the timing generation circuit 1104.

  In step S103, the signal processing circuit 1102 calculates the difference between the signal level in the VOB area and the clamp target level output from the timing generation circuit 1104, and determines whether it is within a predetermined range. Here, if not within the predetermined range, the process returns to step S102, and the signal processing circuit 1102 continues high-speed clamping during the VOB period.

  If the signal processing circuit 1102 determines in step S103 that the signal level in the VOB area is within a predetermined range with respect to the clamp target level, the process proceeds to step S104 to stop high-speed clamping in the VOB area and stop clamping. Generate a signal.

  Subsequently, in step S105, the signal processing circuit 1102 determines the number of pixels during the VOB period, and the DSP 1103 stores the horizontal coordinates at which the high-speed clamping operation is stopped.

  In step S106, the CPU 1105 calculates an output difference between the VOB area and the HOB area. That is, the CPU 1105 determines the VOB area for each CH from the one-dimensional correction value for correcting the horizontal shading caused by the readout circuit 302 of the image sensor 1101 acquired in advance and the horizontal coordinate at which high-speed clamping is stopped. The output difference from the HOB area is calculated.

  Thereafter, in step S107, the CPU 1105 determines a HOB area low-speed clamp target value for each CH as in (Expression 1) and (Expression 2), and sends the value to the signal processing circuit 1102.

  In step S108 (second clamping means), the CPU 1105 starts low-speed clamping of the HOB area, and in step S109, reading of all pixels is completed.

  Thereafter, an ideal image can be provided by performing offset correction for each channel, horizontal shading correction, and the like in the signal processing circuit at the subsequent stage.

  Here, since the one-dimensional correction value is data for correcting the horizontal shading of the image, the horizontal shading shape of the image is almost faithfully reproduced. Based on the difference between the HOB area value of the one-dimensional correction value and the horizontal coordinate value at which high-speed clamping is stopped, the low-speed clamping target value of the HOB area can be determined.

  If the difference between the HOB area value of the one-dimensional correction value and the horizontal coordinate value at which high-speed clamping is stopped is smaller than a predetermined value in step S106, the following is performed. Also good. That is, in the above case, the target value of the clamp may not be changed on the assumption that there is little horizontal shading and no vertical shading occurs at the time of low-speed clamping in the HOB area.

  FIG. 13 is a flowchart illustrating a procedure of the second embodiment of the OB clamping process executed by the imaging apparatus of FIG.

  This process is executed under the control of the CPU 1105 in FIG.

  Further, a case where the signal from the image sensor 1101 has shading in the horizontal direction in the dark in FIG. 7 will be described.

  In FIG. 13, the processing of steps S201 to S205 is the same as the processing of steps S101 to S105 of FIG. In FIG. 13, the processing in steps S208 to S210 is the same as the processing in steps S107 to S109 in FIG.

  In step S206, the CPU 1105 stores the signal for one row in the VOB area while continuing to read the signal while the OB clamping operation by the signal processing circuit 1102 is stopped.

  In step S207, the CPU 1105 calculates an output difference between the VOB area and the HOB area for each CH from the signal for one row in the VOB area and the horizontal coordinate at which high-speed clamping is stopped.

  Here, in step S207, the signal for one row in the VOB area is used as the signal level of the horizontal coordinate at which the high-speed clamping is stopped, but in this case, only one pixel signal per column is obtained. Therefore, it is susceptible to noise. It is hard to say that the horizontal shading shape of the image is reproduced almost faithfully.

  As a countermeasure, the signal data for one row in the VOB area is not used as it is, but the signal data after applying a low-pass filter in the horizontal direction, such as by obtaining a moving average, is used. As a result, the low-speed clamp target value in the HOB region can be accurately determined without being affected by noise.

  In this method, since the horizontal shading shape can be measured in real time, it is possible to cope with the case where horizontal shading due to dark current occurs.

It is a figure which shows the pixel part layout of the whole screen of the image pick-up element (CMOS type image pick-up element) which concerns on embodiment of this invention. It is a block diagram which shows the structural example of the pixel cell Pixel of the image pick-up element of FIG. It is a block diagram which shows the structural example of the image pick-up element of FIG. FIG. 4 is a diagram illustrating a circuit example of one column of the read circuit 302 in FIG. 3. 5 is a timing chart showing an operation example of the image sensor of FIGS. FIG. 5 is a diagram showing output waveforms (a) and (b) and an image (c) at that time when the imaging device of FIGS. 2 to 4 is operated at a high temperature with a relatively large dark current. FIGS. 5A and 5B are diagrams illustrating output waveforms (a) and (b) when there is shading in the horizontal direction in the dark, and an image (c) at that time in the image pickup device of FIGS. It is a block diagram of the signal processing circuit of an imaging device provided with the image sensor of FIGS. FIG. 9 is a diagram illustrating an image (image signal) when a clamp target value is changed in the signal processing circuit of FIG. 8. It is a figure which shows the image which performed offset correction to the image of FIG. It is a block diagram which shows the structure of the imaging device which concerns on embodiment of this invention. 12 is a flowchart illustrating a procedure of a first embodiment of an OB clamp process executed by the imaging apparatus of FIG. 11. 12 is a flowchart illustrating a procedure of a first embodiment of an OB clamp process executed by the imaging apparatus of FIG. 11. It is a figure explaining the OB clamp operation | movement in the conventional imaging device.

Explanation of symbols

1101 Image sensor 1102 Signal processing circuit 1103 DSP
1104 Timing generation circuit 1105 CPU
1106 ROM
1107 RAM
1108 Recording medium

Claims (4)

In an image sensor having a photoelectric conversion element arranged two-dimensionally and having an aperture pixel area and a light-shielded optical black area as a reference,
A first clamping mode for clamping the output signal from the first area of the optical black area to a first predetermined level;
Operation after the end of the first clamp mode, the output signal from the second region of the optical black area so that the second predetermined level, a second clamping slower than the first clamp mode possess and clamp mode, the,
The image sensor according to claim 1, wherein the second predetermined level is determined according to an output difference between the first region and the second region after the operation of the first clamp mode is completed . A correction value for horizontal shading of the image sensor;
The output difference between the first area and the second area is calculated based on a horizontal coordinate when the operation of the first clamp mode is completed and a correction value of the horizontal shading. The imaging device according to claim 1 . The second clamping mode, when the output difference of the first region and the second region is smaller than a predetermined amount, the output signal from the second area is the first predetermined level as such, the imaging device according to claim 1, wherein the clamping slower than the first clamp mode. In an imaging apparatus including an imaging element in which photoelectric conversion elements are two-dimensionally arranged and have an aperture pixel area and a light-shielded optical black area as a reference,
First clamping means for clamping the output signal from the first area of the optical black area to a first predetermined level;
After the operation end of the first clamping means, the output signal from the second region of the optical black area so that the second predetermined level, a second clamping slower than the first clamp mode possess a clamp means, the,
The imaging apparatus according to claim 1, wherein the second predetermined level is determined in accordance with an output difference between the first area and the second area after the operation of the first clamping means is completed .

Images