JP2016035672A - Information processing device and transfer control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device and transfer control method that can prevent data stored in a storage unit from being leaked without changing a control program of the information processing device.SOLUTION: An information processing device includes: a data transfer unit 56; a second storage unit 58 that stores system startup data which is required for a CPU 51 to use a first storage unit 55; a first transfer control unit 591 that detects the execution of first transfer processing by the data transfer unit 56 in which data stored in a predetermined specific storage region of the first storage unit 55 is transferred to a memory 54, and transfers the system startup data stored in the second storage unit 58 to the memory 54; and a second transfer control unit 592 that detects the execution of second transfer processing by the data transfer unit 56 in which the system startup data stored in the memory 54 is transferred to the specific storage region, and transfers the system startup data stored in the memory 54 to the second storage unit 58.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an information processing apparatus and a transfer control method for data processed by the information processing apparatus.

  In general, an information processing apparatus such as a multifunction peripheral is provided with a storage unit such as a hard disk drive for storing data processed by the information processing apparatus. By the way, in this type of information processing apparatus, data that is highly confidential to the user may be stored in the storage unit. Here, the information processing apparatus includes a first storage unit that stores highly confidential data, and a second storage unit that stores system activation data necessary for the processor to use the first storage unit. The configuration is known as related technology (see, for example, Patent Document 1). According to such a configuration, data leakage due to theft of the first storage unit or the like is suppressed.

JP 2004-252968 A

  However, in the related technology, the processor of the information processing apparatus needs to control a plurality of storage units. Therefore, in order to apply the related technique to an existing configuration with one storage unit, it is necessary to change the control program of the information processing apparatus.

  An object of the present invention is to provide an information processing apparatus and a transfer control method capable of suppressing leakage of data stored in a storage unit without changing a control program of the information processing apparatus.

  An information processing apparatus according to one aspect of the present invention includes a data transfer unit, a second storage unit, a first transfer control unit, and a second transfer control unit. The data transfer unit executes a data transfer process between the first storage unit and the memory in response to a request from the processor. The second storage unit stores system activation data necessary for the processor to use the first storage unit. The first transfer control unit detects execution of a first transfer process for transferring data stored in a predetermined specific storage area of the first storage unit to the memory by the data transfer unit, and (2) The system startup data stored in the storage unit is transferred to the memory. The second transfer control unit detects execution of a second transfer process for transferring the system activation data stored in the memory by the data transfer unit to the specific storage area, and is stored in the memory System activation data is transferred to the second storage unit.

  A transfer control method according to another aspect of the present invention is a transfer control method executed by an information processing apparatus including a second storage unit that stores system activation data necessary for a processor to use the first storage unit. The following first step to third step are included. The first step executes a data transfer process between the first storage unit and the memory in response to a request from the processor. The second step detects execution of a first transfer process for transferring the data stored in the predetermined specific storage area of the first storage unit in the first step to the memory, and the second storage The system startup data stored in the unit is transferred to the memory. The third step detects the execution of a second transfer process for transferring the system activation data stored in the memory in the first step to the specific storage area, and the system activation stored in the memory Data is transferred to the second storage unit.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus and transfer control method which can suppress the leakage of the data memorize | stored in a memory | storage part are realized, without changing the control program of information processing apparatus.

FIG. 1 is a diagram illustrating a configuration of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing a system configuration of the image forming apparatus according to the embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the control unit of the image forming apparatus according to the embodiment of the present invention. FIG. 4 is a flowchart illustrating an example of a transfer instruction process executed by the control unit of the image forming apparatus according to the embodiment of the present invention. FIG. 5 is a flowchart illustrating an example of transfer control processing executed by the transfer control unit of the image forming apparatus according to the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention. In addition, the following embodiment is an example which actualized this invention, Comprising: The thing of the character which limits the technical scope of this invention is not.

[Schematic Configuration of Image Forming Apparatus 10]
First, a schematic configuration of an image forming apparatus 10 according to an embodiment of the present disclosure will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a schematic sectional view of the image forming apparatus 10.

  As shown in FIGS. 1 and 2, the image forming apparatus 10 includes an ADF 1, an image reading unit 2, an image forming unit 3, a paper feeding unit 4, a control unit 5, and an operation display unit 7. The image forming apparatus 10 is a multifunction machine having a plurality of functions such as a scan function, a facsimile function, and a copy function, in addition to a printer function for forming an image based on image data. The apparatus provided with the control unit 5 is an example of an information processing apparatus in the present invention. The present invention can also be applied to information processing apparatuses such as scanner apparatuses, printer apparatuses, facsimile apparatuses, copiers, personal computers, tablet terminals, and smartphones.

  The ADF 1 is an automatic document feeder that includes a document setting unit, a plurality of conveyance rollers, a document pressing unit, and a paper discharge unit, and conveys a document read by the image reading unit 2. The image reading unit 2 includes a document table, a reading unit, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device), and can execute image reading processing for reading image data from a document.

  The image forming unit 3 forms an image by an electrophotographic method based on image data read by the image reading unit 2 or image data input from an information processing apparatus such as an external personal computer ( Print processing). Specifically, the image forming unit 3 includes a photosensitive drum, a charging device, an optical scanning device (LSU), a developing device, a transfer roller, a cleaning device, a fixing roller, a pressure roller, and a paper discharge tray. In the image forming unit 3, an image is formed on the sheet supplied from the paper feeding unit 4, and the sheet after the image formation is discharged to the paper discharge tray. The sheet is a sheet material such as paper, coated paper, postcard, envelope, and OHP sheet.

  The operation display unit 7 is a display unit such as a liquid crystal display that displays various types of information according to control instructions from the control unit 5 and an operation that inputs various types of information to the control unit 5 according to user operations. An operation unit such as a key or a touch panel is provided.

  Next, the control unit 5 will be described with reference to FIG.

  The control unit 5 comprehensively controls each component of the image forming apparatus 10. Specifically, as shown in FIG. 3, the control unit 5 includes a CPU 51, a ROM 52, a memory controller 53, a memory 54, a first storage unit 55, a data transfer unit 56, a memory controller 57, a second storage unit 58, and A transfer control unit 59 is provided.

  Here, in the control unit 5, the CPU 51, the memory controller 53, the memory controller 57, and the transfer control unit 59 are connected to each other via a bus 50A so as to communicate with each other. In the control unit 5, the data transfer unit 56 is connected to the bus 50 </ b> A via the transfer control unit 59. Further, in the control unit 5, the CPU 51, the data transfer unit 56, and the transfer control unit 59 are connected via a register bus 50B so as to be able to communicate with each other.

  The CPU 51 is a processor that executes various arithmetic processes. The ROM 52 is a non-volatile storage device in which information such as a control program for causing the CPU 51 to execute various processes is stored in advance. The CPU 51 performs overall control of the image forming apparatus 10 by executing various control programs stored in advance in the ROM 52. The CPU 51 is an example of a processor in the present invention.

  The memory controller 53 performs a data write process or a read process on the memory 54 in response to an access request to the memory 54 from the data transfer unit 56 or the transfer control unit 59.

  The memory 54 is a volatile or non-volatile storage device used as a work area for the CPU 51. For example, the memory 54 is a DDR-SDRAM.

  The first storage unit 55 is a storage unit that stores data processed by the image forming apparatus 10. For example, the first storage unit 55 is a non-volatile storage device such as a hard disk drive. The first storage unit 55 may be a storage device such as a solid state drive, a flash memory, or a DVD drive.

  The data transfer unit 56 is a host bus adapter that executes data transfer processing between the first storage unit 55 and the memory 54 in response to a request from the CPU 51. Specifically, the data transfer unit 56 performs a first data transfer process for transferring data stored in the first storage unit 55 to the memory 54 or stores the data in the memory 54 in response to a request from the CPU 51. A second data transfer process for transferring the stored data to the first storage unit 55 is executed.

  Here, in the image forming apparatus 10, the data transfer unit 56 and the first storage unit 55 are connected by a signal line configured in accordance with the serial ATA standard. The data transfer unit 56 executes the data transfer process between the first storage unit 55 and the memory 54 in accordance with the Advanced-Host-Controller-Interface (AHCI) standard. A configuration in which the data transfer unit 56 executes the data transfer process between the first storage unit 55 and the memory 54 according to another interface standard is conceivable as another embodiment.

  Specifically, the data transfer unit 56 includes a command header in a command list 541 (see FIG. 3) set in the memory 54 by the CPU 51 and a command table 542 (see FIG. 3) set in the memory 54 by the CPU 51. 3), the data transfer process is executed based on the command FIS (Frame Information Structure) and PRDT (Physical-Region-Descriptor-Table).

  The command header includes an address of the command table 542 set in the memory 54. The command FIS includes an LBA (Logical-Block-) indicating a command transmitted to the first storage unit 55 and an address of the first storage unit 55 that is a target of data write processing or read processing by the command. Addressing) is included. The PRDT includes the address and size of the memory 54 to be subjected to data write processing or read processing by the memory controller 53.

  On the other hand, the control unit 5 includes a transfer instruction unit 60 as shown in FIG. Specifically, the control unit 5 functions as the transfer instruction unit 60 by executing the control program stored in the ROM 52 using the CPU 51.

  The transfer instruction unit 60 sets the specific processing content of the data transfer processing in the memory 54 and sets the specific processing content of the data transfer processing set in the memory 54 to the data transfer unit 56. Acquiring the data causes the data transfer unit 56 to execute the data transfer process.

  Specifically, the transfer instruction unit 60 sets the command list 541 including the command header and the command table 542 including the command FIS and the PRDT in the memory 54, so that the data transfer processing is performed. Set the details of processing. Further, the transfer instruction unit 60 accesses the register 561 (see FIG. 3) of the data transfer unit 56 via the register bus 50B, and causes the register 561 to store the address of the command list 541. Then, the transfer instruction unit 60 instructs the data transfer unit 56 to acquire data from the address stored in the register 561, so that the command header, the command FIS, and the data transfer unit 56 are instructed. Get PRDT.

[Transfer instruction processing]
Next, an example of a transfer instruction processing procedure executed by the CPU 51 and the data transfer unit 56 in the control unit 5 of the image forming apparatus 10 will be described with reference to FIG. Here, steps S11, S12,... Represent the numbers of processing procedures (steps) executed by the control unit 5.

<Step S11>
First, in step S <b> 11, the CPU 51 sets the command table 542 in the memory 54 and sets the command FIS and the PRDT in the command table 542.

<Step S12>
In step S 12, the CPU 51 sets the command list 541 in the memory 54 and sets the command header in the command list 541. Here, the command header includes an address in the memory 54 of the command table 542 set in the step S11.

<Step S13>
In step S13, the CPU 51 accesses the register 561 of the data transfer unit 56 via the register bus 50B, whereby the command list 541 set in the step S12 in the register 561 is stored in the memory 54. Remember the address.

<Step S14>
In step S <b> 14, the CPU 51 transmits a control signal to the data transfer unit 56, acquires data from the address stored in the register 561 in the data transfer unit 56, and the data transfer process based on the acquired data Is instructed to execute.

<Step S15>
In step S15, the data transfer unit 56 accesses the address of the memory 54 stored in the register 561 in the step S13 according to the control signal transmitted from the CPU 51 in the step S14. The command header is acquired from the command list 541.

<Step S16>
In step S16, the data transfer unit 56 accesses the address of the memory 54 included in the command header acquired in step S15, and acquires the command FIS and the PRDT from the command table 542.

<Step S17>
In step S17, the data transfer unit 56 executes the data transfer process based on the command FIS and the PRDT acquired in step S16. Specifically, the data transfer unit 56 transfers the data stored in the first storage unit 55 to the memory 54 or the memory 54 based on the command FIS and the PRDT. The second data transfer process for transferring the data stored in the first storage unit 55 to the first storage unit 55 is executed. Here, the processing from the step S15 to the step S17 executed by the data transfer unit 56 is an example of the first step in the present invention.

  More specifically, in the first data transfer process, the data transfer unit 56 transmits a command to the first storage unit 55 based on the command FIS, and acquires data from the first storage unit 55. . Based on the PRDT, the data transfer unit 56 transmits an access request to the memory 54 to the memory controller 53 and transfers the data acquired from the first storage unit 55, so that the memory controller 53 The data write processing to the memory 54 is executed.

  Further, in the second data transfer process, the data transfer unit 56 transmits an access request to the memory 54 to the memory controller 53 based on the PRDT, and transmits the access request to the memory controller 53 from the memory 54. Data read processing is executed and the read data is transferred to the data transfer unit 56. Then, based on the command FIS, the data transfer unit 56 transmits a command to the first storage unit 55 and transfers data transferred from the memory controller 53 to the first storage unit 55. Execute data write processing.

  Incidentally, in an information processing apparatus such as the image forming apparatus 10, data that is highly confidential to a user may be stored in the first storage unit 55. Here, the information processing apparatus stores a first storage unit that stores highly confidential data, and a second storage that stores system activation data necessary for the processor to use the first storage unit. A configuration including a unit is known as a related technology. According to such a configuration, data leakage due to theft of the first storage unit or the like is suppressed.

  However, in the related technology, the processor of the information processing apparatus needs to control a plurality of storage units. Therefore, in order to apply the related technique to an existing configuration with one storage unit, it is necessary to change the control program of the information processing apparatus. In contrast, the image forming apparatus 10 suppresses leakage of data stored in the first storage unit 55 without changing the control program stored in the ROM 52 as described below. Is possible.

  Next, the memory controller 57, the second storage unit 58, and the transfer control unit 59 will be described with reference to FIG.

  The memory controller 57 performs a data write process or a read process on the second storage unit 58 in response to an access request to the second storage unit 58 from the data transfer unit 56 or the transfer control unit 59. .

  The second storage unit 58 stores system activation data necessary for the CPU 51 to use the first storage unit 55. Specifically, the system boot data includes information such as a partition table indicating the configuration of the partition of the first storage unit 55 and information such as a boot loader for booting the operating system stored in the partition. Either one or both are included. For example, the second storage unit 58 is a non-volatile storage device such as a flash memory. The second storage unit 58 may be a storage device such as a hard disk drive, a solid state drive, or a DVD drive.

  Here, in the image forming apparatus 10, the second storage unit 58 is mounted on a control board on which the control unit 5 is provided. Thereby, it is possible to reduce the possibility that the second storage unit 58 together with the first storage unit 55 is illegally taken out.

  When the data transfer unit 56 accesses the predetermined specific storage area of the first storage unit 55, the transfer control unit 59 accesses the specific storage area to the second storage unit 58. Convert to For example, the specific storage area is a master boot record (MBL) predetermined as an area in the first storage unit 55 in which the system activation data is stored. The master boot record is a storage area starting from, for example, the first address of the first storage unit 55. In the image forming apparatus 10, the system activation data is not stored in the master boot record of the first storage unit 55 but is stored in the second storage unit 58.

  As shown in FIG. 3, the transfer control unit 59 is provided between the data transfer unit 56, the memory 54, and the second storage unit 58. The transfer control unit 59 includes a register 593, and the data transfer unit 56 receives the address of the command table 542 included in the command header acquired from the memory 54 via the transfer control unit 59, the data The FIS and the PRDT can be stored in the register 593. Further, the transfer control unit 59 includes a first transfer control unit 591 and a second transfer control unit 592.

  The first transfer control unit 591 detects execution of a first transfer process in which the data transfer unit 56 transfers data stored in the specific storage area of the first storage unit 55 to the memory 54, and The system activation data stored in the second storage unit 58 is transferred to the memory 54.

  Specifically, the first transfer control unit 591 executes the first transfer process based on data transferred between the data transfer unit 56 and the memory 54 via the transfer control unit 59. To detect. For example, the first transfer control unit 591 is sent to the memory 54 transmitted from the data transfer unit 56 to the memory controller 53 when the data transfer unit 56 executes the first data transfer process. The execution of the first transfer process is detected based on the access destination address in the access request, the data FIS and the PRDT stored in the register 593.

  In addition, the first transfer control unit 591 discards the data transferred in the first transfer process. The first transfer control unit 591 changes the transfer destination address of the data transferred in the first transfer process, and transfers it to a predetermined storage area of the second storage unit 58. Also good. Further, the first transfer control unit 591 is configured to overwrite the system transfer data transferred from the second storage unit 58 to the memory 54 on the data transferred to the memory 54 in the first transfer process. May be.

  The second transfer control unit 592 detects the execution of the second transfer process for transferring the system activation data stored in the memory 54 by the data transfer unit 56 to the specific storage area, and stores it in the memory 54. The system startup data being transferred is transferred to the second storage unit 58.

  Specifically, the second transfer control unit 592 executes the second transfer process based on data transferred between the data transfer unit 56 and the memory 54 via the transfer control unit 59. To detect. For example, when the second data transfer process is executed by the data transfer unit 56, the second transfer control unit 592 transmits the data transfer unit 56 to the memory 54 that is transmitted to the memory controller 53. The execution of the second transfer process is detected based on the access destination address in the access request, and the data FIS and the PRDT stored in the register 593.

  The second transfer control unit 592 transfers predetermined dummy data to the specific storage area instead of the system activation data transferred in the second transfer process.

[Transfer control processing]
Hereinafter, an example of a transfer control process executed by the transfer control unit 59 in the image forming apparatus 10 will be described with reference to FIG.

<Step S21>
First, in step S21, the transfer control unit 59 determines whether or not a storage process of the address in the memory 54 of the command list 541 in the step S13 of the transfer instruction process is executed in the register 561. . Specifically, the transfer control unit 59 determines whether or not the process of step S13 of the transfer instruction process is being performed by monitoring communication on the register bus 50B.

  If the transfer control unit 59 determines that the process of step S13 of the transfer instruction process is being executed (Yes in S21), the transfer control unit 59 shifts the process to step S22. If the process of step S13 of the transfer instruction process is not executed (No side of S21), the transfer control unit 59 executes the process of step S13 of the transfer instruction process in step S21. I wait for you.

<Step S22>
In step S22, the transfer control unit 59 stores the address of the command list 541 stored in the register 561 in the step S13 of the transfer instruction process in the register 593. Specifically, the transfer control unit 59 acquires the address of the command list 541 and stores it in the register 593 by intercepting communication between the CPU 51 and the data transfer unit 56 in the register bus 50B. Let

<Step S23>
In step S23, the transfer control unit 59 determines whether or not the process for obtaining the command header from the command list 541 in step S15 of the transfer instruction process is being executed. Specifically, the transfer control unit 59 transmits the command transmitted from the data transfer unit 56 to the memory controller 53 based on the address of the command list 541 stored in the register 593 in the step S22. By detecting an access request to the list 541, it is determined whether or not the process of step S15 of the transfer instruction process is being executed.

  Here, when the transfer control unit 59 determines that the process of step S15 of the transfer instruction process is being executed (Yes in S23), the transfer control unit 59 shifts the process to step S24. If the process of step S15 of the transfer instruction process is not executed (No side of S23), the transfer control unit 59 executes the process of step S15 of the transfer instruction process in step S23. I wait for you.

<Step S24>
In step S24, the transfer control unit 59 causes the register 593 to store the address of the command table 542 included in the command header acquired by the data transfer unit 56 in step S15 of the transfer instruction process. Specifically, the transfer control unit 59 acquires the command header transmitted from the memory controller 53 to the data transfer unit 56 in response to an access request to the command list 541 detected in step S23. Then, the address of the command table included in the acquired command header is stored in the register 593.

<Step S25>
In step S25, the transfer control unit 59 determines whether or not the process for obtaining the command FIS and the PRDT from the command table 542 in the step S16 of the transfer instruction process is being executed. Specifically, the transfer control unit 59 transmits the command transmitted from the data transfer unit 56 to the memory controller 53 based on the address of the command table 542 stored in the register 593 in the step S24. By detecting an access request to the table 542, it is determined whether or not the process of step S16 of the transfer instruction process is being executed.

  If the transfer control unit 59 determines that the process of step S16 of the transfer instruction process is being executed (Yes in S25), the transfer control unit 59 shifts the process to step S26. If the process of step S16 of the transfer instruction process is not executed (No side of S25), the transfer control unit 59 executes the process of step S16 of the transfer instruction process in step S25. I wait for you.

<Step S26>
In step S26, the transfer control unit 59 causes the register 593 to store the command FIS and the PRDT acquired by the data transfer unit 56 in the step S16 of the transfer instruction process. Specifically, the transfer control unit 59 transmits the command FIS and the PRDT transmitted from the memory controller 53 to the data transfer unit 56 in response to the access request to the command table 542 detected in step S25. Is stored in the register 593.

<Step S27>
In step S27, the transfer control unit 59 determines whether the command FIS stored in the register 593 in step S26 includes the LBA of the master boot record (MBL) in the first storage unit 55. to decide. Specifically, the transfer control unit 59 determines whether or not the LBA of the master boot record is included in the command FIS based on the LBA of the master boot record set in the transfer control unit 59 in advance. Judging.

  If the transfer control unit 59 determines that the command FIS includes the LBA of the master boot record (Yes in S27), the transfer control unit 59 shifts the process to step S28. If the command FIS does not include the LBA of the master boot record (No in S27), the transfer control unit 59 shifts the process to step S21.

<Step S28>
In step S28, the transfer control unit 59 determines whether or not the first transfer process is being executed in step S17 of the transfer instruction process. Specifically, the transfer control unit 59 includes an access destination address in an access request to the memory 54 transmitted from the data transfer unit 56 to the memory controller 53, and the data FIS stored in the register 593. Based on the PRDT, it is determined whether or not the first transfer process is being executed.

  Here, when the transfer control unit 59 determines that the first transfer process is being executed in Step S17 of the transfer instruction process (Yes side of S28), the process proceeds to Step S281. If the first transfer process is not executed in step S17 of the transfer instruction process (No in S28), the transfer control unit 59 shifts the process to step S29.

<Step S281>
In step S <b> 281, the transfer control unit 59 transfers the system activation data stored in the second storage unit 58 to the memory 54. The transfer control unit 59 discards data transferred from the data transfer unit 56 toward the memory controller 53 in the first transfer process. As a result, not the data stored in the master boot record of the first storage unit 55 but the system startup data stored in the second storage unit 58 is transferred to the memory 54. Here, the processing of step S28 and step S281 is an example of the second step in the present invention, and is executed by the first transfer control unit 591 of the transfer control unit 59.

<Step S29>
In step S29, the transfer control unit 59 determines whether or not the second transfer process is being executed in step S17 of the transfer instruction process. Specifically, the transfer control unit 59 includes an access destination address in an access request to the memory 54 transmitted from the data transfer unit 56 to the memory controller 53, and the data FIS stored in the register 593. Based on the PRDT, it is determined whether or not the second transfer process is being executed.

  Here, when the transfer control unit 59 determines that the second transfer process is being executed in step S17 of the transfer instruction process (Yes in S29), the process proceeds to step S30. If the second transfer process is not executed in step S17 of the transfer instruction process (No side of S29), the transfer control unit 59 shifts the process to step S28, and transfers the transfer instruction process. In step S17, the process waits for the first transfer process or the second transfer process to be executed.

<Step S30>
In step S <b> 30, the transfer control unit 59 transfers the system activation data stored in the memory 54 to the second storage unit 58. In addition, the transfer control unit 59 transmits the dummy data to the data transfer unit 56 instead of the system activation data transferred in the second transfer process. As a result, the system activation data stored in the memory 54 is transferred to the second storage unit 58 instead of the master boot record in the first storage unit 55. Further, since the dummy data is returned to the data transfer unit 56, an error is not detected based on no response to the access request transmitted from the data transfer unit 56 to the memory controller 53. Here, the processing of step S29 and step S30 is an example of the third step in the present invention, and is executed by the second transfer control unit 592 of the transfer control unit 59.

  As described above, in the transfer control process, in the data transfer process executed by the data transfer unit 56 in response to a request from the CPU 51, access to the master boot record in the first storage unit 55 is not performed. 2 is converted into access to the storage unit 58. Therefore, it is possible to suppress leakage of data stored in the first storage unit 55 without changing the control program of the image forming apparatus 10.

1: ADF
2: Image reading unit 3: Image forming unit 4: Paper feeding unit 5: Control unit 51: CPU
52: ROM
53: Memory controller 54: Memory 55: First storage unit 56: Data transfer unit 57: Memory controller 58: Second storage unit 59: Transfer control unit 591: First transfer control unit 592: Second transfer control unit 60: Transfer Instruction unit 7: operation display unit 10: image forming apparatus

Claims (8)

A data transfer unit that executes data transfer processing between the first storage unit and the memory in response to a request from the processor;
A second storage unit for storing system activation data necessary for the processor to use the first storage unit;
The execution of the first transfer process for transferring the data stored in the predetermined specific storage area of the first storage unit to the memory by the data transfer unit is detected and stored in the second storage unit. A first transfer control unit for transferring the system activation data to the memory;
The execution of a second transfer process for transferring the system activation data stored in the memory by the data transfer unit to the specific storage area is detected, and the system activation data stored in the memory is stored in the second storage. A second transfer control unit for transferring to the unit;
An information processing apparatus comprising: The specific storage area is a master boot record predetermined as an area for storing the system startup data,
The information processing according to claim 1, wherein the system activation data includes one or both of information indicating a configuration of a partition of the first storage unit and information for starting an operating system stored in the partition. apparatus. The first transfer control unit and the second transfer control unit are provided between the data transfer unit and the memory and the second storage unit;
The first transfer control unit detects execution of the first transfer process based on data transferred between the data transfer unit and the memory via the first transfer control unit;
3. The second transfer control unit detects execution of the second transfer process based on data transferred between the data transfer unit and the memory via the second transfer control unit. The information processing apparatus described in 1.   The information processing apparatus according to claim 1, wherein the first transfer control unit discards data transferred in the first transfer process.   5. The information according to claim 1, wherein the second transfer control unit transfers predetermined dummy data to the specific storage area instead of the system activation data transferred in the second transfer process. 6. Processing equipment.   The information processing apparatus according to claim 1, wherein the data transfer unit executes the data transfer process between the first storage unit and the memory according to an AHCI standard.   The information processing apparatus according to claim 1, wherein the second storage unit is mounted on a control board of the information processing apparatus. A transfer control method executed by an information processing apparatus including a second storage unit that stores system activation data necessary for the processor to use the first storage unit,
A first step of executing a data transfer process between the first storage unit and the memory in response to a request from the processor;
The execution of the first transfer process for transferring the data stored in the predetermined specific storage area of the first storage unit in the first step to the memory is detected and stored in the second storage unit. A second step of transferring the system startup data to the memory;
The execution of the second transfer process for transferring the system activation data stored in the memory in the first step to the specific storage area is detected, and the system activation data stored in the memory is stored in the second storage. A third step of transferring to the department;
Including a transfer control method.

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